Display panel, display device and driving method thereof, and image rendering method

Abstract

A display panel, a display device and a driving method thereof, and an image rendering method are provided according to an embodiment of the present invention. The display panel includes a first base substrate, a plurality of scan lines located on one side of the first base substrate, a plurality of data lines located on the same side of the first base substrate as the scan lines, extending in the second direction together with the plurality of data lines and arranged along the first direction, and a plurality of sub-pixels located in each of the areas partitioned by the plurality of scan lines and the plurality of data lines, the plurality of scan lines extending in the first direction and arranged along the second direction, the first direction and the second direction intersecting, the plurality of sub-pixels constituting a plurality of the pixel islands, the plurality of the pixel islands being partitioned into a plurality of control regions, each of the control regions including at least one of the pixel islands, and the control regions being independently driven to emit light.

Description

[Technical Field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a display device and its driving method, and an image rendering method. [Background technology]

[0002] With the development of display technology, interest in three-dimensional (3D) display technology is growing. 3D display technology makes the display screen appear more realistic and three-dimensional. The principle is that the left and right eyes receive left and right images with a certain parallax, respectively. The two parallax images are then received by the left and right eyes, respectively, and the image information is then superimposed and fused via the brain to create a 3D visual display effect. To achieve compatibility between super multi-view 3D display and light field display, conventional subpixels are structured as pixel islands. Each pixel island contains multiple subpixels. When the display information of each subpixel is different and a single eye views multiple viewpoints, conventional light field display is realized. When the display information of multiple subpixels is different and a single eye views a single viewpoint, super multi-view light field 3D display is realized.

[0003] However, as the resolution of display panels improves, problems arise such as a low aperture ratio and high power consumption of display products. Summary of the Invention

[0004] A display panel provided by an embodiment of the present invention includes a first base substrate, a plurality of scan lines located on the first substrate side, a plurality of data lines located on the same side of the first substrate as the scan lines, and a plurality of sub-pixels located in areas defined by the plurality of scan lines and the plurality of data lines, wherein the plurality of scan lines extend in a first direction and are arranged along a second direction, the first direction intersecting with the second direction, the plurality of data lines extend in the second direction and are arranged along the first direction, the plurality of sub-pixels form a plurality of pixel islands, the plurality of pixel islands are divided into a plurality of control regions, each control region includes at least one pixel island, and each control region is independently driven to emit light.

[0005] In some embodiments, the display panel further includes a plurality of scan signal input lines extending in a first direction in one-to-one correspondence with the scan lines and arranged in a second direction, a plurality of control signal lines arranged along the first direction, a plurality of fixed potential lines, and a plurality of control circuits located between adjacent subpixels, wherein at least n control circuits are connected to one pixel island, n representing the number of subpixel rows included in the pixel island, one control circuit corresponds to one row of subpixels included in the pixel island, and the control circuits control the scan signal input lines based on control of the control signal lines. Lines of force and a signal supplied from a fixed potential line to transmit to the scanning line, at least some of the plurality of control signal lines including a plurality of portions extending in the second direction and a plurality of portions extending in the first direction, and the plurality of portions extending in the second direction are alternately connected to the plurality of portions extending in the first direction.

[0006] In some embodiments, the control circuit includes a first transistor and a second transistor, a control electrode of the first transistor electrically connected to one control signal line, a first electrode of the first transistor electrically connected to a scanning signal input line, a second electrode of the first transistor electrically connected to a scanning line, a control electrode of the second transistor electrically connected to one control signal line, a first electrode of the second transistor electrically connected to a fixed potential line, and a second electrode of the second transistor electrically connected to the scanning line.

[0007] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line, and the first transistor is an N-type transistor and the second transistor is a P-type transistor, or the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0008] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.

[0009] In some embodiments, the display panel further includes a gate drive circuit, the gate drive circuit including a plurality of cascaded shift registers, one shift register electrically connected to each scan signal input line in one row of the control area.

[0010] In some embodiments, each scan line includes a plurality of sub-scan lines arranged along a first direction and disconnected from one another, the number of sub-scan lines in each scan line is the same as the number of control regions arranged in the first direction, and each sub-scan line corresponds to one row of sub-pixels in one control region.

[0011] In some embodiments, the display panel is divided into a display area and a peripheral area surrounding the display area, the pixel islands are located in the display area, and the scan lines and data lines extend from the display area to the peripheral area. The display panel further includes a plurality of first data selection control lines located in the peripheral area, a plurality of first data input lines, and a plurality of first data selection circuits, each of the first data selection circuits including at least two multiplexers, and in each of the first data selection circuits, input ends of different multiplexers are electrically connected to different first data input lines, and different The control ends of the multiplexers are electrically connected to different first data selection control lines, and the i-th output ends of the different multiplexers are electrically connected to the same data line, where i is a positive integer; in two adjacent first data selection circuits, the two multiplexers electrically connected to different first data selection control lines are electrically connected to the same first data input line; and the first data selection circuits are configured to supply signals of the corresponding first data input lines to each of the electrically connected data lines under the control of the plurality of first data selection control lines.

[0012] In some embodiments, each subpixel row in a pixel island includes h subpixels, and each subpixel row is divided into a subpixel groups, each including f subpixels, where a=h / f, a, h, and f are all positive integers greater than 1; multiple data lines connected to each subpixel group are electrically connected to one first data selection circuit, and multiple data lines connected to different subpixel groups are electrically connected to different first data selection circuits; and each multiplexer includes f output terminals, one input terminal, and f control terminals.

[0013] In some embodiments, each first data selection circuit includes j multiplexers, the number of first data selection control lines is j*f, the number of first data selection circuits is m, the number of first data input lines is m, m and n satisfy n=m+j-1, and for every j consecutive first data selection circuits, the j multiplexers electrically connected to different first data selection control lines are electrically connected to the first data input lines, where j is a positive integer less than m.

[0014] In some embodiments, one multiplexer includes f switching transistors, the control electrodes of different switching transistors are electrically connected to different first data selection control lines, the first electrodes of different switching transistors are electrically connected to the same first data input line, and the second electrodes of different switching transistors are electrically connected to different data lines, and in each first data selection circuit, the second electrodes of the i-th switching transistors in different multiplexers are electrically connected to the same data line.

[0015] In some embodiments, one multiplexer includes f switching circuits, and each switching circuit Gu times The circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor, a control electrode of the fifth transistor electrically connected to a first data selection control line, a first electrode of the fifth transistor and a first electrode of the sixth transistor both electrically connected to a first data input line, a second electrode of the fifth transistor electrically connected to a control electrode of the sixth transistor, a control electrode of the seventh transistor, and a first electrode of the first capacitor, a second electrode of the sixth transistor and a second electrode of the seventh transistor electrically connected to a data line, and a second electrode of the first capacitor is grounded, and the display panel further includes a dummy signal line electrically connected to the first electrode of the seventh transistor.

[0016] In some embodiments, the subpixels in a row arranged in the first direction are all the same color, and the display panel further includes a light-shielding layer extending in the first direction and including only a plurality of light-shielding portions arranged in the second direction.

[0017] A display device provided by an embodiment of the present invention includes a display panel provided by an embodiment of the present invention, a cylindrical lens structure located on the light-emitting side of the display panel, and a controller connected to the display panel and configured to supply independent drive signals to each control area, wherein the cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array.

[0018] In some embodiments, each subpixel row within a pixel island includes h subpixels, and each pixel island corresponds to N cylindrical lenses, where h and N are positive integers, h>N, and h / N is a non-integer.

[0019] In some embodiments, each row of subpixels within a pixel island includes a shaded region, and the ratio of the area of ​​the subpixel to the area of ​​the shaded region is X, where X=N−1.

[0020] In some embodiments, the controller includes a data analysis circuit that performs data analysis on the image to be displayed to obtain image analysis data, a data placement circuit that generates a data drive signal corresponding to a control area of ​​the display panel based on the current display mode and the image analysis data, and a timing control circuit that generates a gate drive signal for the gate drive circuit according to the current display mode and the gaze area and non-gaze area of ​​the display panel.

[0021] Some embodiments further include an eye tracking system for determining in real time the user's eye gaze area on the display device.

[0022] In some embodiments, the human eye tracking system includes an image acquisition circuit, a camera standardization circuit, a camera standardization circuit, a camera time division partition control circuit, a face detection circuit, an image coordinate system transformation circuit, a pupil detection circuit, a spatial coordinate calculation circuit, and a spatial gaze tracking circuit, wherein the image acquisition circuit includes a plurality of first cameras and at least one second camera, wherein a resolution of the first camera is greater than a resolution of the second camera, the first camera is configured to acquire a pupil image of a user, and the second camera is configured to acquire a face image of a user, the camera standardization circuit is configured to standardize the first camera and the second camera to acquire an internal parameter matrix and an external parameter matrix of the first camera and the second camera, the camera time division partition control circuit controls the shooting timing of the plurality of first cameras, and the plurality of first cameras are configured to alternately acquire images, and the face detection circuit searches for a face frame in the image acquired by the second camera, detects facial feature points, acquires a human eye area within the face frame, and further calculates a human eye area according to a mapping relationship between the facial feature points and a standard human model. The image coordinate system conversion circuit is configured to convert a face image coordinate system into a cylindrical pupil image coordinate system or convert a pupil coordinate system into a face image coordinate system. The pupil detection circuit is configured to calculate pupil coordinates in an image captured by a first camera, and convert the pupil coordinates into the pupil image coordinate system using a coordinate conversion circuit based on the human eye area coordinates obtained by the face detection circuit. Thereafter, the coordinate conversion circuit converts the pupil coordinates into the pupil image coordinate system, obtains the human eye area on the pupil image, detects the pupil in the human eye area, and obtains the pupil coordinates in the pupil image coordinate system. The spatial coordinate calculation circuit The path is configured to convert pupil coordinates into a face image coordinate system and calculate pupil coordinates in three-dimensional space using a spatial coordinate transformation matrix obtained by the face detection circuit, and the spatial gaze tracking circuit is configured to determine eyeball center coordinates using the pupil coordinates and a predetermined human eye model, calculate the direction vector of the pupil coordinates and eyeball center coordinates as a line vector, obtain the gaze intersection between the human eye and the display panel based on the distance from the human eye to the display panel and the plane equation on which the display panel exists, and obtain the human eye gaze point coordinate on the display panel based on the gaze intersection.

[0023] In some embodiments, the display device further includes an image rendering system electrically connected to the controller, the image rendering system including a coordinate extraction circuit, a lens alignment detection circuit, and an image rendering circuit, wherein the coordinate extraction circuit is configured to determine three-dimensional spatial coordinates of the human eye relative to the display panel based on the position of the human eye's line of sight on the display panel in the display device determined by the eye tracking system, the lens alignment detection circuit is configured to obtain a cylindrical lens alignment error, adjust the cylindrical lens alignment parameters based on the alignment error, and obtain a viewpoint crosstalk curve, and the image rendering circuit is configured to generate a multi-viewpoint initial image from the image to be displayed, and optimize the multi-viewpoint initial image based on the human eye position, the alignment detection parameters, and the crosstalk curve, and obtain the optimized multi-viewpoint image as the image to be displayed.

[0024] A driving method for a display device provided by an embodiment of the present invention includes the steps of determining a user's gaze area and non-gaze area on the display device in real time, and independently driving a control area corresponding to the gaze area to display an image at a first resolution, and driving a control area corresponding to the non-gaze area to display an image at a second resolution, where the first resolution is higher than the second resolution.

[0025] In some embodiments, the user's gaze area and non-gaze area on the display device are determined, specifically, the gaze area of ​​the user's eyes on the display device is obtained using an eye tracking system, and areas on the display device other than the gaze area are determined as non-gaze areas.

[0026] In some embodiments, the eye tracking system acquires the gaze area of ​​the user's eyes on the display device. Specifically, a first camera in the controlled eye tracking system alternately acquires the user's pupil image, and a second camera in the controlled eye tracking system acquires the user's face image, searches for a face frame in the image acquired by the second camera, detects facial feature points, acquires the eye area within the face frame, and further acquires a spatial coordinate transformation matrix of the eye area according to the mapping relationship between the facial feature points and the standard human model, transforms the face image coordinate system into a cylindrical pupil image coordinate system, or transforms the pupil coordinate system into the face image coordinate system, calculates the pupil coordinates in the image acquired by the first camera, and converts the coordinates of the eye area to the pupil image. coordinate system, obtain the human eye area on the pupil image, perform pupil detection in the human eye area on the pupil image, obtain pupil coordinates in the pupil image coordinate system, convert the pupil coordinates into a face image coordinate system, further calculate a spatial coordinate transformation matrix to obtain pupil coordinates in three-dimensional space, determine the eyeball center coordinates using the pupil coordinates and a predetermined human eye model, calculate the direction vector of the pupil coordinates and the eyeball center coordinates as a line vector, obtain the line of sight intersection between the human eye and the display panel based on the distance from the human eye to the display panel and the plane equation on which the display panel exists, obtain the human eye gaze point coordinate on the display panel based on the line of sight intersection, and determine the area where the human eye gaze point coordinate on the display panel exists as the gaze area.

[0027] In some embodiments, the control region corresponding to the attention region is independently driven to display an image at a first resolution, and the control region corresponding to the non-attention region is driven to display an image at a second resolution. Specifically, based on the display mode, the attention region, and the non-attention region, display information for each sub-pixel in the pixel island of the control region corresponding to the attention region and display information for each sub-pixel in the pixel island of the control region corresponding to the non-attention region are determined, and based on the display information, a first data selection control signal is supplied to the first data selection control line, and a data signal supplied from the first data write line is supplied to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0028] In some embodiments, independently driving the attention area to display an image at a first resolution and driving the non-attention area to display an image at a second resolution includes supplying gate drive signals to a gate drive circuit of the display panel via a display device controller to control a plurality of rows of pixel islands corresponding to the attention area to be turned on one by one, and to control F rows of pixel islands in the plurality of rows of pixel islands corresponding to the non-attention area to be turned on synchronously, where F is a positive integer and is the ratio between the first resolution and the second resolution.

[0029] In some embodiments, the gate drive circuit included in the display panel includes a plurality of gate drive groups, each gate drive group including B gate drive subgroups, each gate drive subgroup including C shift registers, where B and C are integers greater than 1, and supplies gate drive signals to the gate drive circuit of the display panel via a controller of the display device, specifically, supplies clock control signals to the gate drive groups via the controller, and causes on signals to be sequentially input to the plurality of shift registers in the gate drive subgroups in the order of the first to Bth gate drive subgroups for each gate drive group.

[0030] In some embodiments, the method further comprises driving the attention area to display images at a first refresh rate and driving the non-attention area to display images at a second refresh rate, where the first refresh rate is higher than the second refresh rate.

[0031] In some embodiments, the fixation area is driven to display images at a first refresh rate and the non-fixation area is driven to display images at a second refresh rate, specifically, each sub-pixel in the fixation area is driven to be refreshed Z times and each sub-pixel in the non-fixation area is driven to be refreshed Y times, where Z and Y are positive integers and Z is greater than Y.

[0032] In some embodiments, each sub-pixel in the attention area is driven to perform refresh, specifically, each scan signal input line corresponding to the attention area is driven to sequentially transmit an active level signal, each control signal line is controlled to transmit a control signal, and the scan signal input Lines of force The signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-attention area, thereby driving each sub-pixel in the non-attention area to perform refresh. Specifically, the scanning signal input lines in the display panel are driven to sequentially transmit active level signals, and when each sub-pixel row corresponding to the attention area is scanned, each control signal line is controlled to transmit a control signal, and the signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the scanning signal input lines are driven to sequentially transmit active level signals. Lines of force The signal supplied from the is transmitted to the scanning line corresponding to the non-attention area.

[0033] A 3D image rendering method for a display device provided by an embodiment of the present invention includes the steps of determining the position of the line of sight of a human eye on a display panel in the display device and determining the 3D spatial coordinates of the human eye relative to the display panel; generating an initial multi-view image from an image to be displayed; performing a bonding detection of a cylindrical lens array on the display device to obtain a bonding error and a viewpoint crosstalk curve of the cylindrical lens; optimizing the initial multi-view image based on the position of the human eye, the bonding detection parameters and the crosstalk curve to obtain an optimized multi-view image; and transmitting the optimized multi-view image to a controller. [Brief explanation of the drawings]

[0034] In order to more clearly describe the technical aspects of the embodiments of the present invention, the following briefly describes the drawings that need to be used in the description of the embodiments. The drawings in the following description are only some embodiments of the present invention, and it is obvious that those skilled in the art can obtain other drawings without requiring creative efforts. [Figure 1] 1 is a diagram illustrating the configuration of a display panel provided according to an embodiment of the present invention. [Figure 2] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 3] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 5] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 6] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 7] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 8] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 9] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 10] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 11] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 12] FIG. 10 is a diagram illustrating the configuration of another display panel provided by an embodiment of the present invention. [Figure 13] FIG. 10 is a schematic diagram of a switching circuit of another display panel provided by an embodiment of the present invention. [Figure 14] Timing diagram of a display panel provided by an embodiment of the present invention; [Figure 15] FIG. 4 is a timing diagram of the data lines of a display panel provided by an embodiment of the present invention; [Figure 16] 1 is a schematic diagram illustrating a display panel provided by an embodiment of the present invention, in which sub-pixels within a pixel island correspond to viewpoints. [Figure 17] FIG. 10 is a schematic diagram illustrating sub-pixels in a pixel island in another display panel provided by an embodiment of the present invention, each of which corresponds to a viewpoint. [Figure 18] FIG. 10 is a schematic diagram illustrating sub-pixels in a pixel island corresponding to viewpoints in another display panel provided by an embodiment of the present invention. [Figure 19] FIG. 10 is a schematic diagram illustrating sub-pixels in a pixel island corresponding to viewpoints in another display panel provided by an embodiment of the present invention. [Figure 20] 1 is a block diagram of a display device provided according to an embodiment of the present invention; [Figure 21] 1 is a view showing a viewpoint space distribution diagram of a display device provided according to an embodiment of the present invention; [Figure 22] 1 is a view showing a viewpoint space distribution diagram of a display device provided according to an embodiment of the present invention; [Figure 23] 1 is a schematic diagram of an interocular viewing area of ​​a display device provided by an embodiment of the present invention. [Figure 24] FIG. 2 is a schematic diagram of an interocular viewing area of ​​another display device provided by an embodiment of the present invention. [Figure 25] FIG. 2 is a block diagram of a controller provided by an embodiment of the present invention. [Figure 26] FIG. 10 is a block diagram of another controller provided by an embodiment of the present invention. [Figure 27] FIG. 2 is a schematic diagram of a resolution partition control provided by an embodiment of the present invention; [Figure 28] FIG. 10 is a block diagram of another display device provided by an embodiment of the present invention. [Figure 29] 2 is a flowchart of a driving method for a display device provided by an embodiment of the present invention. [Figure 30] FIG. 2 is a schematic diagram of a gate driving circuit provided by an embodiment of the present invention. [Figure 31] 4 is a timing chart of a gate driving circuit provided by an embodiment of the present invention. [Figure 32] 4 is a timing chart of another gate drive circuit provided by an embodiment of the present invention. [Figure 33]4 is a flowchart of an image rendering method for a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0035] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is clear that the described embodiments are only a part of the present invention and do not cover all the embodiments. In addition, the embodiments and features of the embodiments of the present invention may be combined without conflict. All other embodiments that are obtained by those skilled in the art based on the described embodiments of the present invention without requiring creative work fall within the scope of protection of the present invention.

[0036] Unless otherwise defined, technical or scientific terms used herein shall have the common meaning understood by those skilled in the art. The terms "first," "second," and similar terms used herein do not denote order, quantity, or importance, but are merely used to distinguish between different components. Similar terms such as "comprise" or "contain" mean that the element or object appearing before the term is equivalent to the element or object appearing after the term, and do not exclude other elements or objects. Similar terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0037] The dimensions and shapes of the figures in the drawings do not reflect true scale, but are intended to provide a general description of the present invention. The same or similar reference numerals throughout the drawings represent the same or similar elements or elements having the same or similar functions.

[0038] 1, one embodiment of the present invention relates to a display panel including a first base substrate 1, a plurality of scan lines 2 located on the first base substrate 1 side, a plurality of data lines 3 located on the same side of the first base substrate 1 as the scan lines 2, and a plurality of sub-pixels 4 located in regions defined by the plurality of scan lines 2 and the plurality of data lines 3. The plurality of scan lines 2 extend along a first direction X and are arranged along a second direction Y. The first direction X and the second direction Y intersect. The plurality of data lines 3 extend along the second direction Y and are arranged along the first direction X.

[0039] A plurality of sub-pixels 4 constitute a plurality of pixel islands 5. The plurality of pixel islands 5 are divided into a plurality of control regions 14, each of which includes at least one pixel island 5, and each of which is independently driven to emit light.

[0040] In a display panel provided by an embodiment of the present invention, multiple pixel islands are divided into multiple control regions, and each control region is independently driven to emit light, thereby enabling the resolution and refresh rate of the display panel to be selectively controlled according to the display screen conditions. By selectively controlling the resolution of the display panel, the display panel can be divided into high-definition and low-definition regions, with the resolution of the high-definition region being higher than that of the low-definition region, thereby improving the resolution of the region viewed by the human eye and improving the display effect. By selectively controlling the refresh rate of the display panel, the display panel can be divided into high-refresh rate and low-refresh rate regions, thereby reducing the power consumption of display products. Note that FIG. 1 illustrates only a portion of the subpixels in the display panel. In FIG. 1, the first direction X and the second direction Y are perpendicular.

[0041] In some embodiments, as shown in FIG. 1, in the second direction Y, each pixel island 5 comprises multiple sub-pixel rows 6.

[0042] 1, each pixel island 5 has three subpixel rows 6: a first subpixel row 48, a second subpixel row 49, and a third subpixel row 50. The first subpixel row 48 includes a plurality of subpixels of a first color arranged along a first direction X, the second subpixel row 49 includes a plurality of subpixels of a second color arranged along the first direction X, and the third subpixel row 50 includes a plurality of subpixels of a third color arranged along the first direction X.

[0043] In some embodiments, the first color subpixels are red subpixels R, the second color subpixels are green subpixels G, and the third color subpixels are blue subpixels B, as shown in FIG.

[0044] In some embodiments, as shown in FIG. 1, all of the sub-pixels 4 in a row arranged in the first direction X are the same color.

[0045] Alternatively, in some embodiments, as shown in FIG. 2 , the colors of the subpixels 4 in a row arranged in the first direction X are not completely identical. For example, a first subpixel row 48, a second subpixel row 49, and a third subpixel row 50 are arranged as a repeating unit in a column along the second direction Y, with odd-numbered columns being offset relative to even-numbered columns. A pixel island 5 includes a first pixel island 55 and a second pixel island 56. The first pixel island 55 includes the first subpixel row 48 and the second subpixel row 49. The second pixel island 56 includes the third subpixel row 50. When the display panel is driven for display, a subpixel rendering technique is used to render the second pixel island 56 in an adjacent column using the first pixel island 55 to form a single pixel for display. This improves the resolution of the display panel.

[0046] In a specific embodiment, the display panel provided by the embodiment of the present invention may be a rigid display panel or a flexible display panel, which is bendable or foldable.

[0047] In some embodiments, the display panel provided by embodiments of the present invention is a liquid crystal display panel, including types such as twisted nematic (TN), vertical alignment (VA), in-plane switching (IPS), and advanced super dimension switch (ADS) liquid crystal display panels.

[0048] In some embodiments, the liquid crystal display panel has an array substrate and a counter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the counter substrate. In a specific embodiment, the scan lines and data lines may be provided on the array substrate. In a specific embodiment, the counter substrate has a black matrix 7 and a color film 8, as shown in FIGS.

[0049] In some embodiments, as shown in FIG. 3, the black matrix 7 is provided in the areas between adjacent pixel islands in the second direction.

[0050] In some embodiments, as shown in FIG. 4, the black matrix 7 is provided in the regions between adjacent pixel islands and between adjacent sub-pixel columns in the second direction.

[0051] In some embodiments, as shown in FIG. 5, the black matrix 7 may be provided in the regions between adjacent rows of subpixels and in the regions between adjacent columns of subpixels.

[0052] In some embodiments, when all the subpixels in a row arranged in the first direction X are of the same color, the black matrix 7 may be provided only in the areas between adjacent subpixel rows, as shown in FIG. 6.

[0053] Since all of the subpixels in one row arranged in the first direction X are the same color, there is no crosstalk between adjacent subpixel columns even without providing a black matrix between the subpixel columns, and it is possible to improve the aperture ratio of the display panel by providing a black matrix only between adjacent subpixel rows.

[0054] In some embodiments, the display panel provided by embodiments of the present invention is an electroluminescent display panel, such as an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc. In a specific embodiment, each subpixel includes, for example, an electroluminescent element electrically connected to a pixel driving circuit, and the pixel driving circuit includes, for example, a transistor, a capacitor, etc.

[0055] 7, 8, and 10, the display panel further includes a plurality of scan signal input lines 7 extending along the first direction X corresponding to the scan lines 2 and arranged along the second direction Y, a plurality of control signal lines 8 arranged along the first direction X, a plurality of fixed potential lines 9, and a plurality of control circuits 10 arranged in adjacent subpixels 4. One pixel island 5 is connected to at least n control circuits 10. One control circuit 10 corresponds to one subpixel row 6 in the pixel island 5.

[0056] The control circuit 10 transmits a signal supplied from a scanning signal input line 7 or a signal supplied from a fixed potential line 9 to the scanning line 2 under the control of a control signal line 8 .

[0057] The display panel provided by the embodiment of the present invention includes a control circuit, a control signal line electrically connected to the control circuit, a fixed potential line, and a scanning signal input line, so that the control circuit can be used to input the scanning signal. Lines of force It is possible to transmit signals supplied from the control circuit or signals supplied from fixed potential lines to the scan lines. That is, for areas that require refreshing during image display, the control circuit may input normal scan signals to the corresponding scan lines, and for areas that do not require refreshing, the control circuit may input fixed potential signals transmitted via fixed potential lines to the corresponding scan lines. This makes it possible to drive pixel islands in a partitioned manner, thereby reducing the power consumption of display products. Furthermore, for pixel island array arrangement, each pixel island is electrically connected to a control circuit, enabling partition control of each pixel island in the display panel in the second direction.

[0058] When the display panel is a liquid crystal display panel, in some embodiments, the subpixel 4 includes a drive transistor Td and a pixel electrode (not shown) electrically connected to the drive transistor, as shown in Figures 7, 8, and 10. Here, a control electrode of the drive transistor Td is electrically connected to a scan line 2, a first electrode of the drive transistor Td is electrically connected to a data line 3, and a second electrode of the drive transistor Td is electrically connected to the pixel electrode.

[0059] In some embodiments, the liquid crystal display panel further includes a common electrode layer, which may be provided on the array substrate or the counter substrate.

[0060] In some embodiments, the fixed potential line receives a low level signal.

[0061] 7, 8, and 10, each scan line 2 includes a plurality of sub-scanning lines 11 arranged in the first direction X and disconnected from one another. In each scan line 2, the number of sub-scanning lines 11 is the same as the number of control regions 14 arranged in one row in the first direction X, and each sub-scanning line 11 corresponds to one row of sub-pixels 4 in one control region 14. In other words, the scan lines are disconnected between the control regions, allowing each control region to be independently controlled by a control circuit.

[0062] In some embodiments, as shown in Figures 7, 8 and 10, one pixel island 5 is connected to n corresponding control circuits.

[0063] In some embodiments, as shown in Figures 7, 8, and 10, in each control region 14, one row of pixel islands 5 arranged in a first direction X are connected to corresponding n control circuits 10.

[0064] Of course, in a specific embodiment, n control circuits may be connected to each pixel island.

[0065] In some embodiments, as shown in Figures 7, 8 and 10, each pixel island 5 includes three subpixel rows 6, i.e., n=3, and three corresponding control circuits 10 are connected per pixel island 5.

[0066] In some embodiments, as shown in FIGS. 7, 8, 9, and 10, the control circuit 10 includes a first transistor T1 and a second transistor T2.

[0067] A control electrode of the first transistor T1 is electrically connected to one control signal line 8, a first electrode of the first transistor T1 is electrically connected to a scanning signal input line 7, and a second electrode of the first transistor T1 is electrically connected to a scanning line 2.

[0068] The control electrode of the second transistor T2 is electrically connected to one control signal line 8, the first electrode of the second transistor T2 is electrically connected to a fixed potential line 9, and the second electrode of the second transistor T2 is electrically connected to the scanning line 2.

[0069] In a specific embodiment, for the plurality of control circuits corresponding to one control region, when the first transistor is turned on and the second transistor is turned off under the control of the control signal input to the control signal line, the signal input from the scan signal input line is transmitted to the scan line via the first transistor to refresh the pixel island of the control region, and when the second transistor is turned on and the first transistor is turned off under the control of the control signal input from the control signal line, the low-level signal input from the fixed potential line is transmitted to the scan line via the second transistor, i.e., the pixel island of the control region does not require refreshing.

[0070] In some embodiments, the second electrode of the first transistor T1 and the second electrode of the second transistor T1 in one control circuit are electrically connected to the same sub-scan line.

[0071] 7, the control electrode of the first transistor T1 and the control electrode of the second transistor T1 are electrically connected to the same control signal line 8. The first transistor is an N-type transistor and the second transistor is a P-type transistor, or the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0072] In some embodiments, the control electrode of the first transistor T1 and the control electrode of the second transistor T2 are electrically connected to different control signal lines 8, as shown in FIGS.

[0073] 8, 9, and 10, the plurality of control signal lines 8 includes a plurality of first control signal lines 12 and a plurality of second control signal lines 13. A control electrode of the first transistor T1 is electrically connected to the first control signal line 12, and a control electrode of the second transistor T2 is electrically connected to the second control signal line 13.

[0074] In a specific embodiment, when the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines, the first transistor may be an N-type transistor or a P-type transistor, and the second transistor may be an N-type transistor or a P-type transistor.

[0075] In some embodiments, as shown in FIGS. 7 and 8, the control circuit 10 is located between two subpixels 4 adjacent to each other in the first direction X.

[0076] The plurality of fixed potential lines 9 extend along a first direction X and are arranged along a second direction Y. That is, as shown in FIGS. 7 and 8, the control circuit 10 is located between two adjacent columns of sub-pixels 4.

[0077] In some embodiments, as shown in Figures 7 and 8, each control signal line 8 extends along the second direction Y, and multiple control circuits 10 are arranged in an array, with the corresponding control circuits for each pixel island located in the same column.

[0078] Alternatively, when the control circuit is located between two adjacent columns of subpixels, in some embodiments, at least some of the plurality of control signal lines 8 include a plurality of portions 57 extending in the second direction and a plurality of portions 58 extending in the first direction, as shown in Figure 9. The plurality of portions 57 extending in the second direction are alternately connected to the plurality of portions 58 extending in the first direction.

[0079] In a display panel provided by an embodiment of the present invention, the control signal lines include a plurality of portions extending in a first direction and a plurality of portions extending in a second direction, thereby avoiding optical unevenness caused by a regular longitudinal arrangement of the signal lines when the control signal lines do not extend regularly in the second direction but the signal lines are arranged along the first direction. In some embodiments, as shown in Figure 9, multiple control circuits corresponding to each pixel island are arranged in multiple columns in the second direction. That is, by distributing the control circuits, it is possible to further avoid optical interference. Alternatively, in some embodiments, as shown in Figure 10, a control circuit 10 is located between two subpixels 4 adjacent to each other in the second direction Y.

[0080] The plurality of fixed potential lines 9 extend in the second direction Y and are arranged in the first direction X. That is, the control circuit 10 is located between adjacent rows of sub-pixels.

[0081] In some embodiments, the control circuits corresponding to each pixel island are arranged in a single column in the first direction X. Of course, the control circuits corresponding to each pixel island may be arranged in multiple rows in the first direction X.

[0082] In some embodiments, the display panel further includes a gate drive circuit.

[0083] The gate drive circuit includes a plurality of cascaded shift registers GOA, each electrically connected to a corresponding scan signal input line in a row of the control area, and electrically connected to a clock signal line CLK and a start signal line STV.

[0084] This allows the gate driving circuit to partition multiple rows of pixel islands, i.e., horizontal partition control, i.e., partition control each pixel island in the display panel in a first direction and a second direction. In a specific embodiment, by applying corresponding timing to the gate driving circuit, the gate driving circuit may be used to turn on pixel islands in the display area one row at a time, or the gate driving circuit may be used to turn on multiple rows of pixel islands in the display area simultaneously.

[0085] In some embodiments, the gate drive circuit included in the display panel includes a plurality of gate drive groups, each of which includes B gate drive subgroups, and each of which includes C shift registers, where B and C are integers greater than 1. The activation signal line STV is electrically connected to the C shift registers in the first gate drive subgroup.

[0086] 11, the display panel is divided into a display area 59 and a peripheral area 60 surrounding the display area 59, with the pixel islands 5 located in the display area 59 and the scan lines 2 and data lines 4 extending from the display area 59 to the peripheral area 60. In a specific embodiment, the gate drive circuitry may be provided in the peripheral area, for example.

[0087] In some embodiments, as shown in Figures 11 and 12, the display panel further includes a plurality of first data selection control lines MUX, a plurality of first data input lines D and a plurality of first data selection circuits 15 located in the peripheral region 60.

[0088] Each first data selection circuit 15 includes at least two multiplexers 16. In each first data selection circuit 15, input terminals of different multiplexers 16 are electrically connected to different first data input lines D, control terminals of different multiplexers 16 are electrically connected to different first data selection control lines MUX, and the i-th output terminals of different multiplexers 16 are electrically connected to the same data line 3, where i is a positive integer. In two adjacent first data selection circuits 15, two multiplexers 16 electrically connected to different first data selection control lines MUX are electrically connected to the same first data input line D, and the first data selection circuits 15 supply the signals of the corresponding first data input lines D to each electrically connected data line 3 under the control of the signals of the multiple first data selection control lines MUX.

[0089] The display panel provided by the embodiment of the present invention uses a first data selection circuit to supply signals from the first data input lines to the data lines, thereby making it possible to make the number of first data input lines less than the number of data lines, and thereby reducing the amount of data input.

[0090] In a display panel provided by an embodiment of the present invention, each first data selection circuit includes at least two multiplexers, and different multiplexers in each first data selection circuit are electrically connected to different first data input lines. For one first data selection circuit, signals from the same first data input line may be supplied to each electrically connected data line under the control of signals from multiple first data selection control lines, or signals from different first data input lines may be supplied to corresponding data lines via different multiplexers. The multiple data lines connected to the same first data selection circuit may input the same data signal or may input data signals that are not completely identical. This allows individual display of each subpixel in each pixel island or collectively displaying multiple subpixels in a row, thereby enabling adjustment of the resolution of the display panel. In addition, when multiple subpixels requiring the same row per pixel island are displayed collectively, if the position of the human eye changes, the integrated display subpixel will also change. Therefore, the first data selection circuit of the display panel provided by the embodiment of the present invention makes it possible to change the display information of the integrated display subpixel, and the display information of the subpixel can be smoothly transitioned according to the movement of the human eye, thereby improving the display effect and the user experience. Note that Figure 12 does not show the display area, and Figures 11 and 12 only show some data lines, scanning lines, subpixels, first data input lines, and first data selection circuits.

[0091] 11 , a pixel island 5 includes multiple subpixel rows 6 arranged along a first direction X. Each subpixel row 6 includes h subpixels 4 arranged along a second direction Y. Each subpixel row 6 is divided into a subpixel groups 17. Each subpixel group 17 includes f subpixels 4, where a=h / f, a, h, and f are all positive integers greater than 1.

[0092] In one subpixel row 6, each subpixel group 17 is electrically connected to one first data selection circuit 15 via a data line 3, and different subpixel groups 17 are electrically connected to different first data selection circuits 15 through the data lines 3. Each multiplexer 16 includes f output terminals, one input terminal and f control terminals.

[0093] In this way, for each subpixel group in one subpixel row, under the control of signals from multiple first data selection control lines, the same first data input line signal may be supplied to each electrically connected data line via its corresponding first data selection circuit, or different first data input line signals may be supplied to each electrically connected data line via its corresponding first data selection circuit. That is, the same display information may be input to each subpixel in one subpixel group via the first data selection circuit, or the completely same display information may be input to each subpixel in one subpixel group via the first data selection circuit.

[0094] In a specific embodiment, the subpixels are electrically connected to both the scan lines and the data lines, and the subpixels in a column arranged in the first direction X are electrically connected to the same data line, and the subpixels in a row arranged in the second direction Y are electrically connected to the same scan line. That is, in a specific embodiment, one first data selection circuit is electrically connected to one column of subpixel groups via f data lines.

[0095] In some embodiments, the number of first data selection circuits is equal to the number of subpixel groups in a row of subpixels arranged in the second direction, thereby enabling data signals to be provided to the subpixel groups in the corresponding pixel island via the first data selection circuits.

[0096] In some embodiments, each first data selection circuit includes j multiplexers, the number of first data selection control lines is j*f, the number of first data selection circuits is m, the number of first data input lines is m, and m and n satisfy n=m+j−1.

[0097] For every j consecutive first data selection circuits, j multiplexers electrically connected to different first data selection control lines are electrically connected to the first data input line, where j is a positive integer less than m.

[0098] 11 and 12, each first data selection circuit 15 includes two multiplexers: a first multiplexer 18 and a second multiplexer 19. The number m of first data selection circuits 15 and the number n of first data input lines D satisfy n=m+1.

[0099] In a specific embodiment, the first data input lines D are numbered starting from 0, for example, i.e., the n first data input lines are numbered D0 to Dm. As shown in FIG. 11, when the first data selection circuit 15 on the leftmost side in FIG. 11 is the first data selection circuit, the first multiplexer 18 of the first data selection circuit 15 and the second multiplexer 19 of the second data selection circuit 15 are electrically connected to one first data input line D1. In a specific embodiment, the second multiplexer 19 in the first first data selection circuit 15 is electrically connected to the 0th first data input line D0. The first multiplexer 18 of the mth first data selection circuit 15 is electrically connected to the mth first data input line Dm.

[0100] In some embodiments, one multiplexer includes f switching transistors, the control electrodes of different switching transistors are electrically connected to different first data selection control lines, the first electrodes of different switching transistors are electrically connected to the same first data input line, and the second electrodes of different switching transistors are electrically connected to different data lines, and in each first data selection circuit, the second electrodes of the i-th switching transistors in different multiplexers are electrically connected to the same data line.

[0101] In some embodiments, when the first data selection circuit includes two multiplexers, the first multiplexer 18 includes f third transistors T3, as shown in Figure 11. The control electrodes of different third transistors T3 are electrically connected to different first data selection control lines MUX. The first electrodes of different third transistors T3 are electrically connected to the same first data input line D. The second electrodes of different third transistors T3 are electrically connected to different data lines 3.

[0102] The second multiplexer 19 includes f fourth transistors T4, and the control electrodes of different fourth transistors T4 are electrically connected to different first data selection control lines MUX. The first electrodes of different fourth transistors T4 are electrically connected to the same first data input line D. The second electrodes of different fourth transistors T4 are electrically connected to different data lines 3.

[0103] In each first data selection circuit 15, the second electrode of the i-th third transistor T3i in the first multiplexer 18 and the second electrode of the i-th fourth transistor T4i in the second multiplexer 13 are electrically connected to the same data line 3.

[0104] In some embodiments, the third transistor and the fourth transistor are P-type transistors or N-type transistors. This facilitates control of the first data selection circuit by the first data selection control line. Of course, one of the third transistor and the fourth transistor may be a P-type transistor and the other an N-type transistor. In some embodiments, the display panel has 2f first data selection control lines.

[0105] Here, f first data selection control lines are electrically connected to the control electrodes of the respective third transistors in the first data plexer, and the remaining f first data selection control lines are electrically connected to the control electrodes of the respective fourth transistors in the second data plexer.

[0106] 11, the control electrodes of the ith third transistors T3i in different first data selection circuits 15 are electrically connected to the same first data selection control line MUX, and the control electrodes of the ith fourth transistors T4i in different first data selection circuits are electrically connected to the same first data selection control line MUX.

[0107] 11, the control electrodes of the three transistors T3i are electrically connected to the same first data selection control line MUX, and the control electrodes of the i-th fourth transistors T4i in different first data selection circuits are electrically connected to the same first data selection control line MUX, and the display panel includes 2f first data selection control lines. Of course, in specific embodiments, the control electrodes of the i-th third transistors T3i in different first data selection circuits may be electrically connected to different first data selection control lines MUX, and the control electrodes of the i-th fourth transistors T4i in different first data selection circuits may be electrically connected to different first data selection control lines MUX. The number of first data selection control lines included in the display panel is an integer multiple of 2f.

[0108] In some embodiments, as shown in FIG. 11, each subpixel row 6 within a pixel island 5 includes 16 subpixels 4, and each subpixel row 6 is divided into four subpixel groups 17, each having four subpixels 4.

[0109] Each multiplexer 16 includes four input terminals, one control terminal, and four output terminals. Next, an example of the display panel shown in Figure 11 provided in the embodiment of the present invention, in which each subpixel group is composed of four subpixels, will be described.

[0110] 11, the first multiplexer 18 has four third transistors T31, T32, T33, and T34, and the second multiplexer 19 has four fourth transistors T41, T42, T43, and T44.

[0111] In a specific embodiment, as shown in FIG. 11, there are eight first data selection control lines MUX, which are MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8, respectively. Among these, the control terminal of the first third transistor T31 in each first data selection circuit 15 is electrically connected to MUX1, the control terminal of the first fourth transistor T41 in each first data selection circuit 15 is electrically connected to MUX2, the control terminal of the second third transistor T32 in each first data selection circuit 15 is electrically connected to MUX3, the control terminal of the second fourth transistor T42 in each first data selection circuit 15 is electrically connected to MUX4, the control terminal of the third third transistor T33 in each first data selection circuit 15 is electrically connected to MUX5, the control terminal of the third fourth transistor T43 in each first data selection circuit 15 is electrically connected to MUX6, the control terminal of the fourth third transistor T34 in each first data selection circuit 15 is electrically connected to MUX7, and the control terminal of the fourth fourth transistor T44 in each first data selection circuit 15 is electrically connected to MUX8.

[0112] In a specific embodiment, as shown in FIG. 11 , in each first data selection circuit 15, the output terminal of the first third transistor T31 and the output terminal of the first fourth transistor T41 are electrically connected to the same data line 3, the output terminal of the second third transistor T32 and the output terminal of the second fourth transistor T42 are electrically connected to the same data line 3, the output terminal of the third third transistor T33 and the output terminal of the third fourth transistor T43 are electrically connected to the same data line 3, and the output terminal of the fourth third transistor T34 and the output terminal of the fourth fourth transistor T44 are electrically connected to the same data line 3.

[0113] 11, in each first data selection circuit 15, the input terminals of the third transistors T31, T32, T33, and T34 are electrically connected to the same first data input line D, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to the same first data input line D, while the input terminals of the third transistors T31, T32, T33, and T34 and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to different first data input lines D. For example, in FIG. 11, in the first first data selection circuit 15 from left to right, the input terminals of the third transistors T31, T32, T33, and T34 are electrically connected to D1, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D0. The input terminals of the third transistors T31, T32, T33, and T34 in the second first data selection circuit 15 are electrically connected to D2, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D1. The input terminals of the third transistors T31, T32, T33, and T34 in the third first data selection circuit 15 are electrically connected to D3, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D2. This analogy will not be further discussed here.

[0114] In a specific embodiment, a viewpoint needs to correspond to a red subpixel, a blue subpixel, and a green subpixel. Next, the correspondence between subpixels and viewpoints will be described by taking an example where one subpixel row of a pixel island consists of 16 subpixels.

[0115] When one pixel island corresponds to 16 viewpoints, each subpixel in the same row in each subpixel group within the pixel island needs to display different display information. For example, as shown in FIG. 16, the i-th viewpoint Pi corresponds to Ri, Gi, Bi in the first pixel island 22, where i is a positive integer less than or equal to 16. Taking an example in which the first four first data selection circuits arranged from left to right in FIG. 11 are electrically connected to the first pixel island, in a specific embodiment, data signals corresponding to the viewpoints Pi to P4i are sequentially supplied to Di, and the third transistors T31, T32, T33, and T34 in the first data selection circuits are sequentially turned on via the first data selection control lines MUX1, MUX3, MUX5, and MUX7, and the fourth transistors T41, T42, T43, and T44 in the first data selection circuits are sequentially turned off via the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0116] When one pixel island corresponds to four viewpoints, that is, each row in the pixel island is integrated with four subpixels for display. In some cases, as shown in FIG. 17, the i-th viewpoint Pi may correspond to R4i-3 to R4i, G4i-3 to G4i, and B4i-3 to B4i in the first pixel island 22, where i is a positive integer less than or equal to 4. In a specific embodiment, a data signal corresponding to the viewpoint Pi is sequentially supplied to Di, which controls the third transistors T31, T32, T33, and T34 in the first data selection circuit to be sequentially turned on via the first data selection control lines MUX1, MUX3, MUX5, and MUX7, and controls the fourth transistors T41, T42, T43, and T44 in the first data selection circuit to be sequentially turned off via the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0117] In some cases, for example, when the user's eyes move and the subpixel corresponding to the viewpoint translates to the right in Figure 17, when translated by one subpixel, each subpixel corresponding to the viewpoint in the user's gaze area will be as follows, as shown in Figure 18: the first viewpoint P1 corresponds to R2 to R5, G2 to G5, and B2 to B5 in the first pixel island 22, the second viewpoint P2 corresponds to R6 to R9, G6 to G9, and B6 to B9 in the first pixel island 22, the third viewpoint P3 corresponds to R10 to R13, G10 to G13, and B10 to B13 in the first pixel island 22, and the fourth viewpoint P4 corresponds to R14 to R16, G14 to G16, and B14 to B16 in the first pixel island 22 and R1, G1, and B1 in the second pixel island 23. Specifically, the d4 data signal is input to D0, the d1 data signal is input to D1, the d2 data signal is input to D2, the d3 data signal is input to D3, and the d4 data signal is input to D4. A first data selection control signal is simultaneously supplied to MUX2, MUX3, MUX5, and MUX7, controlling the simultaneous on-state of T41, T32, T33, and T34 in each first data selection circuit. A second data selection control signal is simultaneously supplied to MUX1, MUX4, MUX6, and MUX8, controlling the off-state of T31, T42, T43, and T44 in each first data selection circuit.

[0118] In some cases, for example, when the user's eyes are moved so that the viewpoint-corresponding subpixels are again translated by one position to the right in Figure 18, the viewpoint-corresponding subpixels of the user's gaze area will be as shown in Figure 19, with the first viewpoint P1 corresponding to R3 to R6, G3 to G6, and B3 to B6 in the first pixel island 22, the second viewpoint P2 corresponding to R7 to R10, G7 to G10, and B7 to B10 in the first pixel island 22, the third viewpoint P3 corresponding to R11 to R14, G11 to G14, and B11 to B14 in the first pixel island 22, and the fourth viewpoint P4 corresponding to R15 to R16, G15 to G16, and B15 to B16 in the first pixel island 22 and R1, R2, G1, G2, B1, and B2 in the second pixel island 23. Specifically, the d4 data signal is input to D0, the d1 data signal is input to D1, the d2 data signal is input to D2, the d3 data signal is input to D3, and the d4 data signal is input to D4. A first data selection control signal is simultaneously supplied to MUX2, MUX4, MUX5, and MUX7, controlling the simultaneous on-state of T41, T42, T33, and T34 in each first data selection circuit. A second data selection control signal is simultaneously supplied to MUX1, MUX3, MUX6, and MUX8, controlling the off-state of T31, T32, T43, and T44 in each first data selection circuit.

[0119] Alternatively, in some embodiments, one multiplexer 16 has f switch circuits 20, as shown in Figure 12. In a specific embodiment, when the first data selection circuit 15 includes two multiplexers, the first multiplexer 18 includes f first switching circuits 22, as shown in Figure 12. The second multiplexer 19 includes f second switching circuits 24.

[0120] In the same first data selection circuit 15, the control electrodes of different switching circuits 20 are electrically connected to different first data selection control lines MUX, the input terminals of different first switching circuits 22 are electrically connected to the same first data input line D, the input terminals of different second switching circuits 24 are electrically connected to the same first data input line D, the output terminals of different first switching circuits 22 are electrically connected to different data lines 3, the output terminals of different second switching circuits 24 are electrically connected to different data lines 3, and the output terminals of the i-th first switching circuit 22 and the i-th second switching circuit 24 are electrically connected to the same data line 3.

[0121] 12, the i-th first switching circuits 22 in different first data selection circuits 15 are electrically connected to the same first data selection control line MUX, and the i-th second switching circuits 24 in different first data selection circuits 15 are electrically connected to the same first data selection control line MUX. That is, the display panel includes 2f first data selection control lines MUX.

[0122] In some embodiments, as shown in FIG. 13, each switching circuit 20 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0123] A control electrode of the fifth transistor T5 is electrically connected to the first data selection control line MUX, and a first electrode of the fifth transistor T5 and a first electrode of the sixth transistor T6 are electrically connected to the first data input line D. A second electrode of the fifth transistor T5 is electrically connected to a control electrode of the sixth transistor T6, a control electrode of the seventh transistor T7, and a first electrode of the first capacitor C1. A second electrode of the sixth transistor T6 and a second electrode of the seventh transistor T7 are electrically connected to the data line 3. A second electrode of the first capacitor C1 is grounded.

[0124] The display panel further includes a dummy signal line L0 electrically connected to the first electrode of the seventh transistor T7.

[0125] In a specific embodiment, the first electrode of the seventh transistor of each switching circuit is electrically connected to the same dummy signal line.

[0126] In a specific embodiment, the dummy signal lines have no signal input.

[0127] In a specific embodiment, one of the sixth transistor and the seventh transistor is an N-type transistor and the other is a P-type transistor, so that one of the sixth transistor and the seventh transistor is turned on and the other is turned off, thereby establishing electrical continuity between the first data input line and the data line, or between the data line and the dummy signal line.

[0128] When each switch circuit has the circuit configuration shown in FIG. 13, the corresponding timing chart is as shown in FIG. 14. Here, phase A1 is the display phase for one frame, phase A2 is the black insertion phase for one frame, and the signal transmitted from the first data input line D includes a gate level that determines which data line will be conductive with the first data input line for the next frame. For example, a signal is supplied to each first data selection control line MUX in FIG. 14 to scan each first data selection circuit row by row. In response to the signal transmitted from the first data input line D, as shown in FIG. 15, when the switch circuit electrically connected to MUX4 is turned on, i.e., the second data line da2 of the h data lines corresponding to each pixel island is turned on, the h data line da2 corresponding to each pixel island transmits a grayscale signal in the next frame, and the remaining data lines da1, da3, through dah of the h data lines corresponding to each pixel island transmit DC signals. Controlling the first data selection circuit with the first data input control line according to the timing shown in FIG. 14 makes the charging sampling time constant, thereby enabling system resource conservation. In FIG. 14, only the signals of the first data selection control lines MUX1 to MUX4 will be explained schematically.

[0129] Next, an example of a display panel provided in an embodiment of the present invention, as shown in Figure 12, will be described, in which each subpixel group is composed of four subpixels. In a specific embodiment, as shown in Figure 12, the first multiplexer 18 includes four first switch circuits 22, and the second multiplexer 19 includes four second switch circuits 24. The display panel includes eight first data selection control lines MUX, which are named MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8, respectively.

[0130] Here, the control terminal of the fifth transistor T5 in the first first switching circuit 22 in each first data selection circuit 15 is electrically connected to MUX1, the control terminal of the first second switching circuit 24 in each first data selection circuit 15 is electrically connected to MUX2, the control terminal of the fifth transistor T5 in the second first switching circuit 22 in each first data selection circuit 15 is electrically connected to MUX3, the control terminal of the fifth transistor T5 in the second second switching circuit 24 in each first data selection circuit 15 is electrically connected to MUX4, The control terminal of the fifth transistor T5 in the third first switching circuit 22 in each first data selection circuit 15 is electrically connected to MUX5, the control terminal of the fifth transistor T5 in the third second switching circuit 24 in each first data selection circuit 15 is electrically connected to MUX6, the control terminal of the fifth transistor T5 in the fourth first switching circuit 22 in each first data selection circuit 15 is electrically connected to MUX7, and the control terminal of the fifth transistor T5 in the fourth second switching circuit 24 in each first data selection circuit 15 is electrically connected to MUX8.

[0131] In each first data selection circuit 15, the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the first first switching circuit 22 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the first second switching circuit 24 are electrically connected to the same data line 3. The second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the second first switching circuit 22 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the second second switching circuit 24 are electrically connected to the same data line 3. The second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the third first switching circuit 22 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 in the third second switching circuit 24 are electrically connected to the same data line 3. The second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 in the fourth first switching circuit 22 and the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 in the fourth second switching circuit 24 are electrically connected to the same data line 3.

[0132] In each first data selection circuit 15, a first electrode of the fifth transistor T5 and a first electrode of the sixth transistor T6 in each first switching circuit 22 are electrically connected to the same first data input line D. A first electrode of the fifth transistor T5 and a first electrode of the sixth transistor T6 in each second switching circuit 24 are electrically connected to the same first data input line D.

[0133] When one pixel island corresponds to 16 viewpoints, each subpixel in the same row in each subpixel group within the pixel island may need to display different display information. For example, as shown in FIG. 16, the i-th viewpoint Pi corresponds to Ri, Gi, and Bi in the first pixel island 22, where i is a positive integer less than or equal to 16. Taking an example in which the first four first data selection circuits arranged from left to right in FIG. 12 are electrically connected to the first pixel island, in a specific embodiment, data signals including gate levels corresponding to the viewpoints Pi to P4i may be sequentially supplied to Di via the first data selection control lines MUX1, MUX3, MUX5, and MUX7 to sequentially turn on the fifth transistor T5 of each switch circuit 20 in the first data selection circuit, and the data signal including gate levels may sequentially turn on the sixth transistor T6 of each first switch circuit 22, and the seventh transistor T7 may be sequentially turned off. At the same time, it is possible to control the turning off of the fifth transistor T5 of each second switching circuit 24 by the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0134] When one pixel island corresponds to four viewpoints, that is, each row in the pixel island is integrated with four sub-pixels for display. In some cases, as shown in FIG. 17, the i-th viewpoint Pi corresponds to R4i-3 to R4i, G4i-3 to G4i, and B4i-3 to B4i in the first pixel island 22, where i is a positive integer less than or equal to 4. In a specific embodiment, data signals including gate levels corresponding to the viewpoint Pi are sequentially supplied to Di to control simultaneous on of the fifth transistors T5 in the first switch circuit via the first data selection control lines MUX1, MUX3, MUX5, and MUX7, and simultaneously control simultaneous on of the sixth transistors T6 in the switching circuit electrically connected to MUX1, MUX3, MUX5, and MUX7 under the control of the data signals including gate levels transmitted via the first data input line. The seventh transistor T7 may be simultaneously turned on and the fifth transistor T5 of each second switching circuit 24 may be turned off via the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0135] In some cases, when the user's eyes move and the subpixel corresponding to the viewpoint is translated to the right in Figure 17, translating one subpixel will result in the subpixel corresponding to the user's gaze area viewpoint being displayed as shown in Figure 18. Specifically, a d4 data signal including a gate level is input to D0, a d1 data signal including a gate level is input to D1, a d2 data signal including a gate level is input to D2, a d3 data signal including a gate level is input to D3, and a d4 data signal including a gate level is input to D4. In order to simultaneously turn on the fifth transistor T5 in the switching circuit electrically connected to MUX2, MUX3, MUX5, and MUX7, a first data selection control signal is supplied to MUX2, MUX3, MUX5, and MUX7, and a sixth transistor T6 in the switching circuit electrically connected to MUX2, MUX3, MUX5, and MUX7 is simultaneously turned on by controlling the data signal including the gate level. The second data selection control signal is simultaneously supplied to MUX1, MUX4, MUX6, and MUX8 to turn off the fifth transistor T5 in the switching circuit electrically connected to MUX1, MUX4, MUX6, and MUX8.

[0136] In some cases, for example, when the user's eyes continue to move so that the subpixel corresponding to the viewpoint translates again by one position to the right in Fig. 18, each subpixel corresponding to the user's gaze area viewpoint is shifted as shown in Fig. 19, specifically, a data signal including a gate level is input to d4, a d1 data signal including a gate level is input to D1, a d2 data signal including a gate level is input to D2, a d3 data signal including a gate level is input to D3, and a d4 data signal including a gate level is input to D4. In order to simultaneously turn on the fifth transistor T5 in the switching circuit electrically connected to MUX2, MUX4, MUX5, and MUX7, a first data selection control signal is supplied to MUX2, MUX4, MUX5, and MUX7, and a sixth transistor T6 in the switching circuit electrically connected to MUX2, MUX4, MUX5, and MUX7 is simultaneously turned on by controlling the data signal including the gate level. The second data selection control signal is simultaneously supplied to MUX1, MUX3, MUX6, and MUX8 to turn off the fifth transistor T55 in the switching circuit electrically connected to MUX1, MUX3, MUX6, and MUX8.

[0137] In a specific embodiment, the first, second, third, fourth, fifth, sixth, and seventh transistors may each be a metal-oxide-semiconductor field-effect transistor (MOS), a complementary metal-oxide-semiconductor transistor (CMOS), or a thin film transistor (TFT).

[0138] As shown in the figure, the display device provided by an embodiment of the present invention includes a display panel provided by an embodiment of the present invention, a cylindrical lens structure located on the light-emitting side of the display panel, and a controller connected to the display panel and configured to provide independent drive signals to each control area.

[0139] The cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array.

[0140] Based on the same inventive idea, an embodiment of the present invention further provides a display device, as shown in Figure 20. The display device includes a display panel 51 provided by an embodiment of the present invention and a cylindrical lens structure 52 located on the light-emitting side of the display panel 51.

[0141] The cylindrical lens structure 52 includes a plurality of cylindrical lenses arranged in an array. A controller (not shown) connects to the display panel and is configured to provide independent drive signals to each control area.

[0142] In some embodiments, a display device is provided as shown in Figure 20. The display device includes a light-transmitting spacer layer 53 located between a display panel 51 and a cylindrical lens structure 52, and a flat layer 54 located on the side of the cylindrical lens structure 52 remote from the light-transmitting spacer layer 53.

[0143] In some embodiments, when the display panel is a liquid crystal display panel, the display device further comprises a backlight module, for example located on the side of the display panel remote from the cylindrical lens structure.

[0144] Some embodiments further include an eye-tracking system for determining in real time the user's eye gaze area at the display device.

[0145] In a specific embodiment, for areas requiring refresh during image display, a normal scan signal is input to the scan line corresponding to the pixel island via a drive signal drive control circuit supplied from the controller. For areas not requiring refresh, a fixed potential signal transmitted via a fixed potential line is input to the scan line corresponding to the pixel island via a drive signal drive control circuit supplied from the controller, thereby enabling pixel islands and reducing power consumption of the display device. Furthermore, by supplying signals corresponding to the first data selection control line and the first data input line via the controller, it is possible to control the independent display of subpixels of each pixel island in areas requiring high resolution display and to control the integrated display of multiple subpixels in areas requiring low resolution display, thereby further reducing power consumption of the display device. In a specific embodiment, for example, the area of ​​focus of the human eye corresponds to an area displayed at a high refresh rate and high resolution, and the area not being viewed corresponds to an area displayed at a low refresh rate and low resolution.

[0146] In a specific embodiment, subpixel subdivision is performed within a pixel island (a single pixel that can be displayed as a two-dimensional image (2D)), allowing the same resolution as 2D display to be maintained in three-dimensional image (3D) display mode. By combining eye-tracking, a wide-angle, multi-viewpoint display is possible, enabling a 3D display with a higher pixel density (PPI), increasing the amount of information, reducing color crosstalk between adjacent viewpoints, and improving the user experience and reducing glare when viewing a stereoscopic image. When a cylindrical lens array is provided in a display device, the cylindrical lens array modulates the light field not only of the subpixels within the pixel island but also of the light beam emitted from the pixel island, allowing the light beam emitted from the pixel island to form multiple viewpoints, enabling a light field 3D display.

[0147] In some embodiments, each pixel island corresponds to M viewpoints and each pixel island corresponds to N cylindrical lenses, where M, N are all positive integers and M>N, M / N is a non-integer.

[0148] The diameter P of the cylindrical lens can achieve a resolution smaller than that of the retina at the clear viewing distance relative to the resolution of the human eye, meeting the needs of a single pupil and the need to simultaneously receive at least two viewpoints. It can also reduce the impact of fixed lenses on 2D display in the near field of view while solving the problems of visual fatigue and dizziness caused by convergence collision. That is, P≦L×tan(1 / 60×3.1415926 / 180), where L is the clear viewing distance, typically 250 mm (mm). In a specific embodiment, each subpixel row within a pixel island includes h subpixels, and each pixel island can render h corresponding 3D viewpoints in a multi-tone manner. The width P of the pixel island in the cylindrical lens array direction is set to achieve Retina resolution at the optimal 3D viewing distance. That is, P≦L×tan(1 / 60×3.1415926 / 180), which ensures 3D angular resolution of the retina.

[0149] In a specific embodiment, in the display device provided by the embodiment of the present invention, the lens unit can be used to divide a dot corresponding to a pixel island N times, where M / N is a non-integer, and the diameter of each lens is D=N×(L+H), where H is the distance between the display panel and the cylindrical lens.

[0150] In a specific embodiment, the subpixels within a pixel island may be configured to emit light continuously, and if all the subpixels in a row arranged in a first direction are the same color, a continuous light-emitting surface may be formed in the first direction, thereby realizing a multi-viewpoint light field display while reducing crosstalk between viewpoints and eliminating moiré in 3D displays.

[0151] In the first embodiment, in a subpixel division unit that emits light continuously, the arrangement and spatial and temporal distribution of subpixels in a row within a pixel island are shown in FIG. 21. For one subpixel row within the pixel island, two of the three cylindrical lenses correspond to five viewpoints, and the other cylindrical lens corresponds to six viewpoints. As can be seen from FIG. 21, when M / N is a non-integer, the corresponding viewpoints of each lens do not completely overlap spatially, thereby avoiding crosstalk between viewpoints. Taking viewpoints 1, 2, and 3 as an example, viewpoints 2 and 3 can compensate for the non-emission of viewpoint 1 by misaligning the lenses, thereby avoiding moire.

[0152] Of course, the subpixels within a pixel island may emit light discontinuously. For example, as shown in Figures 4 and 5, the area between adjacent subpixels in the first direction X corresponds to a light-blocking area.

[0153] In some embodiments, each row of subpixels within a pixel island includes a shaded region, and the ratio of the area of ​​the subpixel to the area of ​​the shaded region is X, where X=N−1.

[0154] When the pixel island has 16 subpixels (M = h = 16) and the ratio of subpixels to light-blocking areas is 2:1 (X = 2, N = 3), the distribution of subpixels in one row within the pixel island and their spatial and temporal distribution are shown in Figure 23. For one subpixel row in the pixel island, two of the three cylindrical lenses correspond to five viewpoints, and the other corresponds to six viewpoints. As can be seen from Figure 22, when M / N is a non-integer, the corresponding viewpoints of each lens do not completely overlap in space, thereby avoiding crosstalk between viewpoints. Taking viewpoints 1, 2, and 3 as an example, as shown in Figure 22, the spatial positions of viewpoint 2 on the third lens and viewpoint 1 on the first lens do not completely overlap, and viewpoints 2 and 3 do not completely overlap in space. In the case of two and three viewpoints, stitching compensates for the absence of light emission from viewpoint 1 due to misalignment with the lenses, thereby avoiding moiré.

[0155] Furthermore, the development of 3D display technology is largely limited by the capabilities of display devices and optical devices. Therefore, conventional naked-eye 3D displays cannot be viewed freely, and the viewing range is limited. In particular, the viewing area and viewing range of light field displays are small, making it difficult to observe the light field at close range, especially in medium and large display products. Moreover, the balance between naked-eye 3D resolution and viewpoint continuity is poor, and there is severe crosstalk between viewpoints, resulting in monocular viewpoint 3D maps being relatively blurry and having low contrast.

[0156] In some embodiments, the diameter D of the cylindrical lens and the width P of the pixel island in the cylindrical lens array direction further satisfy the following relationship: D / P=L / (L+H).

[0157] In some embodiments, the width Q of the independent visibility areas for the left and right vision of the user satisfies the following condition: Q=E / (2A+1); where E is the user pupil distance, and A is the number of cylindrical lenses between the pixel islands corresponding to the left and right eye viewpoints.

[0158] In some embodiments, the width Q of the independent visibility areas for the left and right eyes of the user further satisfies the following condition: Q=he / 2M; Here, e is the pupil size of the user. The normal pupil size e is approximately 3 mm to 5 mm.

[0159] In some embodiments, each subpixel row within a pixel island has h subpixels of the same color. When a single-pupil two-view system is used, i.e., h = 16, M = 2, and e = 5 mm, and one viewpoint corresponds to one cylindrical lens, Q = 125 mm. The viewpoint pixels for the left and right eyes can project independent viewing areas Q for each eye via spacer lenses. A specific optical path is shown in FIG. 23. Here, the subpixels within a pixel island are divided into 16 subpixels, with 8 subpixels corresponding to each eye. In the figure, black subpixels correspond to the left eye, and white subpixels correspond to the right eye. Images for each eye are projected via two lenses separated by two lenses. As shown in FIG. 23, the central area between the left and right eyes is 4Q, i.e., the central area between the left and right eyes is 60 mm.

[0160] In some embodiments, each subpixel row within a pixel island has h subpixels of the same color. When a single pupil 4-view is used, i.e., h = 16, M = 4, and e = 5 mm, Q = 10 mm, and the viewpoint pixels for the left and right eyes can project independent viewing areas Q for each eye via spacer lenses. A specific optical path is shown in Figure 24. Each eye corresponds to eight subpixels. In the figure, black subpixels correspond to the left eye, and white subpixels correspond to the right eye. Images for each eye are projected to the left and right eyes via two lenses separated by two lenses. As shown in Figure 24, the central area between the left and right eyes is 6Q, i.e., the central area between the left and right eyes is 60 mm.

[0161] In other words, we provide a display device that realizes a light field display with a central region between the left and right eyes of approximately 60 mm, even when one pixel island corresponds to multiple viewpoints. This generates a light field image with multiple depths when viewed in the central region, enabling monocular focus adjustment, and realizes ultra-multi-viewpoint 3D with low crosstalk outside the central region, enabling 3D information reproduction from different angles. In a specific embodiment, the viewing position of the human eye is fed back in combination with an eye tracking system, and the panel drive is adjusted according to the eye coordinates of the tracking system received by the feedback unit, thereby adjusting the image rendering mode to realize a central region light field and low-crosstalk ultra-multi-viewpoint 3D display outside the central region.

[0162] In some embodiments, the controller 40 includes a data analysis circuit 36 ​​that performs data analysis on the image to be displayed to obtain image analysis data, a data placement circuit 37 that generates data drive signals corresponding to the control areas of the display panel based on the current display mode and the image analysis data, and a timing control circuit 38 that generates gate drive signals for the gate drive circuit in accordance with the current display mode and the gaze area and non-gaze area of ​​the display panel, as shown in Figures 25 and 27.

[0163] In a specific embodiment, the controller further includes a display mode setting circuit 39 that determines the current display mode based on the image analysis data.

[0164] In a specific embodiment, the display mode may be, for example, 2D display or 3D display, which includes light field display and super multi-view light field display.

[0165] In some embodiments, the controller is a Field Programmable Gate Array (FPGA) chip, as shown in FIG.

[0166] In a specific embodiment, the output terminal of the timing control circuit of the FPGA is electrically connected to the gate driving circuit of the display panel, and the data allocation circuit of the FPGA may, for example, supply a signal corresponding to the first data input line or the first data selection control line of the display panel.

[0167] Alternatively, in some embodiments, the controller is a Timing Controller (TCON), as shown in FIG.

[0168] In a specific embodiment, the display mode setting circuit of the TCON performs coordinate analysis and image processing based on the image analysis data, and the data placement circuit decompresses the processed data and places the data driving signals corresponding to the control areas of the display panel.

[0169] In a specific embodiment, the output terminal of the timing control circuit of the TCON is electrically connected to the gate driving circuit of the display panel, and the data arrangement circuit of the TCON may, for example, provide corresponding signals to the first data input line and the first data selection control line of the display panel.

[0170] In a specific embodiment, as shown in Figure 27, the controller can first drive the refresh focus area 41 (in this case, the non-focus areas are not refreshed) and then drive the non-focus areas 42 on both sides of the refresh focus area. The image coordinates, display mode, and lens data are coded in one display line, the focus area resolution is uncompressed, and the non-focus area resolution is compressed by 1 / 4 in horizontal pixels and vertical pixels, and the three are then sequentially linked and transmitted from top to bottom. In this method, the focus area and non-focus areas are driven independently, and the data compression ratio is up to 1:10.7.

[0171] Taking a 16-view multi-view light field 3D display as an example, the resolution of the non-focused area is compressed by 1 / 4, that is, the system compresses a 4x4 pixel island into one pixel island and transmits it to the controller. The controller copies the island data of the pixel island to three adjacent pixel islands, and four rows of pixel islands in the second direction are simultaneously turned on, so that the 4x4 pixel islands in the non-focused area write the same single pixel island data.

[0172] In a specific embodiment, a controller can realize row driving, column driving, and control region selection range driving for 2D display and multi-viewpoint light field 3D display. Here, line driving may be controlled to turn on the region of interest one row at a time and simultaneously turn on multiple lines of the non-interest region. Column driving is controlled by controlling a first data selection circuit to simultaneously turn on multiple columns or shift-on multiple columns. Control region selection range driving is controlled by a control circuit. In a typical light field 3D display, a controller can be used to realize row driving, column driving, and control region selection range driving. Here, row driving may be controlled to turn on the region of interest one row at a time and simultaneously turn on multiple lines of the non-interest region. Column driving is controlled by controlling the first data selection circuit to turn on each column. Control region selection range driving is controlled by a control circuit. In a specific embodiment, a controller can adjust the driving method in real time.

[0173] In some embodiments, the human eye tracking system includes an image acquisition circuit, a camera normalization circuit, a camera time division partition control circuit, a face detection circuit, an image coordinate system conversion circuit, a pupil detection circuit, a spatial coordinate calculation circuit, and a spatial gaze tracking circuit.

[0174] The image capture circuit includes a plurality of first cameras and at least one second camera, the resolution of the first cameras being greater than the resolution of the second cameras, the first cameras being configured to capture a pupil image of the user, and the second camera being configured to capture a facial image of the user.

[0175] The camera standardization circuit is configured to standardize the first camera and the second camera to obtain an internal parameter matrix and an external parameter matrix of the first camera and the second camera, and the camera time division partition control circuit is configured to control the shooting timing of the multiple first cameras so that the multiple first cameras alternately capture images.

[0176] The face detection circuit is configured to search for a face frame in the image captured by the second camera, detect facial feature points, obtain a human eye area within the face frame, and further obtain a spatial coordinate transformation matrix of the human eye area according to a mapping relationship between the facial feature points and a standard human model. The image coordinate system transformation circuit is configured to transform the face image coordinate system into a cylindrical pupil image coordinate system or transform the pupil coordinate system into the face image coordinate system.

[0177] The pupil detection circuit is configured to calculate pupil coordinates in the image captured by the first camera, convert the human eye area coordinates obtained by the face detection circuit into a pupil image coordinate system using a coordinate conversion circuit, obtain the human eye area on the pupil image, detect the pupil within the human eye area, and obtain the pupil coordinates in the pupil image coordinate system.

[0178] The spatial coordinate calculation circuit is configured to convert pupil coordinates into a face image coordinate system and calculate pupil coordinates in three-dimensional space using the spatial coordinate transformation matrix obtained by the face detection circuit. The spatial gaze tracking circuit is configured to determine eyeball center coordinates using pupil coordinates and a predetermined human eye model, calculate the direction vector of the pupil coordinates and eyeball center coordinates as a line vector, obtain the line of sight intersection between the human eye and the display panel based on the distance from the human eye to the display panel and the plane equation on which the display panel exists, and obtain the human eye gaze point coordinates on the display panel based on the line of sight intersection.

[0179] The human eye tracking system for a display device provided by the present invention combines multiple cameras to achieve variable-rate spatial pupil detection and 3D coordinate calculation. The image acquisition circuit includes multiple cameras with different resolutions, and by using a face detection algorithm, a pupil detection algorithm, and a coordinate system transformation algorithm, it can accurately and quickly obtain pupil coordinates in 3D space. This solves the problems of conventional SLR cameras, such as low pupil detection frame rate, poor detection accuracy, and small detection area. This improves detection accuracy and improves the accuracy of gaze area determination.

[0180] In a specific embodiment, the image acquisition circuit includes, for example, three first cameras and one second camera, where the first camera may be, for example, an infrared (IR) camera and the second camera may be, for example, a red, green, and blue (RGB) camera. For example, the RGB camera has an 80° field of view (FOV), a 120 frame rate per second (fps), and a 640 x 480 resolution. The three IR cameras have a 60° field of view, a 30° field of view, a 1280 x 960 resolution, and a 30 fps frame rate. Four infrared light-emitting diode (IR) light sources may be provided around each IR camera.

[0181] In a specific embodiment, a camera time division partition control circuit controls the shooting timing of multiple first cameras so that the multiple first cameras capture images alternately and the eye tracking system outputs spatial pupil coordinates continuously and at equal intervals.

[0182] In some embodiments, as shown in FIG. 28, the camera 43 included in the eye tracking system is located above the display device.

[0183] In some embodiments, the display device further comprises an image rendering system 44 electrically connected to the controller 40 and the display panel 51, as shown in FIG.

[0184] In some embodiments, the image rendering system includes a coordinate extraction circuit, a lens alignment detection circuit, and an image rendering circuit. The coordinate extraction circuit is configured to determine three-dimensional spatial coordinates of a human eye relative to a display panel based on a position of the human eye's line of sight on a display panel in a display device determined by an eye tracking system. The lens alignment detection circuit is configured to obtain a bonding error of a cylindrical lens, adjust bonding parameters of the cylindrical lens based on the bonding error, and obtain a viewpoint crosstalk curve.

[0185] The image rendering circuit is configured to generate a multi-viewpoint initial image from an image to be displayed, and to optimize the multi-viewpoint initial image based on a human eye position, stitching detection parameters, and a crosstalk curve, and to obtain the optimized multi-viewpoint image as an image to be displayed.

[0186] The display device provided by the embodiment of the present invention includes an eye tracking system with an image rendering system for determining the three-dimensional spatial coordinates of the human eye relative to the display panel. A lens alignment detection circuit is provided to obtain alignment errors and crosstalk based on the visual lens alignment detection of the display device, and provide and optimize corresponding parameters for subsequent image rendering, thereby making the image rendering more accurate and improving the display effect.

[0187] In some embodiments, the image rendering system further comprises a subpixel mapping and control circuit that determines a mapping between 3D image subpixels and controllers and a control rule for the image to be displayed optimized by the image rendering circuit.

[0188] In a specific embodiment, the operation principle of the lens stitching detection circuit is to first design the lens stitching parameters based on the raster stitching theory, then determine the display mode, and then initialize the camera shooting position, and then determine the lens stitching parameters and the viewpoint blowing curve simultaneously.

[0189] Here, the determination of the lens bonding parameters involves repeating the following procedure until the analysis result of the image analysis meets the preset requirements: adjusting the bonding parameters based on the camera-captured results, capturing an image again using the camera, and performing image analysis including brightness uniformity analysis; and if the analysis result meets the preset requirements, determining the current bonding parameters as the final lens bonding parameters.

[0190] Here, the determination of the viewpoint crosstalk curve involves repeating the following steps until the analysis result of the image analysis meets the preset requirements: when a different viewpoint view is displayed, an image is captured by a camera, and image analysis including crosstalk curve fitting is performed; and if the analysis result meets the preset requirements, the currently fitted crosstalk curve is set as the viewpoint crosstalk curve.

[0191] In a specific embodiment, the following perspective crosstalk surface equation is used to perform crosstalk curve fitting:

[0192]

number

[0193] Here, x is the position coordinate of the sub-pixel in the first direction, and y is the position coordinate of the sub-pixel in the second direction.

[0194] If the control unit determines that the display mode is 3D display, it is necessary to perform 3D image rendering using the image rendering system. If the control unit determines that the display mode is 2D display, image rendering is not necessary.

[0195] A display device according to an embodiment of the present invention may be any product or component having a display function, such as a television or a monitor. Other essential components of a display device should be understood by those skilled in the art, and will not be mentioned here and may be considered a limitation of the present invention. This embodiment of the display device may refer to the above-described embodiment of the display panel, and overlapping parts will be omitted.

[0196] Based on the same inventive idea, an embodiment of the present invention provides a driving method for a display device, as shown in FIG. 29, which includes the following steps: S101: Determine the user's gaze area and non-gaze area on the display device in real time. S102: independently drive a control area corresponding to a gaze area to display an image at a first resolution, and drive a control area corresponding to a non-gaze area to display an image at a second resolution, where the first resolution is higher than the second resolution.

[0197] In some embodiments, in step S101, the user's gaze area and non-gaze area on the display device are determined in real time, specifically, the gaze area of ​​the user's eyes on the display device is obtained using an eye tracking system, and areas other than the gaze area on the display device are determined as non-gaze areas.

[0198] In some embodiments, acquiring the gaze area of ​​the user's eye on the display device with the eye tracking system specifically includes: a first camera in the controlled eye tracking system alternately capturing a pupil image of the user; a second camera in the controlled eye tracking system capturing a face image of the user; searching for a face frame in the image captured by the second camera; detecting face feature points; acquiring the eye area within the face frame; and, according to the mapping relationship between the face feature points and the standard human model, acquiring a spatial coordinate transformation matrix of the eye area; transforming the face image coordinate system into a cylindrical pupil image coordinate system, or transforming the pupil coordinate system into the face image coordinate system; calculating the pupil coordinates in the image captured by the first camera; and translating the coordinates of the eye area to the pupil. The system converts the image coordinate system to an image coordinate system, obtains the human eye area on the pupil image, detects the pupil in the human eye area on the pupil image, obtains the pupil coordinate in the pupil image coordinate system, converts the pupil coordinate into a face image coordinate system, calculates a spatial coordinate transformation matrix to obtain the pupil coordinate in three-dimensional space, determines the eyeball center coordinate using the pupil coordinate and a predetermined human eye model, calculates the direction vector of the pupil coordinate and the eyeball center coordinate as a line vector, obtains the line of sight intersection between the human eye and the display panel based on the distance from the human eye to the display panel and the plane equation on which the display panel exists, obtains the human eye gaze point coordinate on the display panel based on the line of sight intersection, and determines the area on the display panel where the human eye gaze point coordinate exists as the gaze area.

[0199] In a specific embodiment, for example, the timing of capturing images by the multiple first cameras may be controlled by a camera time division partition control circuit simultaneously with capturing images by the second camera, so that the multiple first cameras alternately capture images.

[0200] In some embodiments, the control region corresponding to the attention region is independently driven to display an image at a first resolution, and the control region corresponding to the non-attention region is driven to display an image at a second resolution. Specifically, based on the display mode, the attention region, and the non-attention region, display information for each sub-pixel in the pixel island of the control region corresponding to the attention region and display information for each sub-pixel in the pixel island of the control region corresponding to the non-attention region are determined. Based on the display information, a data signal corresponding to the display information is supplied to the first data input line, and a first data selection control signal is supplied to the first data selection control line. The data signal supplied from the first data write line is supplied to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0201] In some embodiments, when the multiplexer has f switching transistors, and when each subpixel in one subpixel row of a pixel island corresponds to a viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, where the first multiplexer includes f third transistors and the second multiplexer includes f fourth transistors, supplies a first data selection control signal to the first data selection control line, and supplies a data signal supplied from the first data write line to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0202] Specifically, to control the f third transistors in each first data selection circuit to be sequentially turned on, first data selection control signals are supplied to a plurality of first data selection control lines electrically connected to each third transistor, data signals from a first data input line electrically connected to first electrodes of the f third transistors are transmitted to data lines electrically connected to second electrodes of the f third transistors, and simultaneously, second data selection control signals are supplied to a plurality of first data selection control lines electrically connected to each fourth transistor, thereby controlling the f fourth transistors in each first data selection circuit to be sequentially turned off.

[0203] In some embodiments, when the third transistor of the third transistor and the fourth transistor of the fourth transistor are the same type of transistor, the first data select control signal that controls the select switch to be on is a high-level signal, the second data select control signal that controls the select switch to be off is a low-level signal, or the first data select control signal that controls the select switch to be on is a low-level signal, or the first data select control signal that controls the select switch to be on is a low-level signal and the second data select control signal that controls the select switch to be off is a high-level signal.

[0204] In some embodiments, the subpixels in each row in a pixel island are divided into a subpixel groups, where a=h / f, and each subpixel group includes f adjacent subpixels. When the f adjacent subpixels in each subpixel row in the pixel island correspond to one viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, where the first multiplexer includes f third transistors and the second multiplexer includes f fourth transistors, supplies a first data selection control signal to a first data selection control line, and supplies a data signal provided from the first data write line to a data line corresponding to the first data selection circuit via the first data selection circuit.

[0205] Specifically, when the display information of each subpixel in each subpixel group is the same, first data selection control signals are supplied to f first data selection control lines electrically connected to each third transistor to control simultaneous on of the f third transistors in each first data selection circuit, and data signals of the first data input line electrically connected to the first electrodes of the f third transistors are transmitted to data lines electrically connected to the second electrodes of the f third transistors. Also, second data selection control signals are supplied to f first data selection control lines electrically connected to each fourth transistor to control off of the f fourth transistors in each first data selection circuit.

[0206] In some embodiments, the subpixels in each row in a pixel island are divided into a subpixel groups, where a=h / f, and each subpixel group includes f adjacent subpixels. When the f adjacent subpixels in each subpixel row in the pixel island correspond to one viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, where the first multiplexer includes f third transistors and the second multiplexer includes f fourth transistors, supplies a first data selection control signal to a first data selection control line, and supplies a data signal provided from the first data write line to a data line corresponding to the first data selection circuit via the first data selection circuit.

[0207] Furthermore, in some subpixel groups, when the display information of the 1st to g-1th subpixels is the same, the display information of the g-1th to fth subpixels is the same, and the display information of the g-1th subpixel is different from the display information of the gth subpixel, a first data selection control signal is supplied to a first data selection control line electrically connected to the 1st to g-1th fourth transistors and the gth to fth third transistors, thereby controlling the 1st to g-1th fourth transistors and the gth to fth third transistors in each first data selection circuit to be turned on simultaneously. A data signal of a first data input line electrically connected to the first electrodes of the 1st to g-1th fourth transistors and the first electrodes of the gth to fth third transistors is transmitted to a data line electrically connected to the second electrodes of the 1st to g-1th fourth transistors and the second electrodes of the gth to fth third transistors.

[0208] At the same time, a second data selection control signal is supplied to a first data selection control line electrically connected to the 1st to g-1th third transistors and the gth to fth fourth transistors to control turning off the 1st to g-1th third transistors and the gth to fth fourth transistors in each first data selection circuit.

[0209] The driving method of the display device provided by the embodiment of the present invention not only enables the display information of the sub-pixels to smoothly transition in accordance with the movement of the human eye when the position of the human eye changes, but also improves the display effect and the user experience.

[0210] When the multiplexer does not include f switching circuits, in some embodiments, the first data input line is supplied with a data signal corresponding to the display information, specifically, the first data input line is supplied with a data signal corresponding to the display information and including a gate level.

[0211] In some embodiments, when each subpixel in one subpixel row of a pixel island corresponds to a viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits, and supplies a first data selection control signal to the first data selection control line, and supplies a data signal supplied from the first data write line to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0212] Specifically, a first data selection control signal is supplied to a plurality of first data selection control lines electrically connected to each first switching circuit, thereby controlling to sequentially turn on the fifth transistors in the f first switching circuits in each first data selection circuit. Under control of a data signal including a gate level, a data signal of the first data input line electrically connected to the f first switching circuits is transmitted to the data lines electrically connected to the f first switching circuits, and a second data selection control signal is supplied to a plurality of first data selection control lines electrically connected to each second switching circuit, thereby controlling to turn off the fifth transistors in the f second switching circuits in each first data selection circuit.

[0213] In some embodiments, the first data select control signal that controls turning on the fifth transistor in the switching circuit is a high-level signal and the second data select control signal that controls turning off the fifth transistor in the switching circuit is a low-level signal, or the first data select control signal that controls turning on the fifth transistor in the switching circuit is a low-level signal and the second data select control signal that controls turning off the fifth transistor in the switching circuit is a high-level signal.

[0214] In some embodiments, the subpixels in each row in the pixel island are divided into a subpixel groups, where a=h / f, and each subpixel group includes f adjacent subpixels. When the f adjacent subpixels in each subpixel row in the pixel island correspond to one viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits, and provides a first data selection control signal to the first data selection control line and provides a data signal provided from the first data write line to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0215] Specifically, when the display information of each subpixel in each subpixel group is the same, a first data selection control signal is supplied to f first data selection control lines electrically connected to each first switching circuit, controlling the fifth transistors in the f first switching circuits in each first data selection circuit to be simultaneously turned on. Under control of a data signal including a gate level, data signals from the first data input lines electrically connected to the f first switching circuits are transmitted to data lines electrically connected to the f first switching circuits, and a second data selection control signal is supplied to f first data selection control lines electrically connected to each second switching circuit, controlling the fifth transistors in the f second switching circuits in each first data selection circuit to be simultaneously turned off.

[0216] In some embodiments, the subpixels in each row in the pixel island are divided into a subpixel groups, where a=h / f, and each subpixel group includes f adjacent subpixels. When the f adjacent subpixels in each subpixel row in the pixel island correspond to one viewpoint, each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits, and provides a first data selection control signal to the first data selection control line and provides a data signal provided from the first data write line to the data line corresponding to the first data selection circuit via the first data selection circuit.

[0217] Furthermore, in some subpixel groups, if the display information of the 1st through g-1th subpixels is the same, the display information of the gth through fth subpixels is the same, and the display information of the g-1th subpixel is different from the display information of the gth subpixel, a first data selection control signal is supplied to a first data selection control line electrically connected to the 1st through g-1th second switching circuits and the gth through fth first switching circuits to simultaneously turn on the fifth transistors T5 of the 1st through g-1th second switching circuits and the gth through fth first switching circuits in each first data selection circuit. Under control of a data signal including a gate level, a data signal of the first data input line electrically connected to the 1st through g-1th second switching circuits and the gth through fth first switching circuits is transmitted to a data line electrically connected to the 1st through g-1th second switching circuits and the gth through fth first switching circuits.

[0218] At the same time, a second data selection control signal is supplied to a first data selection control line electrically connected to the 1st to g-1th first switching circuits and the gth to fth second switching circuits, to control the fifth transistor T5 in the 1st to g-1th first switching circuits and the fifth transistor T5 in the gth to fth second switching circuits in each first data selection circuit to be turned off.

[0219] In some embodiments, the attention area is independently driven to display an image at a first resolution, the non-attention area is driven to display an image at a second resolution, and gate drive signals are supplied to a gate drive circuit of the display panel via a controller of the display device to control a plurality of rows of pixel islands corresponding to the attention area to be turned on one by one, and to control F rows of pixel islands in the plurality of rows of pixel islands corresponding to the non-attention area to be turned on synchronously, where F is a positive integer and F is the ratio between the first resolution and the second resolution.

[0220] In some embodiments, as shown in FIG. 30, the gate drive circuit included in the display panel includes multiple gate drive groups, each gate drive group includes B gate drive subgroups, and each gate drive subgroup includes C shift registers, where B and C are integers greater than 1.

[0221] A gate driving signal is supplied to the gate driving circuit of the display panel via a controller of the display device, specifically, a clock control signal is supplied to the gate driving groups via the controller, and for each gate driving group, ON signals are sequentially input to the multiple shift registers in the gate driving subgroups in the order of the first to Bth gate driving subgroups.

[0222] In a specific embodiment, for example, when each subpixel row in a pixel island consists of 12 subpixels, one gate drive group includes, for example, three gate drive subgroups, and each gate drive subgroup includes four shift registers GOA (GOA), as shown in Figure 30. Here, the first gate drive subgroup includes GOA1, GOA4, GOA7, and GOA10, the second gate drive subgroup includes GOA2, GOA5, GOA8, and GOA11, and the third gate drive subgroup includes GOA3, GOA6, GOA9, and GOA12. In a specific embodiment, as shown in Figure 30, the first gate drive subgroup is electrically connected to eight constant signal lines CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. The on signal line STV is electrically connected to GOA1, GOA4, GOA7, and GOA10 in the first gate drive subgroup, i.e., the pixel islands corresponding to GOA1, GOA4, GOA7, and GOA10 are turned on row by row, followed by the pixel islands corresponding to GOA2, GOA5, GOA8, and GOA11, and then the pixel islands corresponding to GOA3, GOA6, GOA9, and GOA12, etc. This configuration can save system resources of the display device.

[0223] FIG. 31 is a timing chart for when the gate drive circuit turns on pixel islands row by row, and FIG. 32 is a timing chart for when the gate drive circuit turns on pixel islands two rows at a time.

[0224] In some embodiments, the driving method further includes driving the attention region to display images at a first refresh rate and driving the non-attention region to display images at a second refresh rate, where the first refresh rate is higher than the second refresh rate.

[0225] In some embodiments, the attention region is driven to display images at a first refresh rate and the non-attention region is driven to display images at a second refresh rate, where each subpixel in the attention region is driven to be refreshed Z times and each subpixel in the non-attention region is driven to be refreshed Y times, where Z and Y are positive integers and Z is greater than Y.

[0226] In some embodiments, each sub-pixel in the attention area is driven to perform refresh, specifically by driving each scan signal input line corresponding to the attention area to sequentially transmit an active level signal, controlling each control signal line to transmit a control signal, and Lines of force The signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-attention area, thereby driving each sub-pixel in the non-attention area to perform refresh.

[0227] Specifically, each scanning signal input line in the display panel is driven to sequentially transmit an active level signal, and when each subpixel row corresponding to the attention area is scanned, each control signal line is controlled to transmit a control signal, and a signal supplied from a fixed potential line is transmitted to the scanning line corresponding to the attention area, and the scanning signal input line is Lines of force The signal supplied from the is transmitted to the scanning line corresponding to the non-attention area.

[0228] In a specific embodiment, when the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line, each control signal line is controlled to transmit a control signal, and the scanning signal input is Lines of forceThe signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-attention area. Specifically, each control signal line in the attention area is driven to transmit a first control signal. Each control signal line in the non-attention area is driven to transmit a second control signal. This controls the first transistor in the attention area to be turned on and the second transistor to be turned off, and the first transistor in the non-attention area to be turned off and the second transistor to be turned on. Scanning signal input Lines of force A signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the control region via each first transistor in the control region, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-focus region via the second transistor in the non-focus region.

[0229] When each subpixel row corresponding to the attention area is scanned, each control signal line is controlled to transmit a control signal, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and a scanning signal input is performed. Lines of force The signal supplied from the scanning line corresponding to the non-attention area is transmitted to the scanning line corresponding to the non-attention area. Specifically, each control signal line of the driving attention area is driven to transmit a second control signal. Each control signal line of the non-attention area transmits a first control signal, and controls so that the first transistor of the attention area is turned off and the second transistor is turned on, and the first transistor of the non-attention area is turned on and the second transistor is turned off. Scanning signal input Lines of force A signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area via each first transistor in the non-control area, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area via the second transistor in the attention area.

[0230] In a specific embodiment, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first control signal is a low-level signal, and the second control signal is a high-level signal. When the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first control signal is a high-level signal and the second control signal is a low-level signal.

[0231] In a specific embodiment, when the control electrode of the first transistor is electrically connected to the first control signal line and the control electrode of the second transistor is electrically connected to the second control signal line, each control signal line is controlled to transmit a control signal, and the scanning signal input Lines of force The signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-attention area. Specifically, each first control signal line in the attention area is driven to transmit a first control signal, each second control signal line is driven to transmit a second control signal, each first control signal line in the non-attention area is driven to transmit a third control signal, and each second control signal line is driven to transmit a fourth control signal, so that the first transistor in the attention area is turned on and the second transistor is turned off, and the first transistor in the non-attention area is turned off and the second transistor is turned on. Lines of force A signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the control region via each first transistor in the control region, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the non-focus region via the second transistor in the non-focus region.

[0232] When each subpixel row corresponding to the attention area is scanned, each control signal line is controlled to transmit a control signal, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area, and a scanning signal input is performed. Lines of force The signal supplied from the scanning signal input is transmitted to the scanning line corresponding to the non-focused area. Specifically, each first control signal line in the focused area is driven to transmit a third control signal, each second control signal line is driven to transmit a fourth control signal, each first control signal line in the non-focused area is driven to transmit a first control signal, and each second control signal line is driven to transmit a second control signal, so that the first transistor in the focused area is turned off and the second transistor is turned on, and the first transistor in the non-focused area is turned on and the second transistor is turned off. Lines of forceA signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area via each first transistor in the non-control area, and a signal supplied from the fixed potential line is transmitted to the scanning line corresponding to the attention area via the second transistor in the attention area.

[0233] In some embodiments, when the first transistor and the second transistor are both P-type transistors, the first control signal and the fourth control signal are low-level signals, and the second control signal and the third control signal are high-level signals. When the first transistor and the second transistor are both N-type transistors, the first control signal and the fourth control signal are high-level signals and the second control signal and the third control signal are low-level signals. When the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first control signal and the second control signal are low-level signals. The third control signal and the fourth control signal are high-level signals; when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first control signal and the second control signal are high-level signals and the third control signal and the fourth control signal are low-level signals.

[0234] Based on the same inventive idea, as shown in FIG. 33, an embodiment of the present invention provides an image rendering method for a display device, including the following steps: S201: The position of the line of sight of the human eye on the display panel in the display device is determined, and the three-dimensional spatial coordinates of the human eye relative to the display panel are also determined. S202: A multi-viewpoint initial image is generated from the image to be displayed. S203: The alignment of the cylindrical lens array with respect to the display device is detected, and the alignment error of the cylindrical lens and the viewpoint crosstalk curve are obtained. S204: Optimize the initial multi-view images based on the human eye position, stitching detection parameters and crosstalk curves to obtain optimized multi-view images. S205: The optimized multi-view image is transmitted to the controller. The image rendering method for a display device provided by an embodiment of the present invention utilizes an image rendering system and an eye tracking system to determine the three-dimensional spatial coordinates of the human eye relative to the display panel. A lens alignment detection circuit obtains alignment errors and crosstalk based on the visual detection of the lens alignment of the display device, and provides appropriate parameters for subsequent image rendering to optimize the image rendering, thereby making the image rendering more accurate and improving the display effect.

[0235] As described above, in the display panel, display device, display device driving method, and display device image rendering method according to embodiments of the present invention, multiple pixel islands are divided into multiple control regions, and each control region is independently driven to emit light, thereby enabling the resolution and refresh rate of the display panel to be selectively controlled according to the display screen conditions. By selectively controlling the resolution of the display panel, the display panel can be divided into high-definition and low-definition regions, and the resolution of the high-definition region can be higher than that of the low-definition region, thereby improving the resolution of, for example, the region of human attention and improving the display effect. By selectively controlling the refresh rate of the display panel, the display panel can be divided into high-refresh rate and low-refresh rate regions, thereby reducing the power consumption of the display product.

[0236] Although preferred embodiments of the present invention have been described, these embodiments may be further changed and modified once those skilled in the art understand the basic inventive concept. It is therefore intended that the appended claims be interpreted to include the preferred embodiments and all changes and modifications that are within the scope of the present invention.

[0237] It is apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations in the embodiments of the present invention fall within the scope of the claims of the present invention and the technical equivalents thereof, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, The display panel includes: a first base substrate; a plurality of scanning lines located on one side of the first base substrate; a plurality of data lines disposed on the same side of the first base substrate as the scan lines, extending in a second direction together with the plurality of data lines, and arranged in the first direction; a plurality of sub-pixels located in respective areas defined by the plurality of scan lines and the plurality of data lines; the plurality of scanning lines extend in a first direction and are arranged along a second direction, the first direction and the second direction intersect with each other; the plurality of sub-pixels constitute a plurality of pixel islands, the plurality of pixel islands are partitioned into a plurality of control regions, each of the control regions including at least one of the pixel islands; The control regions are independently driven to emit light, a display panel, wherein each of the scanning lines includes a plurality of sub-scanning lines arranged along the first direction and disconnected from each other, the number of the sub-scanning lines in each of the scanning lines is the same as the number of the control areas arranged in the first direction, and each of the sub-scanning lines corresponds to one row of the sub-pixels in one of the control areas.

2. The display panel further comprises: a plurality of scanning signal input lines that correspond one-to-one to the scanning lines, extend in the first direction, and are arranged in the second direction; a plurality of control signal lines arranged in the first direction; The multiple fixed potential lines are a plurality of control circuits located between adjacent sub-pixels; One of the pixel islands is connected to at least n of the control circuits, where n is the number of subpixel rows included in the pixel island, and one of the control circuits corresponds to one row of subpixels included in the pixel island; the control circuit is configured to transmit a signal supplied from the scanning signal input line or a signal supplied from the fixed potential line to the scanning line under control of the control signal line; At least some of the control signal lines include a plurality of portions extending along the second direction and a plurality of portions extending in the first direction, The portions extending along the second direction are alternately connected to the portions extending along the first direction. The display panel according to claim 1 .

3. the control circuit includes a first transistor and a second transistor; a control electrode of the first transistor is electrically connected to one of the control signal lines, a first electrode of the first transistor is electrically connected to the scanning signal input line, and a second electrode of the first transistor is electrically connected to the scanning line; a control electrode of the second transistor is electrically connected to one of the control signal lines, a first electrode of the second transistor is electrically connected to the fixed potential line, and a second electrode of the second transistor is electrically connected to the scanning line; The display panel according to claim 2 .

4. a control electrode of the first transistor and a control electrode of the second transistor are electrically connected to the same control signal line; The first transistor is an N-type transistor and the second transistor is a P-type transistor, or the first transistor is a P-type transistor and the second transistor is an N-type transistor. The display panel according to claim 3 .

5. a control electrode of the first transistor and a control electrode of the second transistor are electrically connected to different control signal lines; The display panel according to claim 3 .

6. the display panel further includes a gate driving circuit; the gate drive circuit includes a plurality of cascaded shift registers, one shift register being electrically connected to each of the scanning signal input lines in one row of the control regions; The display panel according to claim 2 .

7. the display panel is divided into a display area and a peripheral area surrounding the display area, the pixel islands are located in the display area, and the scan lines and the data lines extend from the display area to the peripheral area; The display panel further comprises: a plurality of first data selection control lines, a plurality of first data input lines, and a plurality of first data selection circuits located in the peripheral region; each of the first data selection circuits includes at least two multiplexers, and in each of the first data selection circuits, input ends of different multiplexers are electrically connected to different first data input lines, control ends of different multiplexers are electrically connected to different first data selection control lines, and i-th output ends of different multiplexers are electrically connected to the same data line, where i is a positive integer; and in two adjacent first data selection circuits, two multiplexers electrically connected to different first data selection control lines are electrically connected to the same first data input line; the first data selection circuit is configured to supply, under control of a plurality of the first data selection control lines, signals of the corresponding first data input lines to the respective electrically connected data lines; The display panel according to claim 1 .

8. each subpixel row in the pixel island includes h subpixels, and each subpixel row is divided into a subpixel groups, each including f subpixels, where a=h / f, a, h, and f are all positive integers greater than 1; a plurality of the data lines connected to each of the subpixel groups are electrically connected to one of the first data selection circuits, and a plurality of the data lines connected to different subpixel groups are electrically connected to different first data selection circuits; Each of the multiplexers includes f output terminals, one input terminal and f control terminals; The display panel according to claim 7 .

9. Each of the first data selection circuits includes j multiplexers; the number of first data selection control lines is j*f, the number of the first data selection circuits is m, the number of the first data input lines is m, and m and n satisfy n=m+j-1; For every j consecutive first data selection circuits, j multiplexers electrically connected to different first data selection control lines are electrically connected to one first data input line, where j is a positive integer less than m; The display panel according to claim 8 .

10. One of the multiplexers includes f switching transistors, control electrodes of different switching transistors are electrically connected to different first data selection control lines, first electrodes of different switching transistors are electrically connected to the same first data input line, and second electrodes of different switching transistors are electrically connected to different data lines; In each of the first data selection circuits, the second electrodes of the i-th switching transistors in different multiplexers are electrically connected to the same data line. The display panel according to claim 9 .

11. One of the multiplexers includes f switching circuits, each of the switching circuits includes a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; a control electrode of the fifth transistor is electrically connected to the first data selection control line, a first electrode of the fifth transistor and a first electrode of the sixth transistor are electrically connected to the first data input line, a second electrode of the fifth transistor is electrically connected to a control electrode of the sixth transistor, a control electrode of the seventh transistor and a first electrode of the first capacitor, a second electrode of the sixth transistor and a second electrode of the seventh transistor are electrically connected to the data line, and a second electrode of the first capacitor is grounded; the display panel further includes a dummy signal line electrically connected to a first electrode of the seventh transistor. The display panel according to claim 9 .

12. the sub-pixels in one row arranged in the first direction are all of the same color; the display panel further includes a light-shielding layer, the light-shielding layer including a plurality of light-shielding portions extending along the first direction and arranged in the second direction; The display panel according to claim 1 .

13. A display device, A display panel according to any one of claims 1 to 12; a cylindrical lens structure located on the light output side of the display panel; a controller connected to the display panel and supplying independent drive signals to each of the control areas; The cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array. Display device.

14. Each subpixel row in the pixel island includes h subpixels, and each pixel island corresponds to N cylindrical lenses, where h and N are positive integers, h>N, and h / N is a non-integer. The display device according to claim 13.

15. each of the subpixel rows in the pixel island includes a light-shielding region, and the ratio of the area of ​​the subpixel to the area of ​​the light-shielding region is X, where X=N-1; The display device according to claim 14.

16. 16. The display device according to claim 13, The controller a data analysis circuit that performs data analysis on the image to be displayed and acquires image analysis data; a data arrangement circuit that generates a data drive signal corresponding to the control area of ​​the display panel based on a current display mode and the image analysis data; a timing control circuit for generating a gate driving signal for the gate driving circuit based on a current display mode and a gaze area and a non-gaze area of ​​the display panel; Display device.

17. 17. The display device according to claim 13, further comprising an eye tracking system for determining in real time the user's eye gaze area on the display device; Display device.

18. The human eye tracking system includes an image acquisition circuit, a camera standardization circuit, a camera time division partition control circuit, a face detection circuit, an image coordinate system conversion circuit, a pupil detection circuit, a spatial coordinate calculation circuit, and a spatial gaze tracking circuit; the image capture circuitry includes a plurality of first cameras and at least one second camera, the resolution of the first cameras being greater than the resolution of the second cameras, the first cameras being configured to capture a pupil image of the user, and the second camera being configured to capture a face image of the user; the camera standardization circuit is configured to standardize the first camera and the second camera to obtain intrinsic parameter matrices and extrinsic parameter matrices of the first camera and the second camera; the camera time division partition control circuit is configured to control the image capturing timing of the plurality of first cameras so that the plurality of first cameras alternately capture images; the face detection circuit is configured to search for a face frame in the image captured by the second camera, detect face feature points, acquire a human eye area within the face frame, and acquire a spatial coordinate transformation matrix of the human eye area based on a mapping relationship between the face feature points and a standard face model; the image coordinate system transformation circuit is configured to transform a face image coordinate system into a cylindrical pupil image coordinate system or a pupil coordinate system into a face image coordinate system; the pupil detection circuit is configured to calculate pupil coordinates in the image captured by the first camera, convert the calculated pupil coordinates into a pupil image coordinate system by a coordinate conversion circuit based on the human eye region coordinates obtained by the face detection circuit, acquire the human eye region on the pupil image, detect the pupil in the human eye region, and acquire the pupil coordinates in the pupil image coordinate system; the spatial coordinate calculation circuit is configured to convert pupil coordinates into a face image coordinate system, and calculate a spatial coordinate transformation matrix obtained by the face detection circuit to obtain pupil coordinates in three-dimensional space; the spatial gaze tracking circuit is configured to determine eyeball center coordinates using the pupil coordinates and a preset human eye model, calculate a direction vector of the pupil coordinates and the eyeball center coordinates as a line vector, obtain an intersection point between the line of sight of the human eye and the display panel based on a distance from the human eye to the display panel and an equation of a plane on which the display panel exists, and obtain a human eye gaze point coordinate on the display panel based on the line of sight and the intersection point. The display device according to claim 17.

19. the display device further includes an image rendering system electrically connected to the controller; an image rendering system electrically connected to the controller, the image rendering system including a coordinate extraction circuit, a lens alignment detection circuit, and an image rendering circuit; the coordinate extraction circuit is configured to determine three-dimensional spatial coordinates of a human eye relative to the display panel based on a gaze position of the human eye determined by the eye tracking system on the display panel within the display device; the lens bonding detection circuit is configured to acquire a bonding error of the cylindrical lens, acquire bonding parameters of the cylindrical lens according to the bonding error, and acquire a viewpoint crosstalk curve; The image rendering circuit is configured to generate a multi-viewpoint initial image from the image to be displayed, and further to optimize the multi-viewpoint initial image based on the human eye position, the stitching detection parameter, and the viewpoint crosstalk curve, and obtain the optimized multi-viewpoint image as the image to be displayed.

19. The display device according to claim 18.

20. 20. A method for driving a display device according to any one of claims 13 to 19, comprising: determining a user's gaze area and non-gaze area on the display device in real time; independently driving the control region corresponding to the gaze region to display an image at a first resolution, and driving the control region corresponding to the non-gaze region to display an image at a second resolution; the first resolution is higher than the second resolution; Drive method.

21. The step of determining a user's gaze area and a non-gaze area on the display device includes: acquiring a gaze area of ​​a user's eye on the display device by an eye tracking system; determining an area other than the gaze area within the display device as a non-gaze area, The driving method according to claim 20.

22. The step of acquiring a gaze area of ​​the user's eye on the display device by an eye tracking system includes: Controlling a first camera in the eye tracking system to alternately capture a pupil image of a user, and controlling a second camera in the eye tracking system to capture a face image of a user; searching for a face frame in the image captured by the second camera, detecting facial feature points, acquiring a human eye area within the face frame, and acquiring a spatial coordinate transformation matrix of the human eye area based on a mapping relationship between the facial feature points and a standard face model; Transforming a face image coordinate system to a cylindrical pupil image coordinate system or a pupil coordinate system to a face image coordinate system; calculating pupil coordinates in the image captured by the first camera, transforming the coordinates of the human eye region into a pupil image coordinate system, acquiring the human eye region on the pupil image, detecting the pupil in the human eye region on the pupil image, and acquiring pupil coordinates in the pupil image coordinate system; transforming pupil coordinates into a face image coordinate system and calculating the spatial coordinate transformation matrix to obtain pupil coordinates in three-dimensional space; determining an eyeball center coordinate according to the pupil coordinate and a predetermined human eye model; calculating a direction vector of the pupil coordinates and the eyeball center coordinates as a line vector; acquiring an intersection point between the line of sight of the human eye and the display panel based on a distance from the human eye to the display panel and an equation of a plane on which the display panel exists; and acquiring a human eye gaze point coordinate on the display panel based on the line of sight and the intersection point, and determining an area of ​​the display panel where the human eye gaze point coordinate exists as the gaze area. The driving method according to claim 21.

23. a step of independently driving the control region corresponding to the attention region to display an image at a first resolution and driving the control region corresponding to the non-attention region to display an image at a second resolution, determining display information for each of the sub-pixels in the pixel island of the control region corresponding to the attention region based on a display mode, the attention region, and the non-attention region, and determining display information for each of the sub-pixels in the pixel island of the control region corresponding to the non-attention region; supplying a first data selection control signal to a first data selection control line based on the display information, and supplying a data signal supplied from a first data write line to the data line corresponding to the first data selection circuit via a first data selection circuit; 23. The driving method according to any one of claims 20 to 22.

24. The step of independently driving the attention area to display an image at a first resolution and driving the non-attention area to display an image at a second resolution further includes: supplying gate drive signals to a gate drive circuit of the display panel by a controller of the display device, controlling the pixel islands of the plurality of rows corresponding to the attention area to be turned on row by row, and controlling F pixel islands of the pixel islands of the plurality of rows corresponding to the non-attention area to be turned on synchronously; F is a positive integer and is a ratio between the first resolution and the second resolution. The driving method according to claim 23.

25. the gate driving circuit included in the display panel includes a plurality of gate driving groups; each of the gate drive groups includes B gate drive subgroups, and each of the gate drive subgroups includes C shift registers, where B and C are integers greater than 1; The step of supplying a gate driving signal to a gate driving circuit of the display panel by the controller of the display device includes: supplying a clock control signal to the gate drive groups by the controller so that ON signals are sequentially input to the shift registers in the gate drive subgroups according to the order of the first to Bth gate drive subgroups in each of the gate drive groups; The driving method according to claim 24.

26. further comprising driving the attention area to display images at a first refresh rate and driving the non-attention area to display images at a second refresh rate; the first refresh rate is higher than the second refresh rate; 26. The driving method according to any one of claims 20 to 25.

27. The step of driving the attention area to display images at a first refresh rate and driving the non-attention area to display images at a second refresh rate includes: driving each sub-pixel within the attention area to refresh Z times; and driving each sub-pixel in the non-attention region to refresh Y times; Z and Y are positive integers, and Z is greater than Y; 27. The driving method according to claim 26.

28. The step of driving each sub-pixel within the attention area to be refreshed includes: driving each scanning signal input line corresponding to the attention area to sequentially transmit an active level signal; controlling each control signal line to transmit a control signal, transmitting a signal supplied from a scanning signal input line to a scanning line corresponding to the attention area, and transmitting a signal supplied from a fixed potential line to a scanning line corresponding to the non-attention area; The step of driving each of the sub-pixels in the non-attention area to be refreshed includes: driving each of the scanning signal input lines in the display panel to sequentially transmit an active level signal; When each subpixel row corresponding to the attention area is scanned, controlling each of the control signal lines to transmit a control signal, transmitting a signal supplied from the fixed potential line to the scanning line corresponding to the attention area, and transmitting a signal supplied from the scanning signal input line to the scanning line corresponding to the non-attention area.

28. The driving method according to claim 27.

29. 20. A method for rendering an image on a display device according to any one of claims 13 to 19, comprising the steps of: determining a position of a human eye's line of sight on the display panel within the display device and determining three-dimensional spatial coordinates of the human eye relative to the display panel; generating a multi-viewpoint initial image from an image to be displayed; performing a bonding detection of a cylindrical lens array on the display device, and acquiring a bonding error and a viewpoint crosstalk curve of the cylindrical lens; optimizing the initial multi-view images based on the human eye position, the stitching detection parameters, and the viewpoint crosstalk curve to obtain an optimized multi-view image; transmitting the optimized multi-view image to the controller. Image rendering method.

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