Capacitor-embedded sheet, interposer and semiconductor element

Abstract

This capacitor-embedded sheet 1 has a conductor layer 200 and a porous layer 100 provided on the conductor layer 200. The porous layer 100 comprises: a capacitor section 120 that comprises a structure made up of a metal layer 121, a conductor layer 122, and a metal layer 123 which are provided in a porous structure 101 of the porous layer 100; a through-hole section 110 in which conductors 111 in the porous structure 101 of the porous layer 100 are filled; and a porous insulation section 130 which is provided around the through-hole section 110 and in which the conductors in the porous structure 101 are not filled. The conductor layer 200 comprises: a metal conductor 230; a first via section 210 that passes through the metal conductor 230 directly below the through-hole section 110 and is connected to the through-hole section 110; and a first insulation section 220 that is provided around the first via section 210 and insulates the metal conductor 230 from the first via section 210.

Description

[Technical Field]

[0001] The present invention relates to a sheet with built-in capacitors, an interposer, and a semiconductor element. [Background technology]

[0002] A typical capacitor element used in semiconductor integrated circuits is, for example, a metal-insulator-metal (MIM) capacitor, which has a parallel-plate structure in which an insulator is sandwiched between a lower electrode and an upper electrode.

[0003] Patent Document 1 discloses a stacked semiconductor device package in which logic is mounted on one side of a substrate and a capacitor is mounted on the other side of the substrate, and the logic and capacitor are electrically connected. It also discloses that the capacitor is sealed with an insulator, and the insulator has a through hole filled with metal.

[0004] Patent Document 2 describes a capacitor structure having a substrate, a conductive layer on the substrate, and a porous layer on the conductive layer. The porous layer is said to have a first portion provided with a conductor and a second portion provided with an MIM capacitor structure. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2016 / 099523 [Patent Document 2] European Patent Application Publication No. 4009340 Summary of the Invention [Problem to be solved by the invention]

[0006] In the structure described in Patent Document 1, the package substrate is located between the logic and the capacitor, which results in a long distance between the logic and the capacitor, resulting in high ESL and insufficient impedance characteristics in the high frequency range. Furthermore, the structure of Patent Document 2 has the problem that it is not possible to integrate the MIM capacitor structure with the power supply line on the substrate side.

[0007] The present invention has been made to solve the above problems, and aims to provide an integrated capacitor sheet that can have a structure in which the distance between a semiconductor component such as logic and a capacitor section is shortened, thereby improving impedance characteristics in the high frequency range, and that can pull out the conductor provided in the porous layer in which the capacitor structure is provided in the thickness direction and integrate it with the power supply line on the substrate side. [Means for solving the problem]

[0008] The capacitor-embedded sheet of the present invention comprises a conductor layer and a porous layer provided on the conductor layer, wherein the porous layer comprises a capacitor portion having a metal layer-dielectric layer-metal layer structure provided in the porous structure of the porous layer, a through-hole portion in which a conductor is filled in the porous structure of the porous layer, and a porous insulating portion provided around the through-hole portion and in which the porous structure is not filled with a conductor, and the conductor layer comprises a metal conductor, a first via portion that penetrates the metal conductor directly below the through-hole portion and is connected to the through-hole portion, and a first insulating portion that is provided around the first via portion and insulates the first via portion from the metal conductor.

[0009] The interposer of the present invention comprises the capacitor-embedded sheet of the present invention and a rewiring layer disposed on at least one main surface of the capacitor-embedded sheet.

[0010] The semiconductor element of the present invention is formed by integrating at least the capacitor-embedded sheet of the present invention and a semiconductor portion. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a capacitor-embedded sheet which can have a structure in which the distance between semiconductor components such as logic and the capacitor section is shortened, thereby improving impedance characteristics in the high frequency range, and which can also pull out the conductor provided in the porous layer in which the capacitor structure is provided in the thickness direction and integrate it with the power supply line on the substrate side. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is an enlarged cross-sectional view of a capacitor portion. [Figure 2B] FIG. 2B is an enlarged cross-sectional view of the through-hole portion. [Figure 2C] FIG. 2C is an enlarged cross-sectional view of the porous insulating portion. [Figure 3] FIG. 3 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the second embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the third embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the fourth embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to a fifth embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to a sixth embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the seventh embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the eighth embodiment of the present invention. [Figure 10]FIG. 10 is an enlarged view of a portion including areas A and B enclosed by dotted lines in FIG. [Figure 11] FIG. 11 is a cross-sectional view schematically showing an example of an interposer of the present invention. [Figure 12] FIG. 12 is an enlarged view of a portion including the area C enclosed by the dotted line in FIG. [Figure 13A] FIG. 13A is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors. [Figure 13B] FIG. 13B is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors. [Figure 13C] FIG. 13C is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors. [Figure 13D] FIG. 13D is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors. [Figure 13E] FIG. 13E is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors. [Figure 14A] FIG. 14A is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14B] FIG. 14B is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14C] FIG. 14C is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14D] FIG. 14D is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14E] FIG. 14E is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14F] FIG. 14F is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 14G] FIG. 14G is a process diagram schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. [Figure 15] FIG. 15 is a cross-sectional view schematically showing an example of use of a capacitor-embedded sheet and an interposer. [Figure 16] FIG. 16 is a cross-sectional view schematically showing another example of use of a sheet with built-in capacitors and an interposer. [Figure 17] FIG. 17 is a cross-sectional view schematically showing another example of use of a sheet with built-in capacitors and an interposer. [Figure 18] FIG. 18 is a cross-sectional view schematically showing another example of use of a capacitor-embedded sheet and an interposer. [Figure 19] FIG. 19 is a cross-sectional view schematically showing an example of a semiconductor element of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The capacitor-embedded sheet, interposer, and semiconductor element of the present invention will be described below. However, the present invention is not limited to the following configurations, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual preferred configurations of the present invention described below.

[0014] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0015] In the following description, unless otherwise specified, each embodiment will be referred to simply as the "capacitor-embedded sheet of the present invention," the "interposer of the present invention," and the "semiconductor element of the present invention." The shapes and arrangements of the capacitor-embedded sheet, interposer, and semiconductor element of the present invention are not limited to the examples shown in the drawings.

[0016] [Embodiment 1] The capacitor-embedded sheet of the present invention has a conductor layer and a porous layer provided on the conductor layer. The porous layer has a capacitor portion having a metal layer-dielectric layer-metal layer structure provided in the porous structure of the porous layer, a through-hole portion in which the porous structure of the porous layer is filled with a conductor, and a porous insulating portion provided around the through-hole portion and in which the porous structure is not filled with a conductor. The conductor layer also has a metal conductor, a first via portion that penetrates the metal conductor directly below the through-hole portion and is connected to the through-hole portion, and a first insulating portion provided around the first via portion and insulates the first via portion from the metal conductor. A sheet with a built-in capacitor having these configurations will be described below as a sheet with a built-in capacitor according to a first embodiment of the present invention.

[0017] Fig. 1 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to embodiment 1 of the present invention, Fig. 2A is an enlarged cross-sectional view of a capacitor portion, Fig. 2B is an enlarged cross-sectional view of a through-hole portion, and Fig. 2C is an enlarged cross-sectional view of a porous insulating portion.

[0018] 1 includes a conductor layer 200 and a porous layer 100 provided on the conductor layer 200. The porous layer 100 includes a capacitor portion 120, a through-hole portion 110, and a porous insulating portion 130 in its layers.

[0019] The porous layer 100 preferably has a porous structure formed by anodizing aluminum (AAO structure: anodic aluminum oxide). Figures 2A, 2B, and 2C show a wall surface 101a of the porous structure 101. The porous layer 100 has through holes extending in the thickness direction of the porous layer 100 from a surface 103 of the porous layer to the conductor layer 200. 2A, capacitor section 120 has a structure of metal layer 121, dielectric layer 122, and metal layer 123 on wall surface 101a of porous structure 101. This structure is a Metal-Insulator-Metal structure (hereinafter also referred to as an MIM structure) and functions as a capacitor. The MIM structure is preferably formed by atomic layer deposition (ALD).

[0020] The through-hole portion 110 has a structure that allows electrical continuity between the main surface 102 of the porous layer on the conductive layer side and the surface 103 of the porous layer (the main surface of the porous layer opposite the conductive layer). 2B, the through-hole portion 110 has a structure in which a conductor 111 is filled in a porous structure 101. In other words, the through-hole portion 110 has a structure in which a conductor 111 is filled and extends from a main surface 102 on the conductor layer side of the porous layer to a main surface 103 on the opposite side of the conductor layer of the porous layer. By filling the porous structure 101 in the through-hole portion 110 with the conductor 111, the through-hole portion 110 becomes a structure that allows electrical conduction between the main surface 102 on the conductor layer side of the porous layer 100 and the surface 103 of the porous layer. Copper or nickel is preferably used as the conductor 111.

[0021] As shown in Fig. 2C, the porous insulating portion 130 has a structure in which the porous structure 101 is not filled with a conductor. Because the porous structure is not filled with a conductor, the porous insulating portion 130 is an insulator. The porous insulating portion 130 is located between the through-hole portion 110 and the capacitor portion 120, and insulates the through-hole portion 110 from the capacitor portion 120 so that there is no electrical conduction between the through-hole portion 110 and the capacitor portion 120 at the level of the porous layer 100.

[0022] The conductor layer 200 is a layer that includes a metal conductor 230, a first via portion 210, and a first insulating portion 220. The metal conductor 230 comes into contact with the capacitor portion 120, so that one electrode (anode or cathode) of the capacitor portion 120 is drawn out from the metal conductor 230. The metal conductor 230 may be made of one or more types of metal. For example, a multi-layer conductor layer having a three-layer structure of W-Al-Ti from the side closest to the porous layer can be used.

[0023] The first via portion 210 is a via provided so as to penetrate the metal conductor 230 directly below the through-hole portion 110. In other words, the first via portion 210 is provided from the main surface 102 of the porous layer of the through-hole portion 110 on the conductor layer side along the direction in which the through-hole portion 110 extends, and is connected to the through-hole portion 110. The first via portion is preferably made of metal. Copper is preferred as the metal constituting the first via portion 210. Because the through-hole portion 110 and the first via portion 210 are connected on the main surface 202 of the conductor layer facing the porous layer, the through-hole portion 110 can be extended to the main surface 203 of the conductor layer opposite the porous layer. As a result, a structure is obtained in which the surface 103 of the porous layer is electrically connected to the main surface 203 of the conductor layer opposite the porous layer. In other words, a capacitor-embedded sheet is obtained in which the conductor provided in the porous layer can be extended in the thickness direction.

[0024] A first insulating portion 220 is provided around the first via portion 210 to insulate the first via portion 210 from the metal conductor 230. The first insulating portion 220 is preferably made of a resin material, and any resin material that can be used as an insulating material can be used. The metal conductor 230 is electrically connected to one electrode of the capacitor section 120, but since the first via section 210 and the metal conductor 230 are insulated by the first insulating section 220, the capacitor section 120 is electrically insulated from the first via section 210 and the through-hole section 110.

[0025] [Embodiment 2] The capacitor-embedded sheet according to the second embodiment of the present invention has a porous structure of the porous layer filled with a conductor, and further includes an extraction electrode portion connected at the bottom to the metal conductor of the conductor layer.

[0026] FIG. 3 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the second embodiment of the present invention. The capacitor-embedded sheet 2 shown in FIG. 3 has an extraction electrode portion 140 in the layer of the porous layer 100. The lead electrode 140 has a structure in which a conductor is filled in a porous structure. In the porous layer 100, the structure of the through-hole 110 and the structure of the lead electrode 140 are the same. The bottom of the extraction electrode 140 is connected to the metal conductor 230 of the conductor layer 200. The extraction electrode 140 differs from the through-hole 110 in that the first via 210 does not exist directly below the extraction electrode 140, but the metal conductor 230 does. Similarly to the through-hole portion 110, the extraction electrode portion 140 has a structure that allows electrical conduction between the main surface 102 of the porous layer 100 on the conductive layer side and the surface 103 of the porous layer.

[0027] The extraction electrode portion 140 is connected to the metal conductor 230 of the conductor layer 200. The metal conductor 230 is in contact with the capacitor portion 120, and one electrode of the capacitor portion 120 is extracted to the metal conductor 230, so that the extraction electrode portion 140 is electrically connected to the capacitor portion 120 via the metal conductor 230. With this structure, one electrode of the capacitor portion 120 is extracted to the surface 103 of the porous layer via the metal conductor 230. That is, by providing the lead-out electrode section 140, the lead-out position of the electrode from the capacitor section 120 can be changed.

[0028] [Embodiment 3] The capacitor-embedded sheet according to the third embodiment of the present invention further includes, in the same layer as the porous layer, columnar metal electrodes connected at their bottoms to the metal conductors of the conductor layer.

[0029] FIG. 4 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the third embodiment of the present invention. The capacitor-embedded sheet 3 shown in FIG. 4 has pillar-shaped metal electrodes 150 in the layer of the porous layer 100. The pillar-shaped metal electrodes 150 are made of dense metal rather than porous. The pillar-shaped metal electrodes 150 are at the same level as the porous layer (at the same height as the porous layer in the capacitor-embedded sheet), but are not part of the porous layer. The bottom of the pillar-shaped metal electrode 150 is connected to the metal conductor 230 of the conductor layer 200. There is no first via portion 210 directly below the pillar-shaped metal electrode 150, but there is a metal conductor 230. Similarly to the through-hole portion 110, the pillar-shaped metal electrode 150 has a structure that allows electrical conduction between the main surface 102 of the porous layer 100 on the conductive layer side and the surface 103 of the porous layer.

[0030] It is preferable to use aluminum that has not been anodized as the columnar metal electrode. In the process of anodizing the aluminum to form the porous layer, a portion of the aluminum is masked to provide a region that is not exposed to the aqueous acid solution used for anodization. This masked region is then left as a metal portion that is not anodized and does not become a porous layer. The remaining metal portion can be used as the columnar metal electrode 150.

[0031] By providing the columnar metal electrode 150, one electrode of the capacitor section 120 is led out to the surface 103 of the porous layer via the metal conductor 230, just as in the case where the lead-out electrode section 140 is provided. In other words, by providing the columnar metal electrode 150, the lead-out position of the electrode from the capacitor section 120 can be changed.

[0032] [Embodiment 4] In the capacitor-embedded sheet of embodiment 4 of the present invention, the porous layer has multiple capacitor sections, the metal conductor is connected to one of the metal layers of each capacitor section, and the conductor layer further has a third insulating section that provides insulation between the metal conductors connected to different capacitor sections.

[0033] FIG. 5 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the fourth embodiment of the present invention. 5 has a plurality of capacitor portions 120 in a porous layer 100. The capacitor portion 120 shown in the center of the drawing is referred to as capacitor portion 120a, and the capacitor portion 120 shown on the right side of the drawing is referred to as capacitor portion 120b. The plurality of capacitor sections 120 included in the capacitor-embedded sheet 4 may be arranged in an array such as a lattice or staggered pattern in a plan view.

[0034] The metal conductor 230 is connected to each capacitor unit 120. The metal conductor 230 shown in the center of the drawing is referred to as metal conductor 230a, and the metal conductor 230 shown on the right side of the drawing is referred to as metal conductor 230b. The capacitor unit 120a and the metal conductor 230a are connected, and the capacitor unit 120b and the metal conductor 230b are connected, but a third insulating unit 240 is provided between the metal conductors 230a and 230b, electrically insulating the metal conductors 230a and 230b. As a result, the capacitor unit 120a and the capacitor unit 120b are electrically isolated from each other. The material that constitutes the third insulating portion 240 is not limited, but is preferably an inorganic insulating material, and SiO2 can be suitably used.

[0035] [Embodiment 5] The capacitor-embedded sheet according to the fifth embodiment of the present invention further comprises a substrate on which the conductor layer is placed. The substrate further comprises a base material, a second via portion that penetrates the base material directly below the first via portion and is integrated with the first via portion, and a second insulating portion that is provided around the second via portion and is integrated with the first insulating portion.

[0036] FIG. 6 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to a fifth embodiment of the present invention. 6 includes a substrate 300, and the conductive layer 200 is placed on the substrate 300. The substrate 300 may be a silicon substrate, a glass substrate, an organic substrate, or the like. The substrate 300 is provided with a base material 330, a second via portion 310 that penetrates the base material 330, and a second insulating portion 320 that is provided around the second via portion 310. The portion of the substrate 300 other than the through holes in which the second via portion 310 and the second insulating portion 320 are formed is the base material 330 .

[0037] The substrate 330 may be a semiconductor. When the substrate 330 is a semiconductor, it may be made of a material such as silicon. When the substrate is not an insulator, it is preferable to provide an insulating layer between the substrate 330 and the conductor layer 200, and it is preferable to use SiO2 as the insulating layer. In the manufacturing process diagrams described later (FIG. 13A and subsequent figures), an SiO2 layer 340 is shown provided between the substrate 330 and the conductor layer 200. The substrate 330 may be an insulator. When the substrate 330 is an insulator, it may be made of a material such as glass or an organic material.

[0038] The second via portion 310 is integrated with the first via portion 210. When manufacturing the capacitor-embedded sheet 5 of the fifth embodiment, the first via portion 210 and the second via portion 310 can be formed at the same time. The second via portion 310 is preferably made of a metal, and copper is preferable as the metal constituting the second via portion 310. When the material of the substrate 300 is silicon, a via such as the second via portion 310 has a structure called a TSV (Through Silicon Via).

[0039] The second insulating portion 320 is integrated with the first insulating portion 220. When manufacturing the capacitor-embedded sheet 5 of the fifth embodiment, the first insulating portion 220 and the second insulating portion 320 can be formed at the same time. The second insulating portion 320 is preferably made of a resin material, and any resin material that can be used as an insulating material can be used.

[0040] Because second via portion 310 is integrated with first via portion 210 and first via portion 210 is connected to through-hole portion 110 directly below through-hole portion 110, through-hole portion 110 can be extended to main surface 303 on the opposite side of the substrate from the porous layer. As a result, a structure is obtained in which electrical continuity is achieved from surface 103 of the porous layer to main surface 303 on the opposite side of the substrate from the porous layer. In other words, a capacitor-embedded sheet is obtained in which the conductor provided in the porous layer can be extended from the substrate in the thickness direction.

[0041] [Embodiment 6] In the capacitor-embedded sheet according to the sixth embodiment of the present invention, a plurality of first via portions and a plurality of second via portions are provided for one through-hole portion.

[0042] FIG. 7 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to a sixth embodiment of the present invention. 7, four first via portions 210 and four second via portions 310 are provided for one through-hole portion 110, and a first insulating portion 220 is provided around each first via portion 210, and a second insulating portion 320 is provided around each second via portion 310. Fig. 7 shows the two first via portions 210 and two second via portions 310 visible on the near side, and the first insulating portions 220 and second insulating portions 320 around them. With this structure, the cost of forming the first and second via portions (cost of the plating process) can be reduced.

[0043] [Embodiment 7] In the capacitor-embedded sheet according to the seventh embodiment of the present invention, a plurality of first via portions and second via portions are provided for a plurality of through-hole portions.

[0044] FIG. 8 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the seventh embodiment of the present invention. 8 has four first via portions 210 and four second via portions 310 provided for four through-hole portions 110, with a first insulating portion 220 provided around each first via portion 210 and a second insulating portion 320 provided around each second via portion 310. Figure 8 shows two through-hole portions 110, two first via portions 210 and two second via portions 310 visible on the near side, and the first insulating portions 220 and second insulating portions 320 around them. With this structure, the resistance value of the through-hole portion 110, the first via portion 210, and the second via portion 310 can be reduced, and the stress applied to one through-hole portion 110 can be alleviated.

[0045] [Embodiment 8] The capacitor-embedded sheet according to the eighth embodiment of the present invention is provided with third via portions formed by filling with a conductive paste.

[0046] FIG. 9 is a cross-sectional view schematically showing an example of a capacitor-embedded sheet according to the eighth embodiment of the present invention. 9, the capacitor-embedded sheet 8 is the same as the capacitor-embedded sheet 6 shown in Fig. 7, except that a substrate-side resin layer 350 is further provided below the substrate 300. The capacitor-embedded sheet 8 is provided with third via portions 360 formed by filling openings provided in the substrate-side resin layer 350 with a conductive paste. The third via portion 360 is connected to the second via portion 310 provided in the substrate 300 , and therefore the third via portion 360 is connected to the through-hole portion 110 via the second via portion 310 and the first via portion 210 . The through-hole portion 110 is led out to the surface of the substrate-side resin layer 350 (the main surface of the substrate-side resin layer opposite to the substrate). The material of the substrate-side resin layer may be, for example, ABF (Ajinomoto Build-up Film (registered trademark)).

[0047] [Common features of embodiments 1 to 8] In any of the capacitor-embedded sheets of the present invention, it is preferable that part of the first insulating portion penetrates into the porous layer adjacent to the first insulating portion. It is also preferable that a portion of the first via portion penetrates into the porous layer adjacent to the first via portion.

[0048] FIG. 10 is an enlarged view of a portion including areas A and B enclosed by dotted lines in FIG. 10 schematically shows, in region A, a state in which a part of the first insulating portion 220 (resin material) penetrates into the porous structure of the porous insulating portion 130 of the porous layer 100. Also, in region B, a state in which a part of the first via portion 210 (metal) penetrates into the porous structure of the porous insulating portion 130 of the porous layer 100 is shown.

[0049] By having the first insulating portion 220 penetrate into the porous layer 100, the bond between the first insulating portion 220 and the porous layer 100 becomes stronger, improving the connection reliability of the capacitor-embedded sheet. Similarly, by having the first via portion 210 penetrate into the porous layer 100, the bond between the first via portion 210 and the porous layer 100 becomes stronger, improving the connection reliability of the capacitor-embedded sheet.

[0050] There is no particular limitation on the position at which the first insulating portion 220 and the first via portion 210 penetrate into the porous layer 100, but since other materials tend to penetrate into the porous insulating portion 130, it is preferable that the first insulating portion 220 and the first via portion 210 penetrate into the porous insulating portion 130. In addition, the entire first insulating portion 220 may be in contact with the porous insulating portion 130 over the entire main surface 102 on the conductor layer side of the porous layer so that the first insulating portion 220 penetrates into the porous layer 100 over the entire surface where the first insulating portion 220 contacts the porous layer 100, thereby exerting an anchor effect.

[0051] [Interposer] Next, an example of the interposer of the present invention will be described. The interposer of the present invention comprises the capacitor-embedded sheet of the present invention and a rewiring layer disposed on at least one main surface of the capacitor-embedded sheet, and the rewiring layer preferably comprises an organic insulating layer. The redistribution layer is a layer called an RDL (Redistribution Layer).

[0052] FIG. 11 is a cross-sectional view schematically showing an example of an interposer of the present invention. 11 includes the capacitor-embedded sheet 5 shown in FIG. 6 and a rewiring layer 400. The rewiring layer 400 is disposed on the surface 103 of the porous layer of the capacitor-embedded sheet 5. The rewiring layer 400 includes an organic insulating layer 410 and wiring 420, and the wiring 420 is electrically connected to the through-hole portion 110 or the capacitor portion 120. The rewiring layer 400 changes the positions, spacing, etc. of the electrodes provided on the surface of the capacitor-embedded sheet 5. As a result, it becomes easy to connect other semiconductor elements such as logic.

[0053] By the wiring 420 provided in the redistribution layer 400, both the anode and the cathode of the capacitor section 120 may be drawn to the redistribution layer 400, or only one of the anode and the cathode of the capacitor section 120 may be drawn to the redistribution layer 400. When only one electrode is drawn to the redistribution layer 400, it is assumed that the other electrode is drawn to the side opposite the redistribution layer 400 (the conductor layer side, the substrate side).

[0054] Figure 11 shows an example in which a rewiring layer is provided on a capacitor-embedded sheet having a substrate, but the interposer of the present invention may also be a capacitor-embedded sheet (see embodiments 1 to 4) that does not have a substrate and has a rewiring layer provided on it. A redistribution layer may be provided on the main surface of the conductor layer opposite the porous layer, or on the main surface of the substrate opposite the porous layer, or on both main surfaces of the capacitor-embedded sheet.

[0055] 11 shows an example in which the redistribution layer has an organic insulating layer, the redistribution layer may have an inorganic insulating layer and an organic insulating layer. That is, the redistribution layer may be a combination of an inorganic redistribution layer including an inorganic insulating layer and wiring in contact with the capacitor-embedded sheet, and an organic redistribution layer including an organic insulating layer and wiring provided on the inorganic redistribution layer.

[0056] In the interposer of the present invention, it is preferable that a portion of the rewiring layer penetrates into the porous layer adjacent to the rewiring layer. FIG. 12 is an enlarged view of a portion including the area C enclosed by the dotted line in FIG. FIG. 12 schematically shows how, in region C, part of the organic insulating layer 410 and part of the wiring 420 of the rewiring layer 400 penetrate into the porous structure of the porous insulating section 130 of the porous layer 100. When the inorganic insulating layer of the rewiring layer is in contact with the porous layer, a part of the inorganic insulating layer may penetrate into the porous layer adjacent to the rewiring layer.

[0057] By having a portion of the redistribution layer 400 penetrate into the porous layer 100, the bond between the redistribution layer 400 and the porous layer 100 becomes stronger, improving the connection reliability of the interposer.

[0058] There are no particular restrictions on the position where the redistribution layer 400 penetrates into the porous layer 100, but since other materials tend to penetrate into the porous insulating section 130, it is preferable that the redistribution layer 400 penetrate into the porous insulating section 130.

[0059] [Method of manufacturing the capacitor-embedded sheet and interposer] Figures 13A, 13B, 13C, 13D, and 13E are process diagrams schematically showing an example of a manufacturing process for a sheet with built-in capacitors. Figures 14A, 14B, 14C, 14D, 14E, 14F, and 14G are process diagrams schematically showing an example of a manufacturing process for a sheet with built-in capacitors and an interposer. Hereinafter, a process for producing a sheet with built-in capacitors according to the present invention and a process for producing an interposer according to the present invention using the produced sheet with built-in capacitors will be described successively.

[0060] First, a substrate having a conductor layer laminated on its surface is prepared. FIG. 13A shows a structure in which an SiO2 layer 340 is provided on a substrate 300 made of silicon, and conductor layers made of a Ti layer 510, an Al layer 520, a W layer 530, and an Al layer 540 are sequentially stacked on the SiO2 layer 340. The configuration of the conductor layer provided on the substrate 300 is not limited to the above configuration, but the uppermost layer of the conductor layer is preferably an Al layer since it is a porous layer.

[0061] Next, a part or all of the conductor layer is anodized to form a porous layer. Fig. 13B shows the state in which the top Al layer 540 shown in Fig. 13A is anodized to form aluminum oxide, forming porous layer 100 with an AAO structure. The anodization reaction stops at W layer 530, and W layer 530, which is a conductor layer, is exposed at the bottom of the porous structure of porous layer 100. In this process, if a portion of the Al layer is masked to prevent contact with the acid solution used for anodization, the masked portion will remain as a metal portion that will not be anodized and will not become a porous layer. The remaining metal portion can be used as a columnar metal electrode 150 (see FIG. 4).

[0062] Next, as shown in Fig. 13C, a first mask 104 is provided on the surface 103 of the porous layer. An SiO2 film can be used as the first mask 104. The first mask 104 is patterned so as to be formed at a predetermined position on the surface 103 of the porous layer. The first mask 104 is not provided in the portion where the through-hole portion 110 will be formed in the next step. The first mask 104 is preferably formed of a material that does not penetrate into the porous structure but covers the surface 103 of the porous layer.

[0063] Next, as shown in Fig. 13D, the porous layer is filled with a conductor to form through-holes 110. By filling the conductor in the areas of the surface of the porous layer where the first mask 104 is not provided, it is possible to form through-holes 110 only in predetermined areas of the porous layer. Filling the porous layer with the conductor is preferably performed by electrolytic plating. Copper or nickel is preferably used as the conductor.

[0064] The process for forming the extraction electrode portion 140 is also similar, and as with the case of forming the through-hole portion 110, the first mask 104 is not provided in the area where the extraction electrode portion 140 is to be formed, and a conductor is filled into the porous layer. The through-hole portion 110 and the extraction electrode portion 140 have different roles in subsequent processes, but at this stage they have the same configuration. If, in a later process, an opening is not formed in the conductor layer directly below the porous layer filled with the conductor, and the first via portion and first insulating portion are not formed, and the porous layer filled with the conductor and the metal conductor are left connected, that portion becomes an extraction electrode portion rather than a through-hole portion.

[0065] Next, after peeling off the first mask 104, a second mask 105 is provided on the surface of the porous layer as shown in FIG. 13E. A SiO2 film can be used as the second mask 105. The second mask 105 is patterned so as to be formed at a predetermined position on the surface 103 of the porous layer. The second mask 105 is not provided in the area where the capacitor section 120 will be formed in the next step. 13E also shows the step of forming the capacitor section 120. In the portion of the surface 103 of the porous layer where the second mask 105 is not formed, a three-layer structure (MIM structure) of a metal layer, a dielectric layer and a metal layer is formed by the ALD method to form the capacitor section 120. The metal layer, the dielectric layer and the metal layer that make up the MIM structure are preferably materials that enter the porous structure and are formed along the wall surfaces of the porous structure.

[0066] In the steps up to this point, the areas where the porous layer has not been filled with a conductor and no MIM structure has been formed are areas where the porous structure is not filled with a conductor, and these become porous insulating portions 130 (see FIGS. 1 and 2C). When second mask 105 is peeled off, the capacitor-embedded sheet of the present invention is obtained.

[0067] Next, a rewiring layer is provided on the surface of the porous layer. In the following, an example in which an inorganic rewiring layer and an organic rewiring layer are provided as the rewiring layer will be described. First, an inorganic rewiring layer is provided on the surface of the porous layer. When an inorganic rewiring layer is provided as a rewiring layer, the inorganic rewiring layer can be provided by performing processes such as forming an SiO2 layer as an inorganic insulating layer on the surface of the porous layer, patterning, forming a wiring layer, and planarizing by CMP. 14A and 14B show a process for forming an inorganic redistribution layer. The inorganic rewiring layer has an inorganic insulating layer 430 and wiring 440. Of the wiring 440, wiring 440a provided on the capacitor section 120 and wiring 440b provided on the extraction electrode section 140 become the cathode or anode of the capacitor section. Furthermore, the wiring 440c provided on the through-hole portion 110 among the wirings 440 serves as a connection electrode for the through-hole portion. The wiring 440a provided on the capacitor section 120 is preferably an aluminum electrode, and the wiring 440b and wiring 440c provided in other portions are preferably copper electrodes.

[0068] Subsequently, an organic rewiring layer is provided on the surface of the inorganic rewiring layer. When an organic rewiring layer is provided as the rewiring layer, the organic rewiring layer can be provided by carrying out processes such as forming a resin layer as an organic insulating layer on the surface of the inorganic rewiring layer, patterning, and forming a wiring layer. FIG. 14C shows a step of forming an organic redistribution layer. The organic rewiring layer includes an organic insulating layer 410 and wiring 420 . Through the above steps, the rewiring layer 400 including the inorganic rewiring layer and the organic rewiring layer is provided.

[0069] Next, openings are formed on the substrate side, and vias and insulating portions are formed in the openings. 14D shows that the substrate 300 has been ground to make it thinner, and that openings 301 have been formed at predetermined positions in the substrate 300. The openings can be formed in the substrate by etching the material of the substrate (typically silicon).

[0070] 14E, the SiO2 layer 340 and the conductor layers (Ti layer 510, Al layer 520, W layer 530) are etched from the position of the opening 301 to form an opening directly below the through-hole portion 110. Resin 550 is filled into the opening.

[0071] 14F, openings are formed in resin 550 and filled with via conductors 560. Via conductors 560 are connected to through-hole portions 110, and through-hole portions 110 are extended to the surface of substrate 300. The resin 550 provided in the steps up to this point becomes the first insulating portion 220 in the level of the conductor layer 200, and the second insulating portion 320 in the level of the substrate 300. The first insulating portion 220 and the second insulating portion 320 are integrated. Furthermore, the via conductor 560 becomes the first via portion 210 in the level of the conductor layer 200, and the second via portion 310 in the level of the substrate 300. The first via portion 210 and the second via portion 310 are integrated.

[0072] The interposer of the present invention is obtained through the above steps. Furthermore, the structure obtained by removing the rewiring layer from the obtained interposer is the capacitor-embedded sheet of the present invention. In other words, the interposer of the present invention equipped with the capacitor-embedded sheet of the present invention is obtained through the above steps.

[0073] As shown in FIG. 14G, via conductor 560 may be provided with UBM 570 (Under Bump Metal) to improve solder jointability.

[0074] In the above process, the through-holes and capacitors are formed in the substrate, the rewiring layer is provided, and then openings are formed in the substrate and the conductor layer to form the resin and via conductors (first vias, second vias, first insulating portions, and second insulating portions), but the order may be changed. That is, openings may be formed in the substrate and the conductor layer to form the resin and via conductors (first vias, second vias, first insulating portions, and second insulating portions), and then the through-holes and capacitors are formed in the substrate, and the rewiring layer is provided.

[0075] Next, examples of use of the capacitor-embedded sheet and interposer of the present invention will be described. [Usage example 1] FIG. 15 is a cross-sectional view schematically showing an example of use of a capacitor-embedded sheet and an interposer. 15 shows a mounting structure 601 in which, from the bottom, a motherboard 610, a package substrate 620, an interposer 21, and a semiconductor component 630 are stacked. The motherboard 610 and the package substrate 620 are connected by bumps 615, the package substrate 620 and the interposer 21 are connected by bumps 625, and the interposer 21 and the semiconductor component 630 are connected by bumps 635.

[0076] The interposer 21 has the capacitor-embedded sheet 9 including the lead electrode portion 140 described in FIG. 3 and the substrate 300 described in FIG. The anode 124 of the capacitor section 120 of the capacitor-embedded sheet 9 is drawn out onto the capacitor section 120, and the cathode 125 is drawn out onto the extraction electrode section 140 via the metal conductor 230. In other words, both the anode 124 and the cathode 125 of the capacitor section 120 are drawn out to the redistribution layer 400 side.

[0077] Since there is no package substrate between the interposer 21 having the capacitor portion and the semiconductor component 630 such as logic, the distance between the capacitor and the semiconductor component is short, and the ESL can be reduced, thereby improving the impedance characteristics in the high frequency range.

[0078] The first via portion 210 and the second via portion 310 are integrally provided directly below the through-hole portion 110 of the capacitor-embedded sheet 9, so that the through-hole portion 110 is drawn out to the substrate side. The second via portion 310 is connected to a bump 625 that is connected to the package substrate 620. That is, the conductor provided in the porous layer can be pulled out in the thickness direction and integrated with the power supply line on the substrate side.

[0079] [Usage example 2] FIG. 16 is a cross-sectional view schematically showing another example of use of a sheet with built-in capacitors and an interposer. The mounting structure 602 shown in Figure 16 has almost the same configuration as the mounting structure shown in Figure 15, but it has a bumpless connection structure in which bumps are not used to connect the package substrate 620 and the interposer 21. Since ESL is likely to occur at the bumps, bumpless connections can improve impedance characteristics. Furthermore, by not using bumps, the height of the entire mounting structure can be reduced, which contributes to a thinner profile.

[0080] [Usage example 3] FIG. 17 is a cross-sectional view schematically showing another example of use of a sheet with built-in capacitors and an interposer. The interposer 22 used in the mounting structure 603 shown in FIG. In the capacitor-embedded sheet 10, the anode 124 of the capacitor section 120 is extended above the capacitor section 120, and the cathode 125 is extended below the capacitor section 120 via the conductor layer 200. When the capacitor-embedded sheet and interposer of the present invention are used, such a mounting structure can be adopted, allowing for a high degree of freedom in design. The anode and cathode of the capacitor section 120 may be drawn out from different main surfaces, and if the anode and cathode are drawn out from different surfaces, it is easy to use as a coupling capacitor. Furthermore, in this capacitor-embedded sheet 10, there is no need to extract one electrode of the capacitor section 120 to the rewiring layer side, so the extraction electrode section 140 does not have to be provided.

[0081] [Usage example 4] FIG. 18 is a cross-sectional view schematically showing another example of use of a capacitor-embedded sheet and an interposer. In the mounting structure 604 shown in Fig. 18, the interposer 21 is used in an upside-down orientation compared to the mounting structure shown in Fig. 15. That is, the redistribution layer 400 is located on the package substrate 620 side, and the capacitor-embedded sheet 9 is located on the semiconductor component 630 side. Although not shown, an interposer may be formed by providing rewiring layers on both sides of the capacitor-embedded sheet. In this case, the structure is [semiconductor component - (rewiring layer - capacitor-embedded sheet - rewiring layer) - package substrate]. The (rewiring layer - capacitor-embedded sheet - rewiring layer) portion is the interposer. When the capacitor-embedded sheet and interposer of the present invention are used, such a mounting structure can be adopted, allowing for a high degree of freedom in design.

[0082] [Semiconductor element] Next, an example of the semiconductor element of the present invention will be described. The semiconductor element of the present invention is an integrated device that includes at least the capacitor-embedded sheet of the present invention and a semiconductor portion. The capacitor-embedded sheet and the semiconductor portion are preferably integrated via a rewiring layer. FIG. 19 is a cross-sectional view schematically showing an example of a semiconductor element of the present invention.

[0083] 19 includes a portion (arithmetic unit) having a function of performing calculations as a semiconductor unit 710, and an interposer 21. The interposer 21 includes a capacitor-embedded sheet 9 including extraction electrode portions 140 and substrate 300, and a rewiring layer 400, as described in Usage Example 1. The wiring 420 of the rewiring layer of the interposer 21 and the electrodes of the semiconductor section 710 are connected and sealed together to form an integrated element. The semiconductor element 700 shown in Fig. 19 does not have connection parts such as solder bumps, and the wiring 420 of the rewiring layer 400 and the electrodes of the semiconductor section 710 form a continuous laminated structure. In other words, the structure of the interposer of the present invention is partially included within the semiconductor element 700, which is a single element.

[0084] The semiconductor element of the present invention also includes a structure different from that of the semiconductor element 700 shown in Figure 19, in which the interposer and the semiconductor portion are connected with microbumps between them, and the interposer and the semiconductor portion are sealed together and integrated. Also included is a configuration that does not include a rewiring layer, but includes a capacitor-embedded sheet and a semiconductor portion, in which the capacitor-embedded sheet and the semiconductor portion are directly connected and sealed together to form an integrated unit.

[0085] The functions of the semiconductor section include a calculation section (logic), a storage section (memory), and a control section, and the functions are not particularly limited.

[0086] The present specification discloses the following:

[0087] <1> a conductive layer and a porous layer provided on the conductive layer, The porous layer is a capacitor portion having a structure of a metal layer-dielectric layer-metal layer provided in the porous structure of the porous layer; a through-hole portion in which a conductor is filled in the porous structure of the porous layer; a porous insulating portion provided around the through-hole portion, the porous structure of which is not filled with a conductor; The conductor layer is a metal conductor; a first via portion that penetrates a metal conductor directly below the through-hole portion and is connected to the through-hole portion; a first insulating portion provided around the first via portion and insulating the first via portion from the metal conductor; Seat with built-in capacitor.

[0088] <2> the metal conductor is connected to one of the metal layers of the capacitor section; the porous layer further includes an extraction electrode portion having a porous structure filled with a conductor and connected at a bottom thereof to the metal conductor of the conductor layer; <1> The capacitor-embedded sheet according to claim 1.

[0089] <3> a columnar metal electrode, the columnar metal electrode being connected at its bottom to the metal conductor of the conductor layer, at the same level as the porous layer; <1> or <2> The capacitor-embedded sheet according to claim 1.

[0090] <4> the porous layer includes a plurality of capacitor portions; the metal conductor is connected to one of the metal layers of each of the capacitor units; the conductor layer further includes a third insulating section that insulates between the metal conductors connected to different capacitor sections; <1> ~ <3> 10. The capacitor-embedded sheet according to claim 9, wherein

[0091] <5> a substrate on which the conductor layer rests; The substrate is A substrate; a second via portion that penetrates the substrate directly below the first via portion and is integrated with the first via portion; a second insulating portion provided around the second via portion and integrated with the first insulating portion, <1> ~ <4> 10. The capacitor-embedded sheet according to claim 9, wherein

[0092] <6> Further, an insulating layer is provided between the substrate and the conductor layer. <5> The capacitor-embedded sheet according to claim 1.

[0093] <7> The substrate is an insulator. <5> The capacitor-embedded sheet according to claim 1.

[0094] <8> A part of the first insulating portion penetrates into the porous layer adjacent to the first insulating portion. <1> ~ <7> 10. The capacitor-embedded sheet according to claim 9, wherein

[0095] <9> A part of the first via portion extends into the porous layer adjacent to the first via portion. <1> ~ <8> 10. The capacitor-embedded sheet according to claim 9, wherein

[0096] <10> <1> ~ <9> a capacitor-embedded sheet according to any one of the above items; a redistribution layer disposed on at least one main surface of the capacitor-embedded sheet.

[0097] <11> The redistribution layer comprises an organic insulating layer. <10> The interposer according to claim 1.

[0098] <12> A part of the redistribution layer penetrates into the porous layer adjacent to the redistribution layer. <10> or <11> The interposer according to claim 1.

[0099] <13> <1> ~ <9> 10. A semiconductor element integrated with at least the capacitor-embedded sheet according to any one of claims 1 to 9 and a semiconductor portion.

[0100] <14> <1> ~ <9> The capacitor-embedded sheet according to any one of claims 1 to 4, and the semiconductor portion are integrated via a rewiring layer. <13> The semiconductor element according to claim 1. [Explanation of symbols]

[0101] 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 Capacitor built-in sheet 20, 21, 22 Interposer 100 Porous layer 101 Porous structure 101a Porous wall 102 Main surface of the porous layer on the conductive layer side 103 Surface of porous layer (main surface of porous layer opposite to conductor layer (substrate)) 104 First mask (mask on the surface of the porous layer) 105 Second mask (mask on the surface of the porous layer) 110 Through-hole section 111 Conductor 120, 120a, 120b capacitor section 121 Metal layer 122 Dielectric layer 123 Metal layer 124 Capacitor anode 125 Capacitor cathode 130 Porous insulation part 140 Extraction electrode part (porous structure) 150 Columnar metal electrode (dense metal) 200 Conductor Layer 202 Main surface of the conductor layer on the porous layer side 203 Main surface of the conductor layer opposite to the porous layer 210 First Via Section 220 First Insulation Section 230, 230a, 230b Metal conductors 240 Third Insulation Section 300 boards 301 Opening in the board 303 Main surface opposite to the porous layer of the substrate 310 2nd Via Section 320 Second Insulation Section 330 Base material 340 SiO2 layer 350 Resin layer on the substrate side 360 Third Beer Section 400 redistribution layer 410 Organic insulating layer 420 Wiring 430 Inorganic insulating layer 440, 440a, 440b, 440c wiring 510 Ti layer 520 Al layer 530W layer 540 Al layer 550 Resin 560 via conductor 570 UBM 601, 602, 603, 604 Mounting structure 610 motherboard 615 Bump 620 package substrate 625 Bump 630 Semiconductor parts 635 Bump 700 Semiconductor elements 710 Semiconductor Department

Claims

1. a conductive layer and a porous layer provided on the conductive layer, The porous layer is a capacitor portion having a metal layer-dielectric layer-metal layer structure provided in a porous structure made of an insulator of the porous layer; a through-hole portion in which a conductor is filled in the porous structure made of the insulator of the porous layer; a porous insulating portion provided around the through-hole portion, the porous structure being made of the insulator and not filled with a conductor; The conductor layer is a metal conductor; a first via portion that penetrates a metal conductor directly below the through-hole portion and is connected to the through-hole portion; a first insulating portion provided around the first via portion and insulating the first via portion from the metal conductor; Seat with built-in capacitor.

2. a conductive layer and a porous layer provided on the conductive layer, The porous layer is a capacitor portion having a metal layer-dielectric layer-metal layer structure provided in a porous structure made of an insulator of the porous layer; a through-hole portion in which a conductor is filled in the porous structure made of the insulator of the porous layer; a porous insulating portion provided around the through-hole portion, the porous structure being made of the insulator and having nothing filled therein; The conductor layer is a metal conductor; a first via portion that penetrates a metal conductor directly below the through-hole portion and is connected to the through-hole portion; a first insulating portion provided around the first via portion and insulating the first via portion from the metal conductor; Seat with built-in capacitor.

3. the metal conductor is connected to one of the metal layers of the capacitor section; 3. The capacitor-embedded sheet according to claim 1, wherein the porous layer has a conductor filled in the porous structure made of the insulator of the porous layer, and further comprises an extraction electrode portion connected at the bottom to the metal conductor of the conductor layer.

4. 3. The capacitor-embedded sheet according to claim 1, further comprising, in the same layer as the porous layer, columnar metal electrodes connected at their bottoms to the metal conductors of the conductor layer.

5. the porous layer includes a plurality of capacitor portions; the metal conductor is connected to one of the metal layers of each of the capacitor units; The capacitor-embedded sheet according to claim 1 , wherein the conductor layer further comprises a third insulating portion that insulates between the metal conductors connected to different capacitor portions.

6. a substrate on which the conductor layer rests; The substrate is A substrate; a second via portion that penetrates the substrate directly below the first via portion and is integrated with the first via portion; The capacitor-embedded sheet according to claim 1 , further comprising: a second insulating portion provided around the second via portion and integrated with the first insulating portion.

7. The capacitor-embedded sheet according to claim 6 , further comprising an insulating layer between the substrate and the conductor layer.

8. The capacitor-embedded sheet according to claim 6, wherein the substrate is an insulator.

9. The capacitor-embedded sheet according to claim 1 , wherein the first insulating portion and the first via portion are adjacent to each other directly below the porous insulating portion.

10. The capacitor-embedded sheet according to claim 2 , wherein the first insulating portion and the first via portion are adjacent to each other directly below the porous insulating portion.

11. 11. The capacitor-embedded sheet according to claim 2, wherein a part of the first insulating portion penetrates into the porous insulating portion adjacent to the first insulating portion.

12. 11. The capacitor-embedded sheet according to claim 2, wherein a part of the first via portion penetrates into the porous insulating portion adjacent to the first via portion.

13. The capacitor-embedded sheet according to claim 1 or 2; a rewiring layer disposed on at least one main surface of the capacitor-embedded sheet, an interposer, wherein the through-hole portion of the capacitor-embedded sheet and the rewiring layer are connected to each other;

14. The interposer of claim 13 , wherein the redistribution layer comprises an organic insulating layer.

15. The capacitor-embedded sheet according to claim 2 or 10; a rewiring layer having an organic insulating layer and disposed on at least one main surface of the capacitor-embedded sheet, a part of the redistribution layer penetrates into the porous insulating portion adjacent to the redistribution layer; an interposer, wherein the through-hole portion of the capacitor-embedded sheet and the rewiring layer are connected to each other;

16. 3. A semiconductor element integrated with at least the capacitor-embedded sheet according to claim 1 or 2 and a semiconductor portion.

17. The semiconductor device according to claim 16 , wherein the through-hole portion and the semiconductor portion of the capacitor-embedded sheet are integrated via a rewiring layer.

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