Semiconductor Devices

Abstract

To diminish consumption power.SOLUTION: A semiconductor device comprises a sensor circuit having a sensor element, a power management device and an arithmetic processing circuit, the power management device having a function to control the power feed to the arithmetic processing circuit, the arithmetic processing circuit having a first circuit having a first storage circuit and a second circuit having a second storage circuit, the first circuit having a function to hold first data on the first storage circuit in a duration of power feed to the arithmetic processing circuit, the second circuit having a function to read out the first data held on the first storage circuit and write it to the second storage circuit in the duration of power feed to the arithmetic processing circuit and a function to hold the first data on the second storage circuit in the duration of suspension of power feed to the arithmetic processing circuit, the sensor circuit having a function to determine a detection signal of the sensor element and give second data to the power management device in accordance with a determination result, the power management device having a function to resume or stop the power feed to the arithmetic processing circuit in accordance with the second data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD One aspect of the present invention relates to a semiconductor device or a control system.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Alternatively, one aspect of the present invention relates to a method for controlling a semiconductor device, a method for controlling a system including a semiconductor device, or the like.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] Portable information terminals such as smartphones and tablet devices are becoming increasingly popular. As information terminals become more popular, various communication standards have been established. For example, the LTE-Advanced standard, also known as the fourth generation mobile communication system (4G), has begun operation.

[0005] In recent years, advances in information technology, such as the Internet of Things (IoT), have led to an increase in the amount of data handled by information terminals. In addition, there is a demand for improved communication speeds for electronic devices such as information terminals.

[0006] To accommodate various information technologies such as IoT, a new communication standard called the fifth-generation mobile communication system (5G) is being considered, which will achieve faster communication speeds, more simultaneous connections, and shorter latency than 4G. 5G will use communication frequencies in the 3.7 GHz, 4.5 GHz, and 28 GHz bands.

[0007] 5G-compatible semiconductor devices are made using semiconductors that use a single element, such as Si, as their main component, or compound semiconductors that use multiple elements, such as Ga and As, as their main components. Furthermore, oxide semiconductors, a type of metal oxide, are attracting attention.

[0008] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0009] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

[0010] Also, known techniques for reducing power consumption in semiconductor devices include, for example, power gating (PG), clock gating (CG), voltage scaling, etc. For example, Patent Document 1 describes implementing a method that is advantageous for reducing power consumption out of the DVFS (Dynamic Voltage and Frequency Scaling) method and the PG method. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] International Publication No. 2009 / 078081 [Non-patent literature]

[0012] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0013] An object of one embodiment of the present invention is to provide a novel semiconductor device or a method for operating the novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel system including a semiconductor device or a method for operating the novel system including a semiconductor device. Another object of one embodiment of the present invention is to reduce power consumption, for example, to reduce power consumption in a hibernation state. Another object of one embodiment of the present invention is to shorten the time required for returning from a hibernation state to a normal state or to reduce the energy required for the process. Another object of one embodiment of the present invention is to reduce power consumption of a circuit that controls a sensor element. Another object of one embodiment of the present invention is to improve the safety of an object monitored by a sensor element. Another object of one embodiment of the present invention is to provide a system that easily monitors an object. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a control circuit with low power consumption. Another object of one embodiment of the present invention is to provide a highly safe system.

[0014] The description of multiple problems does not preclude the existence of each other. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than those listed will become apparent from the description in the specification, drawings, claims, etc., and these problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0015] One embodiment of the present invention is a semiconductor device including a sensor circuit, a power management device, and an arithmetic processing circuit, wherein the sensor circuit has a sensor element, and the power management device has a function of controlling power supply to the arithmetic processing circuit, and the arithmetic processing circuit has a first circuit having a first memory circuit and a second circuit having a second memory circuit, wherein the first circuit has a function of retaining first data while power is being supplied to the arithmetic processing circuit, and the second circuit has a function of reading the first data retained in the first memory circuit and writing it to the second memory circuit while power is being supplied to the arithmetic processing circuit, and a function of retaining the first data in the second memory circuit while power supply to the arithmetic processing circuit is stopped, the sensor circuit has a function of determining a detection signal of the sensor element and providing second data to the power management device in accordance with the determination result, and the power management device has a function of resuming or stopping power supply to the arithmetic processing circuit in accordance with the second data. The supply of power to the circuit is, for example, supplying power to the circuit.

[0016] In the above-described configuration, it is preferable that the second circuit has a function of reading the first data from the second storage circuit and providing the first data to the first storage circuit after power supply to the arithmetic processing circuit is resumed.

[0017] In the above configuration, it is preferable that the power management device has a function of supplying power from the secondary battery to the arithmetic processing circuit, and the arithmetic processing circuit has a modulation circuit and a demodulation circuit.

[0018] In addition, in the above configuration, it is preferable that the sensor element has the function of measuring one or more selected from force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared rays.

[0019] Alternatively, one embodiment of the present invention is a semiconductor device including a sensor circuit, a power management device, and an arithmetic processing circuit. The sensor circuit includes an acceleration sensor. The power management device has a function of controlling power supply to the arithmetic processing circuit. The arithmetic processing circuit includes a first circuit having a first memory circuit and a second circuit having a second memory circuit. The first circuit has a function of holding first data in the first memory circuit while power is being supplied to the arithmetic processing circuit. The second circuit has a function of reading the first data held in the first memory circuit and writing the data to the second memory circuit while power is being supplied to the arithmetic processing circuit, and a function of holding the first data in the second memory circuit while power supply to the arithmetic processing circuit is stopped. The sensor circuit has a function of determining a detection signal from the acceleration sensor and providing second data to the power management device in accordance with a result of the determination. The power management device has a function of resuming or stopping power supply to the arithmetic processing circuit in accordance with the second data.

[0020] Alternatively, one embodiment of the present invention is a control system including the semiconductor device described above and a control device, wherein the acceleration sensor has a function of detecting vibration of an object, the control device has a function of controlling the object, the sensor circuit has a function of judging a detection signal of the acceleration sensor and, if it determines that the acceleration sensor has detected abnormal vibration of the object, resuming power supply to the arithmetic processing circuit, the arithmetic processing circuit has a function of analyzing the detection signal of the acceleration sensor upon resumption of power supply and providing third data to the control device in accordance with the analysis result, and the control device has a function of controlling the object in accordance with the second data.

[0021] In the above structure, it is preferable that the semiconductor device includes an antenna, the arithmetic processing circuit includes a modulation circuit and a demodulation circuit, and the third data is provided from the semiconductor device to the control device by wireless communication.

[0022] In the above structure, the semiconductor device preferably includes a secondary battery, and the power management device preferably has a function of supplying power from the secondary battery to the arithmetic processing circuit. [Effects of the Invention]

[0023] One embodiment of the present invention makes it possible to provide a novel semiconductor device or a method for operating the novel semiconductor device. Another embodiment of the present invention makes it possible to provide a novel system including the semiconductor device or a method for operating the novel system including the semiconductor device. Another embodiment of the present invention makes it possible to reduce power consumption, for example, power consumption in a hibernation state. Another embodiment of the present invention makes it possible to shorten the time required for a process of returning from a hibernation state to a normal state or to reduce the energy required for the process. Another embodiment of the present invention makes it possible to reduce power consumption of a circuit that controls a sensor element. Another embodiment of the present invention makes it possible to improve the safety of an object monitored by a sensor element. Another embodiment of the present invention makes it possible to provide a system that easily monitors an object. Another embodiment of the present invention makes it possible to provide a semiconductor device with low power consumption. Another embodiment of the present invention makes it possible to provide a control circuit with low power consumption. Another embodiment of the present invention makes it possible to provide a highly safe system.

[0024] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are block diagrams illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 5] FIG. 5 is a flow chart illustrating an example of the operation of the semiconductor device. [Figure 6] Fig. 6A is a diagram showing an example of the configuration of a semiconductor device, Fig. 6B is a diagram showing an example of a plurality of semiconductor devices controlled by a control device, and Fig. 6C is a diagram showing an example of a plurality of semiconductor devices and a plurality of objects controlled by a control device. [Figure 7] 7A, 7B, and 7C illustrate an example of the circuit configuration of one embodiment of the present invention. [Figure 8] 8A and 8B are block diagrams showing configuration examples of a semiconductor device. [Figure 9] 9A to 9D are diagrams illustrating an example of the operation of power management of a semiconductor device. [Figure 10] FIG. 10 is a flowchart showing an example of the power management operation of the semiconductor device. [Figure 11] 11A and 11B are block diagrams showing configuration examples of a semiconductor device. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of a processor core. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of a memory circuit. [Figure 14] FIG. 14 is a timing chart illustrating an example of the operation of the memory circuit. [Figure 15] FIG. 15 is a circuit diagram showing an example of the configuration of a memory cell of a cache. [Figure 16] FIG. 16 is a timing chart illustrating an example of the operation of the memory cell. [Figure 17] 17A is a functional block diagram showing an example of the configuration of a NOSRAM, and FIG. 17B is a circuit diagram showing an example of the configuration of a memory cell. [Figure 18] Fig. 18A is a circuit diagram showing an example of the configuration of a memory cell array, and Fig. 18B and Fig. 18C are circuit diagrams showing an example of the configuration of a memory cell. [Figure 19] Fig. 19A is a circuit diagram showing an example of the configuration of a memory cell of a DOSRAM, and Fig. 19B is a diagram showing an example of a stacked structure of a DOSRAM. [Figure 20] 20A and 20B are diagrams illustrating an example of the configuration of a neural network. [Figure 21] FIG. 21 is a diagram illustrating a configuration example of a semiconductor device. [Figure 22] FIG. 22 is a diagram showing an example of the configuration of a memory cell. [Figure 23] FIG. 23 is a diagram illustrating an example of the configuration of the offset circuit. [Figure 24] FIG. 24 is a timing chart. [Figure 25] FIG. 25 is a diagram illustrating a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a diagram illustrating a configuration example of a semiconductor device. [Figure 27] 27A to 27C are diagrams showing examples of the configuration of a transistor. [Figure 28] 28A to 28C are diagrams showing examples of the configuration of a transistor. [Figure 29] 29A to 29C are diagrams showing examples of the configuration of a transistor. [Figure 30] Figure 30A is a diagram explaining the classification of IGZO crystal structures, Figure 30B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 30C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 31] Figure 31A is a top view of a semiconductor wafer, and Figure 31B is a top view of a chip. [Figure 32]Fig. 32A is a flowchart illustrating an example of a manufacturing process for an electronic component, and Fig. 32B is a perspective schematic view of the electronic component. [Figure 33] FIG. 33 is a diagram showing an example of an electronic device. [Figure 34] 34A to 34F are diagrams showing an example of an electronic device. [Figure 35] FIG. 35 is a photograph of a semiconductor device and a number of housings. [Figure 36] Figure 36A is a photograph of the semiconductor device, and Figure 36B is a photograph of the semiconductor device. [Figure 37] Figure 37A shows the acceleration measurement results, and Figure 37B shows the fast Fourier transform results. [Figure 38] Figure 38A shows the acceleration measurement results, and Figure 38B shows the fast Fourier transform results. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0027] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0028] In addition, in top views (also called "plan views"), perspective views, and the like, some components may be omitted to make the drawings easier to understand.

[0029] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0030] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0031] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0032] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0033] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0034] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0035] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0036] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0037] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0038] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0039] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0040] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0041] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0042] In this specification, a high power supply potential (hereinafter referred to as "power supply potential VDD," "VDD," "H potential," or "H") refers to a power supply potential that is higher than a low power supply potential (hereinafter referred to as "power supply potential VSS," "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is ground potential, VSS is a potential lower than ground potential, and when VSS is ground potential, VDD is a potential higher than ground potential.

[0043] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0044] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0045] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0046] In addition, in drawings, etc., to make the potential of wiring, electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written next to the transistor.

[0047] A terminal may refer to a group of multiple terminals. For example, an independent signal is applied to each terminal of the group of multiple terminals, and one or more wires are electrically connected to each terminal.

[0048] A transistor has three terminals (nodes) called a gate, a source, and a drain. The gate is a terminal that functions as a control terminal that controls the conduction state of the transistor. Of a pair of input / output terminals (nodes) that function as a source or a drain, one becomes the source and the other becomes the drain depending on the type of transistor and the level of the potential applied to each terminal (node). Generally, in an n-type transistor, the node to which a low potential is applied is called the source, and the node to which a high potential is applied is called the drain. Conversely, in a p-type transistor, the node to which a low potential is applied is called the drain, and the node to which a high potential is applied is called the source. In this specification, the two terminals (nodes) other than the gate may be called the first terminal (node) and the second terminal (node).

[0049] In this specification, in order to facilitate understanding of the circuit configuration and its operation, one of the two input / output terminals (nodes) of a transistor may be limited to the source and the other to the drain. Of course, depending on the driving method, the magnitude relationship between the potentials applied to the three terminals of the transistor may change, and the source and drain may be interchanged. Therefore, in one embodiment of the present invention, the distinction between the source and drain of a transistor is not limited to the description in the specification and drawings.

[0050] In this specification, etc., a person skilled in the art may be able to construct an embodiment of an invention without specifying the connection destinations of all terminals of active elements (e.g., transistors, diodes, etc.) and passive elements (e.g., capacitance elements, resistance elements, etc.). In other words, it can be said that an embodiment of an invention is clear even without specifying the connection destinations. Furthermore, when an embodiment in which the connection destinations are specified is described in this specification, etc., it may be possible to determine that an embodiment of an invention in which the connection destinations are not specified is also described in this specification. In particular, when there are multiple possible connection destinations for a terminal, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, it may be possible to construct an embodiment of an invention by specifying the connection destinations of only some of the terminals of active elements (e.g., transistors, diodes, etc.) and passive elements (e.g., capacitance elements, resistance elements, etc.).

[0051] In this specification, etc., a person skilled in the art may be able to identify an invention by at least specifying the connection destination of a certain circuit. Alternatively, a person skilled in the art may be able to identify an invention by at least specifying the function of a certain circuit. In other words, if the function can be identified, it can be said that the aspect of the invention is clear. It may then be possible to determine that one aspect of the invention with a specified function is described in this specification, etc. Therefore, if the connection destination of a certain circuit is specified even without specifying the function, one aspect of the invention is disclosed and can constitute one aspect of the invention. Alternatively, if the function of a certain circuit is specified even without specifying the connection destination, one aspect of the invention is disclosed and can constitute one aspect of the invention.

[0052] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and application examples of the semiconductor device will be described.

[0053] <Configuration example of semiconductor device> The semiconductor device 700 shown in FIG. 1 includes a processing unit (PU) 21, a sensor circuit 301, and a power supply circuit 10.

[0054] The PU21 has terminals 80, 81, 82, 83, 92, and 94. The PU21 has a function of executing instructions included in a program or the like. The PU21 can significantly reduce power consumption in a hibernation state by using a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor). The time required to return from the hibernation state to the normal state can also be significantly shortened. Details of the PU21 will be described later. Alternatively, the PU20, which will be described later, may be used instead of the PU21. As will be described later, the PU20 and PU21 each have a processor core, a power management unit, a clock control circuit, a power switch, and the like. The processor core is a circuit capable of processing instructions and can be called an arithmetic processing circuit.

[0055] The sensor circuit 301 includes a sensor element 710 , a detection unit 711 , a terminal 90 , a terminal 91 , and a terminal 93 .

[0056] The sensor circuit 301 has a function of providing a signal based on the detection result of the sensor element 710 to the PU 21. The PU 21 has a function of processing commands using the signal provided from the sensor circuit 301. The PU 21 also has a function of providing control signals for controlling each circuit included in the sensor circuit 301.

[0057] The sensor circuit 301 may also include either or both of a determination circuit 712 and an analog-to-digital conversion circuit 713 .

[0058] A signal detected by the sensor element 710 is provided to a detection unit 711. The detection unit 711 has a function of providing the detection signal provided from the sensor element 710 to a terminal 91 and to various circuits such as a determination circuit 712 and an analog-to-digital conversion circuit 713. The detection signal provided to the terminal 91 is provided from the terminal 91 to a terminal 92 of the PU 21. The detection unit 711 may perform processing such as amplification and compression on the detection signal beforehand, and then provide the processed detection signal to various circuits or terminals.

[0059] The sensor element 710 preferably has the capability to measure one or more of force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared light.

[0060] The sensor element 710 is capable of measuring a parameter indicative of the state of the object 799 .

[0061] The PU 21 preferably has a function of providing a control signal to the object 799. The PU 21 may be electrically connected to the object 799. The PU 21 may also have a function of providing a control signal to the object 799 wirelessly.

[0062] The sensor element 710 included in the semiconductor device 700 may or may not be electrically connected to the object 799 .

[0063] The semiconductor device 700 is preferably placed so as to be in contact with the object 799, for example. Alternatively, it is preferably installed in the vicinity of the object 799. The distance between the semiconductor device 700 and the object 799 may be determined depending on the range in which a signal can be detected. For example, when detecting vibrations of the object 799, the semiconductor device 700 is preferably placed so as to be in contact with the object 799. Alternatively, it is preferably placed at a distance of 5 mm or less. For example, when detection data is provided from the object 799 to the semiconductor device 700 by wireless communication, the semiconductor device 700 may be placed within a range in which wireless communication is possible.

[0064] The semiconductor device 700 can monitor a signal detected by the sensor element 710 .

[0065] Signal monitoring, for example, refers to comparing a detected signal with reference data. Alternatively, signal monitoring, for example, refers to determining whether a detected signal deviates from a desired range. Determining whether a detected signal deviates from a desired range can be performed, for example, by comparing the detected signal with reference data. Alternatively, for example, feature amounts of a detected waveform, more specifically, frequency components, can be extracted and analyzed.

[0066] The reference data can be stored in a memory included in the semiconductor device 700. For example, it is stored in a cache included in the PU 21. By providing a backup circuit using OS transistors in the cache and saving the data, the data can be retained for a long time even if the power supply or clock signal is cut off. Furthermore, after the power supply is resumed, the saved data can be restored quickly. Details of the cache and the backup circuit will be described later.

[0067] The detected signals can also be stored in a cache.

[0068] Furthermore, during the monitoring process, the detection signal is verified, and a control signal according to the verification result is given from PU 21 to object 799. Depending on the given control signal, object 799, for example, continues to operate, restricts its operation, or stops its operation.

[0069] The PU 21 may also have a neural network. Signals may be monitored and verified by calculations using the neural network. The neural network may be trained in the PU 21, or the results of prior training may be stored in the memory of the PU 21.

[0070] For example, abnormal waveforms are learned as training data, and the detected signals are analyzed using a neural network.

[0071] An example of the configuration of the neural network will be described in detail later.

[0072] Furthermore, it is not necessary to constantly monitor the detection signal, and power gating of the processor core of the PU 21 can be performed during periods when monitoring is not performed, putting the PU 21 into a sleep state and reducing power consumption.

[0073] When the PU 21 is in a dormant state, the sensor circuit 301 may also be in a dormant state. Specifically, for example, the power supply from the power supply circuit 10 is stopped.

[0074] Alternatively, when the PU 21 is in the sleep state, the sensor circuit 301 may be in the normal state. As will be described later, a signal can be given from the sensor circuit 301 to return the PU 21 from the sleep state to the normal state.

[0075] The sensor circuit 301 preferably also includes a determination circuit 712. The determination circuit 712 determines the signal from the sensor element 710. For example, the determination circuit 712 compares the signal from the sensor element 710 with desired data. An example of an abnormality detected by the determination circuit 712 is when the signal detected by the sensor element 710 has a value outside a desired range.

[0076] During the period when the sensor element 710 of the sensor circuit 301 is performing detection, a save sequence can be executed, power gating can be performed on the processor core etc. of the PU 21, and the PU 21 can be put into a sleep state.

[0077] The PU21 determines whether to return from the pause state to the normal state based on the determination result of the determination circuit 712. More specifically, for example, if the determination circuit 712 determines that the signal from the sensor element 710 given to the detection unit 711 is abnormal, the determination circuit 712 gives a signal INT, which is a signal requesting interrupt processing, to the terminal 82. The signal INT causes the PU21 to return to the normal state and start monitoring the detection signal from the detection unit 711.

[0078] The PU 21 according to one embodiment of the present invention can shorten the time required to return from the sleep state to the normal state. In other words, the PU 21 can be quickly restored from the time when the determination circuit 712 detects an abnormality, and signal detection can be started quickly. Therefore, an abnormality signal can be acquired even if the abnormality occurs for a short period of time.

[0079] The sensor circuit 301 may include an analog-to-digital conversion circuit 713. The analog-to-digital conversion circuit 713 converts an analog signal from the sensor element 710 and applied to the detection unit 711 into a digital signal, and applies the digital signal to the determination circuit 712 and the terminal 91. The signal applied to the terminal 91 is applied to the terminal 92 of the PU 21.

[0080] The PU 21 may have an analog-to-digital conversion circuit. The signal provided from the sensor circuit 301 may be processed by an analog-to-digital conversion circuit included in the PU 21.

[0081] The detection unit 711 may include a sample-and-hold circuit 714. The sample-and-hold circuit has a function of holding a signal detected by the sensor element 710. An example of the sample-and-hold circuit 714 using an OS transistor will be described later.

[0082] The sensor circuit 301 may include a memory 715. By configuring the memory 715 using OS transistors, a memory that can be read quickly and retain data for a long time can be realized. An example of a memory configured using OS transistors will be described later.

[0083] The PU21 preferably has a function of providing control signals for controlling circuits such as the sensor element 710, the detection unit 711, the determination circuit 712, the analog-to-digital conversion circuit 713, the sample-and-hold circuit 714, and the memory 715 of the sensor circuit 301. The signals are provided, for example, from a terminal 94 of the PU21 to a terminal 93 of the sensor circuit 301, and then from the terminal 93 to each circuit.

[0084] The terminal 90 is a terminal through which power is supplied from the power supply circuit 10 to the sensor circuit 301 .

[0085] Using a secondary battery as the power supply for the power supply circuit 10 facilitates integration with the PU 21 and the sensor circuit 301. Furthermore, since the power consumption of the PU 21 is reduced by putting it into a sleep state, the capacity of the secondary battery can be reduced. Because integration is easy and the capacity of the secondary battery can be reduced, the semiconductor device 700 can be made smaller.

[0086] The semiconductor device of one embodiment of the present invention is small and consumes low power, and therefore can be easily installed on various objects.

[0087] The semiconductor device of one embodiment of the present invention preferably has a function of performing wireless communication using Bluetooth (registered trademark), Wi-Fi (registered trademark), 4G, 5G, or the like.

[0088] 2A, the PU 21 includes a communication circuit 402. The communication circuit 402 has a function of modulating a signal, a function of demodulating a signal, etc. The communication circuit 402 is electrically connected to an antenna 401.

[0089] 2B shows an example in which semiconductor devices 700 having a function of performing wireless communication are installed on a plurality of objects 799, respectively. A control device 717 shown in FIG. 2B can wirelessly transmit and receive signals to and from the plurality of installed semiconductor devices 700. Each semiconductor device 700 can perform wireless communication with the control device 717 using the antenna 401 described above. When performing wireless communication, wiring between the control device 717 and the semiconductor device 700 is not required, which increases the degree of freedom in installing the semiconductor devices 700 and also makes it easy to collectively control the plurality of semiconductor devices 700 using one control device 717.

[0090] If the power supply circuit 10 mounted on the semiconductor device 700 has a secondary battery, the secondary battery may be charged by wireless power supply.

[0091] The semiconductor device 700 may have a plurality of sensor circuits 301. Fig. 3 shows an example in which the semiconductor device 700 has two sensor circuits 301 (hereinafter referred to as sensor circuit 301a and sensor circuit 301b). The symbols of the circuits, terminals, etc. of the sensor circuit 301a are suffixed with "a," and the symbols of the circuits, terminals, etc. of the sensor circuit 301b are suffixed with "b."

[0092] A control signal is supplied from terminal 94 of PU21 to each circuit of sensor circuit 301a via terminal 93a and to each circuit of sensor circuit 301b via terminal 93b. A signal from detection unit 711a and analog-to-digital conversion circuit 713a is supplied to terminal 94 via terminal 93a, and a signal from detection unit 711b and analog-to-digital conversion circuit 713b is supplied to terminal 94 via terminal 93b.

[0093] A signal INT, which is a signal requesting interrupt processing, is applied to a terminal 82 from each of the decision circuits 712a and 712b.

[0094] The sensor circuit 301 may also have a plurality of sensor elements 710. Fig. 4 shows an example in which the sensor circuit 301 has two sensor elements 710 (hereinafter referred to as sensor element 710c and sensor element 710d).

[0095] The detection signals of sensor element 710c and sensor element 710d are supplied to detection unit 711. Fig. 4 shows an example in which detection unit 711 has two sample and hold circuits 714 (hereinafter referred to as sample and hold circuit 714c and sample and hold circuit 714d), and the detection signal of sensor element 710c is supplied to sample and hold circuit 714c, and the detection signal of sensor element 710d is supplied to sample and hold circuit 714d.

[0096] <Example of semiconductor device operation> Next, an operation example of the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0097] Steps S000 to S009 are steps for explaining the operation of the PU 21, and steps S100 to S106 are steps for explaining the operation of the sensor circuit 301.

[0098] First, steps S000 to S009 and steps S100 to S101 will be described.

[0099] In step S000, the processing of the PU 21 is started, and in step S100, the processing of the sensor circuit 301 is started.

[0100] In step S001, a data request signal is sent from the PU 21 to the sensor circuit 301. In step S101, a first signal is sent from the sensor circuit 301 to the PU 21. The first signal is a signal obtained by processing the detection signal of the sensor element 710 by the detection unit 711, the analog-to-digital conversion circuit 713, etc.

[0101] Next, in step S002, the first signal is processed. Examples of signal processing include extraction of frequency components, noise removal, Fourier transform, waveform differentiation, etc. Note that the process may proceed to step S003 without performing step S002.

[0102] Next, in step S003, the processed signal is analyzed. For example, the signal is compared with reference data. Alternatively, for example, statistical processing of the signal is performed. For example, the maximum value, minimum value, median value, average value, standard deviation, etc. are calculated and compared with reference data. Alternatively, for example, analysis using a neural network is performed.

[0103] Next, in step S004, if an abnormality is detected as a result of the analysis in step S003, the process proceeds to step S009, and if not, the process proceeds to step S005.

[0104] In step S009, the operation of the object is controlled. For example, a signal informing the control device 717 of the abnormality is sent, and the control device 717 controls the operation of the object. Furthermore, the abnormality may be indicated by an indicator in the semiconductor device 700 or the control device 717. Examples of indicators include lighting or blinking lamps, inputting a message on a display screen, sounding an alarm, etc.

[0105] In step S005, the PU 21 transitions to a sleep state.

[0106] Next, in step S006, if the PU 21 does not receive an interrupt signal, the process proceeds to step S007. If the PU 21 receives an interrupt signal, the process proceeds to step S008, where the PU 21 returns to the normal state, and the process returns to step S001.

[0107] In step S007, if a certain time has passed since step S005, the process proceeds to step S008, where the PU 21 returns to the normal state and the process returns to step S001. If the certain time has not passed, the process returns to step S006. The time elapsed since step S005 can be measured using a timer circuit.

[0108] By executing steps S001 to S008, if no interrupt signal is received from the sensor circuit 301, the PU21 returns from the sleep state to the normal state at regular intervals and can receive a detection signal from the sensor circuit 301. Furthermore, if an interrupt signal is received from the sensor circuit 301, the PU21 quickly returns to the normal state, returns to step S001, and can receive a detection signal from the sensor circuit 301. The semiconductor device of one embodiment of the present invention requires a short time to return from the sleep state to the normal state, and after receiving an interrupt signal from the sensor circuit 301, the PU21 quickly returns to the normal state and can process, analyze, and the like a signal from the sensor circuit 301.

[0109] Next, steps S102 to S106 will be described.

[0110] In step S102, the sensor circuit 301 starts the process, and the sensor element 710 performs detection.

[0111] Next, in step S103, the sensor element 710 provides the detection signal to the detection unit 711.

[0112] Next, in step S104, the detection signal is provided to the determination circuit 712, which determines the detection signal. Here, the detection signal is compared with a threshold value stored in advance in the determination circuit 712 or in memory. Note that the detection signal may be provided to the determination circuit 712 after being processed by an analog-to-digital conversion circuit.

[0113] Next, in step S105, if the result of the determination made in step S104 is that the detection signal exceeds the threshold value, the process proceeds to step S106, whereas if the detection signal does not exceed the threshold value, the process returns to step S103.

[0114] Next, in step S106, the sensor circuit 301 sends an interrupt signal to the PU 21.

[0115] Fig. 6A shows an example of a perspective view of a semiconductor device 700 equipped with a PU 21 and a sensor circuit 301. In the semiconductor device 700 shown in Fig. 6A, the PU 21 and the sensor circuit 301 are provided on one substrate.

[0116] FIG. 6B shows an example of a perspective view of a control device 717 and a plurality of semiconductor devices 700 controlled by the control device 717.

[0117] FIG. 6C is a perspective view showing an example in which a fan is used as an example of the object 799, a semiconductor device 700 is mounted on each of a plurality of fans, and each semiconductor device 700 is controlled by a control device 717.

[0118] The semiconductor device 700 has an acceleration sensor as a sensor element 710. Data on the change in acceleration over time can be obtained as a signal from the sensor element. The obtained data can be processed by fast Fourier transform.

[0119] The acceleration sensor can detect vibrations caused by the rotation of the fan. If an abnormality occurs in the motor that drives the rotating part of the fan, a change occurs in the signal obtained from the sensor element. The PU21 included in the semiconductor device 700 analyzes the detection signal obtained from the sensor element, and if it determines that an abnormality has occurred, it sends a signal to the control device 717. At this time, the semiconductor device 700 or the control device 717 may notify the abnormality with an indicator. The control device 717 restricts the operation of the object 799 in which the abnormality has occurred. For example, it may change the rotation speed of the fan or stop the fan from rotating.

[0120] 7A shows an example of a sample-and-hold circuit 714. The sample-and-hold circuit 714 shown in Fig. 7A includes a buffer circuit 121, a transistor 122, and a capacitor 123. Note that a node at the other of the source and the drain of the transistor 122 is referred to as a node ND for the sake of description.

[0121] A potential Vs, which is a signal from the sensor element 710, is applied to a buffer circuit of the sample-and-hold circuit 714. The buffer circuit 121 has a function of amplifying and outputting a signal such as analog data input to the sample-and-hold circuit 714. Note that the buffer circuit 121 may be provided on the gate side of the transistor 122.

[0122] An OS transistor is preferably used as the transistor 122. The OS transistor has extremely low off-state current, and the capacitor 123 has a function of holding charge corresponding to the potential Vin, which is an analog potential, in the node ND by turning off the transistor 122.

[0123] The analog potential obtained by the sensor element may be constant or may constantly fluctuate. To sample a fluctuating analog potential, sampling can be performed through a correlated double sampling (CDS) circuit. Correlated double sampling circuits are used to remove noise by obtaining the relative difference between two timings.

[0124] 7B shows an example of a correlated double sampling circuit. The correlated double sampling circuit has multiple sample-and-hold circuits 714A to 714C. A control signal φ1 is applied to the transistor of sample-and-hold circuit 714A, and a control signal φ2 is applied to the transistors of sample-and-hold circuits 714B and 714C.

[0125] By using OS transistors as the transistors that are turned off by the control signals φ1 and φ2, fluctuations in the potentials sampled to obtain the difference can be reduced. This improves the accuracy of the correlated double sampling circuit. Furthermore, once the potentials are sampled, the supply of power to the buffer circuits in the sample-and-hold circuits 714A to 714C can be stopped, thereby reducing power consumption.

[0126] Figure 7C shows a timing chart illustrating an example of the operation of the correlated double sampling circuit shown in Figure 7B. Note that the potential Vs is a fluctuating potential obtained by the sensor element 710, and the potential Vin is an analog potential that has passed through the correlated double sampling circuit. As shown in Figure 7C, even if the potential Vs fluctuates, by sampling at a regular interval and taking the difference, the potential Vin can be obtained as an analog potential that is a constant potential at voltage ΔV.

[0127] <Processing device configuration example 1> Below, processing device 20 and processing device 21 are shown as processing devices capable of power gating. Processing device 20 and processing device 21 can each be used as processing devices included in semiconductor device 700 described above. Power management mechanisms for processing device 20 and processing device 21 will also be described.

[0128] FIG. 8A shows a power supply circuit 10 and a processing unit (PU) 20. The PU 20 is a circuit that has the function of executing instructions. The PU 20 has multiple functional circuits integrated on a single chip. The PU 20 has a processor core 30, a power management unit (PMU) 60, a clock control circuit 65, a power switch (PSW) 70, and terminals 80 to 83. FIG. 8A shows an example in which the power supply circuit 10 is provided on a chip different from the PU 20. The terminal 80 is a terminal to which a power supply potential MVDD is input from the power supply circuit 10. The terminal 81 is a terminal to which a reference clock signal CLKM is input from the outside. The terminal 82 is a terminal to which a signal INT is input from the outside. The signal INT is an interrupt signal that requests interrupt processing. The signal INT is input to the processor core 30 and the PMU 60. The terminal 83 is a terminal to which a control signal generated by the PMU 60 is output and is electrically connected to the power supply circuit 10.

[0129] In the semiconductor device of one embodiment of the present invention, the number of bits that can be handled by an arithmetic circuit or the like in the processing device of one embodiment of the present invention can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0130] <Processor core 30, memory circuit 31> The processor core 30 is a circuit capable of processing instructions and can be called an arithmetic processing circuit. It includes a memory circuit 31 and multiple combinational circuits 32, which constitute various functional circuits. For example, the memory circuit 31 is included in a register.

[0131] As shown in FIG. 8B, the memory circuit 31 includes a circuit MemC1 and a circuit BKC1. The circuit MemC1 has the function of retaining data generated by the processor core 30 and can be configured, for example, with a flip-flop circuit (FF), a latch circuit, etc. The circuit BKC1 functions as a backup circuit for the circuit MemC1 and is capable of retaining data for a long period of time even when the power supply or clock signal is interrupted. The inclusion of this memory circuit 31 enables power gating of the processor core 30. By saving the data in the circuit MemC1 to the circuit BKC1 in the memory circuit 31 before power is interrupted, the state of the processor core 30 at the time of power interruption can be maintained. When power supply is resumed, the data retained in the circuit BKC1 is written to the circuit MemC1, allowing the processor core 30 to return to the state it was in at the time of power interruption. Therefore, the PU 20 can immediately perform normal processing operations after power supply is resumed.

[0132] The circuit BKC1 includes at least a retention circuit having one transistor (MW1) and one capacitor (CB1). The retention circuit shown in FIG. 8B has a circuit configuration similar to that of a 1T1C (one transistor, one capacitor) memory cell of a standard DRAM (dynamic random access memory), and it can perform write and read operations in the same way. The charge and discharge of the capacitor CB1 are controlled by controlling the conduction state of the transistor MW1. Turning the transistor MW1 off places the node FN1 in an electrically floating state. By minimizing the drain current (off current) of the transistor MW1 in the off state, fluctuations in the potential of the node FN1 can be suppressed, thereby extending the data retention time of the circuit BKC1. The data retention time of the circuit BKC1 is determined by the leakage current of the transistor MW1 and the capacitance of the capacitor CB1. By using a transistor with an extremely small off current for the transistor MW1, refreshing the circuit BKC1 is not necessary while the PU20 is operating. This enables the circuit BKC1 to be used as a nonvolatile memory circuit.

[0133] It is preferable to use a transistor (also referred to as an "OS transistor" or "OS-FET") that contains an oxide semiconductor (OS), which is a type of metal oxide, in a semiconductor layer where a channel is formed as the transistor MW1. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is extremely small. In an OS transistor, the normalized off-state current per 1 μm of channel width when the source-drain voltage is 10 V is 10×10 -21 A (10 zepto-A) or less can be achieved. By using an OS transistor as the transistor MW1, the circuit BKC1 can function substantially as a nonvolatile memory circuit while the PU 20 is operating. The OS transistor will be described in the second embodiment.

[0134] The oxide semiconductor film used in the semiconductor layer where the channel is formed may be formed as a single-layer oxide semiconductor film or as a stacked oxide semiconductor film. The oxide semiconductor constituting the semiconductor layer where the channel is formed is preferably an oxide containing at least one element selected from the group consisting of In, Ga, Sn, and Zn. Examples of such oxides include In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In oxide, Sn oxide, and Zn oxide.

[0135] Circuit BKC1 writes data using voltage, which reduces the write power required compared to MRAM (Magnetoresistive RAM), which writes data using current. Also, because data is held by the load capacitance of node FN1, there is no limit to the number of times data can be rewritten, as there is with flash memory.

[0136] In circuit BKC1, the energy required to write data corresponds to the energy required to charge and discharge capacitive element CB1. On the other hand, in a storage circuit using a two-terminal storage element such as MRAM, the energy required to write data corresponds to the energy consumed when a current flows through the storage element. In MRAM, a current continues to flow during the data write period, so the energy required to write data is high. Compared to such MRAM, circuit BKC1 can reduce the energy consumed when writing data. Therefore, compared to a storage circuit whose backup circuit is configured with MRAM, storage circuit 31 has more opportunities to perform voltage scaling and power gating, which can reduce energy consumption, thereby reducing the power consumption of PU20.

[0137] <Power management> The PMU 60 has the function of controlling power gating operation, clock gating operation, voltage scaling operation, etc. More specifically, the PMU 60 has the function of controlling the power supply circuit 10, the function of controlling the memory circuit 31, the function of controlling the clock control circuit 65, and the function of controlling the PSW 70. Therefore, the PMU 60 has the function of generating control signals to control these circuits (the power supply circuit 10, the memory circuit 31, the clock control circuit 65, and the PSW 70). The PMU 60 has a circuit 61. The circuit 61 has the function of measuring time. The PMU 60 has the function of managing the power supply based on time-related data obtained by the circuit 61.

[0138] The PSW70 has a function of controlling the supply of a power supply potential MVDD to the PU20 in accordance with a control signal from the PMU60. Here, the power supply potential supplied to the PU20 via the PSW70 is referred to as the power supply potential VDD. The processor core 30 may have multiple power domains. In this case, the PSW70 may be able to independently control the power supply to the multiple power domains. The processor core 30 may also have a power domain that does not require power gating. In this case, the power supply potential may be supplied to this power domain without going through the PSW70.

[0139] The clock control circuit 65 receives the reference clock signal CLKM and generates and outputs a gated clock signal. The clock control circuit 65 can block the clock signal to the processor core 30 in accordance with a control signal from the PMU 60. The power supply circuit 10 can change the magnitude of the power supply potential VDD in accordance with a control signal from the PMU 60.

[0140] The signal SLP output from the processor core 30 to the PMU 60 triggers the transition of the processor core 30 to a sleep state. Upon receiving the signal SLP, the PMU 60 generates a control signal for transitioning to the sleep state and outputs it to the functional circuit being controlled. The power supply circuit 10 lowers the power supply potential MVDD to a value lower than that during normal operation based on the control signal from the PMU 60. After a certain period of time has passed in the sleep state, the PMU 60 controls the PSW 70 to cut off the power supply to the processor core 30. When the processor core 30 transitions from the normal state to the sleep state, the PMU 60 performs a voltage scaling operation to lower the power supply potential VDD of the processor core 30. If the duration of the sleep state exceeds a set time, the PMU 60 performs a power gating operation to stop the supply of the power supply potential VDD to the processor core 30 to further reduce the power consumption of the processor core 30. Power management for the semiconductor device shown in FIG. 8 will now be described with reference to FIGS. 9 and 10.

[0141] FIG. 9 shows a schematic diagram of the change in potential of the power line 35. The power line 35 is a wiring to which a power supply potential VDD is supplied via a PSW 70. The horizontal axis of the diagram represents the elapsed time (time) from the normal state to the sleep state, with t0, t1, etc. representing time. FIG. 9A shows an example in which only power gating is performed in the sleep state, and FIG. 9B shows an example in which only voltage scaling is performed in the sleep state. FIGS. 9C and 9D show examples in which both voltage scaling and power gating are performed. In the normal state, the magnitude of the power supply potential MVDD supplied from the power supply circuit 10 is VH1.

[0142] In the following, the power supply modes of the PU 20 are classified into three modes: a power on mode, a power off mode, and a low power mode. The power on mode is a mode in which a power supply potential VDD that enables normal processing is supplied to the PU 20. The power off mode is a mode in which the supply of the power supply potential VDD is stopped by the PSW 70. The low power mode is a mode in which a power supply potential VDD lower than that in the power on mode is supplied.

[0143] The example of FIG. 9A will be described. At time t0, the processor core 30 starts processing to transition to a sleep state. For example, the memory circuit 31 is backed up. The PMU 60 controls the PSW 70 to cut off the power supply to the processor core 30 at time t1. The power supply line 35 naturally discharges, and its potential drops to 0V. This significantly reduces the leakage current of the processor core 30 in the sleep state, thereby reducing power consumption in the sleep state (hereinafter sometimes referred to as standby power). When returning to the normal state due to an external interrupt request or the like, the PMU 60 controls the PSW 70 to resume the supply of VDD. Here, the supply of VDD is resumed at time t4. The potential of the power supply line 35 rises and becomes VH1 at time t6.

[0144] In the example of Figure 9B, to perform voltage scaling, at time t1, PMU 60 controls power supply circuit 10 to lower power supply potential MVDD to VH2. The potential of power supply line 35 eventually reaches VH2. At time t4, power supply potential MVDD returns from VH2 to VH1, and the potential of power supply line 35 rises, reaching VH1 at time t5.

[0145] In the example of Figure 9A, the time required to return from the sleep state to the normal state (overhead time) is the time required for the potential of the power line 35 to rise from 0V to VH1, and the energy overhead required for return is the energy required to charge the load capacitance of the power line 35 from 0V to VH1. If the period (t1-t4) of the power-off mode is sufficiently long, power gating is effective in reducing the standby power of the PU 20. On the other hand, if the period (t1-t4) is short, the power required to return to the normal state becomes greater than the power that can be reduced by cutting off the power supply, and the effect of power gating cannot be obtained.

[0146] In the voltage scaling example shown in FIG. 9B, the potential of the power supply line 35 is VH2 in the sleep state, so the amount of standby power reduction is smaller than in the power gating example shown in FIG. 9A. On the other hand, in the example shown in FIG. 9B, the fluctuation in the potential of the power supply line 35 is small, so the time required to return to the normal state is shorter and the energy required for return is less than in the example shown in FIG. 9A. Therefore, the semiconductor device shown in FIG. 8 enables power management that combines power gating and voltage scaling to more efficiently reduce the standby power of the PU 20. Examples of power management are shown in FIGS. 9C and 9D.

[0147] As shown in Figure 9C, first, voltage scaling operation is performed in the hibernation state, and the system transitions from power-on mode to low-power mode. As in Figure 9B, at time t1, the PMU 60 controls the power supply circuit 10 to lower the power supply potential MVDD to VH2, so that the potential of the power line 35 eventually reaches VH2. After a certain period (t1-t3) has elapsed since the transition to low-power mode, the PMU 60 controls the PSW 70 to enter power-off mode. The period (t3-t4) is a period during which power can be reduced by shutting off the power to the PU 20 using power gating, even if it includes the power consumed to return to the normal state, rather than supplying VH2 to the PU 20.

[0148] For example, assume that potential VH2 is a power supply potential large enough to hold data in circuit MemC1 of memory circuit 31, and potential VH3 is a potential at which the data in circuit MemC1 is lost. In PU20 of FIG. 8A, circuit BKC1 is a circuit capable of holding data even when power supply is stopped. By saving the data in memory circuit 31 to circuit BKC1 during period (t0-t1), it is possible to lower VDD to potential VH3 at which the data in circuit MemC1 is lost in low power mode. This further reduces the standby power of PU20.

[0149] The PMU 60 has a function that can return the PU 20 to a normal state based on an interrupt request or the like. The PMU 60 controls the power supply circuit 10 to boost the magnitude of MVDD to VH1, and also controls the PSW 70 to resume the supply of VDD to the PU 20. From time t4 onwards, the system is in power-on mode. At time t6, the potential of the power supply line 35 stabilizes, allowing the PU 20 to operate normally from time t6 onwards.

[0150] FIG. 9D shows an example in which an interrupt request to return to normal operation occurs before time t3. From time t2 onwards, the power-on mode is active. At time t2, the PMU 60 controls the power supply circuit 10 to change the magnitude of MVDD to the power-on mode potential VH1. At time t3, the potential of the power line 35 rises to VH1.

[0151] 9C and 9D, in the hibernation state, the time required to return the potential of the power line 35 to VH1 is longer when returning from the power-off mode to the power-on mode than when returning from the low power mode to the power-on mode. Therefore, the PMU 60 has a function that can adjust the timing of the operation to return the processor core 30 from the hibernation state to the normal state depending on the power mode. This enables the processor core 30 to return from the hibernation state to the normal state in the shortest time.

[0152] Furthermore, in the hibernation state, transition from low power mode to power off mode is possible by measuring time using a circuit 61 provided in the PMU 60. When a signal SLP is input from the PU 20, the PMU 60 starts measuring time using the circuit 61. After a predetermined time has elapsed since switching to low power mode, the PMU 60 transitions to power off mode. A control signal from the PMU 60 turns off the PSW 70, cutting off the supply of VDD. In this way, transition from low power mode to power off mode is possible using an interrupt request based on measurement data from the circuit 61. An example of the power management operation of the PMU 60 will be described below with reference to FIG. 10.

[0153] The PU 20 is operating normally. The power supply mode is the power-on mode, and the PMU 60 is in an idle state (step S10). The PMU 60 remains in the idle state until the signal SLP is input. The input of the signal SLP triggers the execution of a save sequence (step S11). In the example of the save sequence shown in FIG. 10, the PMU 60 first outputs a control signal to the clock control circuit 65 to stop the output of the clock signal (step S12). Next, it outputs a control signal to the memory circuit 31 to save data (step S13). In the memory circuit 31, the data held in the circuit MemC1 is saved to the circuit BKC1 in accordance with the control signal from the PMU 60. Finally, the PMU 60 controls the power supply circuit 10 to reduce MVDD. These operations transition the power supply mode to the low power mode (step S14). When the signal SLP is input, the PMU 60 controls the built-in circuit 61 to measure the time Ta in the low power mode (step S15). The timing for operating the circuit 61 can be any timing while the backup sequence is being executed, such as when the signal SLP is input, when a control signal is output to the clock control circuit 65, when data backup is started, when data backup is completed, or when a control signal is output to the power supply circuit 10.

[0154] After the execution of the save sequence, the PMU 60 goes into an idle state (step S16), monitors the input of the signal INT, and monitors the time Ta, which is the measurement time of the clock control circuit 65. When the signal INT is input, the PMU 60 moves to the restore sequence (step S17). When the time Ta reaches the set time T vs The PMU 60 determines whether the time Ta exceeds the time T vs If the time T exceeds the time T, the power supply mode is switched to the power-off mode (step S19), and if the time T does not exceed the time T, the idle state is maintained (step S16). vs The time may be set so that the standby power consumption of the processor core 30 can be reduced more effectively by putting the processor core 30 into the power-off mode than by putting the processor core 30 into the low power mode.

[0155] In step S19, the PMU 60 outputs a control signal to the PSW 70 to cut off the power supply to the processor core 30. After entering the power-off mode, the PMU 60 again enters the idle state (step S20) and monitors the input of the signal INT (step S21). When the signal INT is input, the PMU 60 executes a recovery sequence.

[0156] In the recovery sequence, first, the PMU 60 transitions from the power-off mode to the power-on mode (step S22). The PMU 60 controls the power supply circuit 10 to output the power supply potential for normal operation. The PMU 60 also controls the PSW 70 to resume the supply of VDD to the processor core 30. Next, a control signal is output to the memory circuit 31 to restore the data in the memory circuit 31 (step S23). In response to the control signal from the PMU 60, the memory circuit 31 writes the data held in the circuit BKC1 back to the circuit MemC1. The PMU 60 outputs a control signal to the clock control circuit 65 to output a clock signal (step S24). In response to the control signal from the PMU 60, the clock control circuit 65 resumes outputting the clock signal.

[0157] When the recovery sequence is executed from the determination process of step S17, the system returns from the low power mode to the power-on mode, and the potential of the power line 35 can be stabilized more quickly than when the recovery sequence is executed from the determination process of step S21. Therefore, when transitioning from step S17 to the recovery sequence, the PMU 60 executes step S23 earlier than when transitioning from step S21 to the recovery sequence. This shortens the time it takes for the processor core 30 to return from the sleep state to the normal state.

[0158] 8, when the PU 20 enters a sleep state, the power management of the semiconductor device shown in FIG. 8 first performs a voltage scaling operation to lower the power supply potential supplied to the processor core 30, thereby reducing leakage current and minimizing the time and energy overhead required for returning from the sleep state to the normal state. If the sleep state continues for a certain period of time, a power gating operation is performed to minimize leakage current from the processor core 30. This makes it possible to reduce the power consumption of the PU 20 in the sleep state without reducing the processing performance of the PU 20.

[0159] <<Processing device configuration example 2>> FIG. 11A shows a modified example of the processing unit of FIG. 8A. The processing unit (PU) 21 shown in FIG. 11A is obtained by adding a cache 40 and a power switch (PSW) 71 to the PU 20. Like the PU 20, the cache 40 is capable of power gating and voltage scaling, and the power mode of the cache 40 changes in conjunction with the power mode of the PU 21. The PSW 71 is a circuit that controls the supply of a power supply potential MVDD to the cache 40 and is controlled by the PMU 60. Here, the power supply potential input to the cache 40 via the PSW 71 is set to VDD_MEM. Like the processor core 30, the cache 40 receives a control signal from the PMU 60 and a gated clock signal from the clock control circuit 65.

[0160] <Cache 40> The cache 40 is a storage device that has the function of temporarily storing frequently used data. The cache 40 has a memory array 41, a peripheral circuit 42, and a control circuit 43. The memory array 41 has a plurality of memory cells 45. The control circuit 43 controls the operation of the cache 40 in accordance with requests from the processor core 30. For example, it controls the write and read operations of the memory array 41. The peripheral circuit 42 has the function of generating signals that drive the memory array 41 in accordance with control signals from the control circuit 43. The memory array 41 has memory cells 45 that store data.

[0161] As shown in FIG. 11B, the memory cell 45 includes a circuit MemC2 and a circuit BKC2. The circuit MemC2 is a memory cell that is accessed during normal operation. For example, a static random access memory (SRAM) memory cell may be used. The circuit BKC2 functions as a backup circuit for the circuit MemC2 and is capable of retaining data for a long period of time even when the power supply or clock signal is cut off. The provision of such a memory cell 45 enables power gating of the cache 40. Before power is cut off, the memory cell 45 saves data from the circuit MemC2 to BKC2. After power supply is resumed, the data stored in the circuit BKC2 is written back to the circuit MemC2, allowing the PU21 to quickly return to the state it was in before power was cut off.

[0162] Like the circuit BKC1 in FIG. 8B, the circuit BKC2 of the memory cell 45 also includes a retention circuit having one transistor (MW2) and one capacitor (CB2). That is, the circuit BKC2 also has a retention circuit with a configuration similar to that of a standard 1T1C memory cell of a DRAM. The transistor MW2 has an extremely low off-state current. Like the transistor MW1, an OS transistor can be used for the transistor MW2. This configuration allows the circuit BKC2 to suppress fluctuations in the potential of the electrically floating node FN2, thereby enabling the circuit BKC2 to retain data for a long period of time. The data retention time of the circuit BKC2 is determined by the leakage current of the transistor MW2, the capacitance of the capacitor CB2, and other factors. By using a transistor with an extremely low off-state current for the transistor MW2, the circuit BKC2 can be used as a nonvolatile memory circuit that does not require a refresh operation.

[0163] In the PU 21 shown in FIG. 11A, the PMU 60 also performs power management, as in the PU 20 (see FIG. 10). In step S13 shown in FIG. 10, a data saving operation is performed for the memory circuit 31 and the cache 40. In step S19, the PSW 70 and PSW 71 are controlled to stop the power supply to the processor core 30 and the cache 40. In step S22, the PSW 70 and PSW 71 are controlled to resume the power supply to the processor core 30 and the cache 40. In step S23, a data recovery operation is performed for the memory circuit 31 and the cache 40.

[0164] Therefore, like the semiconductor device shown in FIG. 8, the semiconductor device shown in FIG. 11 also performs power management that combines voltage scaling and power gating, making it possible to reduce the power consumed by PU21 when it is in a dormant state without reducing the processing capacity of PU21.

[0165] <<Processor core configuration example>> An example of the configuration of a processor core is shown in Fig. 12. The processor core 130 shown in Fig. 12 has a control unit 131, a program counter 132, a pipeline register 133, a pipeline register 134, a register file 135, an arithmetic logic unit (ALU) 136, and a data bus 137. Data is exchanged between the processor core 130 and peripheral circuits such as a PMU and a cache via the data bus 137.

[0166] The control device 131 has the function of decoding and executing instructions included in an input program such as an application by comprehensively controlling the operations of the program counter 132, pipeline register 133, pipeline register 134, register file 135, ALU 136, and data bus 137. The ALU 136 has the function of performing various arithmetic operations such as arithmetic operations and logical operations. The program counter 132 is a register that has the function of storing the address of the next instruction to be executed.

[0167] The pipeline register 133 is a register that has the function of temporarily storing instruction data. The register file 135 has multiple registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of the arithmetic processing of the ALU 136, etc. The pipeline register 134 is a register that has the function of temporarily storing data used in the arithmetic processing of the ALU 136, data obtained by the arithmetic processing of the ALU 136, etc.

[0168] The storage circuit 31 in FIG. 8B is used for a register included in the processor core 130.

[0169] <Example of memory circuit configuration> A more specific example of the configuration of the memory circuit 31 shown in Fig. 8B will be described. Fig. 13 is a circuit diagram showing an example of the configuration of the memory circuit. The memory circuit 100 shown in Fig. 13 functions as a flip-flop circuit.

[0170] A standard flip-flop circuit (FF) can be applied to the circuit MemC1, such as a master-slave FF. An example of such a configuration is shown in FIG. 13. The FF 110 includes transmission gates (TG1, TG2, TG3, TG4, and TG5), inverter circuits (INV1 and INV2), and NAND circuits (NAND1 and NAND2). The signals RESET and OSR are control signals output from the PMU 60. The signal OSR and its inverted signal are input to TG5. The clock signal CLK and its inverted signal are input to TG1-TG4. A single clocked inverter circuit may be provided instead of TG1 and INV1. A single clocked NAND circuit may be provided instead of TG2 and NAND2. A clocked inverter circuit may be provided instead of TG3 and INV3. TG5 functions as a switch that controls the conduction state between the output node of NAND1 and node NR1. The node NB1 is electrically connected to the input node of the circuit BKC10, and the node NR1 is electrically connected to the output node of the circuit BKC10.

[0171] The circuit BKC10 shown in FIG. 13 functions as a backup circuit for the FF110. The circuit BKC10 includes a circuit RTC10 and a circuit PCC10. The signals (OSG, OSC, OSR) input to the circuit BKC10 are control signals output from the PMU60. The power supply potential VSS is a low power supply potential, which may be, for example, the ground potential (GND) or 0V. The power supply potential VSS and the power supply potential VDD are input to the FF110 as with BKC1. In the memory circuit 100, the supply of VDD is managed by the PMU60.

[0172] The circuit RTC10 has transistors MW1, MA1, and MR1, a node FN1, and a node NK1. The circuit RTC10 has the function of retaining data, and here, is configured as a memory circuit with a 3T-type gain cell structure. The transistor MW1 is a write transistor and an OS transistor. The transistor MR1 is a read transistor, and the transistor MA1 is an amplification transistor and a read transistor. Data is retained at the node FN1. The node NK1 is a data input node. The node NR1 is a data output node of the circuit RTC10.

[0173] FIG. 13 shows an example of a configuration in which circuit BKC10 reads data from the slave latch circuit of FF110 during a save operation and writes the held data back to the master latch circuit during a restore operation. The data to be saved may be data from the master latch circuit. Alternatively, the data may be restored to the slave latch circuit. In this case, TG5 may be provided in the slave latch circuit.

[0174] Furthermore, transistors MR1 ​​and MA1 of circuit RTC10 may be either n-type or p-type, and the potential of signal OSR and the level of the power supply potential supplied to transistor MA1 can be changed depending on the conductivity type of transistors MR1 ​​and MA1. The logic circuit of FF110 can also be configured appropriately. For example, if transistors MR1 ​​and MA1 are p-type transistors, NAND1 and INV3 can be swapped in the master latch circuit, and INV2 and NAND2 can be swapped in the slave latch circuit. Also, VDD can be input to transistor MA1 instead of VSS.

[0175] Because circuit BKC10 writes data using voltage, it can reduce the write power consumption compared to MRAM, which writes data using current. Also, because data is held by the load capacitance of node FN1, there is no limit to the number of times data can be rewritten, as there is in flash memory.

[0176] In the circuit RTC10, the energy required to write data corresponds to the energy required to charge and discharge the capacitance element CB1. On the other hand, in a memory circuit using a two-terminal memory element such as MRAM, the energy required to write data corresponds to the energy consumed when a current flows through the memory element. Therefore, compared to a case where an MRAM or the like is used, in which a current continues to flow during the data write period, the circuit BKC10 can reduce the energy consumed by saving data. Therefore, by providing the circuit BKC10 in the backup circuit, the break-even time (BET) can be shortened compared to a case where an MRAM is provided. As a result, there are more opportunities to perform power gating, which can reduce energy consumption, and the power consumption of the semiconductor device can be reduced.

[0177] The circuit PCC10 includes a transistor MC1 and a transistor MC2. The circuit PCC10 has a function of precharging the node FN1. The circuit PCC10 does not necessarily have to be provided. As will be described later, providing the circuit PCC10 can shorten the data backup time of the circuit BKC10.

[0178] <Memory circuit operation example> FIG. 14 is a timing chart showing an example of the operation of the memory circuit 100, illustrating the waveforms of the control signals (signal SLP, signal RESET, clock signal CLK, signal OSG, signal OSR) and changes in the power supply potential VDD and the potentials of node FN1 and node NR1.

[0179] [Normal operation] The "Normal Operation" period in FIG. 14 will be described. A power supply potential VDD and a clock signal CLK are supplied to the memory circuit 100. FF110 functions as a sequential circuit. Since the signal RESET is maintained at a high level, NAND1 and NAND2 function as inverter circuits. In the circuit BKC1, the transistor MC1 is in an off state, and the transistors MC2 and MW1 are in an on state, so the potential of the node FN1 is precharged to a high level.

[0180] [Data evacuation] Next, the "Back up" period in FIG. 14 will be described. First, the clock signal CLK is stopped. This stops rewriting data at node NB1. In the example of FIG. 14, the potential level of node NB1 is low ("0") when the potential of node NR1 is high ("1"), and is high ("1") when the potential is low ("0"). While the signal OSC is high, the data at node NB1 is saved to node FN1. Specifically, since transistors MC1 and MW1 are on, node FN1 and node NB1 are electrically connected. By setting the signal OSG to low and turning off transistor MW1, node FN1 becomes electrically floating, and circuit BKC10 becomes a data retention state. The potential of node FN1 is high when node NR1 is low ("0"), and is low when the potential is high ("1").

[0181] Since the data backup ends when signal OSG is set to low, the voltage scaling operation of PU20 can be performed immediately after signal OSG is set to low. Also, because transistor MC2 precharges node FN1 to high during normal operation, the data backup operation of setting node FN1 to high does not involve the transfer of charge from node FN1. This allows circuit BKC10 to complete the backup operation in a short time.

[0182] In the data saving operation, it is sufficient that the clock signal CLK is inactive. In the example of FIG. 14, the potential of the clock signal CLK is set to low level, but it may also be set to high level.

[0183] [Voltage scaling, low power mode] Next, the "low power" period in Fig. 14 will be described. In conjunction with the falling edge of the signal OSC, the PMU 60 performs a voltage scaling operation, which causes the storage circuit 100 to transition to a low power mode.

[0184] [Power gating, power off mode] Next, a description will be given of the "power off" period in Fig. 14. After a certain period has elapsed since the transition to the low power mode, the PMU 60 performs a power gating operation to put the storage circuit 100 into the power off mode.

[0185] [Power on mode] Next, the "Power on" period in Fig. 14 will be described. In response to an interrupt request, the PMU 60 returns the memory circuit 100 to the power on mode. In the example of Fig. 14, when the potential of the power supply line that supplies VDD becomes stable, the clock signal CLK becomes high level.

[0186] [Data recovery] A data restoration operation is performed while the signal OSR is at a high level. By setting the signal RESET to a high level, the potential of the node NR1 is precharged to a high level ("1"). By setting the signal OSR to a high level, TG5 enters a high impedance state and the transistor MR1 enters a conductive state. The conductive state of the transistor MA1 is determined by the potential of the node FN1. If the node FN1 is at a high level, the transistor MA1 is in a conductive state, so the potential of the node NR1 drops to a low level ("0"). If the node FN1 is at a low level, the potential of the node NR1 is maintained at a high level. In other words, the state of FF110 is restored to the state before the transition to the sleep state.

[0187] As described above, the rising edges of the signals RESET and OSR allow high-level data to be written back (restored) to the node NR1, thereby enabling the storage circuit 100 to shorten the recovery operation period.

[0188] 14 shows an example of returning from the power-off mode to the power-on mode. When returning from the low power mode to the power-on mode, there is a period T until the potential of the power line that supplies VDD becomes stable. on In this case, it is better to make the rise of the signal OSR earlier than when returning from the power-off mode.

[0189] [Normal operation] Next, the "Normal operation" period in Fig. 14 will be described. By resuming the supply of the clock signal CLK, the state where normal operation is possible is restored. By setting the signal OSG to high level, the node FN1 is precharged by the circuit PCC10 and becomes high level.

[0190] <<Cache>> An example in which the cache 40 is configured using an SRAM will be described below.

[0191] <Memory cell configuration example> FIG. 15 shows an example of the configuration of a cache memory cell. The memory cell 120 shown in FIG. 15 has a circuit SMC20 and a circuit BKC20. The circuit SMC20 may have a circuit configuration similar to that of a standard SRAM memory cell. The circuit SMC20 shown in FIG. 15 has an inverter circuit INV11, an inverter circuit INV12, a transistor M11, and a transistor M12.

[0192] Circuit BKC20 functions as a backup circuit for circuit SMC20. Circuit BKC20 has transistors MW11, MW12, and capacitors CB11 and CB12. Transistors MW11 and MW12 are OS transistors. Circuit SMC20 has two 1T1C-type holding circuits, and data is held at nodes SN1 and SN2, respectively. The holding circuit consisting of transistor MW11 and capacitor CB11 has the function of backing up data at node NET1. The holding circuit consisting of transistor MW12 and capacitor CB12 has the function of backing up data at node NET2.

[0193] The memory cell 120 is supplied with power supply potentials VDDMC and VSS. The memory cell 120 is electrically connected to wirings (WL, BL, BLB, BRL). A signal SLC is input to the wiring WL. When writing data, a data signal D and a data signal DB are input to the wirings BL and BLB. Data is read by detecting the potentials of the wirings BL and BLB. A signal OSS is input to the wiring BRL. The signal OSS is a signal input from the PMU 60.

[0194] <Memory cell operation example> An example of the operation of the memory cell 120 will be described below.

[0195] [Normal operation] An access request is made to the circuit MemC2, and data is written or read. In the circuit BKC2, the signal OSS is at a low level, so the nodes SN1 and SN2 are in an electrically floating state and are in a data retention state. In the example of Figure 16, the potential of the node SN1 is at a low level ("0"), and the potential of the other node, node SN2, is at a high level ("1").

[0196] [Data evacuation] By setting the signal OSS to a high level, the transistors MW11 and MW12 are turned on, and the nodes SN1 and SN2 are set to the same potential level as the nodes NET1 and NET2, respectively. In the example of Figure 16, the potentials of the nodes SN1 and SN2 are set to a high level and a low level, respectively. The signal OSS is set to a low level, the circuit BKC20 is set to a data retention state, and the data save operation is completed.

[0197] [Voltage scaling, low power mode] In response to the falling edge of the signal OSS, the PMU 60 performs a voltage scaling operation, which causes the cache 40 to transition to a low power mode.

[0198] [Power gating, power off mode] After a certain period of time has elapsed since the transition to the low power mode, the PMU 60 performs a power gating operation to put the cache 40 into the power-off mode.

[0199] [Data recovery, power on mode] In response to the interrupt request, the PMU 60 restores the cache 40 to its normal state. The signal OSS is set to high level, and the data held in the circuit BKC 20 is written back to the circuit SMC 20. While the signal OSS is high level, the PMU 60 performs voltage scaling and power gating operations, restoring the memory circuit 100 to power-on mode. In the example of FIG. 14, when the potential of the power supply line supplying VDD stabilizes, the clock signal CLK goes high. When the potential of the power supply line supplying VDDMC stabilizes, the signal OSS is returned to low level, and the data restoration operation is completed. The states of the nodes SN1 and SN2 have returned to the states they were in immediately before entering the sleep state.

[0200] [Normal operation] When the supply of VDDMC is resumed, the circuit SMC20 returns to the normal mode in which normal operation is possible.

[0201] As described above, by using OS transistors, it is possible to configure a backup circuit that can retain data for a long period of time even when power is cut off. The inclusion of this backup circuit enables power gating of the processor core and cache. Furthermore, by combining voltage scaling and power gating in power management during hibernation, it is possible to reduce the energy and time overhead required for returning from hibernation to normal operation. This allows for efficient power reduction without reducing the processing power of the processing unit.

[0202] <Example of memory> A memory including an OS transistor of one embodiment of the present invention will be described below.

[0203] The power storage device of one embodiment of the present invention preferably includes a memory. A memory device including an OS transistor can be used as the memory. For example, NOSRAM (registered trademark), DOSRAM (registered trademark), or the like, which will be described below, can be used.

[0204] NOSRAM is a gain cell type DRAM in which the write transistor of the memory cell is composed of an OS transistor. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. An example of a NOSRAM configuration is shown below.

[0205] 17A is a block diagram showing an example of the configuration of a NOSRAM. The NOSRAM 240 is provided with power domains 242 and 243 and power switches 245 to 247. The power domain 242 is provided with a memory cell array 250, and the power domain 243 is provided with peripheral circuits for the NOSRAM 240. The peripheral circuits include a control circuit 251, a row circuit 252, and a column circuit 253.

[0206] Voltages VDDD, VSSS, VDHW, VDHR, VBG2, a clock signal GCLK2, an address signal Address, CE, WE, and PSE5 are input to the NOSRAM 240 from outside. The CE and WE signals are a chip enable signal and a write enable signal. The PSE5 signal controls the on / off of the power switches 245 to 247. The power switches 245 to 247 control the input of the VDDD, VDHW, and VDHR voltages to the power domain 243, respectively.

[0207] The voltages, signals, etc. input to the NOSRAM 240 are appropriately selected depending on the circuit configuration and operation method of the NOSRAM 240. For example, a power domain that is not power gated may be provided in the NOSRAM 240, and a power gating control circuit that generates the signal PSE5 may be provided.

[0208] The memory cell array 250 includes memory cells 11, write word lines WWL, read word lines RWL, write bit lines WBL, read bit lines RBL, and source lines SL.

[0209] As shown in FIG. 17B, the memory cell 11 is a 2T1C (two transistors, one capacitor) type gain cell and includes a node SN1, transistors M1 and M2, and a capacitor C1. The transistor M1 is a write transistor and is an OS transistor having a back gate. The back gate of the transistor M1 is electrically connected to a wiring BGL2 that supplies a voltage VBG2. The transistor M2 is a read transistor and is a p-channel Si transistor. The capacitor C1 is a storage capacitor that holds the voltage of the node SN1.

[0210] The voltages VDDD and VSSS represent data "1" and "0." The high level voltages of the write word line WWL and the read word line RWL are voltages VDHW and VHDR.

[0211] Fig. 18A shows an example of the configuration of a memory cell array 250. In the memory cell array 250 shown in Fig. 18, one source line is supplied to two adjacent rows.

[0212] In principle, the memory cell 11 has no limit to the number of times it can be rewritten, data can be rewritten with low energy, and data retention does not consume power. Because the transistor M1 is an OS transistor with extremely low off-state current, the memory cell 11 can retain data for a long time. Therefore, by configuring a cache memory device with NOSRAM 240, the cache memory device can be made into a nonvolatile, low-power memory device.

[0213] The circuit configuration of the memory cell 11 is not limited to that shown in FIG. 17B. For example, the read transistor M2 may be an OS transistor with a back gate or an n-channel Si transistor. Alternatively, the memory cell 11 may be a 3T gain cell. FIGS. 18B and 18C show examples of a 3T gain cell. The memory cell 15 shown in FIG. 18B includes transistors M3 to M5, a capacitor C3, and a node SN3. The transistors M3 to M5 are write transistors, read transistors, and select transistors. The transistor M3 is an OS transistor with a back gate, and the transistors M4 and M5 are p-channel Si transistors. The transistors M4 and M5 may be n-channel Si transistors or OS transistors with back gates. In the memory cell 16 shown in FIG. 18C, the three transistors are OS transistors with back gates.

[0214] Node SN3 is a holding node. Capacitor C3 is a holding capacitance for holding the voltage of node SN3. Capacitor C3 may not be intentionally provided, and the holding capacitance may be formed by the gate capacitance of transistor M4 or the like. A fixed voltage (e.g., VDDD) is input to line PDL. Line PDL is a line in place of source line SL, and, for example, voltage VDDD is input to line PDL.

[0215] The control circuit 251 has a function of controlling the overall operation of the NOSRAM 240. For example, the control circuit 251 performs a logical operation on the signals CE and WE to determine whether an external access is a write access or a read access.

[0216] The row circuit 252 has a function of selecting the write word line WWL and read word line of the selected row specified by the address signal, and the column circuit 253 has a function of writing data to the write bit line of the column specified by the address signal and a function of reading data from the read bit line of the column.

[0217] DOSRAM is a RAM having 1T1C type memory cells, and is an abbreviation for Dynamic Oxide Semiconductor RAM. DOSRAM will be described below with reference to FIG.

[0218] As shown in FIG. 19A, the memory cell 16 of the DOSRAM 351 is electrically connected to a bit line BL1 (or BLB1), a word line WL1, and wirings BGL6 and PL. The bit line BLB1 is an inverted bit line. For example, voltages VBG6 and VSSS are input to the wirings BGL6 and PL. The memory cell 16 includes a transistor M6 and a capacitance element C6. The transistor M6 is an OS transistor having a back gate.

[0219] Because data is rewritten by charging and discharging the capacitive element C6, the DOSRAM 351 is theoretically unlimited in the number of rewrites and can write and read data with low energy. Furthermore, the simple circuit configuration of the memory cell 16 makes it easy to increase the capacity. Because the write transistors of the memory cell 16 are OS transistors, the retention time of the DOSRAM 351 is much longer than that of DRAM. Therefore, the frequency of refresh operations can be reduced, or even the refresh operation can be eliminated, thereby reducing the power required for the refresh operation.

[0220] 19B, in the DOSRAM 351, the memory cell array 361 can be stacked on the peripheral circuit 365. This is because the transistor M6 of the memory cell 16 is an OS transistor.

[0221] The memory cell array 361 has a plurality of memory cells 16 arranged in rows and columns, and bit lines BL1, BLB1, word lines WL1, and wirings BGL6 and PL are provided according to the arrangement of the memory cells 16. The peripheral circuit 365 includes a control circuit, a row circuit, and a column circuit. The row circuit selects the word line WL1 to be accessed, and the column circuit writes and reads data to and from the bit line pair consisting of BL1 and BLB1.

[0222] Power switches 371 and 373 are provided to power gate the peripheral circuit 365. The power switches 371 and 373 respectively control the input of voltages VDDD and VDHW6 to the peripheral circuit 365. The voltage VDHW6 is a high-level voltage of the word line WL1. The on / off of the power switches 371 and 373 is controlled by a signal PSE6.

[0223] <Example of an arithmetic circuit> Next, an example of the configuration of a semiconductor device that can be used for neural network calculations will be described.

[0224] As shown in FIG. 20A, the neural network NN can be configured with an input layer ILy, an output layer OLy, and an intermediate layer (hidden layer) HLy. The input layer ILy, output layer OLy, and intermediate layer HLy each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HLy can also be called a DNN (deep neural network), and learning using a deep neural network can also be called deep learning.

[0225] Input data is input to each neuron in the input layer ILy, an output signal from a neuron in the previous or next layer is input to each neuron in the hidden layer HLy, and an output signal from a neuron in the previous layer is input to each neuron in the output layer OLy. Note that each neuron may be connected to all neurons in the previous or next layer (fully connected), or may be connected to only a portion of the neurons in the previous or next layer.

[0226] Figure 20B shows an example of a neuron's operation. It shows neuron N and two neurons in the previous layer that output signals to neuron N. Neuron N receives the output x1 of a neuron in the previous layer and the output x2 of a neuron in the previous layer. Neuron N then multiplies the output x1 by the weight w1 (x1w1) and the output x2 by the weight w2 (x2w2), calculating the sum x1w1+x2w2. After that, a bias b is added as necessary, resulting in a value a = x1w1+x2w2+b. The value a is then transformed by the activation function h, and neuron N outputs an output signal y = h(a).

[0227] As described above, the computation performed by a neuron includes the sum of the product of the output of a neuron in the previous layer and the weight, i.e., the sum-of-products computation (x1w1+x2w2 as described above). This sum-of-products computation may be performed in software using a program, or may be performed by hardware. When performing the sum-of-products computation by hardware, a sum-of-products computation circuit can be used. This sum-of-products computation circuit may be a digital circuit or an analog circuit. When an analog circuit is used for the sum-of-products computation circuit, it is possible to reduce the circuit size of the sum-of-products computation circuit or the number of memory accesses, thereby improving processing speed and reducing power consumption.

[0228] The product-sum operation circuit may be configured using transistors containing silicon (such as single crystal silicon) in their channel formation regions (hereinafter also referred to as Si transistors) or transistors containing an oxide semiconductor in their channel formation regions (hereinafter also referred to as OS transistors). OS transistors, in particular, have extremely low off-state current and are therefore suitable as transistors constituting the memory of the product-sum operation circuit. The product-sum operation circuit may be configured using both Si transistors and OS transistors. Hereinafter, a configuration example of a semiconductor device having the function of a product-sum operation circuit will be described.

[0229] 21 shows a configuration example of a semiconductor device MAC having a function of performing neural network calculations. The semiconductor device MAC has a function of performing a product-sum operation on first data corresponding to the connection strength (weight) between neurons and second data corresponding to input data. Note that the first data and second data can each be analog data or multi-valued digital data (discrete data). The semiconductor device MAC also has a function of converting the data obtained by the product-sum operation using an activation function.

[0230] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.

[0231] The cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. FIG. 21 shows an example of a configuration in which the cell array CA has m rows and n columns (m and n are integers equal to or greater than 1) of memory cells MC (MC[1,1] to [m,n]) and m memory cells MCref (MCref[1] to [m]). The memory cells MC have a function of storing first data. The memory cells MCref also have a function of storing reference data used in a product-sum operation. The reference data can be analog data or multi-level digital data.

[0232] The memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is connected to the wiring WL[i], the wiring RW[i], the wiring WD[j], and the wiring BL[j]. The memory cell MCref[i] is connected to the wiring WL[i], the wiring RW[i], the wiring WDref, and the wiring BLref. Here, the current flowing between the memory cell MC[i,j] and the wiring BL[j] is I MC[i,j] and the current flowing between the memory cell MCref[i] and the wiring BLref is I MCref[i] It is written as follows.

[0233] A specific configuration example of the memory cell MC and memory cell MCref is shown in Figure 22. Although Figure 22 shows memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] as representative examples, similar configurations can be used for other memory cells MC and memory cells MCref. The memory cell MC and memory cell MCref each have transistors Tr11, Tr12, and a capacitance element C11. Here, a case will be described in which transistors Tr11 and Tr12 are n-channel transistors.

[0234] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source and the drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitor C11, and the other of the source and the drain is connected to the wiring WD. One of the source and the drain of the transistor Tr12 is connected to the wiring BL, and the other of the source and the drain is connected to the wiring VR. The second electrode of the capacitor C11 is connected to the wiring RW. The wiring VR is a wiring that has the function of supplying a predetermined potential. Here, as an example, a case where a low power supply potential (such as a ground potential) is supplied from the wiring VR will be described.

[0235] A node connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is referred to as a node NM. The nodes NM of the memory cells MC[1,1] and MC[2,1] are referred to as nodes NM[1,1] and NM[2,1], respectively.

[0236] The memory cell MCref has the same configuration as the memory cell MC. However, the memory cell MCref is connected to a wiring WDref instead of the wiring WD, and to a wiring BLref instead of the wiring BL. In addition, in the memory cells MCref[1] and [2], the nodes connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitance element C11 are denoted as nodes NMref[1] and [2], respectively.

[0237] The node NM and the node NMref function as the storage nodes of the memory cell MC and the memory cell MCref, respectively. The node NM stores first data, and the node NMref stores reference data. In addition, a current I flows from the wiring BL[1] to the transistors Tr12 of the memory cells MC[1,1] and MC[2,1]. MC[1,1] , I MC[2,1] In addition, a current I flows from the wiring BLref to the transistor Tr12 of the memory cells MCref[1] and MCref[2]. MCref[1] , I MCref[2] is playing.

[0238] Since the transistor Tr11 has a function of maintaining the potential of the node NM or the node NMref, it is preferable that the off-state current of the transistor Tr11 be small. Therefore, it is preferable to use an OS transistor with an extremely small off-state current as the transistor Tr11. This can suppress fluctuations in the potential of the node NM or the node NMref, thereby improving the accuracy of calculation. Furthermore, it is possible to reduce the frequency of operations to refresh the potential of the node NM or the node NMref, thereby reducing power consumption.

[0239] The transistor Tr12 is not particularly limited, and may be, for example, a Si transistor or an OS transistor. When an OS transistor is used as the transistor Tr12, the transistor Tr12 can be manufactured using the same manufacturing equipment as that of the transistor Tr11, thereby reducing manufacturing costs. The transistor Tr12 may be either an n-channel type or a p-channel type.

[0240] The current source circuit CS is connected to the wirings BL[1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL[1] to [n] and the wiring BLref. Note that the current value supplied to the wirings BL[1] to [n] may be different from the current value supplied to the wiring BLref. Here, the current supplied from the current source circuit CS to the wirings BL[1] to [n] is referred to as I C, the current supplied from the current source circuit CS to the wiring BLref is I Cref It is written as follows.

[0241] The current mirror circuit CM has wiring IL[1] to [n] and wiring ILref. The wiring IL[1] to [n] are connected to wiring BL[1] to [n], respectively, and the wiring ILref is connected to wiring BLref. Here, the connection points of the wiring IL[1] to [n] and the wiring BL[1] to [n] are denoted as nodes NP[1] to [n]. Also, the connection point of the wiring ILref and the wiring BLref is denoted as node NPref.

[0242] The current mirror circuit CM generates a current I according to the potential of the node NPref. CM The function of flowing this current I CM 21 shows the function of flowing current I from the wiring BLref to the wiring ILref. CM is discharged, and a current I flows from the wiring BL[1] to [n] to the wiring IL[1] to [n]. CM In addition, the current flowing from the current mirror circuit CM to the cell array CA via the wiring BL[1] to [n] is expressed as I B The current flowing from the current mirror circuit CM to the cell array CA via the wiring BLref is represented as I Bref It is written as follows.

[0243] The circuit WDD is connected to the wirings WD[1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to first data stored in the memory cell MC to the wirings WD[1] to [n]. The circuit WDD also has a function of supplying a potential corresponding to reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL[1] to [m]. The circuit WLD has a function of supplying a signal for selecting the memory cell MC or the memory cell MCref to which data is to be written to the wirings WL[1] to [m]. The circuit CLD is connected to the wirings RW[1] to [m]. The circuit CLD has a function of supplying a potential corresponding to second data to the wirings RW[1] to [m].

[0244] The offset circuit OFST is connected to the wirings BL[1] to [n] and the wirings OL[1] to [n]. The offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL[1] to [n] to the offset circuit OFST and / or the amount of change in the current flowing from the wirings BL[1] to [n] to the offset circuit OFST. The offset circuit OFST also has a function of outputting the detection result to the wirings OL[1] to [n]. Note that the offset circuit OFST may output a current corresponding to the detection result to the wiring OL, or may convert the current corresponding to the detection result into a voltage and output it to the wiring OL. The current flowing between the cell array CA and the offset circuit OFST is expressed as I α These are written as [1] to [n].

[0245] An example configuration of the offset circuit OFST is shown in FIG. 23. The offset circuit OFST shown in FIG. 23 includes circuits OC[1] to OC[n]. Each of the circuits OC[1] to OC[n] includes a transistor Tr21, a transistor Tr22, a transistor Tr23, a capacitance element C21, and a resistance element R1. The connection relationship between the elements is as shown in FIG. 23. The node connected to the first electrode of the capacitance element C21 and the first terminal of the resistance element R1 is referred to as node Na. The node connected to the second electrode of the capacitance element C21, one of the source or drain of the transistor Tr21, and the gate of the transistor Tr22 is referred to as node Nb.

[0246] The wiring VrefL has a function of supplying a potential Vref, the wiring VaL has a function of supplying a potential Va, and the wiring VbL has a function of supplying a potential Vb. The wiring VDDL has a function of supplying a power supply potential VDD, and the wiring VSSL has a function of supplying a power supply potential VSS. Here, the power supply potential VDD is a high power supply potential, and the power supply potential VSS is a low power supply potential. The wiring RST has a function of supplying a potential for controlling the conduction state of the transistor Tr21. The transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL form a source follower circuit.

[0247] Next, an example of the operation of the circuits OC[1] to [n] will be described. Note that, although an example of the operation of the circuit OC[1] will be described here as a representative example, the circuits OC[2] to [n] can also be operated in the same manner. First, when a first current flows through the wiring BL[1], the potential of the node Na becomes a potential corresponding to the first current and the resistance value of the resistor R1. At this time, the transistor Tr21 is in an on state, and a potential Va is supplied to the node Nb. After that, the transistor Tr21 is turned off.

[0248] Next, when a second current flows through the wiring BL[1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistor R1. At this time, the transistor Tr21 is in an off state and the node Nb is in a floating state, so the potential of the node Nb changes due to capacitive coupling as the potential of the node Na changes. Here, the change in the potential of the node Na is defined as ΔV Na If the capacitance coupling coefficient is 1, the potential of node Nb is Va+ΔV Na Then, the threshold voltage of the transistor Tr22 is V th Then, the potential from the wiring OL[1] is Va+ΔV Na -V th is output, where Va=V th By doing so, the potential ΔV Na can be output.

[0249] Potential ΔV Na is determined according to the change amount from the first current to the second current, the resistance value of the resistor element R1, and the potential Vref. Here, since the resistance value of the resistor element R1 and the potential Vref are known, the potential ΔV Na From this, the amount of change in the current flowing through the wiring BL can be obtained.

[0250] A signal corresponding to the amount of current and / or the amount of change in current detected by the offset circuit OFST as described above is input to the activation function circuit ACTV via the lines OL[1] to OL[n].

[0251] The activation function circuit ACTV is connected to the wirings OL[1] to [n] and NIL[1] to [n]. The activation function circuit ACTV has a function of performing calculations to convert the signal input from the offset circuit OFST according to a predefined activation function. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function. The signal converted by the activation function circuit ACTV is output as output data to the wirings NIL[1] to [n].

[0252] Using the semiconductor device MAC described above, it is possible to perform a product-sum operation on the first data and the second data. An example of the operation of the semiconductor device MAC when performing a product-sum operation will be described below.

[0253] 24 shows a timing chart of an operation example of the semiconductor device MAC. FIG. 24 shows the transition of the potentials of the wiring WL[1], wiring WL[2], wiring WD[1], wiring WDref, node NM[1,1], node NM[2,1], node NMref[1], node NMref[2], wiring RW[1], and wiring RW[2] in FIG. 22, and the current I B [1]-I α [1], and current I Bref The graph shows the transition of the value of the current I B [1]-I α [1] corresponds to the sum of the currents flowing from the wiring BL[1] to the memory cells MC[1,1] and [2,1].

[0254] Here, the operation will be explained focusing on memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] shown in Figure 22 as representative examples, but other memory cells MC and memory cells MCref can also be operated in the same way.

[0255] First, at time T01-T02, the potential of the wiring WL[1] becomes high level (High), and the potential of the wiring WD[1] becomes V higher than the ground potential (GND). PR -V W[1,1] The potential of the wiring WDref becomes V higher than the ground potential. PR The potential of the wiring RW[1] and the wiring RW[2] becomes the reference potential (REFP). W[1,1] is a potential corresponding to the first data stored in the memory cell MC[1,1]. PR is a potential corresponding to the reference data. As a result, the transistors Tr11 included in the memory cells MC[1,1] and MCref[1] are turned on, and the potential of the node NM[1,1] becomes V PR -V W[1,1] , the potential of node NMref[1] is V PR This becomes:

[0256] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],0 can be expressed by the following equation: where k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. th is the threshold voltage of transistor Tr12.

[0257] I MC[1,1],0 =k(V PR -V W[1,1] -V th ) 2 (E1)

[0258] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],0 can be expressed by the following formula:

[0259] I MCref[1],0 =k(V PR -V th ) 2 (E2)

[0260] Next, at time T02-T03, the potential of the line WL[1] becomes low, which turns off the transistors Tr11 of the memory cells MC[1,1] and MCref[1], and maintains the potentials of the nodes NM[1,1] and NMref[1].

[0261] As described above, it is preferable to use an OS transistor as the transistor Tr11, which can suppress leakage current of the transistor Tr11 and accurately maintain the potentials of the nodes NM[2,1] and NMref[2].

[0262] Next, at time T03-T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring WD[1] becomes V higher than the ground potential. PR -V W[2,1]The potential of the wiring WDref becomes V higher than the ground potential. PR The potential V W[2,1] is a potential corresponding to the first data stored in the memory cell MC[2,1]. As a result, the transistor Tr11 included in the memory cell MC[2,1] and the memory cell MCref[2] is turned on, and the potential of the node NM[2,1] becomes V PR -V W[2,1] , the potential of node NMref[2] is V PR This becomes:

[0263] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],0 can be expressed by the following formula:

[0264] I MC[2,1],0 =k(V PR -V W[2,1] -V th ) 2 (E3)

[0265] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],0 can be expressed by the following formula:

[0266] I MCref[2],0 =k(V PR -V th ) 2 (E4)

[0267] Next, at time T04-T05, the potential of the line WL[2] becomes low, which turns off the transistors Tr11 of the memory cells MC[2,1] and MCref[2], and maintains the potentials of the nodes NM[2,1] and NMref[2].

[0268] Through the above operations, the first data is stored in the memory cells MC[1,1] and [2,1], and the reference data is stored in the memory cells MCref[1] and [2].

[0269] Here, consider the current flowing through the wiring BL[1] and the wiring BLref at time T04-T05. A current is supplied to the wiring BLref from the current source circuit CS. The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current supplied from the current source circuit CS to the wiring BLref is defined as I Cref , the current flowing from the wiring BLref to the current mirror circuit CM is I CM,0 Then, the following formula holds:

[0270] I Cref -I CM,0 =I MCref[1],0 +I MCref[2],0 (E5)

[0271] A current is supplied to the wiring BL[1] from the current source circuit CS. The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1], [2,1]. A current also flows from the wiring BL[1] to the offset circuit OFST. The current supplied from the current source circuit CS to the wiring BL[1] is referred to as I C,0 , the current flowing from the wiring BL[1] to the offset circuit OFST is I α,0 Then, the following formula holds:

[0272] I C -I CM,0 =I MC[1,1],0 +I MC[2,1],0 +I α,0 (E6)

[0273] Next, at time T05-T06, the potential of the wiring RW[1] becomes V X[1] At this time, the potential V X[1] is supplied, and the potential of the gate of the transistor Tr12 rises due to capacitive coupling. X[1] is a potential corresponding to the second data supplied to the memory cell MC[1,1] and the memory cell MCref[1].

[0274] The change in the potential of the gate of transistor Tr12 is calculated by multiplying the change in the potential of the wiring RW by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of the capacitance element C11, the gate capacitance of transistor Tr12, parasitic capacitance, etc. For convenience, the following description will be given assuming that the change in the potential of the wiring RW and the change in the potential of the gate of transistor Tr12 are the same, i.e., the capacitance coupling coefficient is 1. In practice, the potential V is calculated by taking the capacitance coupling coefficient into consideration. X It is sufficient to determine the following.

[0275] The potential V X[1] is supplied, the potentials of the nodes NM[1,1] and NMref[1] are V X[1] Rise.

[0276] Here, at time T05-T06, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],1 can be expressed by the following formula:

[0277] I MC[1,1],1 =k(V PR -V W[1,1] +V X[1] -V th ) 2 (E7)

[0278] That is, the potential V X[1] By supplying the current, the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1] is ΔI MC[1,1] =I MC[1,1],1 -I MC[1,1],0 Increase.

[0279] Also, at time T05-T06, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],1 can be expressed by the following formula:

[0280] I MCref[1],1 =k(V PR +VX[1] -V th ) 2 (E8)

[0281] That is, the potential V X[1] By supplying the current, the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] is ΔI MCref[1] =I MCref[1],1 -I MCref[1],0 Increase.

[0282] Next, consider the current flowing through the wire BL[1] and the wire BLref. The wire BLref receives a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,1 Then, the following formula holds:

[0283] I Cref -I CM,1 =I MCref[1],1 +I MCref[2],1 (E9)

[0284] The wire BL[1] carries the current I from the current source circuit CS. C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and memory cells MC[1,1], [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is referred to as I α,1 Then, the following formula holds:

[0285] I C -I CM,1 =I MC[1,1],1 +I MC[2,1],1 +I α,1 (E10)

[0286] Then, from equations (E1) to (E10), the current I α,0 and current I α,1 Difference in current (ΔI α) can be expressed as follows:

[0287] ΔI α =I α,1 -I α,0 =2kV W[1,1] V X[1] (E11)

[0288] In this way, the differential current ΔI α is the potential V W[1,1] and V X[1] The value depends on the product of these.

[0289] After that, during the period from time T06 to time T07, the potential of the wiring RW[1] becomes the reference potential, and the potentials of the nodes NM[1,1] and NMref[1] become the same as those during the period from time T04 to time T05.

[0290] Next, at time T07-T08, the potential of the wiring RW[1] becomes V X[1] The potential of the wiring RW[2] becomes V higher than the reference potential. X[2] As a result, the potential V X[1] is supplied, and the potentials of the nodes NM[1,1] and NMref[1] are V X[1] In addition, the potential V X[2] is supplied, and the potentials of the nodes NM[2,1] and NMref[2] are V X[2] Rise.

[0291] Here, at time T07-T08, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],1 can be expressed by the following formula:

[0292] I MC[2,1],1 =k(V PR -V W[2,1] +V X[2] -V th )2 (E12)

[0293] That is, the potential V X[2] By supplying the current, the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] is ΔI MC[2,1] =I MC[2,1],1 -I MC[2,1],0 Increase.

[0294] Also, at time T07-T08, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],1 can be expressed by the following formula:

[0295] I MCref[2],1 =k(V PR +V X[2] -V th ) 2 (E13)

[0296] That is, the potential V X[2] By supplying the current, the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] is ΔI MCref[2] =I MCref[2],1 -I MCref[2],0 Increase.

[0297] Next, consider the current flowing through the wire BL[1] and the wire BLref. The wire BLref receives a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,2 Then, the following formula holds:

[0298] I Cref -I CM,2 =I MCref[1],1 +I MCref[2],1 (E14)

[0299] The wire BL[1] carries the current I from the current source circuit CS. CThe current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and memory cells MC[1,1], [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is referred to as I α,2 Then, the following formula holds:

[0300] I C -I CM,2 =I MC[1,1],1 +I MC[2,1],1 +I α,2 (E15)

[0301] Then, from the equations (E1) to (E8) and the equations (E12) to (E15), the current I α,0 and current I α,2 Difference in current (ΔI α ) can be expressed as follows:

[0302] ΔI α =I α,2 -I α,0 =2k(V W[1,1] V X[1] +V W[2,1] V X[2] )(E16)

[0303] In this way, the differential current ΔI α is the potential V W[1,1] and potential V X[1] and the potential V W[2,1] and potential V X[2] The value is determined by adding the product of and .

[0304] After that, at times T08-T09, the potentials of the wirings RW[1] and RW[2] become the reference potential, and the potentials of the nodes NM[1,1] and NMref[1] and NMref[2] become the same as at times T04-T05.

[0305] As shown in equations (E11) and (E16), the differential current ΔI input to the offset circuit OFST is α is the potential V corresponding to the first data (weight) Wand the potential V corresponding to the second data (input data) X That is, the differential current ΔI α By measuring this with the offset circuit OFST, the result of the product-sum operation of the first data and the second data can be obtained.

[0306] Although the above focuses on memory cells MC[1,1], [2,1] and memory cells MCref[1], [2], the number of memory cells MC and memory cells MCref can be set arbitrarily. When the number of rows m of memory cells MC and memory cells MCref is set to an arbitrary number i, the differential current ΔIα can be expressed by the following equation.

[0307] ΔI α =2kΣ i V W[i,1] V X[i] (E17)

[0308] Moreover, by increasing the number n of columns of memory cells MC and memory cells MCref, the number of product-sum operations executed in parallel can be increased.

[0309] As described above, by using the semiconductor device MAC, it is possible to perform a product-sum operation on the first data and the second data. Note that by using the configuration shown in FIG. 22 for the memory cells MC and the memory cells MCref, it is possible to configure a product-sum operation circuit with a small number of transistors. Therefore, it is possible to reduce the circuit scale of the semiconductor device MAC.

[0310] When the semiconductor device MAC is used for calculations in a neural network, the number of rows m of the memory cells MC can be set to correspond to the number of input data supplied to one neuron, and the number of columns n of the memory cells MC can be set to correspond to the number of neurons. For example, consider a case where a product-sum calculation is performed using the semiconductor device MAC in the hidden layer HL shown in Figure 20A. In this case, the number of rows m of the memory cells MC can be set to the number of input data supplied from the input layer IL (the number of neurons in the input layer IL), and the number of columns n of the memory cells MC can be set to the number of neurons in the hidden layer HL.

[0311] The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can be used in a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), etc.

[0312] As described above, by using the semiconductor device MAC, it is possible to perform product-sum operations of a neural network. Furthermore, by using the memory cells MC and MCref shown in Fig. 22 in the cell array CA, it is possible to provide an integrated circuit that can improve operation accuracy, reduce power consumption, or reduce the circuit scale.

[0313] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0314] (Embodiment 2) In this embodiment, a structure of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0315] FIG. 25 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 25 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 27A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 27B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 27C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 is an OS transistor and can be used as the OS transistor described in the above embodiment. The transistor 550 has a structure applicable to the Si transistor described in the above embodiment. The capacitor 600 has a structure applicable to the capacitor element described in the above embodiment.

[0316] The transistor 500 is an OS transistor. The off-state current of the transistor 500 is extremely low. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of refresh operations of the storage node can be reduced or no refresh operations are required, thereby reducing the power consumption of the semiconductor device.

[0317] In FIG. 25, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0318] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b.

[0319] 27C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0320] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0321] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs, or the like.

[0322] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0323] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0324] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0325] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0326] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using the Smart Cut method or the ELTRAN (registered trademark: Epitaxial Layer Transfer) method, which cleaves a semiconductor substrate by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0327] 25 is just an example, and the present invention is not limited to this configuration. An appropriate transistor may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit including only OS transistors (meaning transistors with the same polarity, such as only n-channel transistors), the transistor 550 may have the same configuration as the transistor 500, as shown in FIG. 26. The details of the transistor 500 will be described later.

[0328] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0329] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0330] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0331] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0332] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0333] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0334] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0335] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0336] Furthermore, insulators 320, 322, 324, and 326 are embedded with conductors 328 and 330, which connect to capacitor 600 or transistor 500. Conductors 328 and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be collectively designated by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a portion of a conductor may function as a wiring, and a portion of a conductor may function as a plug.

[0337] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0338] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 25 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0339] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0340] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0341] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 25, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as the conductors 328 and 330.

[0342] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0343] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 25, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or wiring. The conductor 376 can be provided using the same material as the conductors 328 and 330.

[0344] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0345] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 25, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be formed using the same material as the conductors 328 and 330.

[0346] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0347] Although the above describes a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386, the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0348] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0349] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0350] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550.

[0351] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0352] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0353] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulators 512 and 516 can be made of a silicon oxide film or a silicon oxynitride film.

[0354] A conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503) are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0355] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0356] Above the insulator 516 is the transistor 500 .

[0357] 27A and 27B , a transistor 500 includes a conductor 503 disposed so as to be embedded in an insulator 514 and an insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed therebetween so as to overlap the conductors 542a and 542b, an insulator 545 disposed on the bottom and side surfaces of the opening, and a conductor 560 disposed on the surface on which the insulator 545 is formed. The conductors 542a and 542b may be collectively referred to as conductor 542.

[0358] 27A and 27B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 have conductor 560a disposed inside insulator 545 and conductor 560b disposed so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 545, as shown in FIGS.

[0359] In this specification and other documents, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0360] Note that although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in and around the channel formation region, the present invention is not limited to this. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0361] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 25, 26, and 27A is merely an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0362] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0363] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0364] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0365] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0366] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like differs from the fin type configuration and the planar type configuration. By adopting the S-channel configuration, the transistor can be made more resistant to the short channel effect, in other words, less susceptible to the short channel effect.

[0367] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0368] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0369] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0370] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single-layer structure.

[0371] The insulators 520, 522, and 524 function as a second gate insulating film.

[0372] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V O H.) functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 OIt is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0373] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0374] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V OThe reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO, which may be removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542.

[0375] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0376] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0377] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0378] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0379] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0380] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0381] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0382] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0383] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a layered structure that is thermally stable and has a high dielectric constant.

[0384] 27A and 27B, the second gate insulating film has a three-layer structure including insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0385] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, the oxide 530 may be a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like).

[0386] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.

[0387] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0388] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0389] Note that oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0390] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0391] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0392] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0393] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0394] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0395] 27A shows the conductor 542a and the conductor 542b as a single layer, but they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0396] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0397] 27A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0398] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0399] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0400] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0401] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen, the insulator 544 is not an essential component. It can be designed appropriately depending on the desired transistor characteristics.

[0402] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the insulator 545. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen.

[0403] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0404] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0405] By using an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0406] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0407] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a layered structure that is thermally stable and has a high dielectric constant can be achieved.

[0408] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 27A and 27B, it may have a single-layer structure or a laminated structure of three or more layers.

[0409] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The oxygen-suppressing function of the conductor 560a can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 545, which can reduce the conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, an oxide semiconductor that can be used for the oxide 530 can be used for the conductor 560a. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0410] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0411] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0412] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0413] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0414] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0415] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0416] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0417] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0418] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0419] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0420] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0421] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0422] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0423] Furthermore, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0424] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using the same materials as the conductor 328 and the conductor 330.

[0425] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0426] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0427] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0428] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0429] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0430] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0431] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0432] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0433] Examples of substrates that can be used in the semiconductor device of one embodiment of the present invention include glass substrates, quartz substrates, sapphire substrates, ceramic substrates, metal substrates (e.g., stainless steel substrates, substrates having stainless steel foil, tungsten substrates, and substrates having tungsten foil), semiconductor substrates (e.g., single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor substrates), and silicon-on-insulator (SOI) substrates. Plastic substrates that have heat resistance sufficient to withstand the processing temperatures of this embodiment may also be used. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Crystallized glass, for example, can also be used.

[0434] Alternatively, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used as the substrate. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Synthetic resins such as acrylic are also included. Polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride are also included. Polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, and paper are also included. In particular, transistors manufactured using semiconductor substrates, single-crystal substrates, or SOI substrates can be manufactured to have small size, high current capacity, and minimal variations in characteristics, size, and shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0435] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate a semiconductor device, after it has been partially or entirely completed, from the substrate and transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to a substrate with poor heat resistance or a flexible substrate. The release layer may be, for example, a laminated structure of an inorganic film such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0436] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which a semiconductor device may be transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture semiconductor devices that are flexible, durable, heat-resistant, lightweight, or thin.

[0437] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0438] <Transistor variation 1> A transistor 500A shown in Figures 28A, 28B, and 28C is a variation of the transistor 500 having the structure shown in Figures 27A and 27B. Figure 28A is a top view of the transistor 500A, Figure 28B is a cross-sectional view of the transistor 500A in the channel length direction, and Figure 28C is a cross-sectional view of the transistor 500A in the channel width direction. Note that some elements are omitted from the top view in Figure 28A for clarity. The structures shown in Figures 28A, 28B, and 28C can also be applied to other transistors, such as the transistor 550, included in the semiconductor device of one embodiment of the present invention.

[0439] 28A, 28B, and 28C differs from the transistor 500 shown in FIGS. 27A and 27B in that the transistor 500A includes an insulator 552, an insulator 513, and an insulator 404. The transistor 500A also differs from the transistor 500 shown in FIGS. 27A and 27B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500A also differs from the transistor 500 shown in FIGS. 27A and 27B in that the insulator 520 is not provided.

[0440] 28A, 28B, and 28C, an insulator 513 is provided over an insulator 512. Furthermore, an insulator 404 is provided over the insulator 574 and the insulator 513.

[0441] 28A, 28B, and 28C, insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and insulator 404 covers them. That is, insulator 404 is in contact with the top surface of insulator 574, the side surface of insulator 574, the side surface of insulator 580, the side surface of insulator 544, the side surface of insulator 524, the side surface of insulator 522, the side surface of insulator 516, the side surface of insulator 514, and the top surface of insulator 513. As a result, oxide 530 and the like are isolated from the outside by insulators 404 and 513.

[0442] The insulators 513 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 513 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500A. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0443] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0444] <Transistor variation 2> An example configuration of a transistor 500B will be described using Figures 29A, 29B, and 29C. Figure 29A is a top view of the transistor 500B. Figure 29B is a cross-sectional view of the L1-L2 portion indicated by the dashed-dotted line in Figure 29A. Figure 29C is a cross-sectional view of the W1-W2 portion indicated by the dashed-dotted line in Figure 29A. Note that in the top view of Figure 29A, some elements are omitted for clarity.

[0445] The transistor 500B is a modified example of the transistor 500 and can be substituted for the transistor 500. Therefore, to avoid repetition of the description, the differences between the transistor 500B and the transistor 500 will be mainly described.

[0446] The conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. The conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0447] The conductor 560a has the function of suppressing oxygen diffusion, which improves the material selectivity of the conductor 560b. That is, the presence of the conductor 560a suppresses oxidation of the conductor 560b, thereby preventing a decrease in conductivity.

[0448] Furthermore, it is preferable to provide an insulator 544 so as to cover the top surface and side surfaces of the conductor 560 and the side surfaces of the insulator 545. Note that the insulator 544 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0449] Providing the insulator 544 can suppress oxidation of the conductor 560. Furthermore, including the insulator 544 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 into the transistor 500B.

[0450] In the transistor 500B, the conductor 560 overlaps part of the conductor 542a and part of the conductor 542b, and therefore the parasitic capacitance of the transistor 500B is likely to be larger than that of the transistor 500. Therefore, the operating frequency of the transistor 500B tends to be lower than that of the transistor 500. However, the transistor 500B has higher productivity than the transistor 500 because it does not require a step of forming an opening in the insulator 580 or the like and filling it with the conductor 560, the insulator 545, or the like.

[0451] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0452] (Embodiment 3) In this embodiment, an oxide semiconductor, which is a type of metal oxide, will be described.

[0453] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0454] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 30A. Fig. 30A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0455] As shown in FIG. 30A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0456] The structure within the bold frame in Figure 30A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" or "Crystal."

[0457] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 30B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 30B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 30B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 30B is 500 nm.

[0458] As shown in Figure 30B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 30B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0459] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 30C. Figure 30C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 30C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0460] As shown in FIG. 30C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0461] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 30A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0462] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0463] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0464] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0465] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0466] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0467] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0468] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0469] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0470] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0471] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0472] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0473] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0474] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0475] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0476] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0477] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0478] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0479] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0480] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0481] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0482] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0483] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0484] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0485] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0486] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0487] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0488] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0489] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0490] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0491] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0492] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0493] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0494] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0495] (Fourth embodiment) In this embodiment, an application example of the above-described semiconductor device will be described.

[0496] [Semiconductor wafers, chips] 31A illustrates a top view of a substrate 701 before dicing. The substrate 701 can be, for example, a semiconductor substrate (also referred to as a "semiconductor wafer"). A plurality of circuit regions 702 are provided over the substrate 701. The circuit region 702 can include a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, an image sensor, or the like.

[0497] Each of the multiple circuit regions 702 is surrounded by an isolation region 703. Separation lines (also called "dicing lines") 704 are set at positions overlapping the isolation regions 703. By cutting the substrate 701 along the separation lines 704, chips 705 including the circuit regions 702 can be cut out from the substrate 701. An enlarged view of the chips 705 is shown in FIG. 31B.

[0498] Furthermore, a conductive layer or a semiconductor layer may be provided in the separation region 703. By providing a conductive layer or a semiconductor layer in the separation region 703, ESD that may occur during the dicing process can be mitigated, and a decrease in the yield of the dicing process can be prevented. Furthermore, the dicing process is generally performed while pure water, in which carbon dioxide or the like is dissolved to reduce the resistivity, is flowed over the cutting area for the purposes of cooling the substrate, removing shavings, preventing static electricity, etc. By providing a conductive layer or a semiconductor layer in the separation region 703, the amount of pure water used can be reduced. This can reduce the production cost of the semiconductor device. Furthermore, the productivity of the semiconductor device can be increased.

[0499] It is preferable to use a material having a band gap of 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.5 eV, for the semiconductor layer provided in the separation region 703. Use of such a material allows the accumulated charge to be slowly discharged, thereby suppressing the sudden movement of charge due to ESD and making it less likely to cause electrostatic breakdown.

[0500] [Electronic Components] An example of applying chip 705 to an electronic component will be described with reference to Figures 32A and 32B. The electronic component is also called a semiconductor package or an IC package. There are multiple standards and names for electronic components depending on the terminal lead-out direction and terminal shape.

[0501] The electronic component is completed by combining the semiconductor device shown in the above embodiment with components other than the semiconductor device in an assembly process (post-process).

[0502] The following describes the post-process using the flowchart shown in Figure 32A. After the element substrate having the semiconductor device shown in the above embodiment is completed in the pre-process, a "backside grinding process" is performed to grind the backside of the element substrate (the surface on which the semiconductor device, etc. is not formed) (step S721). By thinning the element substrate by grinding, warping of the element substrate can be reduced, and electronic components can be made smaller.

[0503] Next, a "dicing process" is performed to separate the element substrate into a plurality of chips (chips 705) (step S722). Then, a "die bonding process" is performed to individually pick up the separated chips and bond them onto a lead frame (step S723). The bonding between the chip and the lead frame in the die bonding process is performed using a method appropriate for the product, such as bonding with resin or bonding with tape. It is also possible to bond the chip onto an interposer substrate instead of a lead frame.

[0504] Next, a "wire bonding process" is performed (step S724), in which the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. Silver wires or gold wires can be used for the thin metal wires. The wire bonding can be ball bonding or wedge bonding.

[0505] The wire-bonded chip is then subjected to the "encapsulation process (molding process)" in which it is encapsulated with epoxy resin or the like (step S725). The encapsulation process fills the interior of the electronic component with resin, protecting the circuitry built into the chip and the wires connecting the chip to the leads from external mechanical forces, and also reducing the deterioration of characteristics (reduced reliability) due to moisture and dust.

[0506] Next, a "lead plating process" is performed to plate the leads of the lead frame (step S726). Plating prevents the leads from rusting, allowing for more reliable soldering when mounting the device on a printed circuit board later. Next, a "forming process" is performed to cut and form the leads (step S727).

[0507] Next, a "marking process" is carried out to print (mark) the surface of the package (step S728), and then an "inspection process" (step S729) is carried out to check whether the external shape is good or not, whether there are any malfunctions, etc., and the electronic component is completed.

[0508] 32B shows a perspective schematic diagram of a completed electronic component. In FIG. 32B, a perspective schematic diagram of a QFP (Quad Flat Package) is shown as an example of an electronic component. Electronic component 750 shown in FIG. 32B includes leads 755 and a semiconductor device 753. The semiconductor device described in the above embodiment can be used as semiconductor device 753.

[0509] 32B is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined and electrically connected on the printed circuit board 752 to complete a board (mounted board 754) on which electronic components are mounted. The completed mounted board 754 is used in electronic devices and the like.

[0510] [Electronic equipment] Next, examples of electronic devices including the semiconductor device or the electronic component according to one embodiment of the present invention will be described with reference to FIGS.

[0511] Examples of electronic devices using a semiconductor device or electronic component according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Disc) players. Examples of such devices include image playback devices that play back still images or videos stored on recording media such as CDs, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tablet terminals, large game consoles such as pachinko machines, calculators, portable information terminals (also referred to as "mobile information terminals"), electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids.

[0512] Mobile bodies propelled by electric motors using power from power storage devices are also included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) that combine an internal combustion engine with an electric motor, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0513] A semiconductor device or electronic component according to one embodiment of the present invention can be used in a communication device or the like built into these electronic devices.

[0514] The electronic device may have sensors (including those that can measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), etc.

[0515] Electronic devices can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0516] 33 and 34A to 34F illustrate examples of electronic devices. In FIG. 33, a display device 8000 is an example of an electronic device including a semiconductor device 8004 according to one embodiment of the present invention. Specifically, the display device 8000 corresponds to a display device for receiving TV broadcasts and includes a housing 8001, a display portion 8002, a speaker portion 8003, a semiconductor device 8004, a power storage device 8005, and the like. The semiconductor device 8004 according to one embodiment of the present invention is provided inside the housing 8001. The semiconductor device 8004 can store control information, a control program, and the like. The semiconductor device 8004 has a communication function, allowing the display device 8000 to function as an IoT device. The display device 8000 can receive power from a commercial power source or use power stored in the power storage device 8005.

[0517] The display unit 8002 can be a liquid crystal display device, a light-emitting display device in which each pixel has a light-emitting element such as an organic EL element, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emission Display), or other display device.

[0518] The display device includes all display devices for displaying information, such as those for receiving TV broadcasts, those for personal computers, and those for displaying advertisements.

[0519] 33 , a stationary lighting device 8100 is an example of an electronic device including a semiconductor device 8103 according to one embodiment of the present invention. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, a semiconductor device 8103, a power storage device 8105, and the like. Although FIG. 33 illustrates an example in which the semiconductor device 8103 is provided inside a ceiling 8104 on which the housing 8101 and the light source 8102 are installed, the semiconductor device 8103 may be provided inside the housing 8101. The semiconductor device 8103 can store information such as the light emission luminance of the light source 8102, a control program, and the like. The semiconductor device 8103 has a communication function, which allows the lighting device 8100 to function as an IoT device. The lighting device 8100 can receive power from a commercial power source or use power stored in a power storage device.

[0520] Note that although the lighting device 8100 in FIG. 33 is a stationary lighting device provided on the ceiling 8104, the semiconductor device according to one embodiment of the present invention can also be used in a stationary lighting device provided on a side wall 8405, a floor 8406, a window 8407, or the like, other than the ceiling 8104, or can also be used in a tabletop lighting device.

[0521] Furthermore, an artificial light source that artificially obtains light using electric power can be used as the light source 8102. Specifically, examples of the artificial light source include discharge lamps such as incandescent lamps and fluorescent lamps, and light-emitting elements such as LEDs and organic EL elements.

[0522] In FIG. 33 , an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device including a semiconductor device 8203 according to one embodiment of the present invention. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, a power storage device 8205, and the like. Although FIG. 33 illustrates the case where the semiconductor device 8203 is provided in the indoor unit 8200, the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can store control information, a control program, and the like for the air conditioner. The semiconductor device 8203 has a communication function, allowing the air conditioner to function as an IoT device. The air conditioner can receive power from a commercial power source or use power stored in the power storage device 8205.

[0523] Note that although a separate-type air conditioner including an indoor unit and an outdoor unit is illustrated in FIG. 33, the semiconductor device according to one embodiment of the present invention can also be used in an all-in-one air conditioner in which the functions of the indoor unit and the outdoor unit are combined in one housing.

[0524] 33 , an electric refrigerator-freezer 8300 is an example of an electronic device including a semiconductor device 8304 according to one embodiment of the present invention. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, a power storage device 8305, and the like. In FIG. 33 , the power storage device 8305 is provided inside the housing 8301. The semiconductor device 8304 can store control information, a control program, and the like for the electric refrigerator-freezer 8300. The semiconductor device 8304 has a communication function, which allows the electric refrigerator-freezer 8300 to function as an IoT device. The electric refrigerator-freezer 8300 can receive power from a commercial power source or use power stored in the power storage device 8305.

[0525] 34A shows an example of a wristwatch-type mobile information terminal. The mobile information terminal 6100 includes a housing 6101, a display portion 6102, a band 6103, operation buttons 6105, and the like. The mobile information terminal 6100 also includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the mobile information terminal 6100, the mobile information terminal 6100 can function as an IoT device.

[0526] 34B shows an example of a mobile phone. A mobile information terminal 6200 includes a display portion 6202 incorporated in a housing 6201, operation buttons 6203, a speaker 6204, a microphone 6205, and the like.

[0527] The portable information terminal 6200 also includes a fingerprint sensor 6209 in an area overlapping with the display portion 6202. The fingerprint sensor 6209 may be an organic optical sensor. Since fingerprints are different for each person, personal authentication can be performed by acquiring a fingerprint pattern with the fingerprint sensor 6209. Light emitted from the display portion 6202 can be used as a light source for acquiring the fingerprint pattern with the fingerprint sensor 6209.

[0528] The portable information terminal 6200 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. When the portable information terminal 6200 includes the semiconductor device or electronic component according to one embodiment of the present invention, the portable information terminal 6200 can function as an IoT device.

[0529] 34C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the top surface of a housing 6301, a plurality of cameras 6303 arranged on the side, a brush 6304, an operation button 6305, various sensors, and the like. Although not shown, the cleaning robot 6300 is provided with tires, a suction port, and the like. The cleaning robot 6300 can move by itself, detect dust 6310, and suck up the dust from a suction port arranged on the bottom surface.

[0530] For example, the cleaning robot 6300 can analyze an image captured by the camera 6303 and determine whether or not there is an obstacle such as a wall, furniture, or a step. Furthermore, if an object that may become entangled in the brush 6304, such as a wire, is detected through image analysis, the cleaning robot 6300 can stop rotation of the brush 6304. The cleaning robot 6300 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the cleaning robot 6300, the cleaning robot 6300 can function as an IoT device.

[0531] Fig. 34D shows an example of a robot. The robot 6400 shown in Fig. 34D includes a computing device 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a movement mechanism 6408.

[0532] The microphone 6402 has a function of detecting the user's voice, environmental sounds, etc. The speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user using the microphone 6402 and the speaker 6404.

[0533] The display unit 6405 has a function of displaying various information. The robot 6400 can display information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. The display unit 6405 may also be a detachable information terminal, which can be installed in a fixed position on the robot 6400 to enable charging and data transfer.

[0534] The upper camera 6403 and the lower camera 6406 have a function of capturing images of the periphery of the robot 6400. In addition, the obstacle sensor 6407 can detect the presence or absence of an obstacle in the moving direction when the robot 6400 moves forward using the moving mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407. The light-emitting device of one embodiment of the present invention can be used for the display portion 6405.

[0535] The robot 6400 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the robot 6400, the robot 6400 can function as an IoT device.

[0536] Fig. 34E shows an example of an aircraft. Aircraft 6500 shown in Fig. 34E has propeller 6501, camera 6502, battery 6503, etc., and has the function of flying autonomously.

[0537] For example, image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of obstacles when moving. The electronic component 6504 can also estimate the remaining battery charge from a change in the storage capacity of the battery 6503. The flying object 6500 includes a semiconductor device or electronic component according to one embodiment of the present invention therein. By using the semiconductor device or electronic component according to one embodiment of the present invention in the flying object 6500, the flying object 6500 can function as an IoT device.

[0538] 34F illustrates an example of an automobile. The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, and the like. The automobile 7160 includes a semiconductor device or an electronic component according to one embodiment of the present invention inside. By using the semiconductor device or the electronic component according to one embodiment of the present invention in the automobile 7160, the automobile 7160 can function as an IoT device.

[0539] The configurations, structures, methods, and the like shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like shown in other embodiment modes and embodiments. [Example]

[0540] In this example, an example is shown in which an acceleration sensor is used as a sensor element of one embodiment of the present invention, a semiconductor device including the sensor element is placed on a housing having a fan, and vibration is evaluated.

[0541] 35 shows a photograph of the semiconductor device 900, the housing 901, and the housing 902, which are used in the evaluation of this example. Each of the housings 901 and 902 has a built-in fan.

[0542] A semiconductor device 900 shown in Fig. 35 is equipped with a sensor circuit 903 and a processing device 904. The sensor circuit used is an ADXL362 from ANALOG DEVICES. The ADXL362 is a circuit that has a MEMS acceleration sensor. The ADXL362 also has a 12-bit analog-to-digital conversion circuit. The waveform detected by the acceleration sensor is processed by the analog-to-digital conversion circuit and the like of the sensor circuit, and then provided to the processing device 904.

[0543] The semiconductor device 900 is equipped with a battery.

[0544] The semiconductor device 900 can wirelessly transmit and receive signals to and from a personal computer using Bluetooth (registered trademark).

[0545] Fig. 36A shows an enlarged photograph of the semiconductor device 900 shown in Fig. 35. The semiconductor device 900 has a first block 900A, a second block 900B, and a third block 900C.

[0546] 36B shows a photograph of the exterior of the first block 900A to the third block 900C. The first block 900A has a processing device 904. The second block 900B has a sensor circuit 903. The third block 900C has a socket 905 for installing a battery.

[0547] The test objects used were a housing 901 with a built-in first fan and a housing 902 with a built-in second fan. The first and second fans have multiple blades arranged radially from the rotation axis. It was known that the second fan would vibrate more than the first fan during rotation. These housings with fans with different vibration magnitudes were evaluated using semiconductor devices. A battery was installed in the socket 905.

[0548] First, semiconductor device 900 is placed on housing 901, and the signal detected by the acceleration sensor is processed by the sensor circuit to produce a waveform, as shown in Figure 37A. The horizontal axis of the graph shown in Figure 37A represents time, and the vertical axis represents acceleration. The fast Fourier transform of the waveform shown in Figure 37A is shown in Figure 37B. The horizontal axis of Figure 37B represents frequency, and the vertical axis represents intensity.

[0549] Next, semiconductor device 900 was placed on the second fan, and the signal detected by the acceleration sensor was processed by the sensor circuit, resulting in a waveform shown in Figure 38A. The horizontal axis of the graph shown in Figure 38A is time, and the vertical axis is acceleration. The fast Fourier transform of the waveform shown in Figure 38A is shown in Figure 38B. The horizontal axis of Figure 38B is frequency, and the vertical axis is intensity.

[0550] In this example, for simplicity, the same semiconductor device was placed on two fans in turn and evaluated, but if two semiconductor devices are prepared, one semiconductor device can be placed on each fan.

[0551] It can be seen that the amplitude intensity is higher in Figure 38A than in Figure 37A. For example, if the normal range is between -10 [g] and +10 [g] and anything outside this range is deemed abnormal, the condition of the second fan is deemed abnormal. Furthermore, in Figure 38B, a large peak is observed near 100 Hz, indicating that there is an abnormality. The condition of the fan can be estimated by analyzing the characteristics of the waveform after fast Fourier transform. [Explanation of symbols]

[0552] ACTV: activation function circuit, BKC1: circuit, BKC2: circuit, BKC10: circuit, BKC20: circuit, C1: capacitance element, C3: capacitance element, C6: capacitance element, C11: capacitance element, C21: capacitance element, CB1: capacitance element, CB2: capacitance element, CB11: capacitance element, CB12: capacitance element, CE: signal, CLD: circuit, CLKM: reference clock signal, CLK: clock signal, CM: current mirror circuit, CS: current source circuit, D: data signal, DB: data signal, FN1: node, FN2: node, GCLK2: clock signal, INT: signal, INV11: inverter inverter circuit, INV12: inverter circuit, M1: transistor, M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, M11: transistor, M12: transistor, MA1: transistor, MAC: semiconductor device, MC: memory cell, MCref: memory cell, MC1: transistor, MC2: transistor, MemC1: circuit, MemC2: circuit, MR1: transistor, MW1: transistor, MW11: transistor, MW2: transistor, MW12: transistor, Na: node, Nb : Node, NB1: Node, ND: Node, NET1: Node, NET2: Node, NK1: Node, NM: Node, NMref: Node, NP: Node, NPref: Node, NR1: Node, OC: Circuit, OFST: Offset Circuit, OSC: Signal, OSG: Signal, OSR: Signal, OSS: Signal, RESET: Signal, PCC10: Circuit, PSE5: Signal, PSE6: Signal, R1: Resistor Element, RTC10: Circuit, SLC: Signal, SLP: Signal, SMC20: Circuit, SN1: Node, SN2: Node, SN3: Node, Tr11: Transistor, Tr12 :Transistor, Tr21:Transistor, Tr22:Transistor, Tr23:Transistor, WDD:Circuit, WLD:Circuit, WE:Signal, 10:Power supply circuit, 11:Memory cell, 15:Memory cell, 16:Memory cell, 20:PU, 21:PU, 30:Processor core, 31:Memory circuit, 32:Circuit, 35:Power supply line, 40:Cache, 41:Memory array, 42:Peripheral circuit, 43:Control circuit, 45:Memory cell, 60:PMU, 61:Circuit, 65:Clock control circuit, 70:PSW, 71:PSW, 80:Terminal, 81:Terminal, 82:Terminal, 83:Terminal,90: terminal, 91: terminal, 92: terminal, 93: terminal, 93a: terminal, 93b: terminal, 94: terminal, 100: memory circuit, 110: FF, 120: memory cell, 121: buffer circuit, 122: transistor, 123: capacitance element, 130: processor core, 131: control device, 132: program counter, 133: pipeline register, 134: pipeline register, 135: register file, 136: ALU, 137: data bus, 202: cache memory device, 203: cache memory device, 240: NOSRAM, 242: power domain , 243: power domain, 245: power switch, 247: power switch, 250: memory cell array, 251: control circuit, 252: row circuit, 253: column circuit, 301: sensor circuit, 301a: sensor circuit, 301b: sensor circuit, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 351: DOSRAM, 352: insulator, 354: insulator, 356: conductor Conductor, 360: insulator, 361: memory cell array, 362: insulator, 364: insulator, 365: peripheral circuit, 366: conductor, 370: insulator, 371: power switch, 372: insulator, 373: power switch, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 401: antenna, 402: communication circuit, 404: insulator, 500: transistor, 500A: transistor, 500B: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 5 13: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 548: conductor, 550: transistor, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator,586: insulator, 600: capacitor, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 700: semiconductor device, 701: substrate, 702: circuit region, 703: separation region, 704: separation line, 705: chip, 710: sensor element, 710c: sensor element, 710d: sensor element, 711: detection unit, 711a: detection unit, 711b: detection unit, 712: determination circuit, 712a: determination circuit, 712b: determination circuit, 713: analog-to-digital conversion circuit, 713a: analog-to-digital conversion circuit, 713b: analog-to-digital conversion circuit, 714 : Sample and hold circuit, 714A: Sample and hold circuit, 714B: Sample and hold circuit, 714c: Sample and hold circuit, 714C: Sample and hold circuit, 714d: Sample and hold circuit, 715: Memory, 717: Control device, 750: Electronic component, 752: Printed circuit board, 753: Semiconductor device, 754: Mounting board, 755: Lead, 799: Object, 900: Semiconductor device, 900A: Block, 900B: Block, 900C: Block, 901: Housing, 902: Housing, 903: Sensor circuit, 904: Processing device, 905: Socket, 6100 : Mobile information terminal, 6101: housing, 6102: display unit, 6103: band, 6105: operation button, 6200: Mobile information terminal, 6201: housing, 6202: display unit, 6203: operation button, 6204: speaker, 6205: microphone, 6209: fingerprint sensor, 6300: cleaning robot, 6301: housing, 6302: display unit, 6303: camera, 6304: brush, 6305: operation button, 6310: dust, 6400: robot, 6401: illuminance sensor, 6402: microphone, 6403: upper camera, 6404: speaker, 6405: display unit, 6 406: lower camera, 6407: obstacle sensor, 6408: moving mechanism, 6409: computing device, 6500: flying object, 6501: propeller, 6502: camera, 6503: battery, 6504: electronic component, 7160: automobile, 8000: display device, 8001: housing, 8002: display unit, 8003: speaker unit, 8004: semiconductor device, 8005: power storage device, 8100: lighting device, 8101: housing, 8102: light source, 8103: semiconductor device, 8104: ceiling, 8105: power storage device, 8200: indoor unit, 8201: housing, 8202: air outlet, 8203: semiconductor device,8204: Outdoor unit, 8205: Power storage device, 8300: Electric refrigerator-freezer, 8301: Housing, 8302: Refrigerator door, 8303: Freezer door, 8304: Semiconductor device, 8305: Power storage device, 8405: Side wall, 8406: Floor, 8407: Window,

Claims

1. A power supply control device comprising a sensor circuit, a power management device, and a processing circuit, the sensor circuit includes a sensor element, a determination circuit, and a memory; the power management device has a function of controlling the power supply to the arithmetic processing circuit, the arithmetic processing circuit includes a first circuit having a first storage circuit and a second circuit having a second storage circuit; the first circuit has a function of holding first data in the first memory circuit while power is being supplied to the arithmetic processing circuit; the second circuit has a function of reading the first data stored in the first storage circuit and writing the first data to the second storage circuit while power is being supplied to the arithmetic processing circuit, and a function of storing the first data in the second storage circuit while power supply to the arithmetic processing circuit is stopped; the sensor circuit has a function of providing second data from the determination circuit to the power management device when the determination circuit compares the detection signal from the sensor element with reference data and determines that an abnormality has occurred; the second data includes a signal requesting an interrupt process; the power management device has a function of resuming power supply to the arithmetic processing circuit in accordance with the second data; the memory includes a first transistor having an oxide semiconductor in a channel formation region, a second transistor having silicon in a channel formation region, and a capacitor; a gate of the second transistor is electrically connected to one of the source and the drain of the first transistor and a first electrode of the capacitor element; The reference data is stored in the memory.

2. In claim 1, The oxide semiconductor includes In, Ga, and Zn.

3. In claim 1 or 2, The sensor element is a semiconductor device having a function of measuring one or more selected from force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared rays.

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