Image display device manufacturing method and image display device

Abstract

A method for manufacturing an image display device according to an embodiment comprises: a step of preparing a first substrate including a circuit element formed on a first surface of the substrate, a first wiring layer connected to the circuit element, and a first insulating film that covers the circuit element and the first wiring layer; a step of forming a graphene-including layer on the first insulating film; a step of forming a semiconductor layer including a light-emitting layer on the graphene-including layer; a step of processing the semiconductor layer to form a light-emitting element including a light-emitting surface on the graphene-including layer and a top surface on the side opposite to the light-emitting surface; a step of forming a second insulating film that covers the first insulating film, the graphene-including layer, and the light-emitting element; a step of forming a first via penetrating the first insulating film and the second insulating film; and a step of forming a second wiring layer on the second insulating film.

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device. [Background technology]

[0002] There is a demand for thin image display devices that have high brightness, a wide viewing angle, high contrast, and low power consumption. To meet these market demands, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is anticipated as a self-emitting element. A method of manufacturing display devices using micro LEDs has been introduced in which individually formed micro LEDs are sequentially transferred to a driving circuit. However, as the number of micro LED elements increases with the trend toward higher image quality, such as full HD, 4K, and 8K, the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and then sequentially transferred to a substrate on which a driving circuit, etc., is formed. Furthermore, there is a risk of poor connections between the micro LEDs and the driving circuit, etc., resulting in reduced yields.

[0004] A technique is known in which a semiconductor layer including a light-emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-141492 [Non-patent literature]

[0006] [Non-Patent Document 1] H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils", SCIENTIFIC REPORTS, 7:2112, 18 May 2017 [Non-patent document 2] JW Shon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes on amorphous substrates by pulsed sputtering", SCIENTIFIC REPORTS, 4:5325, 23 June 2014 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0008] A method for manufacturing an image display device according to one embodiment of the present invention includes the steps of: preparing a first substrate including circuit elements formed on a first surface of the substrate, a first wiring layer connected to the circuit elements, and a first insulating film covering the circuit elements and the first wiring layer; forming a graphene-containing layer on the first insulating film; forming a semiconductor layer including a light-emitting layer on the graphene-containing layer; processing the semiconductor layer to form a light-emitting element including a light-emitting surface on the graphene-containing layer and a top surface opposite the light-emitting surface; forming a second insulating film covering the first insulating film, the graphene-containing layer, and the light-emitting element; forming a first via that penetrates the first insulating film and the second insulating film; and forming a second wiring layer on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer.

[0009] An image display device according to one embodiment of the present invention includes a first member having a first surface, a circuit element provided on the first surface, a first wiring layer electrically connected to the circuit element, a first insulating film covering the first surface, the circuit element, and the first wiring layer, a layer including graphene provided on the first insulating film, a light-emitting element including a light-emitting surface on the layer including graphene and a top surface opposite the light-emitting surface, a second insulating film covering the first insulating film and the light-emitting element, a first via provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer.

[0010] An image display device according to one embodiment of the present invention includes a first member having a first surface, a circuit element provided on the first surface, a first wiring layer electrically connected to the circuit element, a first insulating film covering the first surface, the circuit element, and the first wiring layer, a translucent member provided through the first insulating film and the first member, a light-emitting element including a light-emitting surface on the translucent member and a top surface opposite the light-emitting surface, a second insulating film covering the first insulating film and the light-emitting element, a first via provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The first member includes a light-shielding portion having a lower light transmittance than the translucent member. The first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer.

[0011] An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a plurality of transistors provided on the first surface, a first wiring layer electrically connected to the plurality of transistors, a first insulating film covering the first surface, the plurality of transistors, and the first wiring layer, a layer including graphene provided on the first insulating film, a first semiconductor layer including a light-emitting surface on the layer including graphene, on which a plurality of light-emitting regions can be formed, a plurality of light-emitting layers provided on the first semiconductor layer, a plurality of second semiconductor layers provided on the plurality of light-emitting layers, each having a conductivity type different from that of the first semiconductor layer, a second insulating film covering the first insulating film, the first semiconductor layer, the plurality of light-emitting layers, and the plurality of second semiconductor layers, a plurality of first vias provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The plurality of second semiconductor layers are separated by the second insulating film. The plurality of light-emitting layers are separated by the second insulating film. The plurality of first vias are provided between the first wiring layer and the second wiring layer and electrically connect the first wiring layer and the second wiring layer.

[0012] An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, circuit elements provided on the first surface, a first wiring layer electrically connected to the circuit elements, a first insulating film covering the first surface, the circuit elements, and the first wiring layer, a layer including graphene provided on the first insulating film, a plurality of light-emitting elements each including a light-emitting surface on the layer including graphene and a top surface opposite the light-emitting surface, a second insulating film covering the first insulating film and the plurality of light-emitting elements, a first via provided through the first insulating film and the second insulating film, and a second wiring layer provided on the second insulating film. The first via is provided between the first wiring layer and the second wiring layer and electrically connects the first wiring layer and the second wiring layer. [Effects of the Invention]

[0013] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer step of light emitting elements and improves yield.

[0014] According to one embodiment of the present invention, it is possible to reduce the size of the light emitting element, and a high-definition image display device is realized. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic cross-sectional view illustrating a part of an image display device according to a first embodiment. [Figure 2] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the first embodiment. [Figure 3] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 4] FIG. 1 is a schematic plan view illustrating a part of an image display device according to a first embodiment. [Figure 5A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 5B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6A]3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 8] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9C] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9D] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 10] 5A to 5C are schematic cross-sectional views illustrating a part of a modified example of the manufacturing method of the image display device of the first embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a modified example of the first embodiment. [Figure 12] 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 13] FIG. 10 is a schematic perspective view illustrating an image display device according to a modified example of the first embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a second embodiment. [Figure 15] FIG. 10 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 16A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 16B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 17A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 17B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 18] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment. [Figure 20A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 20B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 21A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 21B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 22A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 22B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 23A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 23B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 24] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment. [Figure 25A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 25B]10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 26A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 26B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 27] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fifth embodiment. [Figure 28A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 28B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 29] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 30] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 31] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a seventh embodiment. [Figure 32] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a seventh embodiment. [Figure 33] FIG. 13 is a block diagram illustrating an image display device according to an eighth embodiment. [Figure 34] FIG. 13 is a block diagram illustrating an image display device according to a modified example of the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0017] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. FIG. 1 shows a schematic configuration of a sub-pixel 20 of the image display device of this embodiment. In the following, the description may be made using the XYZ three-dimensional coordinate system. The light-emitting elements 150 are arranged in a two-dimensional plane as shown in FIGS. 12 and 13 (described later). A light-emitting element 150 is provided for each subpixel 20. The two-dimensional plane on which the subpixels 20 are arranged is defined as the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line AA' in FIG. 4 (described later), and is a cross section obtained by connecting multiple cross sections perpendicular to the XY plane on a single plane. In other figures, as in FIG. 1, in cross sections of multiple planes perpendicular to the XY plane, the X and Y axes are not shown, but only the Z axis perpendicular to the XY plane is shown. In other words, in these figures, the plane perpendicular to the Z axis is defined as the XY plane.

[0018] In the following, the positive direction of the Z axis may be referred to as "up" or "above," and the negative direction of the Z axis may be referred to as "down" or "below," but the direction along the Z axis is not necessarily limited to the direction in which gravity acts. The length along the Z axis may be referred to as height.

[0019] The subpixel 20 has a light-emitting surface 151S that is substantially parallel to the XY plane. The light-emitting surface 151S is a surface that emits light mainly in the negative direction of the Z axis, which is perpendicular to the XY plane. In this embodiment, its modifications, and all embodiments and modifications thereof described below, the light-emitting surface emits light mainly in the negative direction of the Z axis.

[0020] 1, a subpixel 20 of the image display device includes a substrate (first member) 102, a transistor (circuit element) 103, a first wiring layer 110, a first interlayer insulating film (first insulating film) 112, a graphene sheet 140a, a light-emitting element 150, a second interlayer insulating film (second insulating film) 156, a via (first via) 161d, and a second wiring layer 160. The subpixel 20 further includes a color filter 180.

[0021] In this embodiment, the transistor 103 is provided on one surface (first surface) 102a of the substrate 102. A color filter 180 is provided on the other surface 102b of the substrate 102. The substrate 102 is light-transmitting and is, for example, a glass substrate.

[0022] The transistor 103 is formed on a TFT lower layer film 106 provided on the surface 102a. The transistor 103 is, for example, a thin film transistor (TFT). The transistor 103 is covered with an insulating film 108, and the insulating film 108, together with a first wiring layer 110 provided on the insulating film 108, is covered with a first interlayer insulating film 112.

[0023] The light emitting element 150 is provided on the first interlayer insulating film 112 via the graphene sheet 140a. The light emitting element 150 is driven by a transistor 103 provided below the light emitting element 150 to emit light. The light emitted from the light emitting element 150 is incident on the color filter 180 via the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102. The light incident on the color filter 180 is converted by the color filter 180 into light having a desired wavelength and is emitted to the outside. In this embodiment, the light emitted from the light emitting element 150 travels in the negative direction of the Z axis and is emitted to the outside. The same applies to the modified examples and other embodiments described below.

[0024] The configuration of the sub-pixel 20 will be described in detail below. The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided below the light-emitting surface 151S of the light-emitting element 150 in accordance with the shape of the light-emitting surface 151S. In the color filter 180, the portion other than the color conversion portion 182 is made into a light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a clear image.

[0025] The color conversion section 182 may have one layer or two or more layers. FIG. 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., wavelength, of the light emitted by the subpixel 20. When the emitted color of the subpixel 20 is red, the color conversion section 182 preferably has two layers, that is, a color conversion layer 183 and a filter layer 184 that transmits red light. When the emitted color of the subpixel 20 is green, the color conversion section 182 preferably has two layers, that is, a color conversion layer 183 and a filter layer 184 that transmits green light. When the emitted color of the subpixel 20 is blue, the color conversion section 182 preferably has one layer, that is, a filter layer 184.

[0026] When color conversion section 182 has two layers, one layer is color conversion layer 183 and the other layer is filter layer 184. Color conversion layer 183 is stacked on filter layer 184, and is provided at a position closer to light emitting element 150 than filter layer 184.

[0027] Color conversion layer 183 converts the wavelength of light emitted by light emitting element 150 to a desired wavelength. In the case of a subpixel 20 that emits red light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 630 nm±20 nm. In the case of a subpixel 20 that emits green light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 532 nm±20 nm.

[0028] Filter layer 184 of the sub-pixels that emit red or green light blocks wavelength components of blue light that remain without being color converted by color conversion layer 183. Filter layer 184 of the sub-pixels that emit blue light blocks wavelength components of light other than blue.

[0029] When the color of light emitted by subpixel 20 is blue, the light may be output via color conversion layer 183, or may be output via filter layer 184 without via color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is approximately 467 nm±30 nm, the light may be output without via color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is 410 nm±30 nm, it is preferable to provide color conversion layer 183 in order to convert the wavelength of the output light to approximately 467 nm±30 nm.

[0030] Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with a filter layer 184 that transmits blue light, minute reflections of external light other than blue light that occur on the surface of the light-emitting element 150 are suppressed.

[0031] The color filter 180 is provided in contact with the surface 102b of the substrate 102, and the TFT lower layer film 106 is provided over the surface 102a opposite to the surface 102b. The transistor 103 is provided on the TFT lower layer film 106. The TFT lower layer film 106 is provided to ensure flatness during the formation of the transistor 103 and to protect the TFT channel of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is an insulating film made of SiO2 or the like, and is light-transmitting.

[0032] In addition to the transistor 103, other circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and a circuit 101 is configured with wiring and the like. For example, in FIG. 3 described below, the transistor 103 corresponds to the drive transistor 26. Other circuit elements in FIG. 3 include the selection transistor 24 and the capacitor 28. The circuit 101 includes a TFT channel 104, an insulating layer 105, an insulating film 108, vias 111s and 111d, and a first wiring layer 110.

[0033] In this example, the transistor 103 is a p-channel TFT. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous silicon region formed on the TFT underlayer film 106. For example, laser annealing using a laser is used to polycrystallize and activate the amorphous silicon region. A TFT formed by the LTPS process has sufficiently high mobility.

[0034] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the regions 104s and 104d. The regions 104s and 104d contain impurities such as boron (B) and boron fluoride (BF), forming p-type semiconductor regions. The region 104s is in ohmic contact with the via 111s, and the region 104d is in ohmic contact with the via 111d.

[0035] The insulating layer 105 is provided on the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is made of, for example, SiO2. The insulating layer 105 may be a multi-layer insulating layer containing SiO2, Si3N4, or the like.

[0036] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate it from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, thereby controlling the current flowing between the regions 104s and 104d.

[0037] The gate 107 may be formed of, for example, polycrystalline Si, or may be formed of a high-melting point metal such as W or Mo. When the gate 107 is formed of a polycrystalline Si film, it is formed by, for example, CVD or the like.

[0038] The insulating film 108 is provided on the insulating layer 105 and the gate 107. The insulating film 108 is an inorganic film such as SiO2 or Si3N4. Preferably, the insulating film 108 is a laminated film of SiO2 and Si3N4. The insulating film 108 is provided to separate adjacent circuit elements such as the transistors 103 from each other. The insulating film 108 provides a surface with a flatness sufficient to allow the formation of the first wiring layer 110. The insulating film 108, the insulating layer 105, and the TFT lower film 106 are light-transmitting.

[0039] The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 can include a plurality of wirings that can have different potentials. The first wiring layer 110 includes wirings 110s and 110d. The wirings 110s and 110d are formed separately and can be connected to different potentials.

[0040] In the cross-sectional views from Figure 1 onwards, unless otherwise specified, the reference numerals representing the wiring layers are shown next to the wires that make up the wiring layers. In the case of Figure 1, for example, the reference numeral for the first wiring layer 110 is shown next to the wire 110s.

[0041] The wiring 110s is provided above the region 104s. The wiring 110s is connected to, for example, a power supply line 3 shown in FIG. 3, which will be described later. The wiring 110d is provided above the region 104d. One end of a via 161d is connected to the wiring 110d. The other end of the via 161d is connected to the second wiring layer 160.

[0042] The vias 111s and 111d are provided to penetrate the insulating film 108 and the insulating layer 105. The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0043] The wiring 110s is connected to the region 104s through the via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to, for example, the power supply line 3 of the circuit in FIG. 3 through the via 111s and the wiring 110s.

[0044] The wiring 110d is connected to the region 104d through the via 111d. The region 104d is the drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the second wiring layer 160 through the via 111d, the wiring 110d, and the via 161d.

[0045] The first interlayer insulating film 112 is provided to cover the insulating film 108 and the first wiring layer 110. As will be described in the manufacturing method later, the first interlayer insulating film 112 provides a planarized surface 112F for forming a graphene layer and growing a semiconductor layer on the graphene layer. The first interlayer insulating film 112 is formed of a light-transmitting organic material, such as a transparent resin. The transparent resin can be, for example, a silicon-based resin such as SOG (Spin On Glass) or a novolac-type phenolic resin.

[0046] A graphene sheet 140a is provided on the planarized surface 112F for each light emitting element 150. The light emitting surface 151S is in contact with the graphene sheet 140a. The light emitting element 150 is provided on the planarized surface 112F via the graphene sheet 140a. The outer periphery of the graphene sheet 140a in the XY plane view approximately matches the outer periphery of the light emitting element 150 in the XY plane view. The thickness of the graphene sheet 140a is sufficiently thin, so that the graphene sheet 140a can transmit light.

[0047] The graphene sheet 140a is formed by etching the graphene layer 1140, as described below in connection with Figures 6B and subsequent figures. The graphene layer 1140 is used as a seed for forming the light-emitting element 150.

[0048] The light emitting element 150 includes a top surface 153U provided on the opposite side of the light emitting surface 151S. In this example, the outer peripheral shapes of the light emitting surface 151S and the top surface 153U in the XY plane are square or rectangular, and the light emitting element 150 is, for example, a prismatic element provided on the planarized surface 112F via the graphene sheet 140a. The cross section of the prismatic element may be a polygon with five or more sides. The light emitting element 150 is not limited to a prismatic element, and may also be a cylindrical element.

[0049] The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from the light-emitting surface 151S toward the top surface 153U. The light-emitting surface 151S is provided by the n-type semiconductor layer 151. The light-emitting element 150 emits light in the negative direction of the Z axis through the graphene sheet 140a, the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower film 106, the substrate 102, and the color filter 180.

[0050] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided on the planarized surface 112F together with the graphene sheet 140a so as to protrude in one direction from the n-type semiconductor layer 151. The height of the connection portion 151a from the light emitting surface 151S is the same as or smaller than the height of the n-type semiconductor layer 151 from the light emitting surface 151S. The connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0051] When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane is, for example, approximately square or rectangular. When the shape of the light emitting element 150 in the XY plane is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane is cylindrical, the shape of the light emitting element 150 in the XY plane is not limited to a circle and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element in the planar view, the degree of freedom in the wiring layout, etc. is improved.

[0052] The light emitting element 150 may include, for example, In X Al Y Ga 1-X-Y A gallium nitride compound semiconductor including a light emitting layer such as N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, approximately 467 nm±30 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of approximately 410 nm±30 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned values ​​and can be any appropriate wavelength.

[0053] The second interlayer insulating film 156 covers the planarized surface 112F, the graphene sheet 140a, and the light emitting element 150. The second interlayer insulating film 156 separates adjacently arranged light emitting elements 150. By covering the light emitting elements 150, the second interlayer insulating film 156 protects the light emitting elements 150 from the surrounding environment. The surface of the second interlayer insulating film 156 only needs to be flat enough to allow the second wiring layer 160 to be formed on the second interlayer insulating film 156.

[0054] The second interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used for the second interlayer insulating film 156 is preferably a resin having light reflectivity, such as a white resin. By using a white resin for the second interlayer insulating film 156, light emitted laterally from the light emitting element 150 can be reflected and guided toward the light emitting surface 151S, thereby substantially improving the light emitting efficiency of the light emitting element 150.

[0055] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG or a novolac-type phenolic resin. The scattering particles are colorless or white and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. Suitable scattering particles have a diameter of about 1 / 2 the wavelength of the light. Examples of such scattering particles include TiO2, Al2O3, and ZnO.

[0056] In addition to the above, the white resin can also be formed by utilizing a large number of minute pores dispersed in the transparent resin. When the second interlayer insulating film 156 is whitened, a SiO2 film formed by ALD (Atomic-Layer-Deposition) or CVD may be used on top of the SOG film or the like.

[0057] The second interlayer insulating film 156 may be a black resin. By using a black resin for the second interlayer insulating film 156, scattering of light within the subpixels 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display clearer images.

[0058] The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 can include multiple wirings that can have different potentials. The second wiring layer 160 includes wirings 160d and 160k. The wirings 160d and 160k are formed separately and can be connected to different potentials.

[0059] A connecting member 161a is provided between the top surface 153U and a wiring 160d provided above the top surface 153U, and the top surface 153U is connected to the wiring 160d by the connecting member 161a. The wiring 160d is also provided above the wiring 110d. The wiring 160k is provided above the connecting portion 151a. The wiring 160k is connected to the ground line 4 of the circuit in FIG. 3, for example.

[0060] The via 161d is provided to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring (first wiring) 160d and the wiring 110d, and electrically connects the wiring 160d and the wiring 110d. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection member 161a, the wiring 160d, the via 161d, the wiring 110d, the wiring 160d, the wiring 160d, and the via 111d.

[0061] The via (second via) 161k is provided to penetrate the second interlayer insulating film 156 and reach the connection portion 151a. The via 161k is provided between the wiring (second wiring) 160k and the connection portion 151a, and connects the wiring 160k to the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 via the connection portion 151a, the via 161k, and the wiring 160k.

[0062] The first wiring layer 110, the connection member 161a, and the vias 111s, 111d, 161d, and 161k are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0063] A protective layer may be further provided over the second interlayer insulating film 156 and the second wiring layer 160 to provide protection from the external environment.

[0064] (Variation 1) FIG. 2 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of this embodiment. 2, in subpixel 20a of the image display device of this modified example, a portion of color filter 180 is provided so as to penetrate graphene sheet 140a1, first interlayer insulating film 112, insulating film 108, insulating layer 105, TFT lower film 106, and substrate 102. In this example, a portion of color filter 180 is color conversion layer 183. Light-emitting surface 151S is provided over graphene sheet 140a1 and color conversion layer 183. Therefore, light emitted by light-emitting element 150 is directly incident on color conversion layer 183 via light-emitting surface 151S, passes through filter layer 184, and is emitted to the outside.

[0065] Each element of the circuit 101 including the transistor 103 is provided on a light-shielding portion 181 of a color filter 180 via a substrate 102 .

[0066] Color conversion layer 183 fills the opening that penetrates graphene sheet 140a1, first interlayer insulating film 112, insulating film 108, insulating layer 105, TFT lower film 106, and substrate 102 to reach light-emitting surface 151S, and is provided to cover wall surface 158W of the opening and light-emitting surface 151S. In this modification, light emitted from light-emitting element 150 is directly incident on color filter 180, so that attenuation of intensity before reaching color filter 180 can be suppressed.

[0067] In this modified example, the color filter 180 is provided over the surface 102b of the substrate 102, the wall surface 158W, and the light-emitting surface 151S. However, as in the third embodiment described later, elements of the circuit 101, such as the transistor 103, may be provided on the color filter 180 without the substrate 102 in between.

[0068] First interlayer insulating film 112 and insulating film 108 may be formed of a light-reflective material such as white resin, similar to second interlayer insulating film 156. This prevents light traveling through color conversion layer 183 from leaking into first interlayer insulating film 112 or insulating film 108, thereby suppressing attenuation of intensity.

[0069] The thickness of graphene sheet 140a1 can be made thin enough to have high light transmittance, so color conversion layer 183 may be provided so as not to penetrate the graphene sheet.

[0070] FIG. 3 is a schematic block diagram illustrating an image display device according to this embodiment. As shown in Fig. 3, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged, for example, in a lattice pattern. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.

[0071] A pixel 10 includes multiple subpixels 20 that emit light of different colors. Subpixel 20R emits red light. Subpixel 20G emits green light. Subpixel 20B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 20R, 20G, and 20B emitting light at desired brightness.

[0072] One pixel 10 includes three subpixels 20R, 20G, and 20B, which are arranged linearly on the X axis, as shown in Fig. 3. In each pixel 10, subpixels of the same color may be arranged in the same column, or, as in this example, subpixels of different colors may be arranged in different columns.

[0073] The image display device 1 further includes power lines 3 and ground lines 4. The power lines 3 and ground lines 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power lines 3 and ground lines 4 are electrically connected to each subpixel 20, and supply power to each subpixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and the GND terminal 4a are provided at the ends of the power lines 3 and the ground lines 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power terminal 3a with respect to the GND terminal 4a.

[0074] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction of the sub-pixels 20.

[0075] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 in each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0076] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0077] The subpixel 20 includes a light-emitting element 22, a select transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3 and Figure 4 described below, the select transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0078] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness that corresponds to the current flowing through the light-emitting element 22.

[0079] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a power line 3.

[0080] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current that has passed through it.

[0081] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. In other words, the row selection circuit 5 scans the rows in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned subpixels 20, causing them to emit light. The brightness of the subpixels 20 is determined by the current flowing through the light-emitting elements 22. The subpixels 20 emit light at a gradation based on the determined brightness, and an image is displayed in the display area 2.

[0082] FIG. 4 is a schematic plan view illustrating a part of the image display device of this embodiment. In Fig. 4, line AA' represents a cutting line in the cross-sectional view of Fig. 1 etc. In this embodiment, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction with a first interlayer insulating film 112 and a second interlayer insulating film 156 interposed therebetween. The light-emitting element 150 corresponds to the light-emitting element 22 in Fig. 3. The driving transistor 103 corresponds to the driving transistor 26 in Fig. 3 and is also denoted as T2.

[0083] As shown in Fig. 4, the anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in Fig. 1. A connection member 161a is provided on an upper surface 153U of the p-type semiconductor layer 153. The p-type semiconductor layer 153 is connected to a wiring 160d via the connection member 161a. The wiring 160d is connected to a via 161d by a contact hole 161d1, and the wiring 160d is connected to a wiring 110d provided in a lower layer via the via 161d.

[0084] The wiring 110d is connected to the drain electrode of the transistor 103 through the via 111d shown in FIG. 1. The drain electrode of the transistor 103 is part of the TFT channel 104, which is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through the via 111s shown in FIG. 1. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the first wiring layer 110 includes the power line 3, and the wiring 110s is connected to the power line 3.

[0085] The cathode electrode of the light-emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided in a layer above the transistor 103 and the first wiring layer 110. The connection portion 151a is electrically connected to the wiring 160k through a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 160k through a contact hole 161k1. The wiring 160k is connected to the ground line 4.

[0086] In this way, the light emitting element 150 can electrically connect the first wiring layer 110 provided below the light emitting element 150 to the second wiring layer 160 by using the via 161d. The light emitting element 150 can electrically connect the connection portion 151a provided below the second wiring layer 160 to the second wiring layer 160 by using the via 161k.

[0087] A method for manufacturing the image display device of this embodiment will be described. 5A to 8 are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. As shown in FIG. 5A, in the manufacturing method of the image display device of this embodiment, a substrate 102 is prepared. The substrate 102 is a light-transmitting substrate, for example, a substantially rectangular glass substrate measuring approximately 1500 mm × 1800 mm. A TFT lower layer film 106 is formed on one surface (first surface) 102a. The TFT lower layer film 106 is formed, for example, by a CVD method. A Si layer 1104 is formed on the formed TFT lower layer film 106. The Si layer 1104 is an amorphous Si layer when formed, and after formation, the Si layer 1104 is polycrystallized by, for example, scanning with an excimer laser pulse multiple times to form the Si layer 1104.

[0088] 5B, the transistor 103 is formed at a predetermined position on the TFT lower layer film 106. For example, in the LTPS process, the transistor 103 is formed as follows.

[0089] The polycrystallized Si layer 1104 shown in FIG. 5A is processed into an island shape like the transistor 103 shown in FIG. 4, and the TFT channel 104 is formed. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104 with the insulating layer 105 interposed therebetween. The transistor 103 is formed by selectively doping the gate 107 with impurities such as B and thermally activating it. Regions 104s and 104d are p-type active regions and function as the source and drain regions of the transistor 103, respectively. Region 104i is an n-type active region and functions as the channel.

[0090] 6A, the insulating film 108 is formed to cover the insulating layer 105 and the gate 107. An appropriate manufacturing method is applied to form the insulating film 108 depending on the material of the insulating film 108. For example, when the insulating film 108 is made of SiO2, a technique such as ALD or CVD is used.

[0091] The flatness of the insulating film 108 may be such that the first wiring layer 110 can be formed thereon, and a flattening step does not necessarily have to be performed. If the flattening step is not performed on the insulating film 108, the number of steps for the flattening step can be reduced.

[0092] Vias 111s and 111d are formed to penetrate the insulating film 108 and the insulating layer 105. The via 111s is formed to reach the region 104s. The via 111d is formed to reach the region 104d. For example, RIE or the like is used to form via holes to form the vias 111s and 111d.

[0093] A first wiring layer 110 including wirings 110s and 110d is formed on the insulating film 108. The wiring 110s is connected to one end of the via 111s. The wiring 110d is connected to one end of the via 111d. The first wiring layer 110 may be formed simultaneously with the formation of the vias 111s and 111d.

[0094] A first interlayer insulating film (first insulating film) 112 is formed to cover the insulating film 108 and the first wiring layer 110. The surface of the first interlayer insulating film 112 is planarized by chemical mechanical polishing (CMP) or the like, and a planarized surface 112F is formed.

[0095] In this way, the drive circuit board (first board) 100 is formed. The manufacturing process of the drive circuit board 100 may be performed in a plant separate from the process of forming the semiconductor layer and subsequent processes described later, or may be performed in the same plant.

[0096] As shown in FIG. 6B , the graphene layer 1140 is formed on the planarized surface 112F. The graphene layer 1140 is a layer containing graphene, and is preferably formed by stacking several to approximately ten monolayers of graphene. The graphene layer 1140, cut to an appropriate size and shape, is placed at a predetermined position on the planarized surface 112F and is adsorbed to the planarized surface 112F due to the flatness of the planarized surface 112F. The graphene layer 1140 may be adhered to the planarized surface 112F, for example, by an adhesive or the like.

[0097] The periphery of the cut graphene layer 1140 in the XY plane view is determined according to the periphery of the semiconductor layer 1150 in the XY plane view shown in Fig. 7A described below. The periphery of the graphene layer 1140 in the XY plane view and the periphery of the semiconductor layer 1150 in the XY plane view are set so as to sufficiently include the periphery of the light-emitting element 150 in the XY plane view shown in Fig. 7B described below. In other words, the periphery of the light-emitting element 150 is disposed within the periphery of the graphene layer 1140 and the periphery of the semiconductor layer 1150 in the XY plane view.

[0098] 7A, the semiconductor layer 1150 is formed over the graphene layer 1140. The semiconductor layer 1150 is formed by sequentially forming an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153 from the graphene layer 1140 side toward the positive direction of the Z axis. The semiconductor layer 1150 includes, for example, GaN, and more specifically, In X Al Y Ga 1-X-Y N (0≦X, 0≦Y, X+Y<1), etc. Crystal defects due to mismatch of crystal lattices are likely to occur in the early stages of growth of the semiconductor layer 1150, and crystals containing GaN as the main component generally exhibit n-type semiconductor characteristics. Therefore, by growing the n-type semiconductor layer 1151 on the graphene layer 1140, it is possible to improve the yield.

[0099] The semiconductor layer 1150 can be formed by physical vapor deposition methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering, with low-temperature sputtering being preferred. Low-temperature sputtering is preferably performed using light or plasma assistance during film formation, since this allows for lower temperatures. Epitaxial growth by MOCVD can sometimes exceed 1000°C. In contrast, it is known that low-temperature sputtering can epitaxially grow GaN crystals, including a light-emitting layer, on the graphene layer 1140 at low temperatures of approximately 400°C to 700°C (see Non-Patent Documents 1 and 2, etc.). The drive circuit substrate 100 is formed on, for example, a glass substrate 102, and low-temperature sputtering is suitable for forming the semiconductor layer 1150 on the drive circuit substrate 100.

[0100] By growing a GaN semiconductor layer 1150 on the graphene layer 1140 using an appropriate deposition technique, a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 is formed on the graphene layer 1140. The semiconductor layer 1150 is formed within the region indicated by the two-dot chain line in FIG. 7A.

[0101] During the growth process of the semiconductor layer 1150, amorphous deposits 1162 containing Ga and other growth seed materials may be deposited on the planarized surface 112F where the graphene layer 1140 is not present. In this example, the deposits 1162 are stacked in the order of deposits 1162a, 1162b, and 1162c from the planarized surface 112F toward the positive direction of the Z axis. The deposit 1162a is deposited when the n-type semiconductor layer 1151 is formed, the deposit 1162b is deposited when the light-emitting layer 1152 is formed, and the deposit 1162c is deposited when the p-type semiconductor layer 1153 is formed, but this is not limitative.

[0102] The semiconductor layer 1150 may not only be formed directly on the graphene layer 1140, but also be formed on a buffer layer formed on the graphene layer 1140. Providing a buffer layer may promote GaN crystal growth. The buffer layer can be formed thin enough not to impair light transparency, and may be made of any material that promotes GaN crystal growth, such as an insulating material or a metal material.

[0103] As shown in FIG. 7B, the semiconductor layer 1150 shown in FIG. 7A is processed by etching to form the light emitting element 150.

[0104] In the process of forming the light emitting element 150, the connection portion 151a is formed, and then other portions are formed by further etching. This makes it possible to form the light emitting element 150 having the connection portion 151a that protrudes from the n-type semiconductor layer 151 on the planarized surface 112F in the positive direction of the X axis. To form the light emitting element 150, for example, a dry etching process is used, and preferably anisotropic plasma etching (reactive ion etching, RIE) is used.

[0105] 7A is over-etched and formed into a graphene sheet 140a when the light emitting device 150 is formed. Therefore, the outer periphery of the graphene sheet 140a in the XY plane view substantially coincides with the outer periphery of the light emitting device 150 in the XY plane view.

[0106] The second interlayer insulating film (second insulating film) 156 is formed to cover the planarized surface 112F, the graphene sheet 140a, and the light emitting element 150.

[0107] 8, the via 161d (first via) is formed by filling a via hole that penetrates the second interlayer insulating film 156 and the first interlayer insulating film 112 and reaches the wiring 110d with a conductive material. The via (second via) 161k is formed by filling a via hole that penetrates the second interlayer insulating film 156 and reaches the connecting portion 151a with a conductive material. The connecting member 161a is formed by filling a contact hole that is formed so as to reach the top surface 153U with a conductive material. The via hole and the contact hole are formed by, for example, RIE or the like.

[0108] A second wiring layer 160 including wirings 160d and 160k is formed on the second interlayer insulating film 156. The wiring 160d is connected to the connection member 161a and one end of the via 161d. The wiring 160k is connected to one end of the via 161k. The second wiring layer 160 may be formed simultaneously with the formation of the vias 161k and 161d and the connection member 161a. In this way, the wiring 160d and the wiring 110d are electrically connected by the via 161d, and the wiring 160k and the connection portion 151a are electrically connected by the via 161k.

[0109] The color filter forming process will be described. 9A to 9D are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. 9A to 9D show a method for forming a color filter by an inkjet method.

[0110] 9A, a structural body 1192 is prepared. In addition to the drive circuit board 100 and the light emitting element 150, the structural body 1192 includes the second interlayer insulating film 156, the second wiring layer 160, the vias 161d and 161k, and the connection member 161a shown in FIG.

[0111] 9B, a light-shielding portion 181 is formed in a region on surface 102b that does not include the outer periphery of light-emitting surface 151S in the XY plane view. Light-shielding portion 181 is formed using, for example, screen printing or photolithography technology.

[0112] 9C, phosphors corresponding to the emitted light color are ejected from an inkjet nozzle to form color conversion layer 183. The phosphors that form color conversion layer 183 are ejected onto surface 102b. The phosphors also color the areas between light-shielding portions 181 on surface 102b.

[0113] The phosphor may be, for example, a fluorescent paint using a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. When a perovskite phosphor material or a quantum dot phosphor material is used, it is possible to realize each emitted color, and it is preferable because it has high monochromaticity and high color reproducibility.

[0114] After the image is formed by jetting from the inkjet nozzle, a drying process is carried out at an appropriate temperature for an appropriate time.

[0115] As already explained, if no color conversion unit is formed for a blue-emitting subpixel, no color conversion layer 183 is formed. Furthermore, when forming a blue color conversion layer for a blue-emitting subpixel, if one layer of color conversion unit is sufficient, the ejection amount of the blue phosphor is preferably set so as to fill the entire area formed by the light-shielding unit 181.

[0116] 9D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The amount of paint sprayed is set so as to fill the entire area formed by the light-shielding portion 181.

[0117] After the color filter 180 is formed, the structural body 1192 is diced together with the color filter 180 to form an image display device. Note that the step of forming the color filter 180 may be performed after the structural body 1192 is diced.

[0118] FIG. 10 is a schematic cross-sectional view illustrating a part of a modified example of the manufacturing method of the image display device of this embodiment. FIG. 10 shows a method for forming a film-type color filter 180a. 10, the diagram above the arrow shows the structure 1192. The diagram below the arrow shows the glass substrate 186, the color filter 180a bonded to the glass substrate 186, and the transparent thin-film adhesive layer 189 that bonds the color filter 180a to the structure 1192. The arrow represents the state in which the color filter 180a, together with the glass substrate 186 and the transparent thin-film adhesive layer 189, is attached to the structure 1192. 10, to avoid complexity, the reference numerals and the components themselves including the reference numerals are omitted for some of the components of the structure 1192. The components in the structure 1192 that are not shown in FIG. 10 are shown in FIG. 8. The components shown in FIG. 8 are the components of the circuit 101 in the drive circuit board 100, the vias 161d and 161k, and the second wiring layer 160.

[0119] As shown in FIG. 10, color filter 180a includes light-shielding portion 181a, color conversion layers 183R, 183G, and 183B, and filter layer 184a. Light-shielding portion 181a has the same function as light-shielding portion 181 in the inkjet system. Color conversion layers 183R, 183G, and 183B have the same function as color conversion layer 183 in the inkjet system and are formed of the same materials. Color conversion layer 183R is a conversion layer that outputs red light. Color conversion layer 183G is a conversion layer that outputs green light. Color conversion layer 183B is a conversion layer that outputs blue light. Filter layer 184a also has the same function as filter layer 184 in the inkjet system and is formed of the same material.

[0120] One surface of color filter 180a is bonded to structural body 1192. The other surface of color filter 180a is bonded to glass substrate 186. A transparent thin film adhesive layer 189 is provided on one surface of color filter 180a, and color filter 180a is bonded to surface 102b of structural body 1192 via transparent thin film adhesive layer 189.

[0121] In the subpixels using the film-type color filters 180a, a transparent thin film adhesive layer 189 is formed between the substrate 102 and the color filters 180a by the procedure described above.

[0122] In the case of the image display device of the modified example shown in FIG. 2, the color filters are formed as follows. 11A to 11C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this modified example. In a modified example, before the step of forming the color filter is performed, the step described with reference to Fig. 11 is performed after the step described with reference to Fig. 8. As shown in Fig. 11, an opening 158 is formed. The opening 158 is formed so as to expose the light-emitting surface 151S from the surface 102b of the substrate 102. More specifically, the opening 158 is formed by sequentially removing parts of the substrate 102, the TFT lower layer film 106, the insulating layer 105, the insulating film 108, the first interlayer insulating film 112, and the graphene sheet 140a shown in Fig. 8. The opening 158 is formed by wet etching or the like using a solvent appropriate for the material.

[0123] 9A to 9D, a color filter is formed by inkjet printing. In the process of forming color conversion layer 183, the phosphor is ejected so as to fill opening 158, and the phosphor is formed so as to cover wall surface 158W of opening 158 and light-emitting surface 151S. The phosphor is also ejected between light-shielding portions 181. Filter layer 184 is formed so as to fill between light-shielding portions 181.

[0124] When forming a film-type color filter, the opening 158 shown in Fig. 11 is filled with, for example, a transparent resin. Thereafter, the color filter can be formed by attaching the color filter to the surface 102b of the substrate 102 and the exposed surface of the transparent resin filled in the opening 158 via the transparent thin film adhesive layer 189 shown in Fig. 10.

[0125] Whether the color filter 180 is formed by an inkjet method or the film-type color filter 180a, it is desirable that the color conversion layer 183 be as thick as possible to improve color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light will approximate Lambertian, while the emission angle of the unconverted blue light will be limited by the light-shielding portion 181. This will cause the problem of viewing-angle dependency in the display color of the displayed image. In order to match the light distribution of the unconverted blue light with the light distribution of the subpixels provided with the color conversion layer 183, it is desirable that the thickness of the color conversion layer 183 be approximately half the opening size of the light-shielding portion 181.

[0126] For example, in the case of a high-resolution image display device with a resolution of about 250 ppi (pitch per inch), the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, if the color conversion material is made of spherical phosphor particles, it is preferable that they be stacked in a close-packed structure to suppress light leakage from the light emitting element 150. To achieve this, at least three particle layers are required. Therefore, the particle size of the phosphor material that makes up the color conversion layer 183 is preferably about 5 μm or less, and more preferably about 3 μm or less.

[0127] FIG. 12 is a schematic perspective view illustrating the image display device according to this embodiment. 12, the image display device of this embodiment includes a drive circuit substrate 100 on which a circuit 101 including transistors is formed on a color filter 180, and a light-emitting circuit section 172 having a large number of light-emitting elements 150 is provided on a planarized surface 112F of the drive circuit substrate 100. In addition to the light-emitting elements 150, the light-emitting circuit section 172 includes the graphene sheet 140a, the second interlayer insulating film 156, and the second wiring layer 160 shown in FIG. 1. The drive circuit substrate 100 and the light-emitting circuit section 172 are electrically connected via vias 161d and 161k shown in FIG. 1.

[0128] (Variation 2) FIG. 13 is a schematic perspective view illustrating an image display device according to a modified example of this embodiment. In the embodiment shown in FIG. 1 and the modified example shown in FIG. 2, an image display device can be formed without providing color filters 180, 180a, and an image display device that emits monochromatic light can be formed as in this example. As shown in FIG. 13, in the image display device of this modified example, a light-emitting circuit section 172 having a large number of light-emitting elements 150 is provided on a flattened surface 112F of a drive circuit board 100. This modification can also be applied to other embodiments and their modifications described below.

[0129] The effects of the image display device of this embodiment will be described. In the manufacturing method of the image display device of this embodiment, the light emitting element 150 is formed by etching the semiconductor layer 1150 that has been crystal-grown on the planarized surface 112F of the drive circuit substrate 100. Thereafter, the light emitting element 150 is covered with a second interlayer insulating film 156, and is electrically connected to the circuit 101 built in the drive circuit substrate 100. Therefore, the manufacturing process is significantly shortened compared to the case where individual light emitting elements are transferred to the substrate 102.

[0130] In the manufacturing method of the image display device 1 of this embodiment, the graphene layer 1140 formed on the planarized surface 112F can be used as a seed for crystal growth of the semiconductor layer 1150. Since the graphene layer 1140 can be easily formed on the planarized surface 112F, sufficiently high productivity can be achieved.

[0131] For example, an image display device with 4K resolution has more than 24 million subpixels, and an image display device with 8K resolution has more than 99 million subpixels. Individually forming such a large number of light-emitting elements and mounting them on a circuit board requires an enormous amount of time. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, mounting a large number of light-emitting elements individually reduces yield due to poor connections during mounting, and further increases in costs are unavoidable. However, the manufacturing method for the image display device of this embodiment provides the following advantages.

[0132] In the manufacturing method for the image display device of this embodiment, the light emitting element 150 is formed after the entire semiconductor layer 1150 is formed on the graphene layer 1140 formed on the planarized surface 112F, which makes it possible to eliminate the transfer step of the light emitting element 150. Therefore, in the manufacturing method for the image display device 1 of this embodiment, the time required for the transfer step can be shortened and the number of steps can be reduced compared to conventional manufacturing methods.

[0133] Since the semiconductor layer 1150 having a uniform crystal structure is grown on the graphene layer 1140, the light emitting element 150 can be arranged in a self-aligned manner by appropriately cutting the graphene layer 1140 and attaching it to the planarized surface 112F. Therefore, there is no need to align the light emitting element on the drive circuit board 100, and the light emitting element 150 can be easily miniaturized, which is suitable for a high-definition display.

[0134] In this embodiment, after forming the light emitting element directly by etching or the like on the drive circuit board 100 already incorporating the circuit 101, the light emitting element 150 and the circuit 101 below the light emitting element 150 are electrically connected by forming a via or the like. Therefore, a uniform connection structure can be realized, and a decrease in yield can be suppressed.

[0135] The drive circuit board 100 can include a drive circuit including a TFT, a scanning circuit, etc. By using an LTPS process or the like, the circuit 101 that constitutes the drive circuit board 100 can be fabricated on a light-transmitting substrate such as a glass substrate, which has the advantage of allowing the use of existing flat panel display manufacturing processes and plants.

[0136] In the image display device of this embodiment, light emitting elements 150 are stacked on drive circuit board 100, and the optical path from light emitting surface 151S to the outside may be long. The optical path of light emitted from light emitting element 150 has a distance from light emitting surface 151S to surface 102b. This distance may range from approximately 1 μm to several μm. In other words, light output from light emitting surface 151S travels an optical path of approximately 1 μm to several μm before being emitted to the outside. Therefore, the light output from light emitting surface 151S is attenuated according to the length of the optical path compared to when the light is directly emitted to the outside. In the modified example shown in FIG. 2, color conversion layer 183 is filled in the optical path, and the intensity of the light emitted to the outside is attenuated according to the light absorption rate of the phosphor that constitutes color conversion layer 183.

[0137] The light emitting element 150 is covered with a second interlayer insulating film 156 except for the light emitting surface 151S. By forming the second interlayer insulating film 156 from a highly light reflective material such as a white resin, scattered light and the like toward the sides of the light emitting element 150 can be reflected and prevented from leaking out to the sides of the light emitting element 150.

[0138] As described above, in the image display device of this embodiment, light emitting element 150 is covered with second interlayer insulating film 156, and light traveling in a direction other than light emitting surface 151S can be confined within light emitting element 150. The light confined within light emitting element 150 is reflected at the interface between light emitting element 150 and second interlayer insulating film 156, and a portion of the light is guided toward light emitting surface 151S. Therefore, light emitting element 150 has an improved substantial light emission efficiency, and can radiate light of sufficient intensity to the outside even if the light intensity is attenuated due to the long optical path from light emitting surface 151S to the outside and the light absorption rate of the phosphor.

[0139] In the modified example shown in FIG. 2, if the first interlayer insulating film 112 and the insulating film 108 are formed from a light-reflective material such as white resin, it becomes possible to further prevent light leakage, and the attenuation of the intensity of the emitted light can be more effectively suppressed.

[0140] (Second embodiment) FIG. 14 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. In this embodiment, the configurations of the light-emitting element 250 and the transistor 203 differ from those of the other embodiments described above. Specifically, the light-emitting surface 253S is provided by the p-type semiconductor layer 253, and the transistor 203 is an n-channel. Another difference from the other embodiments described above is that the p-type semiconductor layer 253 and the via 261a are connected by the third wiring layer 230. The same components as those in the other embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0141] 14, the image display device of this embodiment includes a subpixel 220. The subpixel 220 includes a substrate 102, a third wiring layer 230, a graphene sheet 140a, a transistor 203, a first wiring layer 110, a first interlayer insulating film 112, a light-emitting element 250, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. The subpixel 220 further includes a color filter 180.

[0142] In this embodiment, as in the other embodiments described above, the circuit 101 including the transistor 203 is provided on one surface 102a of the substrate 102. The color filter 180 is provided on the other surface 102b of the substrate 102. The configuration of the color filter 180 is the same as in the other embodiments described above, and detailed description thereof will be omitted.

[0143] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the insulating film 108, the vias 111s and 111d, and the first wiring layer 110.

[0144] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with impurities such as phosphorus (P) and activated to form n-type semiconductor regions. The region 204s is in ohmic contact with the via 111s. The region 204d is in ohmic contact with the via 111d.

[0145] The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0146] In transistor 203, when a voltage higher than that of region 204s is applied to gate 107, a channel is formed in region 204i. The current flowing between regions 204s and 204d is controlled by the voltage applied to region 204s by gate 107. The TFT channel 204 and gate 107 are formed using the same materials and methods as the TFT channel 104 and gate 107 in the other embodiments described above.

[0147] The first wiring layer 110 includes wirings 110s and 110d. The wiring 110s is connected to a ground line 4 shown in FIG.

[0148] The vias 111s and 111d are provided so as to penetrate the insulating film 108. The via 111s is provided between the wiring 110s and the region 204s. The via 111s electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d. The via 111d electrically connects the wiring 110d and the region 204d. The vias 111s and 111d are formed using the same materials and manufacturing methods as in the other embodiments described above.

[0149] The third wiring layer 230 is provided on the planarized surface 112F. The third wiring layer 230 includes a plurality of wirings 230a that can have different potentials. The plurality of wirings 230a is provided for each light-emitting element 250. The light-emitting element 250 is provided on the wirings 230a via a graphene sheet 140a. The graphene sheet 140a is sufficiently thin, and therefore has sufficiently small electrical resistance in the thickness direction. Therefore, the light-emitting surface 253S is electrically connected to the wirings 230a via the graphene sheet 140a.

[0150] The third wiring layer 230 including the wiring 230a is formed of a light-transmitting conductive film, such as an ITO film or a ZnO film. The graphene sheet 140a is also formed thin enough to have sufficient light-transmitting properties, and light emitted from the light-emitting element 250 passes through the graphene sheet 140a and the wiring 230a.

[0151] The periphery of the wiring 230a is set to include the periphery of the light-emitting element 250 when the light-emitting element 250 is projected onto the wiring 230a in the XY plane. In other words, the periphery of the light-emitting element 250 is disposed within the periphery of the wiring 230a in the XY plane. This ensures a sufficient contact area between the wiring 230a and the light-emitting surface 253S, and can suppress an increase in contact resistance between the wiring 230a and the light-emitting surface 253S. The wiring 230a is provided so as to protrude in one direction above the planarized surface 112F. One end of the via 261a is connected to the wiring 230a, and the light-emitting element 250 is electrically connected to the via 261a via the graphene sheet 140a and the wiring 230a.

[0152] The light emitting element 250 includes a top surface 251U provided on the opposite side of the light emitting surface 253S. The light emitting element 250 is a prismatic or cylindrical element, as in the other embodiments described above.

[0153] The light-emitting element 250 includes a p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked in this order from the light-emitting surface 253S toward the top surface 251U. In this embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253, and the top surface 251U is provided by the n-type semiconductor layer 251.

[0154] The light emitting element 250 has the same shape in the XY plane as the light emitting element 150 of the other embodiments described above. An appropriate shape of the light emitting element 250 is selected depending on the layout of other circuit elements, etc.

[0155] The light emitting element 250 is a so-called light emitting diode, similar to the light emitting element 150 of the other embodiments described above.

[0156] The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 includes wirings 160d and 260a. As in the other embodiments described above, a portion of the wiring 160d is provided above the light-emitting element 250, and another portion is provided above the wiring 110d. A portion of the wiring 260a is provided above the wiring 230a. The wiring 260a is connected to, for example, a power supply line 3 of the circuit in FIG. 15, which will be described later.

[0157] The via 161d is provided in the same manner as in the other embodiments described above. That is, the via 161d is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring 160d and the wiring 110d and electrically connects the wiring 160d and the wiring 110d. A connecting member 161a is provided between the wiring 160d and the top surface 251U, and the wiring 160d is electrically connected to the top surface 251U by the connecting member 161a. Therefore, the n-type semiconductor layer 251 is electrically connected to the drain region of the transistor 203 via the connecting member 161a, the wiring 160d, the via 161d, the wiring 110d, and the via 111d.

[0158] The via (second via) 261a is provided to penetrate the second interlayer insulating film 156 and reach the wiring 230a. The via 261a is provided between the wiring (second wiring) 260a and the wiring 230a, and electrically connects the wiring 260a to the wiring 230a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power supply line 3 of the circuit in FIG. 15 via the wiring 230a, the via 261a, and the wiring 260a.

[0159] FIG. 15 is a schematic block diagram illustrating an image display device according to this embodiment. 15, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, subpixels 220 are arranged in a lattice pattern on the XY plane.

[0160] As in the other embodiments described above, pixel 10 includes multiple subpixels 220 that emit light of different colors. Subpixel 220R emits red light. Subpixel 220G emits green light. Subpixel 220B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 220R, 220G, and 220B emitting light at desired brightnesses.

[0161] One pixel 10 includes three subpixels 220R, 220G, and 220B, which are arranged linearly on the X axis, as in this example. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, may have subpixels of different colors arranged in different columns.

[0162] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 15, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0163] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the ground line 4 side. In other words, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0164] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0165] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

[0166] In this embodiment, the polarity of the drive transistor 226 is n-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of subpixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each subpixel 220 in the selected row. The drive transistor 226 of the subpixel 220 in the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the current that has passed through it.

[0167] The manufacturing method of this embodiment will be described. 16A to 18 are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. This embodiment uses the substrate 102 described in relation to Fig. 5A of the other embodiment described above. In Fig. 5A, a Si layer 1104 is formed on the substrate 102 via a TFT underlayer film 106. In the following description, it is assumed that the steps in Fig. 16A and subsequent steps are applied after the step in Fig. 5A.

[0168] As shown in FIG. 16A, the polycrystallized Si layer 1104 shown in FIG. 5A is processed into an island shape to form a TFT channel 204. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 204. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. A transistor (circuit element) 203 is formed by selectively doping the gate 107 with impurities such as P and thermally activating it. Regions 204s and 204d are n-type active regions and function as the source region and drain region of the transistor 203, respectively. Region 204i is a p-type active region and functions as a channel. In this manner, an n-channel TFT is formed.

[0169] As shown in FIG. 16B, an insulating film 108 is formed to cover the insulating layer 105 and the transistor 203. Vias 111s and 111d are formed to penetrate the insulating film 108 and the insulating layer 105. A first wiring layer 110 including wirings 110s and 110d is formed on the insulating film 108. The wiring 110s is connected to the via 111s, and the wiring 110d is connected to the via 111d. A first interlayer insulating film 112 is formed to cover the insulating film 108 and the first wiring layer 110. In this manner, a drive circuit substrate (first substrate) 100 including a p-channel TFT is formed.

[0170] The light-transmitting conductive film 1130 is formed on the planarized surface 112 F. The graphene layer 1140 is formed at a predetermined position on the formed light-transmitting conductive film 1130.

[0171] 17A, a semiconductor layer 1150 is formed over the graphene layer 1140. In the semiconductor layer 1150, a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151 are formed in this order from the graphene layer 1140 toward the positive direction of the Z axis.

[0172] The semiconductor layer 1150 is formed over the graphene layer 1140 as indicated by the dashed-dotted line in FIG. 17A . As in the other embodiments described above, amorphous deposits 1162 containing Ga, a growth seed material, may be deposited on the transparent conductive film 1130 where the graphene layer 1140 is not present. In this example, the deposits 1162 are stacked in the order of deposits 1162d, 1162e, and 1162f from the transparent conductive film 1130 toward the positive direction of the Z axis. The deposit 1162d is deposited when the p-type semiconductor layer 1153 is formed, the deposit 1162e is deposited when the light-emitting layer 1152 is formed, and the deposit 1162f is deposited when the n-type semiconductor layer 1151 is formed, but this is not limiting.

[0173] As shown in Fig. 17B, a third wiring layer 230 including a light emitting element 250, a graphene sheet 140a, and wiring 230a is formed. The semiconductor layer 1150 shown in Fig. 17A is processed by etching to form the light emitting element 250. The graphene layer 1140 shown in Fig. 17A is over-etched during the formation of the light emitting element 250 and formed into the graphene sheet 140a. Therefore, the outer periphery of the graphene sheet 140a in the XY plane view substantially coincides with the outer periphery of the light emitting element 250 in the XY plane view.

[0174] In the process of forming the third wiring layer 230, the wiring 230a is formed so as to protrude from the light emitting element 250 in one direction on the planarized surface 112F. The periphery of the wiring 230a is set so as to include the periphery of the light emitting element 250 when the light emitting element 250 is projected onto the wiring 230a in an XY planar view. In other words, the periphery of the light emitting element 250 is disposed within the periphery of the wiring 230a in an XY planar view. The protruding portion of the wiring 230a is formed so as to ensure an area for connecting one end of a via 261a shown in FIG. 18 , which will be described later. Because the light emitting surface 253S is connected to the via 261a via the wiring 230a, the light emitting element 250 is formed into a single rectangular pillar or cylindrical shape without forming a connecting portion as in the other embodiments described above.

[0175] After forming the light emitting element 250, the graphene sheet 140a, and the third wiring layer 230, a second interlayer insulating film 156 is formed. The second interlayer insulating film 156 is formed to cover the planarized surface 112F, the third wiring layer 230 including the wiring 230a, the graphene sheet 140a, and the light emitting element 250.

[0176] As shown in FIG. 18, the via (second via) 261a is formed by filling a via hole formed to penetrate the second interlayer insulating film 156 and reach the wiring 230a with a conductive material. The via 161d and the connecting member 161a are formed in the same manner as in the other embodiments described above. That is, the via 161d is formed by filling a via hole formed to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d with a conductive material. The connecting member 161a is formed by filling a contact hole formed to reach the top surface 251U with a conductive material. As in the other embodiments described above, the via hole and the contact hole are formed by, for example, RIE or the like.

[0177] Thereafter, the second wiring layer 160 is formed on the second interlayer insulating film 156, the wiring 160d is connected to the via 161d and the connection member 161a, and the wiring 260a is connected to the via 261a.

[0178] Thereafter, a color filter is formed on the exposed surface 102b of the substrate 102, and sub-pixels 220 are formed, as in the other embodiments described above.

[0179] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 250 and reducing the number of processes. In addition, by setting the polarity of the TFT to n-channel, it becomes possible to use the light-emitting surface 253S as the p-type semiconductor layer 253. This has the advantage of improving the degree of freedom in arranging circuit elements and designing the circuit.

[0180] In this embodiment, the light emitting element 250 is provided on the wiring 230a and the graphene sheet 140a, and the light emitting surface 253S is provided in contact with the graphene sheet 140a. The third wiring layer 230 including the wiring 230a is formed of a light-transmitting conductive film or a light-transmitting metal thin film. The graphene sheet 140a is formed to be sufficiently thin and has sufficient light transmittance. Therefore, in this embodiment, the light emitted from the light emitting element 250 has sufficient intensity even when passing through the graphene sheet 140a and the wiring 230a.

[0181] That is, sufficient emission intensity is ensured without adding a step of removing the wiring 230a or the graphene sheet 140a, so that an increase in the number of steps can be suppressed, and manufacturing costs can be reduced.

[0182] In this embodiment, the wiring 230a is electrically connected to the light-emitting surface 253S, and the light-emitting element 250 can be connected to the via 261a with low resistance. Therefore, the current component of the current flowing in the light-emitting element 250 in a direction intersecting the Z axis is reduced, and therefore the voltage drop is also reduced, thereby reducing the power loss of the light-emitting element 250. In other words, the light-emitting element 250 with a vertical structure can substantially improve its light-emitting efficiency.

[0183] (Third embodiment) FIG. 19 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that a light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 103. The light-emitting element 150 of this embodiment also differs from the other embodiments described above in that the light-emitting surface 151S is roughened. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0184] 19, the image display device includes a subpixel 320. The subpixel 320 includes a color filter (first member) 180, a transistor 103, a first wiring layer 110, a light-shielding layer 330, a first interlayer insulating film 112, a light-emitting element 150, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. The subpixel 320 further includes an electrode 165a having light reflectivity. The subpixel 320 further includes a light-shielding layer 330.

[0185] In this embodiment, each component of the circuit 101, including the transistor 103, is provided on a color filter 180. In this example, the transistor 103 is provided on a light-shielding portion 181 that constitutes the color filter 180. The transistor 103 is formed on a TFT lower layer film 106 that is provided on the color filter 180. The TFT lower layer film 106 is provided on a formation surface (first surface) 180S of the color filter (first member) 180, and the transistor 103 is provided on the light-shielding portion 181 via the TFT lower layer film 106.

[0186] Color conversion section (light-transmitting member) 182 of color filter 180 is provided so as to penetrate first interlayer insulating film 112, light-shielding layer 330, insulating film 108, insulating layer 105, and TFT lower film 106. Light-emitting surface 151S of light-emitting element 150 is provided over color conversion layer 183. Light emitted from light-emitting surface 151S passes through color conversion layer 183 and filter layer 184 and is radiated to the outside.

[0187] In this embodiment, light-emitting surface 151S is roughened. Color conversion layer 183 fills an opening that penetrates first interlayer insulating film 112, light-shielding layer 330, insulating film 108, insulating layer 105, and TFT lower film 106. Color conversion layer 183 is provided to cover roughened light-emitting surface 151S and wall surface 158W of the opening.

[0188] In this embodiment, the first interlayer insulating film 112 includes two insulating films 112a and 112b. The insulating films 112a and 112b are formed of, for example, the same material and form the first interlayer insulating film 112. The insulating film 112a is provided on the insulating film 108 and the first wiring layer 110. A light-shielding layer 330 is provided on the insulating film 112a. The insulating film 112b is provided on the light-shielding layer 330. In other words, the light-shielding layer 330 is provided between the insulating films 112a and 112b. The light-shielding layer 330 is provided over almost the entire surface of the first interlayer insulating film 112, except for the through-holes 331, between the first interlayer insulating film 112 and the second interlayer insulating film 156.

[0189] In this embodiment, the color conversion portion 182 of the color filter 180 is provided so as to penetrate the insulating film 112b, the light-shielding layer 330, the insulating film 112a, the insulating film 108, the insulating layer 105, and the TFT lower film 106. Of these, the light-shielding layer 330 has a through-hole 331 having a diameter larger than that of the color conversion portion 182 in the XY plane view. The color conversion portion 182 is provided via the through-hole. In this example, since the via 161d is provided close to the color conversion portion 182, the through-hole 331 has a diameter large enough to allow the via 161d to pass through.

[0190] The light-shielding layer 330 may be made of any material, whether conductive or non-conductive, as long as it has light-shielding properties. For example, the light-shielding layer 330 may be made of a metal material that is light-reflective. The light-shielding layer 330 may be made of a black resin. When the light-shielding layer 330 is made of a black resin, it can be formed together with the insulating films 112a and 112b when forming the openings for the color conversion units 182, without having to previously form through-holes with sufficiently large diameters.

[0191] In this embodiment, the light-shielding layer 330 is set so as to include most of the periphery of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding layer 330 in the XY plane. In other words, the periphery of the TFT channel 104 is disposed within the periphery of the light-shielding layer 330 in the XY plane. This makes it possible to block scattered light from the light-emitting element 150 and prevent malfunction of the transistor 103 due to light.

[0192] Light emitting element 150 has roughened light emitting surface 151S and is provided directly on color conversion layer 183, and other than that, it is the same as in the other embodiments described above, and detailed description thereof will be omitted.

[0193] The electrode 165a is provided over the top surface 153U. The electrode 165a is provided between the top surface 153U and the connecting member 161a. The electrode 165a is made of a conductive material having optical reflectivity. The electrode 165a establishes an ohmic connection with the p-type semiconductor layer 153. Because the electrode 165a has optical reflectivity, it reflects upwardly emitted light and scattered light from the light-emitting element 150 toward the light-emitting surface 151S. This improves the substantial light-emitting efficiency of the light-emitting element 150.

[0194] The second interlayer insulating film 156 is provided to cover the planarized surface 112F, the light emitting element 150, and the electrode 165a. The vias 161d and 161k are provided in the same manner as in the other embodiments described above, and the second wiring layer 160 including the wirings 160d and 160k is provided in the same manner as in the other embodiments described above.

[0195] The manufacturing method of this embodiment will be described. 20A to 23B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. In the manufacturing method of the image display device of this embodiment, among the steps of preparing the drive circuit substrate 100 shown in Fig. 6A, the steps described with reference to Fig. 6A are applied up to the formation of the first wiring layer 110. In the manufacturing method of this embodiment, the description will start from the steps after the formation of the first wiring layer 110 in the description with reference to Fig. 6A. 20A, an insulating film 112a is formed on the insulating film 108 and the first wiring layer 110. A light-shielding layer 330 having a through-hole 331 is formed on the insulating film 112a.

[0196] 20B, insulating film 112b is formed on insulating film 112a and light-shielding layer 330. Insulating film 112b is also formed inside through-hole 331. The surface of insulating film 112b is planarized to form planarized surface 112F. In this manner, drive circuit substrate (first substrate) 100 having light-shielding layer 330 is formed.

[0197] As shown in FIG. 21A, a graphene layer 1140 is formed in place on the planarized surface 112F.

[0198] As shown in Fig. 21B, a semiconductor layer 1150 is formed over the graphene layer 1140. The process for forming the semiconductor layer 1150 and the techniques to be applied are similar to those in the example described in relation to Fig. 7A. After the semiconductor layer 1150 is formed, a metal layer 1160 is formed on the p-type semiconductor layer 1153. The metal layer 1160 is formed of a conductive material such as a light-reflective metal.

[0199] 22A, the electrode 165a, the light-emitting element 150, and the graphene sheet 140a are formed. The same techniques and procedures as those in the other embodiments described above are applied for forming these. A second interlayer insulating film 156 is formed to cover the planarized surface 112F, the formed electrode 165a, the light-emitting element 150, and the graphene sheet 140a.

[0200] In the process of forming the electrode 165a, the light-emitting element 150, and the graphene sheet 140a, the metal layer 1160 shown in FIG. 21B is processed by etching to form the electrode 165a. The semiconductor layer 1150 shown in FIG. 21B is processed by etching to form the light-emitting element 150. In the process of forming the light-emitting element 150, the connecting portion 151a is formed, and then other portions are formed. When forming the light-emitting element 150, the graphene layer 1140 shown in FIG. 21A is over-etched to form the graphene sheet 140a. For these etching processes, RIE or the like is used, as in the other embodiments described above.

[0201] 22B, a via 161d is formed penetrating the second interlayer insulating film 156 and the first interlayer insulating film 112. A via 161k is formed penetrating the second interlayer insulating film 156. A contact hole formed in the second interlayer insulating film 156 is filled with a conductive material to form a connection member 161a. A second wiring layer 160 is formed on the second interlayer insulating film 156, and the wiring 160d is connected to the via 161d and the connection member 161a, and the wiring 160k is connected to the via 161k. These steps are also performed using the same techniques and procedures as in the other embodiments described above.

[0202] 23A, an adhesive layer 1170 is formed over the second interlayer insulating film 156 and the second wiring layer 160, and a reinforcing substrate 1180 is bonded via the adhesive layer 1170. The provision of the reinforcing substrate 1180 provides protection from damage due to stress or impact during the subsequent substrate 102 removal process or transportation. After bonding the reinforcing substrate 1180, the substrate 102 is removed by wet etching or laser lift-off, exposing the surface 106S of the TFT lower layer film 106.

[0203] As shown in FIG. 23B, an opening 158 is formed from the surface 106S toward the light-emitting surface 151S. The opening 158 is formed to penetrate the TFT lower film 106, the insulating layer 105, the insulating film 108, the light-shielding layer 330, and the first interlayer insulating film 112, and reach the light-emitting surface 151S. In this embodiment, when the opening 158 is formed, the graphene sheet 140a shown in FIG. 23A is entirely removed. The process of forming the opening 158 can be performed using the same techniques and procedures as those in the other embodiments described above.

[0204] The light-emitting surface 151S exposed by the formation of the openings 158 is roughened by wet etching or the like. Then, the steps described in relation to FIGS. 9A to 9D are applied to form color filters, resulting in the formation of subpixels 320. As described in relation to FIG. 11, the openings 158 may be filled with a transparent resin to form inkjet-type or film-type color filters. Alternatively, after the step of FIG. 22B, the openings 158 may be formed including the substrate 102 without removing the substrate 102, thereby forming inkjet-type or film-type color filters. The reinforcing substrate 1180 may be removed after the color filters are formed, or may be removed separately without removing the substrate 102.

[0205] In this manner, color filters can be formed and sub-pixels 320 can be formed.

[0206] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the manufacturing method for the image display device of this embodiment has the effect of shortening the time required for the transfer step and reducing the number of steps required to form the light emitting element 150. In addition, since the light emitting surface 151S is made of the n-type semiconductor layer 151, which has a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thick, and the light emitting surface 151S can be sufficiently roughened.

[0207] In the image display device of this embodiment, the emitted light is diffused by roughening the light-emitting surface 151S, so that even a small light-emitting element 150 can be used as a light source with a sufficient light-emitting area.

[0208] In the image display device of this embodiment, the light-shielding layer 330 is provided between the insulating films 112a and 112b. That is, the light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 103. Therefore, even if the light-emitting element 150 emits light, the emitted light and scattered light are unlikely to reach the TFT channel 104, and malfunction of the transistor 103 can be prevented.

[0209] The light-shielding layer 330 can be formed of a conductive material such as metal, and can be connected to any potential. For example, by arranging a part of the light-shielding layer 330 directly under a switching element such as the transistor 103 and connecting it to a ground potential or a power supply potential, it can be used to suppress noise.

[0210] When light-shielding layer 330 is formed of an insulating material such as black resin, opening 158 can be formed without providing through-hole 331 when forming via 161d described with reference to Fig. 22B or opening 158 described with reference to Fig. 23B. This makes it possible to omit the step of forming through-hole 331 and to prevent through-hole 331 from creating a gap through which light can pass, thereby more reliably preventing malfunction of transistor 103.

[0211] The light-shielding layer 330 is not limited to application in this embodiment, but can be commonly applied to the subpixels of the other embodiments described above and other embodiments to be described later. Even when applied to other embodiments, the same effects as those described above can be obtained.

[0212] In this embodiment, the periphery of the light-emitting element 150 except for the light-emitting surface 151S is covered with a second interlayer insulating film 156. The second interlayer insulating film 156 can be formed of a light-reflective material, such as a white resin. Furthermore, in this embodiment, a light-reflective electrode 165a is provided across the top surface 153U opposite the light-emitting surface 151S. As a result, the light emitted by the light-emitting element is confined within the light-emitting element 150, and some or most of the light is guided to the light-emitting surface 151S. Therefore, the substantial light-emitting efficiency of the light-emitting element 150 is improved.

[0213] In this example, the insulating films 112a, 112b and the insulating film 108 are made of a light-transmitting resin, such as a transparent resin. If the insulating films 112a, 112b and the insulating film 108 are also made of a light-reflective material, such as a white resin, the substantial light-emitting efficiency of the light-emitting element 150 can be further improved.

[0214] In the above example, the configuration and manufacturing method of a light-emitting element having a roughened light-emitting surface were described. For a light-emitting element having a connecting portion, a roughened light-emitting surface can be applied as in the present embodiment by adding a process of forming an opening that exposes the light-emitting surface. Specific applications include the light-emitting element 150 of the first embodiment and the semiconductor layer 750 of the seventh embodiment described below. Furthermore, in the fifth and sixth embodiments described below, changing the connection using transparent wiring to a connection using a connecting portion formed on the light-emitting element makes it possible to roughen the light-emitting surface. By roughening the light-emitting surfaces of the components of these light-emitting elements, the above-mentioned effects can be achieved.

[0215] (Fourth embodiment) FIG. 24 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. This embodiment differs from the other embodiments described above in that it includes a fourth wiring layer 470 provided on the light emitting element 150. In other respects, it is the same as the other embodiments described above, and the same components are denoted by the same reference numerals and detailed descriptions thereof are omitted as appropriate. In this embodiment, the n-type semiconductor layer 151 that provides the light emitting surface 151S is connected to the second wiring layer 160 by a third wiring layer 230 that is light-transmitting.

[0216] 24, the image display device of this embodiment includes a subpixel 420. The subpixel 420 includes a substrate 102, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a third wiring layer 230, a light-emitting element 150, a fourth wiring layer 470, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. The subpixel 420 further includes a color filter.

[0217] In this embodiment, the drive circuit substrate 100 includes a substrate 102, a TFT lower layer film 106, a circuit 101, and a first interlayer insulating film 112. The configuration of the drive circuit substrate 100 is the same as that of the first embodiment, and detailed description thereof will be omitted.

[0218] The third wiring layer 230 including the wiring 230a is provided on the planarized surface 112F. The configurations of the third wiring layer 230 and the wiring 230a are the same as those in the second embodiment described with reference to FIG. 14, and detailed description thereof will be omitted.

[0219] The light emitting element 150 is provided on the wiring 230a via the graphene sheet 140a.

[0220] A resin layer 457 is provided on the planarized surface 112F, the third wiring layer 230 including the wiring 230a, the graphene sheet 140a, and the light emitting element 150. The resin layer 457 is, for example, a transparent resin. A fourth wiring layer 470 is provided on the resin layer 457. The fourth wiring layer 470 may include a plurality of wirings. Each of the plurality of wirings may be connected to a different potential. In this example, the fourth wiring layer 470 includes wirings 470a and 470b formed separately.

[0221] The wiring (first electrode) 470a is provided above and to the sides of the light-emitting element 150, and covers the top surface 153U and side surfaces of the light-emitting element 150. The wiring 470a functions as a member for reflecting light. The wiring 470a covers most of the light-emitting element except for the light-emitting surface 151S. This allows the wiring 470a to reflect scattered light or reflected light toward the sides or above the light-emitting element 150 toward the light-emitting surface 151S, thereby improving the substantial light-emitting efficiency of the light-emitting element 150. The connection electrode 461a is provided between the top surface 153U and the wiring 470a, and electrically connects the top surface 153U and the wiring 470a.

[0222] When resin layer 457 is made of a transparent resin, scattered light and the like emitted from above or from the sides of light emitting element 150 is reflected by wiring 470a toward light emitting surface 151S, thereby improving the substantial light emitting efficiency of light emitting element 150. When resin layer 457 is made of a material with high light reflectivity, such as white resin, wiring 470a is further provided on resin layer 457, so that scattered light and the like leaking from resin layer 457 can be reflected toward light emitting surface 151S, thereby achieving higher light reflectivity.

[0223] The second interlayer insulating film 156 is provided to cover the resin layer 457 and the fourth wiring layer 470. On the second interlayer insulating film 156, a second wiring layer 160 including wirings 160d and 160k is provided.

[0224] The via 161d is provided to penetrate the second interlayer insulating film 156, the resin layer 457, and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring 160d and the wiring 110d and electrically connects the wiring 160d and the wiring 110d. The wiring 160d is connected to the wiring 470a via the connection member 471a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection electrode 461a, the wiring 470a, the connection member 471a, the wiring 160d, the via 161d, the wiring 110d, and the via 111d.

[0225] The via 161k is provided to penetrate the second interlayer insulating film 156 and the resin layer 457 and reach the wiring 230a. The via 161k is provided between the wiring 160k and the wiring 230a and electrically connects the wiring 160k and the wiring 230a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 via the graphene sheet 140a, the wiring 230a, the via 161k, and the wiring 160k.

[0226] A method for manufacturing the image display device of this embodiment will be described. 25A to 26B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. In this embodiment, as described with reference to FIG. 17A , the steps of forming the light-transmitting conductive film 1130, forming the graphene layer 1140, and forming the semiconductor layer 1150 are the same as those in the other embodiments described above. Hereinafter, the description will be given assuming that the step of FIG. 25A is performed after the step of FIG. 17A . However, in this embodiment, the semiconductor layer 1150 formed on the graphene layer 1140 is formed by stacking the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 in this order from the graphene layer 1140 side. Therefore, when applying FIG. 17A to this embodiment, the semiconductor layer 1150 is formed by stacking the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 in this order. The process of forming such a semiconductor layer 1150 is the same as that described with reference to FIG. 7A .

[0227] 25A, the transparent conductive film 1130 shown in FIG. 17A is processed by etching to form a third wiring layer 230 including wirings 230a. The semiconductor layer 1150 shown in FIG. 17A is processed by etching to form the light emitting element 150. The graphene layer 1140 is over-etched during the formation of the light emitting element 150 to be shaped into a graphene sheet 140a.

[0228] The resin layer 457 is formed to cover the planarized surface 112F, the third wiring layer 230 including the wiring 230a, the graphene sheet 140a, and the light emitting element 150. An opening 462a is formed in the resin layer 457 so that a portion of the top surface 153U of the light emitting element 150 is exposed.

[0229] 25B, metal layer 1470 is formed to cover resin layer 457. When forming metal layer 1470, opening 462a shown in FIG. 25A may be filled at the same time to form connection electrode 461a, or opening 462a may be filled to form connection electrode 461a, and then metal layer 1470 may be formed.

[0230] As shown in Fig. 26A, the metal layer 1470 shown in Fig. 25B is processed by etching to form the fourth wiring layer 470. When the fourth wiring layer 470 is formed, the wiring 470a and the wiring 470b are formed separately. The wiring 470a is formed so as to cover the top surface 153U and the side surfaces of the light-emitting element. The second interlayer insulating film 156 is formed so as to cover the resin layer 457 and the fourth wiring layer 470.

[0231] As shown in FIG. 26B, a second wiring layer 160 including wirings 160d and 160k is formed on the second interlayer insulating film 156. A via 161k is formed to penetrate the second interlayer insulating film 156 and reach the wiring 230a. The via (second via) 161k is located between the wiring 160k and the wiring 230a and electrically connects the wiring 160k and the wiring 230a. As in the other embodiments described above, a via 161d is formed and electrically connects the second wiring layer 160 and the first wiring layer 110. A connecting member 471a is formed by filling a contact hole formed by opening the second interlayer insulating film 156 with a conductive material, and connects the wiring 160d and the wiring 470a.

[0232] Thereafter, a color filter is formed on the exposed surface 102 b of the substrate 102 to form the sub-pixels 420 .

[0233] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the advantage of being able to shorten the time required for the transfer process to form the light emitting element 150 and reduce the number of processes. In addition, the image display device has the following advantages.

[0234] The third wiring layer 230 including the wiring 230a is formed from a light-transmitting conductive film such as an ITO film or a metal thin film, and is therefore easy to process, which may shorten the series of manufacturing steps for the light-emitting element 150 and the third wiring layer 230.

[0235] In this embodiment, the wiring 230a is used to lead out the electrode on the light-emitting surface 151S side, which allows the light-emitting element 150 to have a vertical structure. In the light-emitting element 150 having a vertical structure, the component of the current flowing in the semiconductor layer in a direction intersecting the Z-axis can be reduced and the current can be directed substantially along the Z-axis, which has the advantage of reducing loss in the semiconductor layer.

[0236] In the image display device of this embodiment, the subpixel 420 includes a fourth wiring layer 470. The fourth wiring layer 470 is electrically isolated from the light-emitting element 150 by the resin layer 457. The fourth wiring layer 470 includes wiring 470a, which covers the top surface 153U and side surfaces of the light-emitting element 150 via the resin layer 457. This allows scattered light, such as light scattered upward or to the sides of the light-emitting element 150, to be reflected toward the light-emitting surface 151S. This improves the substantial light-emitting efficiency of the light-emitting element 150. The resin layer 457 may be smoothed by reflow or the like, so that the wiring 470a has a parabolic curved shape. This can also make the light emitted from the light-emitting element 150 closer to parallel light in the negative Z-axis direction.

[0237] (Fifth embodiment) FIG. 27 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. This embodiment differs from the other embodiments described above in that an electrode 565a is provided to cover the top surface 153U of the light-emitting element 150, and the electrode 565a is connected to a wiring 560d formed in a contact hole 561a for the electrode 565a. In other respects, this embodiment is the same as the other embodiments, and the same components are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0238] 27, the image display device of this embodiment includes a subpixel 520. The subpixel 520 includes a color filter (first member) 180, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a third wiring layer 230, a graphene sheet 140a, a light-emitting element 150, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160. In this embodiment, the subpixel 520 includes a second wiring layer 160 that includes a wiring 560d. A light-reflective electrode (second electrode) 565a is provided over the top surface 153U, and the electrode 565a is connected to the wiring 560d.

[0239] In this embodiment, each element of the circuit 101, including the transistor 103, is provided on a formation surface (first surface) 180S of the color filter (first component) 180, with a TFT lower layer film 106 interposed therebetween. The light-emitting element 150 is provided on the color filter 180, with an insulating film 108 provided to cover the transistor 103 and the like, and a first interlayer insulating film 112 on the insulating film 108 interposed therebetween. In this example, each element of the circuit 101 is provided on a light-shielding portion 181 of the color filter 180, and the light-emitting element 150 is provided on a color conversion portion 182 of the color filter 180. Light emitted from the light-emitting element 150 is incident on the color conversion portion 182 of the color filter 180 through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, and the TFT lower layer film 106. The configurations of the color filter 180, the transistor 103, and the like are the same as those in the other embodiments described above, and detailed description thereof will be omitted.

[0240] As in the other embodiments described above, the third wiring layer 230 including the wiring 230a is provided on the planarized surface 112F, and the light emitting element 150 is provided on the wiring 230a with the graphene sheet 140a interposed therebetween. The wiring 230a is provided to protrude in one direction above the planarized surface 112F, and as in the other embodiments described above, one end of the via 161k is connected to the wiring 230a.

[0241] The light-emitting element 150 has an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153 laminated in this order from the light-emitting surface 151S toward the top surface 153U. An electrode 565a is provided on the top surface 153U opposite to the light-emitting surface 151S. The electrode 565a is made of a light-reflective conductive material.

[0242] A contact hole 561a is formed above the light emitting element 150. The contact hole 561a is formed by removing a portion of the second interlayer insulating film 156. The opening diameter of the contact hole is set to be sufficiently large, and the inner periphery of the contact hole 561a is set to be the same as the outer periphery of the top surface 153U in the XY plane view or slightly inside the outer periphery of the top surface 153U in the XY plane view.

[0243] The electrode 565a is provided at the bottom of the contact hole 561a. Therefore, the outer periphery of the electrode 565a in the XY plane view substantially coincides with the inner periphery of the contact hole 561a in the XY plane view. Therefore, the electrode 565a is provided so as to cover all or most of the top surface 153U. The electrode 565a is light reflective, and therefore reflects scattered light and the like upward from the light emitting element 150 toward the light emitting surface 151S. This improves the substantial light emitting efficiency of the light emitting element 150. The electrode 565a may be formed integrally with the wiring 560d formed on the wall surface of the contact hole 561a.

[0244] The second wiring layer 160 includes a wiring 560d. The wiring 560d is provided on the second interlayer insulating film 156 and also on the wall surface of the contact hole 561a, and is connected to the electrode 565a. The wiring 560d is connected to the wiring 110d through the via 161d, and therefore the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 through the electrode 565a, the wiring 560d, the via 161d, the wiring 110d, and the via 111d.

[0245] A method for manufacturing the image display device of this embodiment will be described. 28A and 28B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In the manufacturing method of the image display device of this embodiment, as in the case of the fourth embodiment described above, the steps up to the step of forming the semiconductor layer 1150 shown in Fig. 17A are the same as those in the other embodiments described above. The description will be given assuming that the step of Fig. 28A is performed after the step of Fig. 17A. However, in the application of Fig. 17A to the present embodiment, the semiconductor layer 1150 will be described assuming that the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 are stacked in this order from the graphene layer 1140 side.

[0246] As shown in Fig. 28A, the translucent conductive film 1130 shown in Fig. 17A is processed by etching to form the third wiring layer 230 including the wiring 230a. The semiconductor layer 1150 shown in Fig. 17A is processed by etching to form the light emitting element 150. The graphene layer 1140 shown in Fig. 17A is over-etched during the formation of the light emitting element 150 to be shaped into a graphene sheet 140a. The second interlayer insulating film 156 is formed to cover the planarized surface 112F, the third wiring layer 230 including the wiring 230a, the graphene sheet 140a, and the light emitting element 150.

[0247] A via hole 162d is formed so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. A via hole 162k is formed so as to penetrate the second interlayer insulating film 156 and reach the wiring 230a. A portion of the second interlayer insulating film 156 on the light emitting element 150 is removed, and the top surface 153U is exposed from the opening 561.

[0248] It is preferable that the entire top surface 153U is exposed through the opening 561 of the contact hole 561a, but the shape of the exposed top surface 153U is appropriately set depending on the formation accuracy of the contact hole 561a. For example, the inner periphery of the contact hole 561a in the XY plane is set to be slightly smaller than the outer periphery of the top surface 153U in the XY plane.

[0249] The via holes 162d and 162k are formed, for example, at the same time. The contact hole 561a may be formed at the same time as the via holes 162d and 162k, or may be formed separately.

[0250] As shown in Fig. 28B, the via holes 162d and 162k shown in Fig. 28A are filled with a conductive material to form the vias 161d and 161k. During the process of forming the vias 161d and 161k, the bottom of the contact hole 561a, i.e., the top surface 153U, may be covered with a conductive material.

[0251] The second wiring layer 160 is formed on the second interlayer insulating film 156. When forming the second wiring layer 160, a conductive layer that forms the second wiring layer 160 is formed on the second interlayer insulating film 156 and processed by etching to form the second wiring layer 160 including the wirings 560d and 160k. The conductive layer is formed not only on the second interlayer insulating film 156 but also on the exposed top surface 153U and the wall surfaces of the contact holes 561a.

[0252] In this way, a wiring 560d connected to the via 161d is formed, and a wiring 160k connected to the via 161k is formed. The wiring 560d is provided over the wall surface of the contact hole 561a, and is therefore also electrically connected to the top surface 153U.

[0253] An adhesive layer 1170 is provided on the second interlayer insulating film 156 and the second wiring layer 160, and a reinforcing substrate 1180 is bonded by the adhesive layer 1170. Thereafter, the substrate 102 is removed by wet etching or the like, and the surface 106S of the TFT lower layer film 106 is exposed.

[0254] Thereafter, a color filter is formed on the surface 106S, and the sub-pixels 520 are formed.

[0255] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light emitting element 150 and reducing the number of processes. In addition, in this embodiment, since the electrode 565a is provided over the top surface 153U, the upward scattered light emitted by the light emitting element 150 can be reflected toward the light emitting surface 151S. Therefore, the substantial light emitting efficiency of the light emitting element 150 is improved.

[0256] In this embodiment, the contact hole 561a for forming the electrode 565a can be formed during the process of forming the vias 161d and 161k. Furthermore, the connection to the top surface 153U by the second wiring layer 160 can also be performed during the process of forming the second wiring layer 160. Therefore, there is no need to add a process for forming the electrode 565a, which shortens the manufacturing process and the time from input of materials to completion of the product.

[0257] (Sixth embodiment) FIG. 29 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the configuration of the light-emitting element 650 differs from that of the other embodiments. The other components are the same as those of the other embodiments described above. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. 29, the image display device of this embodiment includes a subpixel 620. The subpixel 620 includes a substrate 102, a transistor 103, a first wiring layer 110, a light-shielding layer 330, a first interlayer insulating film 112, a third wiring layer 230, a graphene sheet 140a, a light-emitting element 650, a second interlayer insulating film 156, and a second wiring layer 160. The subpixel 620 further includes a color filter 180.

[0258] In this embodiment, a light-shielding layer 330 is provided. The light-shielding layer 330 has the same configuration as that described in relation to FIG. 19 in the third embodiment. The light-shielding layer 330 is set so as to include the outer periphery of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding layer 330 in the XY plane. In other words, the outer periphery of the TFT channel 104 is disposed within the outer periphery of the light-shielding layer 330 in the XY plane. The light-shielding layer 330 has a through-hole 331. The through-hole 331 is provided for insulation from the optical path and the via 161d, as in the third embodiment.

[0259] In this embodiment, the light emitting surface 651S is provided on the wiring 230a via the graphene sheet 140a, and is connected to the via 161k via the wiring 230a.

[0260] The light emitting element 650 is a truncated pyramidal or truncated conical element formed so that the area in the XY plane view decreases in the positive direction of the Z axis.

[0261] FIG. 30 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. FIG. 30 is a partial enlarged view of FIG. 29, showing the relationship between the light emitting surface 651S and the side surface 655a in the light emitting element 650. In FIG. 30 , the planarized surface 112F is a plane substantially parallel to the XY plane. The light emitting element 650 is provided on the planarized surface 112F via the graphene sheet 140a and the wiring 230a. The light emitting surface 651S is a plane substantially parallel to the planarized surface 112F and the XY plane. Light emitted from the light emitting surface 651S is incident on the first interlayer insulating film 112 via the graphene sheet 140a and the wiring 230a, but the thicknesses of the graphene sheet 140a and the wiring 230a are sufficiently thin, and the reflection and absorption of light are sufficiently small.

[0262] The light-emitting element 650 has a top surface 653U opposite to the light-emitting surface 651S. The light-emitting element 650 has a side surface 655a. The side surface 655a is a surface between the top surface 653U and the planarized surface 112F and adjacent to the light-emitting surface 651S. The interior angle θ between the light-emitting surface 651S and the side surface 655a is smaller than 90°. Preferably, the interior angle θ is approximately 70°. More preferably, the interior angle θ is smaller than a critical angle of the side surface 655a, which is determined based on the refractive index of the light-emitting element 650 and the refractive index of the second interlayer insulating film 156. The light-emitting element 650 is covered with the second interlayer insulating film 156, and the side surface 655a is in contact with the second interlayer insulating film 156.

[0263] The critical angle θc of the interior angle θ formed between the side surface 655a of the light emitting element 650 and the planarized surface 112F is determined, for example, as follows. When the refractive index of light emitting element 650 is n0 and the refractive index of second interlayer insulating film 156 is n1, the critical angle θc of light emitted from light emitting element 650 to second interlayer insulating film 156 is found using the following equation (1).

[0264] θc=90°-sin -1 (n1 / n0) (1)

[0265] For example, it is known that the refractive index of a typical transparent organic insulating material such as acrylic resin is approximately 1.4 to 1.5. Therefore, if light-emitting element 650 is made of GaN and second interlayer insulating film 156 is made of a typical transparent organic insulating material, the refractive index n0 of light-emitting element 650 can be set to 2.5, and the refractive index n of second interlayer insulating film 156 can be set to 1.4. By substituting these values ​​into equation (1), the critical angle θc can be obtained as 56°.

[0266] This indicates that when the interior angle θ between planarized surface 112F and side surface 655a is θc = 56°, light emitted from light-emitting layer 652 that is parallel to light-emitting surface 651S is totally reflected by side surface 655a. It also indicates that light emitted from light-emitting layer 652 that has a component in the positive direction of the Z axis is totally reflected by side surface 655a. For simplicity, the second interlayer insulating film 156 is made of a transparent resin in the above description. Even if the transparent resin is a white resin, the effect of the white resin on the refractive index of the scattering particles is small, so the refractive index of the scattering particles is ignored in the above calculations.

[0267] On the other hand, of the light emitted from light-emitting layer 652, light having a component in the negative direction of the Z axis is emitted from side surface 655a at an emission angle according to the refractive index at side surface 655a. Light incident on second interlayer insulating film 156 is emitted from second interlayer insulating film 156 at an angle determined by the refractive index of second interlayer insulating film 156.

[0268] The light totally reflected by side surface 655a is reflected again by other element interfaces and top surface 653U, and the light having a component in the negative direction of the Z axis among the reflected light is emitted from light-emitting surface 651S and side surface 655a. The light parallel to planarized surface 112F and the light having a component in the positive direction of the Z axis are totally reflected by side surface 655a.

[0269] In this way, of the light emitted from light-emitting layer 652, light parallel to planarized surface 112F and light having a component in the positive direction of the Z axis are converted by side surface 655a and top surface 653U into light having a component in the negative direction of the Z axis. Therefore, the proportion of light emitted from light-emitting element 650 that is directed toward light-emitting surface 651S increases, and the substantial light-emitting efficiency of light-emitting element 650 improves.

[0270] By setting θ<θc, most of the light having a component parallel to the planarized surface 112F can be totally reflected into the light-emitting element 650. If the refractive index of the second interlayer insulating film 156 is n=1.4, the critical angle θc is approximately 56°, so it is more preferable to set the interior angle θ to 45°, 30°, or the like. Furthermore, the critical angle θc becomes smaller for materials with a larger refractive index n. However, even if the interior angle θ is set to approximately 70°, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis. Therefore, taking into account manufacturing variations, the interior angle θ may be set to, for example, 80° or less.

[0271] A method for manufacturing the image display device of this embodiment will be described. In this embodiment, the manufacturing process of the light emitting device 650 is different from that of the other embodiments, and the other manufacturing processes can be applied to the other embodiments described above. The different parts of the manufacturing process will be described below. In this embodiment, the following steps are performed to form the light-emitting device 650 in the shape shown in Fig. 29. Note that, in the case of this embodiment as well, the steps described below are applied after the steps described in relation to Fig. 17A. When the steps of Fig. 17A are applied to this embodiment, the semiconductor layer 1150 is configured such that the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order from the graphene sheet 140a side.

[0272] The semiconductor layer 1150 shown in FIG. 17A is etched into the shape of the light-emitting element 650 shown in FIG. 29. To form the light-emitting element 650, an etching rate is selected so that the side surface 655a shown in FIG. 30 forms an interior angle θ with the light-emitting surface 651S. For example, a higher etching rate is selected closer to the top surface 653U. Preferably, the etching rate is set to increase linearly from the light-emitting surface 651S side toward the top surface 653U side.

[0273] Specifically, for example, the resist mask pattern used in dry etching is designed to become gradually thinner toward its edge during exposure. This allows the resist to gradually recede from the thinner portion during dry etching, increasing the amount of etching from light-emitting surface 651S toward top surface 653U. As a result, side surface 655a is formed to form a substantially constant angle with respect to light-emitting surface 651S. Therefore, in light-emitting element 650, the areas of the layers in the XY plane view from top surface 653U increase in the order of p-type semiconductor layer 653, light-emitting layer 652, and n-type semiconductor layer 651.

[0274] Subpixels 620 are then formed in the same manner as in the other embodiments.

[0275] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 650 and reducing the number of processes, as well as the following effects. In the image display device of this embodiment, light emitting element 650 is formed to have a side surface 655a that forms an interior angle θ with respect to light emitting surface 651S on which light emitting element 650 is provided. Interior angle θ is set to be smaller than 90° based on a critical angle θc that is determined by the refractive indexes of the materials of light emitting element 650 and second interlayer insulating film 156. Interior angle θ enables light emitted from light emitting layer 652 that is directed to the side or above light emitting element 650 to be converted into light directed toward light emitting surface 651S and then emitted. By making interior angle θ sufficiently small, the substantial light emitting efficiency of light emitting element 650 is improved.

[0276] In this embodiment, the light-emitting element 650 can be configured with a vertical structure by connecting it to the via 161k using the wiring 230a of the third wiring layer 230. Therefore, the component of the current flowing through the light-emitting element 650 that intersects with the Z axis can be reduced, thereby improving the substantial light-emitting efficiency. In this embodiment, the light-emitting element is not limited to a vertical structure; it may also be configured with a horizontal structure by providing a connecting portion. Here, a horizontally structured light-emitting element refers to a light-emitting element having a structure in which the connecting portion 151a is provided next to the semiconductor layer on which the light-emitting surface is provided, as in the first embodiment. By configuring the light-emitting element with a horizontal structure, the light-emitting surface can be easily roughened, thereby improving the substantial light-emitting efficiency and diffusing light.

[0277] (Seventh embodiment) FIG. 31 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the image display device differs from the other embodiments in that it includes a subpixel group 720 including a plurality of light-emitting regions on one light-emitting surface. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. 31 , the image display device of this embodiment includes a subpixel group 720. The subpixel group 720 includes a substrate 102, a graphene sheet 740a, a plurality of transistors 103-1 and 103-2, a first wiring layer 110, a first interlayer insulating film 112, a semiconductor layer 750, a second interlayer insulating film 156, vias 761d1 and 761d2, and a second wiring layer 160. The subpixel group 720 further includes a color filter 180.

[0278] In the subpixel group 720, the transistors 103-1 and 103-2 are provided on a TFT lower layer 106 provided on one surface 102a of the substrate 102. Each element of the circuit 101, including the transistors 103-1 and 103-2, is covered with an insulating film 108, which, together with the first wiring layer 110, is covered by a first interlayer insulating film 112. The semiconductor layer 750 is provided on a planarized surface 112F of the first interlayer insulating film 112. The color filter 180 is provided on the other surface 102b of the substrate 102.

[0279] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one side of the semiconductor layer 750 via the first wiring layer 110 and vias 761d1 and 761d2. By turning on the p-channel transistors 103-1 and 103-2, electrons are injected from the other side of the semiconductor layer 750 via the second wiring layer 160. Holes and electrons are injected into the semiconductor layer 750, and the separated light-emitting layers 752a1 and 752a2 emit light due to the recombination of the holes and electrons. A drive circuit for driving the light-emitting layers 752a1 and 752a2 may have the circuit configuration shown in FIG. 3, for example. Using the example of the second embodiment, the n-type and p-type semiconductor layers of the semiconductor layers may be interchanged, and the semiconductor layers may be driven by n-channel transistors. In this case, the drive circuit may have the circuit configuration shown in FIG. 15.

[0280] The configuration of the sub-pixel group 720 will now be described in detail. The TFT lower layer film 106 is formed on the surface 102a. The TFT lower layer film 106 is flattened, and the TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

[0281] An insulating layer 105 covers the TFT lower film 106 and the TFT channels 104-1 and 104-2. A gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0282] TFT channel 104-1 includes p-doped regions 104s1 and 104d1, which are the source and drain regions, respectively, of transistor 103-1. Region 104i1 is n-doped and forms the channel of transistor 103-1. TFT channel 104-2 similarly includes p-doped regions 104s2 and 104d2, which are the source and drain regions, respectively, of transistor 103-2. Region 104i2 is n-doped and forms the channel of transistor 103-2.

[0283] The insulating film 108 covers the insulating layer 105 and the gates 107-1 and 107-2. In this embodiment, the circuit 101 includes the TFT channels 104-1 and 104-2, the insulating layer 105, the insulating film 108, the vias 111s1, 111d1, 111s2, and 111d2, and the first wiring layer 110.

[0284] The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 includes wirings 710f, 710s1, 710s2, 710d1, and 710d2.

[0285] Wiring 710f is provided between light-emitting regions 751R1 and 751R2. In this example, wiring 710f is not electrically connected to any of the circuit elements shown in FIG. 31, but it can be connected to any potential or circuit element. By being disposed between light-emitting regions 751R1 and 751R2, wiring 710f blocks the light emitted from light-emitting regions 751R1 and 751R2. Wiring 710f not only blocks light from transistors 103-1 and 103-2, but also prevents the light emitted by light-emitting regions 751R1 and 751R2 from intersecting and mixing with each other.

[0286] The wiring 710s1 is provided above the region 104s1. The via 111s1 is provided between the wiring 710s1 and the region 104s1, and electrically connects the wiring 710s1 and the region 104s1. The wiring 710s2 is provided above the region 104s2. The via 111s2 is provided between the wiring 710s2 and the region 104s2, and electrically connects the wiring 710s2 and the region 104s2. The wirings 710s1 and 710s2 are connected to the power supply line 3 of the circuit shown in FIG. 3, for example.

[0287] The wiring 710d1 is provided above the region 104d1. The via 111d1 is provided between the wiring 710d1 and the region 104d1, and electrically connects the wiring 710d1 and the region 104d1. The wiring 710d1 is connected to one end of the via 761d1. The wiring 710d2 is provided above the region 104d2. The via 111d2 is provided between the wiring 710d2 and the region 104d2, and electrically connects the wiring 710d2 and the region 104d2. The wiring 710d2 is connected to one end of the via 761d2.

[0288] The first interlayer insulating film 112 is provided to cover the insulating film 108 and the first wiring layer 110. The first interlayer insulating film 112 has a planarized surface 112F.

[0289] The graphene sheet 740a is provided on the planarized surface 112F. The graphene sheet 740a is sufficiently thin and has high light transmittance.

[0290] The semiconductor layer 750 is provided on a graphene sheet 740a. The outer periphery of the graphene sheet 740a in the XY plane view approximately coincides with the outer periphery of the semiconductor layer 750 in the XY plane view. A light emitting surface 751S of the semiconductor layer 750 is in contact with the graphene sheet 740a. The light emitting surface 751S is a surface of the n-type semiconductor layer 751. The light emitting surface 751S includes a plurality of light emitting regions 751R1 and 751R2.

[0291] The semiconductor layer 750 includes an n-type semiconductor layer 751, light-emitting layers 752a1 and 752a2, and p-type semiconductor layers 753a1 and 753a2. The light-emitting layer 752a1 is provided on the n-type semiconductor layer 751. The light-emitting layer 752a2 is provided on the n-type semiconductor layer 751, separated and spaced apart from the light-emitting layer 752a1. The p-type semiconductor layer 753a1 is provided on the light-emitting layer 752a1. The p-type semiconductor layer 753a2 is provided on the light-emitting layer 752a2, separated and spaced apart from the p-type semiconductor layer 753a1.

[0292] The p-type semiconductor layer 753a1 has a top surface 753U1 provided on the side opposite the surface on which the light emitting layer 752a1 is provided, and the p-type semiconductor layer 753a2 has a top surface 753U2 provided on the side opposite the surface on which the light emitting layer 752a2 is provided.

[0293] Light-emitting region 751R1 is a region of light-emitting surface 751S that roughly corresponds to the region on the opposite side of top surface 753U1. Light-emitting region 751R2 is a region of light-emitting surface 751S that roughly corresponds to the region on the opposite side of top surface 753U2.

[0294] FIG. 32 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. FIG. 32 is a schematic diagram for explaining light emitting regions 751R1 and 751R2. As shown in Fig. 32, light-emitting regions 751R1 and 751R2 are surfaces on light-emitting surface 751S. In Fig. 32, the portions of semiconductor layer 750 that include light-emitting regions 751R1 and 751R2 are referred to as light-emitting portions R1 and R2, respectively. Light-emitting portion R1 includes a portion of n-type semiconductor layer 751, light-emitting layer 752a1, and p-type semiconductor layer 753a1. Light-emitting portion R2 includes a portion of n-type semiconductor layer 751, light-emitting layer 752a2, and p-type semiconductor layer 753a2.

[0295] In this embodiment, in the light-emitting unit R1, the light-emitting region 751R1 is the surface opposite to the top surface 753U1. In the light-emitting unit R2, the light-emitting region 751R2 is the surface opposite to the top surface 753U2. The entire light-emitting surface 751S is covered with a graphene sheet 740a. The graphene sheet 740a is formed by etching the graphene layer 1140, as described with reference to FIG. 7B and other figures, regarding the manufacturing method of the image display device. The graphene sheet 740a is formed by over-etching the graphene layer 1140 when forming the semiconductor layer 750. Therefore, the outer periphery of the graphene sheet 740a in the XY plane view substantially coincides with the outer periphery of the semiconductor layer 750 in the XY plane view.

[0296] The semiconductor layer 750 includes a connection portion R0. The connection portion R0 is provided between the light emitting portions R1 and R2 and is a part of the n-type semiconductor layer 751. One end of the via 761k shown in FIG. 31 is connected to the connection portion R0, and provides a current path between the light emitting portions R1 and R2.

[0297] In the light-emitting portion R1, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 752a1. In the light-emitting portion R1, holes supplied from the top surface 753U1 are supplied to the light-emitting layer 752a1. The electrons and holes supplied to the light-emitting layer 752a1 combine to emit light. The light emitted from the light-emitting layer 752a1 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R1. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R1, the light-emitting portion 751R1 is the portion of the light-emitting surface 751S that emits light. Therefore, in this example, the light-emitting region 751R1 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 752a1 projected onto the light-emitting surface 751S in an XY planar view.

[0298] The light-emitting portion R2 is similar to the light-emitting portion R1. That is, in the light-emitting portion R2, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 752a2. In the light-emitting portion R2, holes supplied from the top surface 753U2 are supplied to the light-emitting layer 752a2. The electrons and holes supplied to the light-emitting layer 752a2 combine to emit light. The light emitted from the light-emitting layer 752a2 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R2. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R2, the light-emitting portion 751R2 is the portion of the light-emitting surface 751S that emits light. Therefore, in this example, the light-emitting region 751R2 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 752a2 projected onto the light-emitting surface 751S in the XY plane view.

[0299] In this way, in the semiconductor layer 750, the n-type semiconductor layer 751 can be shared to form a plurality of light emitting regions 751R1 and 751R2 on the light emitting surface 751S.

[0300] In this embodiment, the semiconductor layer 750 can be formed by using a part of the n-type semiconductor layer 751 as the connection portion R0 in the plurality of light-emitting layers 752a1, 752a2 and the plurality of p-type semiconductor layers 753a1, 753a2 of the semiconductor layer 750. Therefore, the semiconductor layer 750 can be formed in the same manner as the method for forming the light-emitting elements 150, 250 in the first embodiment, second embodiment, etc. described above.

[0301] Returning to FIG. 31, the explanation continues. The second interlayer insulating film 156 is provided to cover the planarized surface 112F, the graphene sheet 740a, and the semiconductor layer 750.

[0302] The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 includes wirings 760d1, 760d2, and 760k. The wiring 760d1 is connected to the top surface 753U1 via a connecting member 761a1. The wiring 760d2 is connected to the top surface 753U2 via a connecting member 761a2. The wiring 760k is connected to, for example, the ground line 4 of the circuit in FIG. 3.

[0303] The via 761d1 is provided to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 710d1. The via 761d1 is provided between the wiring 760d1 and the wiring 710d1 and electrically connects the wiring 760d1 and the wiring 710d1. The via 761d2 is provided to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 710d2. The via 761d2 is provided between the wiring 760d2 and the wiring 710d2 and electrically connects the wiring 760d2 and the wiring 710d2.

[0304] The via 761k is provided to penetrate the second interlayer insulating film 156 and reach the n-type semiconductor layer 751. The via 761k is located between the wiring 760k and the n-type semiconductor layer 751, and electrically connects the wiring 760k and the n-type semiconductor layer 751.

[0305] For example, transistors 103-1 and 103-2 are drive transistors for adjacent subpixels and are driven sequentially. When holes supplied from transistor 103-1 are injected into light-emitting layer 752a1 and electrons supplied from wiring 760k are injected into light-emitting layer 752a1, light-emitting layer 752a1 emits light and light is emitted from light-emitting region 751R1. When holes supplied from transistor 103-2 are injected into light-emitting layer 752a2 and electrons supplied from wiring 760k are injected into light-emitting layer 752a2, light-emitting layer 752a2 emits light and light is emitted from light-emitting region 751R2.

[0306] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the advantage of being able to shorten the time required for the transfer process for forming the semiconductor layer 750 and reduce the number of processes. Furthermore, since the connection portion R0 can be shared by multiple light-emitting portions R1 and R2, it is possible to reduce the number of vias 761k provided in the connection portion R0. Reducing the number of vias makes it possible to reduce the pitch between the light-emitting portions R1 and R2 that make up the subpixel group 720, resulting in a compact, high-resolution image display device.

[0307] In this embodiment, the emitted light from the light-emitting regions 751R1 and 751R2 must pass through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102 before being emitted to the outside. Therefore, it is conceivable that the light will spread along the path before being emitted to the outside. In this embodiment, the wiring 710f is provided along the path of the light before being emitted to the outside, thereby blocking the spreading light and preventing the light emitted from adjacent pixels from mixing. This makes it possible to narrow the pixel pitch and realize a high-quality image display device. While the above example describes a case where two light-emitting regions are provided, the number of light-emitting regions is not limited to two, and any number of light-emitting regions greater than or equal to three may be used.

[0308] (Eighth embodiment) The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0309] FIG. 33 is a block diagram illustrating an image display device according to this embodiment. FIG. 33 shows the main components of a computer display. 33, an image display device 801 includes an image display module 802. The image display module 802 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 802 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0310] The image display device 801 further includes a controller 870. The controller 870 receives control signals separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each subpixel and to control the driving order.

[0311] (Variation) FIG. 34 is a block diagram illustrating an image display device according to a modified example of this embodiment. FIG. 34 shows the configuration of a high-definition flat-screen television. As shown in Fig. 34, an image display device 901 includes an image display module 902. The image display module 902 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 901 includes a controller 970 and a frame memory 980. The controller 970 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied via a bus 940. The frame memory 980 stores one frame's worth of display data and is used for processing such as smooth video playback.

[0312] The image display device 901 has an I / O circuit 910. The I / O circuit 910 is simply represented as "I / O" in Fig. 34. The I / O circuit 910 provides an interface circuit or the like for connecting to an external terminal, device, or the like. The I / O circuit 910 includes, for example, a USB interface for connecting an external hard disk drive, an audio interface, or the like.

[0313] The image display device 901 has a receiving unit 920 and a signal processing unit 930. An antenna 922 is connected to the receiving unit 920, which separates and generates necessary signals from radio waves received by the antenna 922. The signal processing unit 930 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by the receiving unit 920 are separated by the signal processing unit 930 into image data, audio data, etc., and generated.

[0314] By configuring the receiving unit 920 and the signal processing unit 930 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for Wi-Fi, a GPS receiver, etc., other image display devices can also be used. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be used as a mobile information terminal such as a smartphone or a car navigation system.

[0315] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified version thereof or a version of another embodiment. The image display module in this embodiment and the modified version includes a large number of sub-pixels, as shown in Figures 12 and 13.

[0316] According to the embodiment described above, it is possible to realize a method for manufacturing an image display device and an image display device that shortens the transfer step of light emitting elements and improves yield.

[0317] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0318] 1,201,801,901 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20, 20a, 220, 320, 420, 520, 620 Subpixel, 22, 222 Light emitting element, 24, 224 Selection transistor, 26, 226 Drive transistor, 28, 228 Capacitor, 100 Drive circuit board, 101 Circuit, 102 Board, 102a, 102b, 106S surface, 103, 103-1, 103-2, 203 Transistor, 104, 104-1, 104-2, 204 TFT channel, 105 Insulating layer, 107, 107-1, 107-2 gate, 108 insulating film, 110 first wiring layer, 112 first interlayer insulating film, 140a graphene sheet, 150, 250, 650 light-emitting element, 151S, 253S, 651S, 751S light-emitting surface, 156 second interlayer insulating film, 160d, 160k, 230a, 260a, 470a, 470b, 560d, 760d1, 760d2, 760k wiring, 161d, 161k, 261a, 761d1, 761d2, 761k via, 180, 180a color filter, 230 third wiring layer, 470 fourth wiring layer, 720 subpixel group, 1130 transparent conductive film, 1140 Graphene layer, 1150 semiconductor layer, 1160 metal layer, 1180 reinforcing substrate, 1192 structure

Claims

1. preparing a first substrate including circuit elements formed on a first surface of the substrate, a first wiring layer connected to the circuit elements, and a first insulating film covering the circuit elements and the first wiring layer; forming a layer including graphene on the first insulating film; forming a semiconductor layer including a light-emitting layer on the graphene-containing layer; processing the semiconductor layer to form a light-emitting device including a light-emitting surface on the graphene-containing layer and a top surface opposite the light-emitting surface; forming a second insulating film covering the first insulating film, the graphene-containing layer, and the light-emitting element; forming a first via that penetrates the first insulating film and the second insulating film; forming a second wiring layer on the second insulating film; removing the substrate; forming a wavelength conversion member in place of the substrate; Equipped with The method for manufacturing an image display device, wherein the first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

2. forming a second via that penetrates the second insulating film; Furthermore, the light-emitting element includes a connection portion provided along the first surface, The method for manufacturing an image display device according to claim 1 , wherein the second via is provided between the second wiring layer and the connection portion, and electrically connects the second wiring layer and the connection portion.

3. forming a third wiring layer having light-transmitting properties on the first insulating film before forming the layer including graphene; forming a second via that penetrates the second insulating film; Furthermore, 2. The method for manufacturing an image display device according to claim 1, wherein the second via is provided between the second wiring layer and the third wiring layer to electrically connect the second wiring layer and the third wiring layer.

4. 4. The method for manufacturing an image display device according to claim 1, wherein the substrate has light-transmitting properties.

5. The method for manufacturing an image display device according to claim 4, further comprising the step of forming a wavelength conversion member on a second surface opposite to the first surface.

6. 6. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a fourth wiring layer so as to cover the top surface and the side surfaces of the light-emitting element before the step of forming the second insulating film.

7. The method for manufacturing an image display device according to claim 1 , further comprising the steps of exposing the light-emitting surface through an opening that penetrates the first insulating film, and roughening the light-emitting surface.

8. the wavelength conversion member includes a light-shielding portion and a color conversion portion, The method for manufacturing an image display device according to claim 7 , wherein the color conversion portion is formed in the opening.

9. 9. The method for manufacturing an image display device according to claim 1, wherein the step of preparing the first substrate includes a step of forming a light-shielding layer on the circuit elements.

10. 10. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer contains a gallium nitride compound semiconductor.

11. a first member having a first surface; a circuit element provided on the first surface; a first wiring layer electrically connected to the circuit element; a first insulating film covering the first surface, the circuit element, and the first wiring layer; a layer including graphene provided on the first insulating film; a light-emitting element including a light-emitting surface on the graphene-containing layer and a top surface opposite to the light-emitting surface; a second insulating film covering the first insulating film and the light emitting element; a first via provided through the first insulating film and the second insulating film; a second wiring layer provided on the second insulating film; a second via provided through the second insulating film; Equipped with the first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer; the light-emitting element includes a connection portion provided along the light-emitting surface, the second wiring layer includes a first wiring and a second wiring separated from the first wiring; the first via is provided between the first wiring and the first wiring layer, and electrically connects the first wiring and the first wiring layer; The second via is provided between the second wiring and the connection portion, and electrically connects the second wiring and the connection portion.

12. The image display device according to claim 11 , wherein the first member includes a color conversion section that converts the wavelength of light from the light emitting element and outputs the converted light.

13. a third wiring layer having optical transparency and provided on the first insulating film; a second via provided through the second insulating film; Furthermore, the second wiring layer includes a first wiring and a second wiring separated from the first wiring, the first via is provided between the first wiring and the first wiring layer, and electrically connects the first wiring and the first wiring layer; 13. The image display device according to claim 11, wherein the second via is provided between the second wiring and the third wiring layer, and electrically connects the second wiring and the third wiring layer.

14. a fourth wiring layer covering the top surface and a side surface of the light-emitting element and including a first electrode electrically connected to the top surface; The image display device according to claim 13 , wherein the first electrode is electrically connected to the first via through the first wiring.

15. a second electrode disposed across the top surface and electrically connected to the top surface; The image display device according to claim 13 , wherein the second electrode is electrically connected to the first via through the first wiring.

16. 13. The image display device according to claim 11, wherein an interior angle formed between the light emitting surface and a side surface of the light emitting element is smaller than 90 degrees.

17. 17. The image display device according to claim 11, further comprising a light-shielding layer provided between the circuit element and the light-emitting element.

18. 18. The image display device according to claim 11, wherein the light emitting element includes a gallium nitride compound semiconductor.

19. a light-transmitting member having a first surface; a plurality of transistors provided on the first surface; a first wiring layer electrically connected to the plurality of transistors; a first insulating film covering the first surface, the plurality of transistors, and the first wiring layer; a layer including graphene provided on the first insulating film; a first semiconductor layer including a light emitting surface on the graphene-containing layer, on which a plurality of light emitting regions can be formed; a plurality of light emitting layers provided on the first semiconductor layer; a plurality of second semiconductor layers provided on the plurality of light emitting layers, each second semiconductor layer having a different conductivity type from the first semiconductor layer; a second insulating film covering the first insulating film, the first semiconductor layer, the plurality of light emitting layers, and the plurality of second semiconductor layers; a plurality of first vias provided through the first insulating film and the second insulating film; a second wiring layer provided on the second insulating film; Equipped with the plurality of second semiconductor layers are separated by the second insulating film; the plurality of light-emitting layers are separated by the second insulating film; The image display device includes a plurality of first vias provided between the first wiring layer and the second wiring layer, and electrically connecting the first wiring layer and the second wiring layer.

20. a light-transmitting member having a first surface; a circuit element provided on the first surface; a first wiring layer electrically connected to the circuit element; a first insulating film covering the first surface, the circuit element, and the first wiring layer; a layer including graphene provided on the first insulating film; a plurality of light-emitting elements each including a light-emitting surface on the graphene-containing layer and a top surface opposite to the light-emitting surface; a second insulating film covering the first insulating film and the plurality of light emitting elements; a first via provided through the first insulating film and the second insulating film; a second wiring layer provided on the second insulating film; Equipped with The image display device, wherein the first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

Images