Node assembly, concept sequencer, node assembly generation program, and node assembly generation method

Abstract

A node assembly 4 is composed of all nodes 2 that are connected by one edge 3 to nodes 2 other than said nodes 2, from among nodes 2 that fired within a threshold time period from a specified time as a result of information transmission efficiency w, which indicates transmission efficiency of bit information at each edge 3, being changed in accordance with the difference between firing times at nodes 2 that connect to both ends of the edge 3. ,

Description

[Technical Field]

[0001] The disclosed technology relates to a node assembly using an artificial neural network, a concept sequencer, a node assembly generation program, and a node assembly generation method. [Background technology]

[0002] Artificial neural networks can store numerical values ​​in their parameters (see, for example, non-patent literature: Takayuki Okatani, "Deep Learning," Journal of the Institute of Image Information and Television Engineers, Vol. 68, No. 6, 2014, pp. 466-471). These parameters are parameters of a function that converts input into output, and do not represent any concept. In other words, they are not conceptual memories.

[0003] Although unrelated to artificial neural networks, memory elements used in computers can also store numerical values. Therefore, by associating numerical values ​​with concepts, concepts can be stored in memory elements. However, concepts stored in memory elements do not change. Furthermore, concepts stored in memory elements do not interact with other concepts to create new concepts, as do concepts stored by humans. Summary of the Invention [Problem to be solved by the invention]

[0004] Supervised learning in artificial neural networks can reproduce the input and output that it has been taught. Furthermore, for inputs that it has not been taught, supervised learning in artificial neural networks can search for similar inputs that it has already been taught and select the corresponding output. However, supervised learning in artificial neural networks cannot select an output if the input is not similar to the inputs that it has already been taught. Furthermore, supervised learning in artificial neural networks cannot create new outputs other than the outputs that it was originally taught.

[0005] On the other hand, reinforcement learning in artificial neural networks can find unknown inputs that maximize rewards when a reward is given. However, since rewards are given, reinforcement learning in artificial neural networks cannot create rewards by itself, nor can it find true rewards when the reward is unknown.

[0006] This is because existing artificial neural networks are unable to generate concepts on their own. This inability to generate concepts on their own also means that existing artificial neural networks cannot possess intelligence.

[0007] The disclosed technology has been made in consideration of the above points, and aims to provide a node assembly, a concept sequencer, a node assembly generation program, and a node assembly generation method that can generate concepts on their own. [Means for solving the problem]

[0008] A first aspect of the present disclosure is The method is used by a computer including an external input unit, an edge information transmission efficiency change unit, an edge selection unit, and a storage unit, It includes at least one node connected by at least one edge that carries bit information. , stored in the storage unit network A node assembly comprising: The internal state of each of the nodes is expressed by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is expressed by a potential that affects the firing state of the node and time, and the sum of input values ​​input to each of the nodes from all of the connected edges, and the external state of each of the nodes is determined to be a firing state or a non-firing state by comparing the potential with a predetermined firing threshold, The edge selection unit selects an edge from the network. Information transmission efficiency, which represents the transmission efficiency of bit information at each edge The edge information transmission efficiency change unit It changes according to the difference in firing time between both ends of the edge and each of the nodes connected to it. When the external input unit inputs bit information to the network, Among the nodes that fire within a predetermined threshold time from a specific time, all nodes that are connected to other nodes by one edge Consists ofThis is a node assembly.

[0009] A second aspect of the present disclosure is First aspect and at least one or more edges that connect the node assemblies together by connecting any of the nodes included in each of the node assemblies, a closed circuit that is generated when the external input unit continues to input bit information to the edges connected to the nodes that constitute the node assembly even after the node assembly is generated, At least one recursive circuit in which a plurality of the node assemblies are connected in a circular fashion by the edges It is a network that includes It is a conceptual sequencer.

[0010] A third aspect of the present disclosure is a node assembly generation program that causes a computer to execute a process of generating a node assembly including all nodes that are connected to other nodes other than itself by one edge among the nodes that fired within a predetermined threshold time from a specific time by expressing the internal state of each of the nodes as the sum of a predetermined function that is expressed by a value that numerically represents the internal state of the node and is expressed by a potential and time that affects the firing state of the node, and a sum of input values ​​input to each of the nodes from all of the connected edges, determining the external state of each of the nodes as fired or non-fired by comparing the potential with a predetermined firing threshold, and changing the information transmission efficiency that represents the transmission efficiency of the bit information on each of the edges according to the difference in firing time at each of the nodes connected to both ends of the edge.

[0011] A fourth aspect of the present disclosure is a network including at least one or more nodes connected by at least one or more edges that transmit bit information, wherein the internal state of each of the nodes is expressed by the sum of a predetermined function that is a value that numerically represents the internal state of the node and is expressed by potentials that affect the firing state of the node and time, and a sum of input values ​​input to each of the nodes from all of the connected edges, outside The state of each edge is determined to be an ignition state or a non-ignition state by comparing the potential with a predetermined ignition threshold. Expresses the efficiency of bit information transmission This is a node assembly generation method in which a computer executes a process to generate a node assembly including all nodes that are connected to other nodes by a single edge, among the nodes that fire within a predetermined threshold time from a specific time, by changing the information transmission efficiency according to the difference in firing time at each of the nodes connected to both ends of the edge. [Effects of the Invention]

[0012] The node assembly, concept sequencer, node assembly generation program, and node assembly generation method disclosed herein have the effect of enabling users to generate concepts on their own. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 illustrates an example of an artificial neural network. [Figure 2] FIG. 1 illustrates an example of a node assembly. [Figure 3] FIG. 2 is a diagram illustrating an example of a functional configuration of an information processing device. [Figure 4] FIG. 2 is a block diagram illustrating an example of a hardware configuration of an information processing device. [Figure 5] 10 is a flowchart illustrating an example of the flow of a node assembly generation process. [Figure 6] FIG. 1 is a diagram illustrating an example of a node assembly that configures a recursive circuit. [Figure 7] FIG. 10 is a diagram showing an example of a conceptual sequencer including node assemblies that do not constitute a recursive circuit. [Figure 8] FIG. 1 illustrates an example of a conceptual sequencer with multiple recursive circuits. [Figure 9] FIG. 1 illustrates an example network including a concept sequencer and a node assembly that accepts input from outside the network. [Figure 10] FIG. 1 illustrates an example of a concept sequencer that recalls memories without external input. [Figure 11] 10 is a flowchart showing an example of the flow of a growth process. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. Note that identical or equivalent components, parts, and processes will be given the same reference numerals throughout the drawings, and redundant description will be omitted.

[0015] Figure 1 shows an example of an artificial neural network 1 including nodes 2 and edges 3. For ease of explanation, the artificial neural network 1 will be referred to as "network 1."

[0016] In network 1, edge 3 transmits input values ​​(called "bit information") unidirectionally along the arrow direction. Node 2, which is the source of the bit information flowing through edge 3, is defined as the "origin node 2," and node 2, which receives the bit information from edge 3, is defined as the "end node 2." Furthermore, when there is no need to distinguish between the origin node 2 and the end node 2, they are referred to as "node 2."

[0017] The network 1 includes at least one or more nodes 2 connected by one or more edges 3 .

[0018] Node 2 has a potential v, a firing threshold θ, a reset value r, and a refractory period rp in its internal state, and a firing bit in its external state. The firing bit takes the value of “0” or “1.” The firing bit is an output that represents the firing state of node 2.

[0019] Edge 3 has a delay d in its internal state and an information transmission efficiency w. Also, for network 1, we define the time of the entire network 1, that is, network time t.

[0020] Here, the potential v of node 2 is a value that numerically represents the internal state of node 2 and is a value that affects the firing state of node 2. The potential v of node 2 is expressed as the sum of two terms. The first term is a predetermined function expressed by the potential v and the network time t. The second term is the sum of the bit information input to node 2 from all connected edges 3.

[0021] The internal state of node 2 is expressed, for example, by equation (1). In equation (1), "v" is the internal state of node 2, i.e., the potential of node 2, "t" is network time, and "Σw" is the sum of the products of the bit information input to each edge 3 connected to node 2 and the information transmission efficiency w of edge 3 at network time t.

[0022] (Number 1) dv / dt=Σw (1)

[0023] The internal state of node 2 can also be expressed by, for example, equations (2) and (3). "u" is a variable used only in equations (2) and (3) and is a recovery variable that recovers the potential v of node 2 that has fired. "a" is a time constant that controls how much the recovery variable u decays over time. "b" is a constant that affects the sensitivity of the recovery variable u to the internal state of node 2.

[0024] (Number 2) dv / dt=0.04v 2 +5v+140-u+Σw (2) du / dt=a(bv-u) (3)

[0025] Furthermore, the internal state of node 2 is also represented by a system of differential equations called the Hodgkin-Huxley model (e.g.,<https: / / compneuro-julia.github.io / neuron-model / hodgkin-huxley.html> reference).

[0026] In network 1, node 2 fires when the potential v of node 2 exceeds the firing threshold θ. When node 2 fires, the firing bit of node 2 becomes "1" only until a predetermined time has elapsed since node 2 fired. When node 2 fires, the potential v of node 2 is set to a reset value r, and after the predetermined time has elapsed, the firing bit of node 2 becomes "0". Once node 2 fires, it will not fire even if the potential v of node 2 exceeds the firing threshold θ until the refractory period rp has elapsed from the time node 2 fires.

[0027] The bit information that flows through edge 3 when node 2 fires is the firing bit of node 2. When the time represented by delay d has passed since the firing time when source node 2 of edge 3 fires, the firing bit arrives at destination node 2 of edge 3, and the real value of firing bit x information transmission efficiency w is input to destination node 2. In other words, information transmission efficiency w represents the transmission efficiency of bit information at each edge 3. When source node 2 is not firing, the firing bit of source node 2 is "0", so "0" is input to destination node 2.

[0028] The information transmission efficiency w of edge 3 has the property of changing depending on the firing timing of both end nodes 2 of edge 3, i.e., the difference between the firing times of the origin node 2 and the destination node 2. Furthermore, the information transmission efficiency w of edge 3 may have the property of changing depending on the instructions of the edge information transmission efficiency change unit 5A (see Figure 3), which will be explained later. The property of the information transmission efficiency w changing depending on the firing timing of both end nodes 2 is called the "plasticity of edge 3."

[0029] The change in information transmission efficiency w due to the firing timing of the end nodes 2 is determined by which of the end nodes 2 fires first, and the positive or negative sign representing the increase or decrease in information transmission efficiency w is determined by the magnitude of the difference in firing times of the end nodes 2.

[0030] When multiple nodes 2 fire by providing input to a network 1 such as that shown in Figure 1, in which nodes 2 are fully or randomly connected, the information transmission efficiency w of edge 3 is autonomously strengthened or weakened due to the plasticity of edge 3. A group of nodes that are strongly connected due to changes in the information transmission efficiency w of edge 3 is defined as a "node assembly 4." The measure for measuring the strength of the connections of a node group is time. A threshold time (e.g., 10 ms) is set as a measure for measuring the strength of the connections of a node group, and the node assembly 4 is the set of all nodes 2 that fire within the threshold time from a specific time and are connected to other nodes 2 other than themselves by a single edge 3.

[0031] FIG. 2 is a diagram showing an example of a node assembly 4. In the network 1 of FIG. 2, a set of nodes 2 connected by edges 3 that are thicker than the other edges 3 is a node assembly 4. A state in which one or more nodes 2 in the node assembly 4 are firing is expressed as "the node assembly 4 is activated." When multiple inputs are repeatedly input to the network 1, a node assembly 4 that is likely to be activated in response to a specific input is generated. The node assembly 4 generated in this way represents a concept related to the input.

[0032] FIG. 3 is a diagram showing an example of the functional configuration of an information processing device 5 that generates such a node assembly 4.

[0033] The information processing device 5 includes an edge information transmission efficiency change unit 5A, a reward evaluation unit 5B, an edge selection unit 5C, an external input unit 5D, and a storage unit 5E.

[0034] The network 1 is stored in the memory unit 5E, and the edge information transmission efficiency change unit 5A changes the information transmission efficiency w of the edge 3 selected by the edge selection unit 5C described later in accordance with the reward evaluation result evaluated by the reward evaluation unit 5B.

[0035] The reward evaluation unit 5B evaluates the degree of match between the contents of the output bit string generated by arranging firing bits representing the firing states of a predetermined number of nodes 2 included in the network 1 and the contents of the expected output bit string as a reward, and notifies the edge information transmission efficiency change unit 5A of the reward evaluation result.

[0036] The edge selection unit 5C selects an edge 3 from the network 1 whose information transmission efficiency w is to be changed by the edge information transmission efficiency change unit 5A. There are two methods for selecting edges 3 in the edge selection unit 5C. The first is a selection method in which all edges 3 included in the network 1 are selected. The second is a selection method in which edges 3 whose evaluation time at which the reward evaluation unit 5B evaluates the reward is closer to the firing time of the connected node 2 are selected preferentially. Specifically, from nodes 2 that are in an firing state at a judgment time that is a predetermined time away from the evaluation time at which the reward evaluation unit 5B evaluates the reward, all edges 3 that input bit information to each node 2 selected according to a predetermined probability are selected. The method for selecting edges 3 in the edge selection unit 5C will be explained in detail later.

[0037] The external input unit 5D inputs bit information from outside the network 1 to at least one node 2 of the network 1.

[0038] On the other hand, the node assembly 4 illustrated in FIG. 2 not only receives input but also outputs bit information to other nodes 2. Therefore, the information transmission efficiency w of the edge 3 may change depending on the input from outside the network 1 via the external input unit 5D and the input from the node assembly 4 within the network 1, and a new node assembly 4 may be generated. The newly generated node assembly 4 represents a concept that combines the concept represented by the input from outside the network 1 and a concept related to the concept represented by the node assembly 4 within the network 1. In other words, the concept represented by the newly generated node assembly 4 is a new concept that is different from both the concept represented by the input from outside the network 1 and the concept represented by the node assembly 4 within the network 1. In this way, the node assembly 4 generates its own concept.

[0039] Furthermore, after a node assembly 4 is generated, the information transmission efficiency w of the edge 3 may change due to input from outside the network 1 via the external input unit 5D and input from other node assemblies 4 within the network 1, i.e., existing node assemblies 4, and the number of nodes included in the existing node assembly 4 may change. Such events represent the expansion or contraction of the concept of the existing node assembly 4. The expansion or contraction of concepts helps to change concepts and create new concepts.

[0040] When network 1 includes a recursive circuit, node 2 may continue to fire only with input from within network 1, without external input. Here, a "recursive circuit" refers to a closed circuit formed by nodes 2 connected in a circular fashion by edges 3. A state in which node 2 continues to fire without external input is referred to as "network 1 running on its own." There may be multiple paths by which node 2 continues to fire. As network 1 continues to run on its own, the activity of multiple node assemblies 4 within network 1, such as the first node assembly 4 and the second node assembly 4, may change the information transmission efficiency w of edge 3, resulting in the creation of a new node assembly 4 within network 1. The concept represented by this new node assembly 4 is a new concept different from both the concept represented by the first node assembly 4 and the concept represented by the second node assembly 4. In this way, node assembly 4 generates a new concept without external input from network 1. This mechanism works similarly to how the human brain can make new discoveries and inventions while asleep.

[0041] As network 1 continues to operate independently, the information transmission efficiency w of edges 3 connecting nodes 2 may change, and the boundaries of existing node assemblies 4 may change. This situation indicates that the concepts represented by existing node assemblies 4 expand or contract. The expansion or contraction of concepts helps to change concepts and generate new concepts. Therefore, concepts expand or contract without input from outside network 1, and new concepts are generated.

[0042] Furthermore, if we continue to provide input to Network 1 and allow it to run independently during periods when there is no input, it is probabilistic that Network 1 will begin to acquire the intelligence to acquire new concepts. This is because the history of evolution of life has proven that if we conduct a large number of trials on Network 1, we will obtain Network 1 that has acquired intelligence in some of the trials. To increase the probability that Network 1 will be intelligent, we can, for example, change the information transmission efficiency w of Edge 3 using rewards. For example, by increasing the information transmission efficiency w of Edge 3 using rewards, it becomes more likely that Node Assembly 4 will be generated in a direction that increases the reward. When the probability of generating Node Assembly 4 increases, the probability of concepts emerging increases, and so does the probability of complex relationships between concepts emerging. In other words, the probability that Network 1 will be intelligent increases.

[0043] In known reinforcement learning artificial neural networks, after the reward and input generation rules are taught to the reinforcement learning artificial neural network, it operates without any input from outside the network 1. Therefore, like the node assembly 4 of the present disclosure, the reinforcement learning artificial neural network appears to operate without any input from outside the network 1. However, the reinforcement learning artificial neural network can only perform operations that maximize the taught reward. Furthermore, the reinforcement learning artificial neural network cannot create new inputs that deviate from the input generation rules. In other words, the reinforcement learning artificial neural network cannot generate rewards based on different definitions, nor can it come up with new ideas that go beyond the input generation rules, i.e., discover solutions outside the assumed solution space. Therefore, the node assembly 4 of the present disclosure differs from known reinforcement learning artificial neural networks in that it can define new rewards and discover solutions that are not bound by the existing solution space.

[0044] Next, an example of a hardware configuration of the information processing device 5 of the present disclosure will be described. Fig. 4 is a block diagram showing an example of a hardware configuration of the information processing device 5. As shown in Fig. 4, the information processing device 5 is configured using a computer 10, and includes a CPU (Central Processing Unit) 11, which is an example of a processor, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a non-volatile memory 14, and an input / output interface (I / O) 15. The CPU 11, ROM 12, RAM 13, non-volatile memory 14, and I / O 15 are connected to each other via a bus 16.

[0045] The nonvolatile memory 14 is an example of a storage device that maintains stored information even if the power supplied to the nonvolatile memory 14 is cut off, and is, for example, a semiconductor memory or a hard disk. The nonvolatile memory 14 stores, for example, the network 1.

[0046] To the I / O 15, for example, a communication unit 17, an input unit 18, and a display unit 19 are connected.

[0047] The communication unit 17 is connected to a communication line and has a communication protocol for performing data communication with an external device (not shown). For data communication, a wired communication standard such as Ethernet (registered trademark) or FDDI, or a wireless communication standard such as 4G, 5G, or Wi-Fi (registered trademark) is used.

[0048] The input unit 18 is an example of a unit that receives user operations and notifies the CPU 11 of the operations, and includes, for example, a button, a touch panel, a keyboard, a mouse, a pointing device, and the like.

[0049] The display unit 19 is an example of a unit that visually displays information processed by the CPU 11, and includes, for example, a liquid crystal display and an organic EL (Electro Luminescence) display.

[0050] The communication unit 17, the input unit 18, and the display unit 19 do not necessarily need to be connected to the I / O 15, but are connected to the I / O 15 as needed.

[0051] Next, the operation of the node assembly 4 generated by the information processing device 5 will be described.

[0052] FIG. 5 is a flowchart showing an example of the flow of the generation process of the node assembly 4.

[0053] A node assembly generation program that defines the process for generating the node assembly 4 is stored in advance in, for example, the ROM 12 of the information processing device 5. The CPU 11 of the information processing device 5 reads the node assembly generation program stored in the ROM 12 and executes the process for generating the node assembly 4. It is assumed that the non-volatile memory 14 stores the network 1 before the node assembly 4 is generated, as shown in FIG. 1. For ease of explanation, input from outside the network 1 will be referred to as an "external input."

[0054] When bit information is input to edge 3 of network 1 from external input unit 5D, the bit information flows to edge 3, and node 2 fires accordingly.

[0055] Therefore, in step S10, the CPU 11 updates the information transmission efficiency w of each edge 3 according to the firing order of the end nodes 2 and the magnitude of the difference in firing time between the end nodes 2.

[0056] In this way, when both end nodes 2 connected by an edge 3 fire, the information transmission efficiency w of the edge 3 changes. Changes in the information transmission efficiency w include changes in which the information transmission efficiency w increases and changes in which the information transmission efficiency w decreases. As the number of edges 3 with increased information transmission efficiency w increases, nodes 2 that fire in sync become more likely to occur. Here, "nodes 2 firing in sync" means that multiple nodes 2 fire within a threshold time from a specific time. As already explained, nodes 2 that fire in sync form a node assembly 4.

[0057] Therefore, in step S20, the CPU 11 determines whether or not a node assembly 4 has been generated in the network 1. If a node assembly 4 has not been generated, the CPU 11 repeatedly executes the determination process of step S20 while repeatedly inputting bit information into the network 1 from within and outside the network 1, thereby monitoring the generation status of the node assembly 4. On the other hand, if a node assembly 4 has been generated, the process proceeds to step S30.

[0058] In step S30, the CPU 11 determines whether or not an end instruction has been received from the user via, for example, the input unit 18. If an end instruction has been received, the process of generating the node assembly 4 shown in Fig. 5 ends. In this case, the node assembly 4 representing the concept related to the input as shown in Fig. 2 is obtained.

[0059] On the other hand, if it is determined in the determination process of step S30 that an end instruction has not been received from the user, the process proceeds to step S40.

[0060] Further bit information is input from within and outside network 1 to edges 3 connected to nodes 2 included in node assembly 4, and as network 1 progresses in learning, a node assembly 4 that constitutes a recursive circuit may be generated.

[0061] 6 is a diagram showing an example of node assemblies 4 that make up a recursive circuit. Each node assembly 4 is connected by an edge 3. The edge 3 connecting two node assemblies 4 does not necessarily have to be one, but can be multiple. There are no restrictions on the starting node 2 of one node assembly 4 and the ending node 2 of the other node assembly 4 connected by the edge 3, and any node 2 within each node assembly 4 can be connected.

[0062] In this way, a network 1 that includes multiple node assemblies 4 and at least one edge 3 that connects the node assemblies 4 to each other by connecting any of the nodes 2 included in the node assemblies 4, and that forms at least one recursive circuit in which the multiple node assemblies 4 are connected in a circular manner by the edges 3, is called a ``concept sequencer 6.''

[0063] The concept sequencer 6 may include a node assembly 4 that does not constitute a recursive circuit.

[0064] 7 is a diagram showing an example of a conceptual sequencer 6 including a node assembly 4 that does not constitute a recursive circuit. In FIG. 7, a node assembly 4A is a node assembly 4 that does not constitute a recursive circuit.

[0065] 5, the CPU 11 determines whether or not such a concept sequencer 6 has been generated. If a concept sequencer 6 has not been generated, the CPU 11 repeatedly executes the determination process of step S40 while repeatedly inputting bit information into the network 1 from within the network 1 and from outside the network 1, thereby monitoring the generation status of the concept sequencer 6. On the other hand, if a concept sequencer 6 has been generated, the CPU 11 proceeds to step S50.

[0066] In step S50, the CPU 11 determines whether or not an end instruction has been received from the user via, for example, the input unit 18. If an end instruction has been received, the process of generating the node assembly 4 shown in Fig. 5 ends. In this case, a concept sequencer 6 is obtained that changes the concept represented by the node assembly 4 and generates a new concept.

[0067] On the other hand, if it is determined in the determination process of step S50 that an end instruction has not been received from the user, the process proceeds to step S60.

[0068] Naturally, not all nodes 2 in network 1 are necessarily included in any node assembly 4, and so there are nodes 2 around the concept sequencer 6 that do not constitute a node assembly 4. Therefore, as bit information is repeatedly input to network 1 from within and outside network 1, and nodes 2 that were not previously included in node assembly 4 begin to constitute node assembly 4, a new recursive circuit may be generated.

[0069] 8 is a diagram showing an example of a concept sequencer 6 including a plurality of recursive circuits. The example of the concept sequencer 6 shown in FIG. 8 includes two recursive circuits, a recursive circuit A and a recursive circuit B.

[0070] In step S60 of Fig. 5, the CPU 11 determines whether a concept sequencer 6 including multiple recursive circuits has been generated. If a concept sequencer 6 including multiple recursive circuits has not been generated, the CPU 11 repeatedly executes the determination process of step S60 while repeatedly inputting bit information into the network 1 from within and outside the network 1, thereby monitoring the generation status of the concept sequencer 6 including multiple recursive circuits. On the other hand, if a concept sequencer 6 including multiple recursive circuits has been generated, the CPU 11 terminates the generation process of the node assembly 4 shown in Fig. 5. In this case, a concept sequencer 6 is obtained that generates a new concept different from the concept sequencer 6 including one recursive circuit shown in Figs. 6 and 7.

[0071] According to this process of generating node assemblies 4, multiple concept sequencers 6 may be generated within the network 1. The generated multiple concept sequencers 6 are connected to each other by edges 3 and exchange bit information. External inputs are also input to the concept sequencer 6 on an irregular or regular basis. Therefore, these inputs cause complex changes in the information transmission efficiency w of the edges 3 included in the concept sequencer 6. As a result, the node assembly 4 expands, contracts, or splits into multiple pieces, generating new paths for the concept sequencer 6. As concepts expand and contract in the concept sequencer 6, the concept sequencer 6 grows autonomously and new concepts are created. In other words, the concept sequencer 6 can be a source of advanced intelligence.

[0072] The concept sequencer 6 thus generated can recall memories without external input, that is, it can recall memories.

[0073] Figure 9 is a diagram showing an example of a network 1 including at least one concept sequencer 6, a node assembly 4C that accepts input from any one of the node assemblies 4 (referred to as "node assembly 4B") that constitute the concept sequencer 6, and an edge 3 that inputs external input to the node assembly 4C.

[0074] In network 1, assume that an external input and an input from node assembly 4B are input to node assembly 4C, activating node assembly 4C. In this case, node assembly 4C memorizes the memory of the external input. After this, network 1 operates and the information transmission efficiency w of edge 3 changes. Eventually, the information transmission efficiency w of edge 3 within node assembly 4C is strengthened, and node assembly 4C becomes activated by input from node assembly 4B alone, without any external input. In this way, memory recall without external input is achieved in node assembly 4C.

[0075] Figure 10 is a diagram showing an example of a concept sequencer 6 that recalls memories without external input for the network 1 shown in Figure 9. The concept sequencer 6 shown in Figure 10 includes a node assembly 4C that recalls memories only with input from a node assembly 4B.

[0076] Next, it will be explained how the concepts stored by the node assembly 4 change due to a change in the threshold time that affects the generation of the node assembly 4.

[0077] For example, if a node assembly 4 (referred to as "former node assembly 4") is generated when the threshold time is set to 10 ms, and a node assembly 4 (referred to as "latter node assembly 4") is generated when the threshold time is set to 15 ms, the number of nodes constituting the latter node assembly 4 will be greater. While it is possible that the number of nodes constituting each of the former node assembly 4 and the latter node assembly 4 will be the same, it is assumed here that the number of nodes constituting the latter node assembly 4 is greater than the number of nodes constituting the former node assembly 4. Therefore, for example, the former node assembly 4 represents the concept of "sea fish," and the latter node assembly 4 represents the concept of "sea creatures," which is a broader concept than "sea fish."

[0078] When Network 1 is operational, there is no need to fix the threshold time that affects the generation of Node Assembly 4. There are situations where the concept of "ocean fish" produces useful output in one situation, and the concept of "ocean creature" produces useful output in another situation. In Concept Sequencer 6, there is no restriction that only one concept can be used; both concepts can be used. In this case, Network 1 itself is not aware of the switching of the threshold time, and CPU 11 virtually uses multiple threshold times, creating a state in which Concept Sequencer 6 is simultaneously recalling multiple concepts.

[0079] Next, a growth process that encourages the growth of the node assembly 4 and the concept sequencer 6 by providing rewards to the network 1 will be described.

[0080] FIG. 11 is a flowchart showing an example of the flow of the growth process.

[0081] A node assembly generation program that defines the growth process is stored in advance in, for example, the ROM 12 of the information processing device 5. The CPU 11 of the information processing device 5 reads the node assembly generation program stored in the ROM 12 and executes the growth process.

[0082] It is assumed that the non-volatile memory 14 stores a network 1. The network 1 may include at least one of a node assembly 4 and a concept sequencer 6. An external input may also be input to the network 1. Specifically, when the network 1 includes a node assembly 4, an external input may be input to an edge 3 connected to a node 2 included in the node assembly 4.

[0083] First, in step S100, the CPU 11 generates an output bit string, which is a bit string in which firing bits representing firing states in a predetermined plurality of nodes 2 (also called a "node group") included in the network 1 are arranged.

[0084] In step S110, CPU 11 evaluates the degree of match between the content of a preset expected output bit string and the content of the output bit string generated in step S100 as a reward. In this case, CPU 11 increases the value of the reward, for example, as the degree of match between the content of the output bit string and the content of the expected output bit string increases. Examples of the content of the expected output bit string include maximizing and minimizing the physical quantity represented by the output bit string, and maximizing and minimizing the amount of information represented by the output bit string.

[0085] In step S120, the CPU 11 selects an edge 3 that changes the information transmission efficiency w from within the network 1. As already explained, there are two methods for selecting the edge 3.

[0086] The first is a selection method for selecting all edges 3 included in the network 1. The second is a selection method for selecting all edges 3 that input bit information to each node 2 selected according to a predetermined probability from nodes 2 that are in an firing state at a judgment time that is a predetermined time away from the evaluation time of the reward evaluated by the processing of step S110. The CPU 11 selects edges 3 from the network 1 that change the information transmission efficiency w using the selection method selected by the user.

[0087] The second selection method will be described in detail. Assume that the CPU 11 evaluates the reward at network time t through the process of step S110. Note that the granularity Δt, which represents the minimum time measurement capability of the CPU 11, is predetermined. There are no restrictions on the time granularity Δt, but it may be 1 ms, for example. Furthermore, the variable n is a natural number, and the function f(x) is an arbitrary monotonically decreasing real function that takes a value between 0 and 100, with the natural number x as an explanatory variable. The CPU 11 randomly selects f(n) percent of the nodes 2 that fired at network time t-nΔt. Then, the CPU 11 selects all edges 3 that input bit information to each of the selected nodes 2. The network time t-nΔt is an example of a judgment time, and for example, f(n) percent of the nodes 2 that fired at network time t+nΔt may be randomly selected.

[0088] In step S130, the CPU 11 updates the information transmission efficiency w of the edge 3 selected from the network 1 by the process of step S120, depending on the evaluation result of the reward evaluated by the process of step S110. Specifically, the CPU 11 increases the information transmission efficiency w of the selected edge 3 as the reward value increases, and decreases the information transmission efficiency w of the selected edge 3 as the reward value decreases.

[0089] This completes the growth process shown in Fig. 11. Through the growth process, the node assembly 4 and the concept sequencer 6 grow so as to increase the reward.

[0090] In this way, the node assembly 4 and concept sequencer 6 of the present disclosure store a concept in response to an input, and generate a new concept by changing the stored concept. Furthermore, the node assembly 4 and concept sequencer 6 of the present disclosure can generate a new concept by changing the stored concept even without an external input.

[0091] The above describes one embodiment of the node assembly 4 and the concept sequencer 6. However, the disclosed method for generating the node assembly 4 and the concept sequencer 6 is merely an example and is not limited to the scope of the embodiment. Various modifications or improvements can be made to the embodiment without departing from the spirit of the present disclosure, and embodiments incorporating such modifications or improvements are also included in the technical scope of the disclosure. For example, the internal processing order of each process shown in Figures 5 and 11 may be changed without departing from the spirit of the present disclosure.

[0092] In addition, in the present disclosure, as an example, a form in which each process shown in Figures 5 and 11 is realized by software has been described. However, processes equivalent to the flowcharts of each process shown in Figures 5 and 11 may be implemented in, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a PLD (Programmable Logic Device) and processed by hardware. In this case, the processing speed can be increased compared to when each process is realized by software.

[0093] In this way, the CPU 11 of the information processing device 5 may be replaced with a dedicated processor specialized for specific processing, such as an ASIC, FPGA, PLD, GPU (Graphics Processing Unit), or FPU (Floating Point Unit).

[0094] The generation process and growth process of the node assembly 4 may be performed by one CPU 11, or may be performed by a combination of two or more processors of the same or different types, such as multiple CPUs 11 or a combination of a CPU 11 and an FPGA.

[0095] Furthermore, the generation process and growth process of the node assembly 4 may be realized by the cooperation of processors located in physically separate locations connected via the Internet, for example.

[0096] Furthermore, in the embodiment, an example has been described in which the node assembly generation program is stored in the ROM 12 of the information processing device 5, but the storage location of the node assembly generation program is not limited to the ROM 12. The node assembly generation program of the present disclosure can also be provided in a form recorded on a storage medium readable by the computer 10. For example, the node assembly generation program may be provided in a form recorded on an optical disc such as a CD-ROM (Compact Disk Read Only Memory) or a DVD-ROM (Digital Versatile Disk Read Only Memory). Furthermore, the node assembly generation program may be provided in a form recorded on a portable semiconductor memory such as a USB (Universal Serial Bus) memory or a memory card.

[0097] ROM 12, non-volatile memory 14, CD-ROM, DVD-ROM, USB, and memory cards are examples of non-transitory storage media.

[0098] Furthermore, the information processing device 5 may download a node assembly generation program from an external device via the communication unit 17 and store the downloaded node assembly generation program in, for example, the non-volatile memory 14. In this case, the information processing device 5 reads the node assembly generation program downloaded from the external device and executes the generation process and growth process of the node assembly 4.

Claims

1. A node assembly used by a computer having an external input unit, an edge information transmission efficiency change unit, an edge selection unit, and a memory unit, the node assembly comprising a network stored in the memory unit, the network including at least one or more nodes connected by at least one or more edges that transmit bit information, the internal state of each of the nodes is expressed by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is expressed by a potential that affects the firing state of the node and time, and the sum of input values ​​input to each of the nodes from all of the connected edges; The external state of each of the nodes is determined to be a firing state or a non-firing state by comparing the potential with a predetermined firing threshold; When the external input unit inputs bit information to the network in which the edge selection unit changes the information transmission efficiency representing the transmission efficiency of bit information at each edge selected from the network by the edge information transmission efficiency change unit in accordance with the difference in firing time at each node connected to both ends of the edge, the network is configured of all nodes that are connected to other nodes other than itself by one edge among the nodes that have fired within a predetermined threshold time from a specific time. Node assembly.

2. a plurality of the node assemblies according to claim 1; and at least one or more of the edges connecting the node assemblies together by connecting any of the nodes included in each of the node assemblies; A closed circuit is generated when the external input unit continues to input bit information to the edges connected to the nodes that make up the node assembly even after the node assembly is generated, and the network includes at least one recursive circuit in which a plurality of the node assemblies are connected in a circular fashion by the edges. Concept sequencer.

3. The computer further includes a reward evaluation unit, the reward evaluation unit evaluates, as a reward, a degree of match between a content of a bit string generated by arranging outputs representing firing states of a predetermined number of the nodes included in the network and an expected content; The edge information transmission efficiency change unit updates the information transmission efficiency of the edge selected in advance by the edge selection unit from the network in accordance with the evaluation result of the reward.

3. The concept sequencer of claim 2.

4. The edge selection unit selects, as the edge to be subject to change in information transmission efficiency, any of all the edges included in the network or all the edges that input bit information to each of the nodes selected according to a predetermined probability from the nodes that are in an ignition state at a judgment time that is a predetermined time away from the evaluation time at which the reward is evaluated.

4. The concept sequencer of claim 3.

5. In a network including at least one node connected by at least one edge carrying bit information, The internal state of each of the nodes is represented by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is represented by potentials that affect the firing state of the node and time, and the sum of input values ​​input to each of the nodes from all of the connected edges; determining an external state of each of the nodes as a firing state or a non-firing state by comparing the potential with a predetermined firing threshold; The information transmission efficiency, which indicates the transmission efficiency of bit information at each edge, is changed according to the difference in firing time at each node connected to both ends of the edge, and the computer is caused to execute a process of generating a node assembly including all nodes that are connected to other nodes other than itself by one edge, among the nodes that have fired within a predetermined threshold time from a specific time. Node assembly generation program.

6. In a network including at least one node connected by at least one edge carrying bit information, The internal state of each of the nodes is represented by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is represented by potentials that affect the firing state of the node and time, and the sum of input values ​​input to each of the nodes from all of the connected edges; determining an external state of each of the nodes as a firing state or a non-firing state by comparing the potential with a predetermined firing threshold; The information transmission efficiency, which indicates the transmission efficiency of bit information on each edge, is changed according to the difference in firing time between each of the nodes connected to both ends of the edge, and a process is executed by the computer to generate a node assembly including all nodes that are connected to other nodes other than itself by one edge among the nodes that have fired within a predetermined threshold time from a specific time. Node assembly generation method.

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