Photoelectric assembly, light source pool, photoelectric switching device, and control method for photoelectric assembly

Abstract

The present application relates to the field of optical communication, and discloses an opto-electric assembly, a light source pool, an opto-electric switching device, and a control method for the opto-electric assembly to improve the efficiency of the opto-electric assembly. The opto-electric assembly includes a voltage conversion circuit, an opto-electric semiconductor device, an opto-electric detection circuit, and a controller. The voltage conversion circuit is configured to provide a bias voltage to the opto-electric semiconductor device, and adjust the output optical power output by the opto-electric semiconductor device by changing the bias voltage. The differential resistance value Rdiff of the opto-electric semiconductor device within the range of the target optical power satisfies 0.1Ω≦Rdiff≦50Ω, and the differential resistance value is a ratio of the voltage fluctuation to the current fluctuation corresponding to the voltage fluctuation. The opto-electric detection circuit is configured to detect the output optical power output by the opto-electric semiconductor device and output a detection signal to the controller. The controller is configured to determine a control signal based on the detection signal, and output the control signal to the voltage conversion circuit, and the control signal is used to adjust the bias voltage.

Description

[Technical Field]

[0001] The present application relates to the field of optical communications, and in particular to an opto-electrical assembly, a light source pool, an opto-electrical switching device, and a control method for the opto-electrical assembly. [Background technology]

[0002] The optical power output by an opto-electrical semiconductor device may be excessively large or small. For example, the output optical power may decrease due to device aging or an increase in ambient temperature. In order to stabilize the optical power output by the opto-electrical semiconductor device within a preset range, a driving circuit may be added to the opto-electrical semiconductor device to form an opto-electrical assembly, so that the opto-electrical assembly can adjust the optical power output by the opto-electrical semiconductor device to complete an automatic power control (APC) function.

[0003] However, current optoelectronic assemblies use adjustable current sources to regulate the optical power output by optoelectronic semiconductor devices, resulting in low efficiency. Summary of the Invention

[0004] SUMMARY OF THE INVENTION Embodiments of the present application provide an opto-electric assembly, a light source pool, an opto-electric switching device, and a control method for the opto-electric assembly to improve the efficiency of the opto-electric assembly.

[0005] In order to achieve the above objectives, the following technical solutions are used in the embodiments of the present application.

[0006] According to a first aspect, an optoelectronic assembly is provided, including a voltage conversion circuit, an optoelectronic semiconductor device, an optoelectronic detection circuit, and a controller. The voltage conversion circuit is configured to provide a bias voltage to the optoelectronic semiconductor device and adjust the output optical power output by the optoelectronic semiconductor device by varying the bias voltage, where a differential resistance value Rdiff of the optoelectronic semiconductor device within a target optical power range satisfies 0.1 Ω≦Rdiff≦50 Ω, where the differential resistance value is the ratio of a voltage fluctuation to a current fluctuation corresponding to the voltage fluctuation. The optoelectronic detection circuit is configured to detect the output optical power output by the optoelectronic semiconductor device and output a detection signal to the controller. The controller is configured to determine a control signal based on the detection signal and output the control signal to the voltage conversion circuit, where the control signal is used to adjust the bias voltage. The target optical power is typically determined based on the optical power budget range of an optical link in a system in which the optoelectronic assembly, light source pool, or optoelectronic switching device is installed to ensure that the system can operate normally with a bit error rate less than a specific index. In this application, the optoelectronic assembly includes a load link and a feedback link. The load link serves as a load for the voltage conversion circuit and includes a voltage conversion circuit and an opto-electrical semiconductor device. The feedback link includes an opto-electrical detection circuit and a controller. The controller does not need to receive current sampling information from the load link. The bias voltage can be adjusted based on the output signal of the opto-electrical detection circuit.

[0007] In the opto-electrical assembly provided in this embodiment of the present application, the voltage conversion circuit provides a bias voltage to the opto-electrical semiconductor device to adjust the output optical power output by the opto-electrical semiconductor device. The opto-electrical detection circuit receives the light output by the opto-electrical semiconductor device, detects the output optical power output by the opto-electrical semiconductor device, and outputs a detection signal to the controller. The controller can determine a control signal to be used to adjust the bias voltage based on the detection signal and send the control signal to the voltage conversion circuit. No separate detection circuit needs to be coupled between the voltage conversion circuit and the opto-electrical semiconductor device, and additional power output by the voltage conversion circuit is not consumed; most of the power output by the voltage conversion circuit is converted into the output optical power output by the opto-electrical semiconductor device. This can therefore improve the efficiency of the opto-electrical assembly.

[0008] The differential resistance Rdiff of the optoelectronic semiconductor device within the target optical power range satisfies the requirement of 0.1Ω≦Rdiff≦50Ω mainly for the following reasons.

[0009] When the differential resistance Rdiff of an optoelectronic semiconductor device within the target optical power range is excessively large, the optoelectronic semiconductor device needs to input a large bias voltage fluctuation to allow the equivalent current of the optoelectronic semiconductor device to generate a small current fluctuation. In other words, when the bias voltage input to the optoelectronic semiconductor device has a large fluctuation, the fluctuation of the equivalent current flowing through the optoelectronic semiconductor device is small, and correspondingly, the carrier concentration fluctuation is small, which is insufficient to effectively change the output optical power output by the optoelectronic semiconductor device. For example, assume that the differential resistance Rdiff = 100 Ω. A voltage fluctuation of 100 mV is required to generate a current fluctuation of 1 mA, which usually corresponds to a state before the turn-on threshold of the optoelectronic semiconductor device is reached and cannot be used for normal operation of an automatic power control (APC) loop. Even if the optoelectronic semiconductor device is in a good lasing state above the turn-on threshold at this time, a voltage fluctuation of 1 V is required to realize a current fluctuation of 10 mA for such an optoelectronic semiconductor device. In practical application, it is difficult to apply due to limitations in the voltage output capacity and voltage conversion efficiency of the voltage conversion circuit.

[0010] When the differential resistance Rdiff of an optoelectronic semiconductor device within a target optical power range is excessively small, a small bias voltage fluctuation input to the optoelectronic semiconductor device can cause the current in the optoelectronic semiconductor device to generate large current fluctuations, resulting in excessively large carrier concentration fluctuations. The output optical power output by the optoelectronic semiconductor device can change significantly, falling into a range where the optical power is excessively large or excessively small, or falling into the roll-off behavior of the optoelectronic semiconductor device (i.e., the output optical power decreases with increasing injection current). Therefore, it is difficult to apply APC. For example, assume that the differential resistance Rdiff of an optoelectronic semiconductor device within a target optical power range is 0.01 Ω. When the input voltage fluctuation is 1 mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device is 100 mA. This is unacceptable for the feedback regulation of the APC loop.

[0011] The optoelectronic semiconductor device in the embodiments of the present application is a light emitting device made from semiconductor materials, and includes, for example, a light source (e.g., a laser diode (LD), a laser, or a LIDAR) or a semiconductor optical amplifier (SOA).

[0012] The bias adjustment circuit in this embodiment of the present application is a circuit, for example, an adjustable voltage source or an adjustable current source, configured to adjust the bias voltage or bias current of an opto-electrical semiconductor device.

[0013] In this embodiment of the present application, the voltage conversion circuit replaces the adjustable current source to provide a bias voltage to the optoelectronic semiconductor device. Instead of collecting the current of the load link, only the output optical power output by the optoelectronic assembly is collected as feedback to control the bias voltage output by the voltage conversion circuit. Therefore, linear control is implemented, and the control logic is simple. Compared with the conventional technology in which an adjustable current source provides a drive current to the optoelectronic semiconductor device, in this technology, the voltage conversion circuit provides the bias voltage to the optoelectronic semiconductor device. This can improve the conversion efficiency. This is because the solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. For example, the optoelectronic assembly can be used as an externally modulated light source (i.e., a light source separated from the optical modulator) or as an optical amplifier. The optoelectronic assembly, light source pool, or optoelectronic switching device needs to output light to multiple silicon photonic links, has a high output optical power of up to approximately 100 mW, and requires a high carrier density, i.e., a high drive current needs to be injected. However, an adjustable current source provides a drive current to the optoelectronic semiconductor device. As a result, a larger drive current results in a larger additional voltage drop generated by the current sampling circuit and a lower conversion efficiency of the entire optoelectronic assembly. A voltage conversion circuit (e.g., a direct current-direct current (DC-DC) conversion circuit) provides a bias voltage to the optoelectronic semiconductor device. Essentially, voltage conversion is implemented through the charging and discharging of high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop occurs, and the conversion efficiency can reach 90% or even 93%. In addition, no operational amplifier is required in an optoelectronic assembly based on an adjustable current source. This can therefore reduce the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization.

[0014] In a possible implementation, the optoelectronic assembly can be an externally modulated light source (i.e., a light source separate from the optical modulator) or an optical amplifier. The optoelectronic assembly can be used as a device requiring high power and high drive current, such as an externally modulated light source or an optical amplifier.

[0015] In a possible implementation, the optoelectronic semiconductor device is a light source, and the resistance of the light source is less than or equal to 60 Ω within the range of the target optical power.

[0016] In a possible implementation, the opto-electrical semiconductor device is an optical amplifier, the resistance of which is less than or equal to 60 Ω within the range of the target optical power.

[0017] When the resistance value of the optoelectronic semiconductor device is small, it indicates that the optoelectronic semiconductor device is well turned on and enters a good lasing state. In this case, the current-voltage relationship curve of the optoelectronic semiconductor device changes smoothly and has an obvious linear characteristic. The differential resistance value of the optoelectronic semiconductor device is also reasonable. A change in the bias voltage of the optoelectronic semiconductor device will cause a linear change in the corresponding current of the optoelectronic semiconductor device, which will then cause a linear change in the carrier concentration of the optoelectronic semiconductor device. This can linearly and effectively change the output optical power output by the optoelectronic semiconductor device. Conversely, when the resistance value of the optoelectronic semiconductor device is large, it indicates that the optoelectronic semiconductor device is in a state close to threshold. In this case, a change in the bias voltage of the optoelectronic semiconductor device will cause a nonlinear change in the corresponding current of the optoelectronic semiconductor device, which will then cause a nonlinear change in the carrier concentration of the optoelectronic semiconductor device. It is difficult to linearly and effectively change the output optical power output by the optoelectronic semiconductor device.

[0018] In a possible implementation, the voltage conversion circuit is a unique bias adjustment circuit for the optoelectronic semiconductor device. Specifically, the output optical power of the optoelectronic semiconductor device is controlled solely by the bias voltage output by the voltage conversion circuit, and no adjustable current source or the like is required to provide a drive current.

[0019] In a possible implementation, the bit width of the digital signal processed by the controller is greater than or equal to 6 bits. The controller can be a micro-control unit (MCU), a field-programmable gate array (FPGA), etc.

[0020] In this application, the bit width of the digital signal processed by the controller is required to be at least 6 bits, and the voltage fluctuation corresponding to the least significant bit satisfies the requirement for fine adjustment of the bias voltage output by the voltage conversion circuit, thereby enabling accurate control of the bias voltage output by the voltage conversion circuit. If the digital signal processed by the controller has only 4 bits, for example, if the controller's internal reference voltage of 2.5V corresponds to the maximum value of a 4-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller is 2.5V / 2^4 ≒ 156 mV. This voltage adjustment precision is unacceptable. If the bit width of the digital signal processed by the controller is 6 bits, for example, if the controller's internal reference voltage of 2.5V corresponds to the maximum value of a 6-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller is 2.5V / 2^6 ≒ 39 mV. Even if the precision of the bias voltage output by the voltage conversion circuit is the same as the voltage fluctuation of 39 mV corresponding to the least significant bit of the control signal Z, when the differential resistance value Rdiff of the optoelectronic semiconductor device within the target optical power range is 10 Ω and the bias voltage fluctuation output by the voltage conversion circuit is 39 mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device is 3.9 mA. This may be considered a large equivalent adjustment current step in APC loop control, but it is still acceptable. Furthermore, if the bit width of the digital signal processed by the controller is 8 bits, for example, if the internal reference voltage of the controller is 2.5 V corresponding to the maximum value of an 8-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller is 2.5 V / 2^8 ≒ 9.8 mV. Even if the precision of the bias voltage output by the voltage conversion circuit is the same as the voltage variation of 9.8 mV corresponding to the least significant bit of the control signal Z, when the differential resistance value Rdiff of the optoelectronic semiconductor device within the target optical power range is 10 Ω and the bias voltage variation output by the voltage conversion circuit is 9.8 mV, the current variation of the current flowing through the optoelectronic semiconductor device is 0.98 mA.This may be considered as a case where the equivalent regulating current step is small in the APC loop control, which is acceptable.

[0021] In a possible implementation, the controller is further configured to enable or disable the voltage conversion circuit.

[0022] When the controller is initialized, the voltage conversion circuit is first disabled, and then the voltage conversion circuit is enabled after the controller outputs a control signal to the voltage conversion circuit. Alternatively, in the controller initialization process, the voltage conversion circuit can be disabled based on a fixed high / low level as an input or through another logic gate circuit. Alternatively, in the controller initialization process, the voltage conversion circuit can be enabled through a soft-start circuit to turn on the optoelectronic semiconductor device. In this way, the optoelectronic semiconductor device can be prevented from burning out due to an unstable control signal in the initialization process and an excessively large bias voltage output by the voltage conversion circuit. Otherwise, if the voltage conversion circuit is enabled before the controller outputs the control signal, the bias voltage output by the voltage conversion circuit will not be controlled and may therefore become excessively large. As a result, the optoelectronic semiconductor device in the load link will burn out. In addition, these methods can be combined.

[0023] In a possible implementation, the controller is configured to obtain load link information and determine the control signal based on the load link information and the detection signal, where the load link information includes a value of the bias voltage.

[0024] When the load link information indicates the actual value of the bias voltage, the deviation between the theoretical value and the actual value of the bias voltage caused by device parameter deviations and fluctuations in the feedback network can be eliminated, and a more accurate input is provided for the controller to obtain the control signal Z. For example, the controller may calculate the control signal Z according to the formula Z=A*X+B*Y+C, or may obtain the control signal Z through table lookup, where A is an adjustment rule corresponding to the load link information X, B is an adjustment rule corresponding to the backlight sampling voltage Y, and C is an adaptation constant, and the values ​​of A, B, and C can be obtained by searching a pre-calibrated or pre-adapted table in the controller or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-adapted table in the controller can be corrected based on the actual accurate input.

[0025] In a possible implementation, the optoelectronic assembly further includes a temperature control drive circuit and a temperature control circuit, the temperature control drive circuit configured to provide power to the temperature control circuit, and the temperature control circuit configured to perform temperature control on the optoelectronic semiconductor device.

[0026] The temperature control may include, for example, cooling or heating so that the optoelectronic semiconductor device operates at a preset operating temperature to increase the output optical power or extend the service life of the optoelectronic semiconductor device. For example, the temperature control circuit may be a thermoelectric cooler (TEC).

[0027] In a possible implementation, the power supply voltage input by the temperature control drive circuit ranges from 2V to 18V.

[0028] The value of the power supply voltage can be optimized and set based on the voltage, current, cooling capacity, heating capacity, cooling power consumption, heating power consumption, etc. of the temperature control drive circuit and the temperature control circuit to improve the power supply energy efficiency of the temperature control circuit. For example, the power supply voltage can be 3.3V, 5V, 12V, etc., and the deviation accuracy of the power supply voltage can be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage can be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage can be less than or equal to 5%.

[0029] Possible implementations include voltage conversion circuit The power supply voltage input by ranges from 1.8V to 18V.

[0030] The value of the power supply voltage may be optimized and set based on the input-output voltage change efficiency curve of the voltage conversion circuit to improve the voltage conversion efficiency of the voltage conversion circuit as much as possible. For example, the power supply voltage may be 3.3V, 5V, 12V, etc., and the deviation accuracy of the power supply voltage may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0031] In a possible implementation, the power supply voltage input by the controller ranges from 1.5V to 6V. The value of the power supply voltage may be optimized and set based on the voltage, current, and power consumption of devices such as the controller, the analog-to-digital converter, and the digital-to-analog converter to ensure normal operation of the devices and improve system stability. For example, the power supply voltage may range from 1.8V to 3.6V. Furthermore, the power supply voltage may be 3.3V, and the deviation accuracy of the power supply voltage may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0032] The power supply voltages connected to the voltage conversion circuit, the temperature control drive circuit, and the controller are determined based on the load characteristics of the associated devices, which can improve power supply energy efficiency, reduce power consumption, and improve system stability.

[0033] In a possible implementation, when the detection signal is less than a first threshold, the control signal indicates to increase the bias voltage. The detection signal corresponds to the output optical power output by the opto-electrical semiconductor device. The detection signal being less than the first threshold indicates an excessively low output optical power output by the opto-electrical semiconductor device. Thus, the control signal indicates to the voltage conversion circuit to increase the bias voltage, thereby increasing the output optical power output by the opto-electrical semiconductor device.

[0034] In a possible implementation, the control signal indicates to decrease the bias voltage when the detection signal is greater than a second threshold. The detection signal corresponds to the output optical power output by the opto-electrical semiconductor device. The detection signal being greater than the second threshold indicates an excessively large output optical power output by the opto-electrical semiconductor device. Thus, the control signal indicates to the voltage conversion circuit to decrease the bias voltage, thereby decreasing the output optical power output by the opto-electrical semiconductor device. decrease To make.

[0035] In a possible implementation, the voltage conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit. The optoelectric semiconductor device includes a first optoelectric semiconductor device and a second optoelectric semiconductor device. The optoelectric detection circuit includes a first optoelectric detection circuit and a second optoelectric detection circuit. The first optoelectric detection circuit is configured to detect an output optical power output by the first optoelectric semiconductor device and output a first detection signal to the controller. The second optoelectric detection circuit is configured to detect an output optical power output by the second optoelectric semiconductor device and output a second detection signal to the controller. The controller is configured to determine a first control signal based on the first detection signal and send the first control signal to the first voltage conversion circuit, where the first control signal is used to adjust a bias voltage provided to the first optoelectric semiconductor device, and to determine a second control signal based on the second detection signal and send the second control signal to the second voltage conversion circuit, where the second control signal is used to adjust a bias voltage provided to the second optoelectric semiconductor device.

[0036] The opto-electrical assembly provided in this embodiment of the present application is not limited to supporting two opto-electrical semiconductor devices to output light, and may further include more opto-electrical semiconductor devices to output multiple paths of light.

[0037] In one possible implementation, the optoelectronic assembly further includes a digital-to-analog converter. The controller is configured to continuously send a first control signal and a second control signal to the digital-to-analog converter. The digital-to-analog converter is configured to perform digital-to-analog conversion on the first control signal and output a signal obtained through the digital-to-analog conversion to the first voltage conversion circuit, and to perform digital-to-analog conversion on the second control signal and output a signal obtained through the digital-to-analog conversion to the second voltage conversion circuit.

[0038] This implementation improves the design flexibility of the optoelectronic assembly, further reduces the resource requirements for the controller's digital-to-analog conversion interface, reduces the number of digital-to-analog converters, reduces the cost of the optoelectronic assembly, improves integration, and facilitates miniaturization. For example, when a digital-to-analog converter converts two digital signals into one analog signal, the number of digital-to-analog converters can be reduced by 50%. When a digital-to-analog converter can convert more digital signals into one analog signal, more digital-to-analog converters can be reduced.

[0039] In a possible implementation, the bit width of the digital-to-analog converter is greater than or equal to 6 bits, e.g., the bit width of the digital-to-analog converter matches the bit width of the digital signal processed by the controller.

[0040] In one possible implementation, the optoelectric semiconductor device includes a first optoelectric semiconductor device and a second optoelectric semiconductor device. The optoelectric detection circuit includes a first optoelectric detection circuit and a second optoelectric detection circuit. The first optoelectric detection circuit is configured to detect an output optical power output by the first optoelectric semiconductor device and output a first detection signal to the controller. The second optoelectric detection circuit is configured to detect an output optical power output by the second optoelectric semiconductor device and output a second detection signal to the controller. The controller is configured to determine a control signal based on the first detection signal and the second detection signal and send the control signal to the voltage conversion circuit, where the control signal is used to adjust a bias voltage provided to the first optoelectric semiconductor device and a bias voltage provided to the second optoelectric semiconductor device.

[0041] In a possible implementation, if the first detection signal is less than the second detection signal and the first detection signal is less than a first threshold, the control signal indicates to increase the bias voltage.

[0042] In a possible implementation, if the first detection signal is less than the second detection signal and the second detection signal is greater than a second threshold, the control signal indicates to decrease the bias voltage.

[0043] In a possible implementation, the opto-electrical assembly further includes an analog-to-digital converter, which performs analog-to-digital conversion on the first detection signal, performs analog-to-digital conversion on the second detection signal, and converts the first detection signal and the second detection signal obtained through the analog-to-digital conversion. 2 The detection signal is continuously output to the controller.

[0044] This implementation can improve the design flexibility of the optoelectronic assembly, further reduce the resource requirements for the analog-to-digital conversion interface, reduce the number of analog-to-digital converters, reduce the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization. For example, when an analog-to-digital converter converts two analog signals into one digital signal, the analog-to-digital converter can be reduced by 50%. When an analog-to-digital converter can convert more analog signals into one digital signal, more analog-to-digital converters can be reduced.

[0045] In a possible implementation, the bit width of the analog-to-digital converter is greater than or equal to 6 bits, e.g., the bit width of the analog-to-digital converter matches the bit width of the digital signal processed by the controller.

[0046] In a possible implementation, the opto-electrical assembly further includes a feedback network configured to increase or decrease the voltage range of the control signal.

[0047] The feedback network can further improve the accuracy of the control signal, and further improve the accuracy of the bias voltage output by the voltage conversion circuit, that is, equivalently improve the resolution of the analog-to-digital conversion interface in the DAC or controller.

[0048] In one possible implementation, the feedback network includes a first resistor, a second resistor, and a third resistor. The second end of the first resistor is grounded. The first end of the first resistor, the second end of the second resistor, and the first end of the third resistor are coupled to a feedback end of a voltage conversion circuit. The first end of the second resistor is coupled to an output end of the voltage conversion circuit. The second end of the third resistor is coupled to an output end of a controller. The output end of the controller is configured to output a control signal. The feedback end of the voltage conversion circuit is configured to input a control signal that increases or decreases the voltage range of the voltage conversion circuit.

[0049] The feedback network based on the resistor voltage divider network implements a linear increase or decrease of the control signal based on the feedback control signal, thereby meeting the requirements for the range of the signal input by the voltage conversion circuit and improving the accuracy of the control signal. In addition, the feedback network is simple in design and compact in structure, which facilitates the miniaturization of the entire optoelectronic assembly.

[0050] In a possible implementation, the voltage conversion circuit is a DC to DC conversion circuit.

[0051] In this application, voltage conversion is implemented in a DC-DC conversion circuit through charging and discharging high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop occurs, and the conversion efficiency can reach 90% or even 93%.

[0052] According to a second aspect, there is provided a light source pool including at least one opto-electric assembly according to any one of the first aspect and implementations of the first aspect.

[0053] The solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. The light source pool needs to output light to multiple silicon photonic links, with a high output optical power of up to approximately 100 mW and a high carrier density, i.e., a high drive current needs to be injected. For a 10 W light source pool, the power consumption can be reduced by approximately 3 W by using the optoelectronic assembly in this application. This can significantly improve the product's thermal design, reliability, and external power supply pressure, significantly extend the product's service life, reduce product size, and further improve the product's overall competitiveness.

[0054] According to a third aspect, there is provided an optoelectronic switching device including at least one of the optoelectronic assembly of the first aspect or any one of the implementations of the first aspect, or the light source pool of the second aspect, a light modulator, and a switching chip. The optoelectronic assembly or the light source pool is configured to output light. The switching chip is configured to control the light modulator to modulate the light output by the optoelectronic assembly or the light source pool.

[0055] The solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. The optoelectronic switching device requires at least one of an optoelectronic assembly or a light source pool to output light to multiple silicon photonic links of an optical modulator in the optoelectronic switching device, has a high output optical power of up to approximately 100 mW, and requires a high carrier density, i.e., a high drive current. This can implement the miniaturization of the optoelectronic switching device, improve the drive efficiency, and reduce the power consumption of the entire optoelectronic switching device.

[0056] In a possible implementation, the opto-electrical switching device further includes a first controller, which may determine a board control signal based on whether the value of the optical power output by the opto-electrical switching device meets a requirement, and output the board control signal to a controller of the opto-electrical assembly to request an adjustment of the output optical power output by the opto-electrical assembly or the light source pool, or output the board control signal to a controller of the light source pool to request an adjustment of the output optical power output by the light source pool, to increase or decrease the optical power output by the opto-electrical switching device, or to reduce the output optical power to 0.

[0057] According to a fourth aspect, there is provided a control method for an optoelectronic assembly. The method can be applied to the optoelectronic assembly in any one of the first aspect and its implementations. The method includes receiving a detection signal from an optoelectronic detection circuit in the optoelectronic assembly, the detection signal indicating an output optical power output by an optoelectronic semiconductor device in the optoelectronic assembly, and determining a control signal based on the detection signal and sending the control signal to a voltage conversion circuit in the optoelectronic assembly, the control signal being used to adjust a bias voltage.

[0058] In a possible implementation, the method further includes disabling the voltage conversion circuit and outputting a preset control signal to the voltage conversion circuit to enable the voltage conversion circuit.

[0059] In a possible implementation, if the detected signal is less than a first threshold, the control signal indicates to increase the bias voltage.

[0060] In a possible implementation, if the detection signal is greater than a second threshold, the control signal indicates to decrease the bias voltage.

[0061] In a possible implementation, the method further includes obtaining load link information, where the load link information includes a value of the bias voltage. Determining the control signal based on the sensed signal includes determining the control signal based on the load link information and the sensed signal.

[0062] In a possible implementation, the method further includes the step of sequentially sending a first control signal and a second control signal to a digital-to-analog converter in the opto-electrical assembly, where the first control signal is used to adjust a bias voltage provided to the first opto-electrical semiconductor device and the second control signal is used to adjust a bias voltage provided to the second opto-electrical semiconductor device.

[0063] In a possible implementation, the method further includes determining a control signal based on the first detection signal and the second detection signal, and sending the control signal to a voltage conversion circuit, where the control signal is used to adjust a bias voltage provided to the first opto-electrical semiconductor device and a bias voltage provided to the second opto-electrical semiconductor device, and the first detection signal is indicative of an output optical power output by the first opto-electrical semiconductor device, and the second detection signal is indicative of an output optical power output by the second opto-electrical semiconductor device.

[0064] In a possible implementation, if the first detection signal is less than the second detection signal and the first detection signal is less than a first threshold, the control signal indicates to increase the bias voltage.

[0065] In a possible implementation, if the first detection signal is less than the second detection signal and the second detection signal is greater than a second threshold, the control signal indicates to decrease the bias voltage.

[0066] For the technical effects of the second to fourth aspects, please refer to the technical effects of the first aspect and any one of the implementations of the first aspect. [Brief explanation of the drawings]

[0067] [Figure 1] 1 is a schematic diagram of the structure of an opto-electrical switching device according to an embodiment of the present application; [Figure 2] 1 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application; [Figure 3] 2 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application; [Figure 4] 3 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application; [Figure 5] 4 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 6] 5 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 7A] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 7B] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 7C] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 7D] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 7E] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 7F] FIG. 2 is a schematic diagram of a coupling manner between a power source, a voltage conversion circuit, and an opto-electrical semiconductor device according to an embodiment of the present application. [Figure 8A] FIG. 1 is a schematic diagram of a coupling scheme between an ADC and a controller according to an embodiment of the present application. [Figure 8B] FIG. 1 is a schematic diagram of a coupling scheme between an ADC and a controller according to an embodiment of the present application. [Figure 8C]FIG. 1 is a schematic diagram of a coupling scheme between an ADC and a controller according to an embodiment of the present application. [Figure 8D] FIG. 1 is a schematic diagram of a coupling scheme between an ADC and a controller according to an embodiment of the present application. [Figure 9A] FIG. 1 is a schematic diagram of a coupling scheme between a DAC and a controller according to an embodiment of the present application. [Figure 9B] FIG. 1 is a schematic diagram of a coupling scheme between a DAC and a controller according to an embodiment of the present application. [Figure 9C] FIG. 1 is a schematic diagram of a coupling scheme between a DAC and a controller according to an embodiment of the present application. [Figure 9D] FIG. 1 is a schematic diagram of a coupling scheme between a DAC and a controller according to an embodiment of the present application. [Figure 10] 6 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 11] 7 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application; [Figure 12] 8 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 13] 9 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 14] 1 is a schematic diagram 10 of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 15] 11 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 16] 12 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 17] FIG. 2 is a schematic diagram of the coupling between the power supply, the voltage conversion circuit, the temperature control drive circuit, and the controller according to an embodiment of the present application. [Figure 18] 13 is a schematic diagram of the structure of an opto-electrical assembly according to an embodiment of the present application. [Figure 19] 1 is a schematic flow chart of a control method for an opto-electric assembly according to an embodiment of the present application. [Figure 20] 4 is a schematic flow chart of another control method for an opto-electric assembly according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0068] With the rapid development of technologies such as cloud computing, big data, fifth-generation (5G) communications, and autonomous driving, higher requirements such as miniaturization, high bandwidth, and low power consumption have also been proposed for optoelectronic modules or components used in optical communication networks. However, high bandwidth requires increased optical power, increased drive current, and increased power consumption of the optoelectronic semiconductor devices used in the optoelectronic modules or components. For example, Table 1 shows the drive current and power consumption of optoelectronic semiconductor devices in different application scenarios. This has a negative impact on the design of miniaturization and low power consumption, further posing unprecedented challenges to the design of drive circuits for optoelectronic semiconductor devices.

[0069] [Table 1]

[0070] The optoelectronic semiconductor device in the embodiments of the present application is a light emitting device made from semiconductor materials, including, for example, a laser diode (LD), a laser, a semiconductor optical amplifier (SOA), a lidar, or another device.

[0071] Existing optoelectronic assemblies adjust the optical power output by an optoelectronic semiconductor device by using a drive current (sometimes called a bias current) output by an adjustable current source. This solution has the following drawbacks:

[0072] 1. Low driving efficiency. The photoelectric assembly needs to convert the input voltage and then output the converted voltage to an adjustable current source, which reduces the conversion efficiency. The driving current output by the adjustable current source needs to be detected by a current sampling circuit. This causes unnecessary voltage drops, further reducing the conversion efficiency. Therefore, the conversion efficiency of the entire photoelectric assembly is approximately 66.5%.

[0073] 2. There are multiple feedback loops, multiple input parameters for adjustment, and complex rules. When adjusting the bias current output by the adjustable current source, the optoelectronic assembly depends on multiple input parameters, including, for example, the current value of the drive current and the optical power output by the optoelectronic semiconductor device. As a result, simple linear control cannot be implemented, and the control rules are complex.

[0074] 3. The system requires an additional current sampling circuit, resulting in high hardware costs. Because a current sampling circuit needs to be added to detect the drive current, an operational amplifier sometimes needs to be added to amplify the sampled value of the drive current and improve the resolution of detecting the drive current. This is disadvantageous for system miniaturization and cost reduction.

[0075] 4. In order to precisely control the driving current, the voltage or current fluctuation corresponding to the least significant bit for digital-to-analog or analog-to-digital conversion needs to reach a certain amount of bits for digital-to-analog or analog-to-digital conversion in the optoelectronic assembly to meet the requirements for precise control, usually about 10 bits.

[0076] 5. The power-on sequence of different components in the system and the protection of the opto-electrical semiconductor devices are not considered. As a result, the opto-electrical semiconductor devices are easily burned out due to excessively large bias voltages.

[0077] Therefore, embodiments of the present application provide an optoelectronic assembly, a light source pool including the optoelectronic assembly, an optoelectronic switching device including at least one of the optoelectronic assembly or the light source pool, and a control method for the optoelectronic assembly. A voltage conversion circuit in the optoelectronic assembly provides a bias voltage to an optoelectronic semiconductor device in the optoelectronic assembly to adjust the output optical power output by the optoelectronic semiconductor device. An optoelectronic detection circuit in the optoelectronic assembly receives light output by the optoelectronic semiconductor device, detects the output optical power output by the optoelectronic semiconductor device, and outputs a detection signal to a controller in the optoelectronic assembly. The controller can determine a control signal to be used to adjust the bias voltage based on the detection signal and send the control signal to the voltage conversion circuit. The differential resistance value Rdiff of the optoelectronic semiconductor device within a target optical power range satisfies 0.1 Ω≦Rdiff≦50 Ω, where the differential resistance value is the ratio of a voltage fluctuation to a current fluctuation corresponding to the voltage fluctuation. For example, the differential resistance value Rdiff of the optoelectronic semiconductor device within the target optical power range satisfies 0.1 Ω≦Rdiff≦20 Ω. In another example, the differential resistance Rdiff of the optoelectronic semiconductor device within the target optical power range satisfies 1Ω≦Rdiff≦15Ω, or 2Ω≦Rdiff≦10Ω, or 2Ω≦Rdiff≦8Ω, or 2Ω≦Rdiff≦6Ω.

[0078] The voltage conversion circuit replaces the adjustable current source to provide a bias voltage to the optoelectronic semiconductor device. Instead of collecting the current of the load link, only the output optical power output by the optoelectronic assembly is collected as feedback to control the bias voltage output by the voltage conversion circuit. Therefore, linear control is implemented, and the control logic is simple. In addition, since the current sampling circuit for collecting the current of the load link is canceled, there is only the optoelectronic semiconductor device in the load link, and there is no voltage drop caused by the current sampling circuit. Therefore, the conversion efficiency of the power output by the voltage conversion circuit can reach 90% or even 93%. Compared with a solution in which an adjustable current source provides the driving current, this solution in this application improves the conversion efficiency by (90-66.5) / 66.5=35%. There is no operational amplifier. This can reduce the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization.

[0079] The optoelectronic assembly, light source pool, optoelectronic switching device, and control method for the optoelectronic assembly provided in the embodiments of the present application can be applied to application scenarios requiring large driving current, such as 10G passive optical network (XGPON), 50G passive optical network (50G PON), SOA, or autonomous driving lidar.

[0080] As shown in FIG. 1 , the opto-electrical switching device 11 provided in this embodiment of the present application includes at least one of an opto-electrical assembly 111 or a light source pool 112, a plurality of optical power splitters 113, a plurality of optical modulators 114, a plurality of wavelength division multiplexers 115, a multi-channel optical fiber array 116, a first opto-electrical switching chip 117, and a controller 118.

[0081] It should be noted that in a first implementation, the optoelectronic switching device 11 may include an optical source pool 112, an optical power splitter 113, an optical modulator 114, and a multi-channel optical fiber array 116. Alternatively, in a second implementation, the optoelectronic switching device 11 may include an optoelectronic assembly 111, an optical power splitter 113, an optical modulator 114, and a multi-channel optical fiber array 116. Alternatively, in a third implementation, the optoelectronic switching device 11 may include an optical source pool 112, an optical power splitter 113, an optical modulator 114, and a wavelength division multiplexer 115. Alternatively, the three implementations may be freely combined.

[0082] The light source pool 112 may include at least one opto-electrical assembly 111. Each of the opto-electrical assemblies 111 is configured to output light of one wavelength (e.g., laser or fluorescent light), and the wavelengths of the output light output by different opto-electrical assemblies 111 may be the same or different. The optical power splitter 113 may split one path of the output light output by one opto-electrical assembly 111 based on optical power to output multiple paths of the output light to multiple optical modulators 114. The first opto-electrical switching chip 117 controls each of the optical modulators 114 to modulate one path of the output light from the optical power splitter 113 to output one optical signal. Each of the wavelength division multiplexers 115 is configured to multiplex multiple optical signals of different wavelengths and transmit the multiple optical signals to the receiving end 12 through one optical fiber in a coarse wavelength division multiplexing (CWDM) manner, thereby reducing the amount of optical fiber. The multiplexing in this specification can be medium wavelength division multiplexing (MWDM), lane wavelength division multiplexing (LWDM), dense wavelength division multiplexing (DWDM), etc. based on different wavelength combinations of laser devices, and can also be a combination of the above different wavelength division multiplexing based on actual applications. The optical fiber array 116 is configured to combine and output optical signals of multiple wavelengths through a multi-fiber push on (MPO) connector, and transmit the multiple optical signals to the receiving end 12 through parallel single-mode optical fibers (PSM). The second opto-electrical switching chip 121 in the receiving end 12 demodulates the optical signals received by the high-speed optical module 122.For example, if each of the channels of the optical modulator 114 is 100 Gbps, the high-speed optical module 122 corresponding to the PSM solution may be a 400G DR4 optical module. Therefore, the high-speed optical module 122 corresponding to the CWDM solution corresponding to each of the 100G channels may be a 400G FR4 optical module. For example, if each of the channels of the optical modulator 114 is 50 Gbps and each of the optical fiber arrays 116 is connected to eight silicon photonic links of the optical modulator 114, the high-speed optical module 122 corresponding to the LWDM solution may be a 400G LR8 optical module. Additionally, if the receiving end 12 is also located on another optoelectronic switching device similar to the optoelectronic switching device 11, the high-speed optical module 122 may also be a silicon photonic receiving end on the corresponding optical modulator, configured to receive and restore multiple optical signals.

[0083] The controller 118 may determine a board control signal based on whether the value of the optical power output by the opto-electric switching device 11 satisfies the requirements, and output the board control signal to the controller of the opto-electric assembly 111 to request an adjustment of the output optical power output by the opto-electric assembly 111, or output the board control signal to the controller of the light source pool 112 to request an adjustment of the output optical power output by the light source pool 112, thereby increasing or decreasing the optical power output by the opto-electric switching device 11, or reducing the output optical power to 0.

[0084] Typically, the power supply or power interface in the opto-electric assembly 111 or the light source pool 112 is located within the opto-electric switching device 11, and more particularly, is located on the board of the opto-electric switching device 11. More particularly, a compact parallel multi-path drive with high driving efficiency on the light source pool 112 or the opto-electric assembly 111 is located on the board of the opto-electric switching device 11.

[0085] In a co-packaged, near-packaged, or on-board optical communication system using the optoelectronic switching device 11, the light source pool 112 or the optoelectronic assembly 111 can be configured as a pluggable module to provide an external high-power light source for the co-packaged, near-packaged, or on-board optical communication system. The co-packaged, near-packaged, or on-board optical communication system can implement optical communication speeds of 1.6 Tbps, 3.2 Tbps, 25.6 Tbps, 21.2 Tbps, or even higher. The optoelectronic assembly 111, the light source pool 112, or the optoelectronic switching device 11 is configured to output light to multiple silicon photonic links and has a high output optical power of up to approximately 100 mW. The improved driving efficiency can reduce the overall power consumption of the optoelectronic switching device 11, which is very important for the power consumption and heat dissipation design of the entire co-packaged, near-packaged, or on-board optical communication system. In the case of a 10W light source pool, the power consumption can be reduced by approximately 3W by using the optoelectronic assembly of this application. This significantly improves the product's thermal design, reliability, and external power supply pressure, significantly extending its service life and further improving the product's overall competitiveness. In addition, the compact structure of the driving circuit of the light source pool 112 or optoelectronic assembly 111 improves the panel utilization of the optoelectronic switching device 11, helping to miniaturize the device and improve the system's communication capacity, further improving the product's overall competitiveness.

[0086] The following describes possible structures of the opto-electrical assembly provided in the embodiments of the present application.

[0087] 2 and 3, the optoelectric assembly includes a voltage conversion circuit 21, an optoelectric semiconductor device 22, an optoelectric detection circuit 23, and a controller 24. Optionally, as shown in Fig. 3, the optoelectric assembly may further include a feedback network 31. When the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include an analog-to-digital converter (ADC) 32 and a digital-to-analog converter (DAC) 33. When the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input) and a digital-to-analog conversion interface (in other words, an analog signal can be directly output), or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are sufficient, the ADC32 can be the analog-to-digital conversion interface in the controller 24, and the DAC33 can be the digital-to-analog conversion interface in the controller 24.

[0088] The power supply 25 may supply power to the entire optoelectronic assembly through M (M≧1) power supply interfaces, and the power supply voltages of the M power supply interfaces may be the same or different. A common optoelectronic assembly is used as an example, and the supply voltage of the power supply 25 may be a fixed voltage of 3.3V.

[0089] The voltage conversion circuit 21 may be an adjustable voltage source, a DC-DC conversion circuit, a DC-DC conversion chip, or a device or component with an adjustable voltage output. The input power supply voltage may be converted into W (W≧1) bias voltages through DC-DC conversion, and the bias voltages are output to the opto-electrical semiconductor devices 22 to drive them. In addition, the bias voltages output by the voltage conversion circuit 21 may be independently adjusted based on W control signals Z output by the controller 24 to adjust the output optical power of the opto-electrical semiconductor devices 22. The voltage conversion circuit 21 may be used as a unique bias adjustment circuit for the opto-electrical semiconductor devices 22. Specifically, the output optical power of the opto-electrical semiconductor devices 22 is controlled solely by the bias voltages output by the voltage conversion circuit 21. Each of the bias voltages output by the voltage conversion circuit 21 must be greater than 1.0 V, and the power supply voltage Vcc of the power supply 25 must be greater than 1.3 V to turn on the opto-electrical semiconductor devices 22 for normal operation. Each of the bias voltages output by the voltage conversion circuit 21 needs to be less than 0.9*Vcc to ensure that the voltage conversion circuit 21 has high energy conversion efficiency when performing voltage conversion.

[0090] A bias adjustment circuit is an adjustable voltage source or an adjustable current source configured to adjust the bias voltage or bias current of a circuit, for example, an opto-electrical semiconductor device.

[0091] Compared with the conventional technology in which an adjustable current source provides a drive current to the optoelectronic semiconductor device 22, in this technology, a voltage conversion circuit 21 provides a bias voltage to the optoelectronic semiconductor device 22. This can improve conversion efficiency. This is because the solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. An optoelectronic assembly, light source pool, or optoelectronic switching device needs to output light to multiple silicon photonic links, has a high output optical power of up to approximately 100 mW, and requires a high carrier density, i.e., a high drive current needs to be injected. However, it can be seen from the analysis of an adjustable current source providing a drive current to the optoelectronic semiconductor device that a larger drive current results in a larger additional voltage drop generated by the current sampling circuit and a lower conversion efficiency of the entire optoelectronic assembly. A voltage conversion circuit (e.g., a DC-DC conversion circuit) 21 provides a bias voltage to the optoelectronic semiconductor device 22. Essentially, voltage conversion is implemented through the charging and discharging of high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop is generated and the conversion efficiency can reach 90% or even 93%.

[0092] As shown in FIG. 4, the optoelectric semiconductor device 22 can be a light source (e.g., an LED, laser, or LIDAR). In this case, a bias voltage is used to drive the optoelectric semiconductor device 22 to emit light. Alternatively, as shown in FIG. 5, the optoelectric semiconductor device 22 can be an SOA. In this case, the optoelectric semiconductor device 22 is further coupled to a light source 51. The light source 51 can be an external light source or a light source in the optoelectric assembly. The bias voltage is used to drive the optoelectric semiconductor device 22 to amplify the light output by the light source 51. The optoelectric semiconductor devices 22 can be arranged in P load links, and the number of optoelectric semiconductor devices 22 can be N (N≧1). The output light of the optoelectric semiconductor device 22 includes two parts. The first part is the output light of the entire optoelectric assembly (e.g., laser and fluorescent light), and the second part (usually a backlight) is output to an optoelectric detection circuit 23 for detecting the optical power of the optoelectric semiconductor device 22. To ensure that the APC loop operates within a normal range and that the current-voltage relationship curve of the optoelectronic semiconductor device 22 has a smooth linearity, the differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range cannot be too small or too large. The differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range satisfies 0.1Ω≦Rdiff≦50Ω.

[0093] In this embodiment of the present application, the target optical power is typically determined based on the optical power budget range of the optical link of the system in which the opto-electrical assembly, light source pool, or opto-electrical switching device is located, to ensure that the system can be in a normal operating state with a bit error rate less than a certain index. For example, four hundred GbpsTo support normal operation of a silicon photonic modulation link, the target optical power of the optoelectronic assembly, light source pool, or optoelectronic switching device may range from 50 mW to 150 mW. Additionally, the target optical power of the optoelectronic assembly, light source pool, or optoelectronic switching device may range from 64 mW to 120 mW. Additionally, the target optical power of the optoelectronic assembly, light source pool, or optoelectronic switching device may range from 64 mW to 100 mW. This reduces the power consumption of the system when the optical power budget of the system's optical links is guaranteed. In another example, eight 100 Gbps To support normal operation of the silicon photonic modulation link, the target optical power of the optoelectronic assembly, light source pool, or optoelectronic switching device may range from 150 mW to 300 mW. Additionally, the target optical power of the optoelectronic assembly, light source pool, or optoelectronic switching device may range from 150 mW to 250 mW.

[0094] In this embodiment of the present application, the differential resistance Rdiff of the opto-electrical semiconductor device within the target optical power range is dV / dI, where dI is the current variation generated by the current flowing through the opto-electrical semiconductor device when the input voltage generates a voltage variation dV, i.e., the differential resistance Rdiff is the ratio of the voltage variation dV to the current variation dI corresponding to the voltage variation dV.

[0095] It should be noted that in this embodiment of the present application, the controller 24 performs APC to keep the output laser optical power stable within a specific range. The APC loop is formed by the voltage conversion circuit 21, the opto-electrical semiconductor device 22, the opto-electrical detection circuit 23, and the controller 24, and the controller 24 can detect the output optical power output by the opto-electrical semiconductor device 22 through the opto-electrical detection circuit 23. Furthermore, the bias voltage output by the voltage conversion circuit 21 to the opto-electrical semiconductor device 22 is controlled to adjust the output optical power output by the opto-electrical semiconductor device 22; that is, the controller 24 can implement APC on the opto-electrical semiconductor device 22. The APC loop operating within a normal range means that the bias voltage output by the voltage conversion circuit 21 is appropriate, so that the opto-electrical semiconductor device 22 can emit light normally, and the output optical power output by the opto-electrical semiconductor device 22 is within the target optical power range. The load link includes a device coupled to the voltage output end of the voltage conversion circuit 21, such as the opto-electrical semiconductor device 22.

[0096] When the differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range is excessively large, the optoelectronic semiconductor device 22 needs to input a large bias voltage fluctuation to allow the equivalent current of the optoelectronic semiconductor device 22 to generate a small current fluctuation. In other words, when the bias voltage input to the optoelectronic semiconductor device 22 has a large fluctuation, the fluctuation of the equivalent current flowing through the optoelectronic semiconductor device 22 is small, and correspondingly, the carrier concentration fluctuation is small, which is insufficient to effectively adjust the output optical power output by the optoelectronic semiconductor device 22. For example, assume that the differential resistance Rdiff = 100 Ω. A voltage fluctuation of 100 mV is required to generate a current fluctuation of 1 mA, which usually corresponds to a state before the turn-on threshold of the optoelectronic semiconductor device 22 is reached and cannot be used for normal operation of the APC loop. Even if the optoelectronic semiconductor device 22 is in a lasing state above the turn-on threshold at this time, a voltage fluctuation of 1 V is required to achieve a current fluctuation of 10 mA. In actual application processes, it is difficult to apply this photoelectric semiconductor device due to limitations in the voltage output capacity and voltage conversion efficiency of the voltage conversion circuit 21.

[0097] When the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range is excessively small, a small bias voltage fluctuation input to the opto-electrical semiconductor device 22 can cause the current of the opto-electrical semiconductor device 22 to generate large current fluctuations, and correspondingly, the carrier concentration fluctuations will be excessively large. The output optical power output by the opto-electrical semiconductor device 22 will change significantly, and may fall within a range in which the optical power is excessively large or excessively small, or may fall within the roll-off operating range of the opto-electrical semiconductor device 22 (i.e., the output optical power decreases with increasing injection current). Therefore, it is difficult to apply APC. For example, assume that the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range is 0.01 Ω. When the input voltage fluctuation is 1 mV, the current fluctuation of the current flowing through the opto-electrical semiconductor device 22 is 100 mA. This is unacceptable for the feedback adjustment of the APC loop.

[0098] Therefore, in this embodiment of the present application, the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range satisfies the condition 0.1 Ω≦Rdiff≦50 Ω. For example, the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range is 0.2 Ω. When the variation in the bias voltage output by the voltage conversion circuit 21 is 1 mV, the variation in the current flowing through the opto-electrical semiconductor device 22 is 5 mA. In the APC loop adjustment process, it is applicable when the equivalent adjustment current step is large. For example, the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range is 2 Ω. When the variation in the bias voltage output by the voltage conversion circuit 21 is 1 mV, the variation in the current flowing through the opto-electrical semiconductor device 22 is 0.5 mA. In the APC loop adjustment process, it is applicable when the equivalent adjustment current step is small. For example, the differential resistance Rdiff of the opto-electrical semiconductor device 22 within the target optical power range is 20 Ω. When the variation of the bias voltage output by the voltage conversion circuit 21 is 1 mV, the variation of the current flowing through the optoelectronic semiconductor device 22 is 0.05 mA. In the APC loop adjustment process, it is applicable when the equivalent adjustment current step is fine.

[0099] In addition, when the APC loop operates within a normal range, the resistance of the optoelectronic semiconductor device 22 within the target optical power range is less than or equal to 60 Ω. A small resistance of the optoelectronic semiconductor device 22 indicates that the optoelectronic semiconductor device 22 is successfully turned on and enters a good lasing state. In this case, the current-voltage curve of the optoelectronic semiconductor device 22 changes smoothly and has a clear linear characteristic. The differential resistance of the optoelectronic semiconductor device 22 is also reasonable. A change in the bias voltage of the optoelectronic semiconductor device 22 causes a corresponding linear change in the current of the optoelectronic semiconductor device 22, which in turn causes a linear change in the carrier concentration of the optoelectronic semiconductor device 22. This can linearly change the output optical power output by the optoelectronic semiconductor device 22. Conversely, a large resistance of the optoelectronic semiconductor device 22 indicates that the optoelectronic semiconductor device 22 is close to the threshold state. In the close-to-threshold state, the current-voltage curve changes abruptly and has an unclear linear characteristic. In this case, a change in the bias voltage of the opto-electrical semiconductor device 22 may cause a corresponding nonlinear change in the current of the opto-electrical semiconductor device 22, which in turn may cause a nonlinear change in the carrier concentration of the opto-electrical semiconductor device 22. It is difficult to linearly change the output optical power output by the opto-electrical semiconductor device 22. The opto-electrical semiconductor device 22 is not suitable for operation within the range.

[0100] In addition, when the APC loop operates within a normal range, to ensure that the voltage step and the current step corresponding to the voltage step obtained during the APC loop adjustment change uniformly to cause a linear change in the carrier concentration of the opto-electrical semiconductor device 22, the output optical power output by the opto-electrical semiconductor device 22 may be changed linearly, and the selected differential resistance of the opto-electrical semiconductor device 22 within a target optical power range may be uniform, i.e., the differential resistance value Rdiffsub of the opto-electrical semiconductor device 22 within a specific sub-range of the target optical power is close to an average differential resistance value Rdiffavg within the target optical power range. The average differential resistance value Rdiffavg indicates the ratio of the bias voltage variation dV corresponding to the lower optical power limit and the upper optical power limit within the target optical power range to the corresponding current variation dI.

[0101] For example, the differential resistance value Rdiffsub within a particular sub-range of the target optical power satisfies max(0.02*Rdiffavg,0.1Ω)≦Rdiffsub≦min(50*Rdiffavg,50Ω), where max(0.02*Rdiffavg,0.1Ω) indicates the larger value of 0.02*Rdiffavg and 0.1Ω, and min(50*Rdiffavg,50Ω) indicates the smaller value of 50*Rdiffavg and 50Ω.

[0102] For example, the differential resistance value Rdiffsub within a particular sub-range of the target optical power satisfies max(0.1*Rdiffavg,0.1Ω)≦Rdiffsub≦min(10*Rdiffavg,50Ω), where max(0.1*Rdiffavg,0.1Ω) indicates the larger value of 0.1*Rdiffavg and 0.1Ω, and min(10*Rdiffavg,50Ω) indicates the smaller value of 10*Rdiffavg and 50Ω.

[0103] For example, the differential resistance value Rdiffsub within a particular sub-range of the target optical power satisfies max(0.2*Rdiffavg,0.1Ω)≦Rdiffsub≦min(5*Rdiffavg,50Ω), where max(0.2*Rdiffavg,0.1Ω) indicates the larger value of 0.2*Rdiffavg and 0.1Ω, and min(5*Rdiffavg,50Ω) indicates the smaller value of 5*Rdiffavg and 50Ω.

[0104] For example, the differential resistance value Rdiffsub within a particular sub-range of the target optical power satisfies max(0.5*Rdiffavg,0.1Ω)≦Rdiffsub≦min(2*Rdiffavg,50Ω), where max(0.5*Rdiffavg,0.1Ω) indicates the larger value of 0.5*Rdiffavg and 0.1Ω, and min(2*Rdiffavg,50Ω) indicates the smaller value of 2*Rdiffavg and 50Ω.

[0105] For example, the differential resistance value Rdiffsub within a particular sub-range of the target optical power satisfies max(0.8*Rdiffavg,0.1Ω)≦Rdiffsub≦min(1.25*Rdiffavg,50Ω), where max(0.8*Rdiffavg,0.1Ω) indicates the larger value of 0.8*Rdiffavg and 0.1Ω, and min(1.25*Rdiffavg,50Ω) indicates the smaller value of 1.25*Rdiffavg and 50Ω.

[0106] For example, the differential resistance value Rdiffsub within a certain sub-range of the target optical power satisfies max(0.5*Rdiffavg,0.1Ω)≦Rdiffsub≦min(4*Rdiffavg,50Ω), where max(0.5*Rdiffavg,0.1Ω) indicates the larger value of 0.5*Rdiffavg and 0.1Ω, and min(4*Rdiffavg,50Ω) indicates the smaller value of 4*Rdiffavg and 50Ω. In another example, under the target optical power, the differential resistance value of the optoelectric semiconductor device 22 under a bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the target optical power range, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 satisfies max(0.1*Rdiff1,0.1Ω)≦Rdiff≦min(10*Rdiff1,50Ω), where max(0.1*Rdiff1,0.1Ω) indicates the larger value of 0.1*Rdiff1 and 0.1Ω, and min(10*Rdiff1,50Ω) indicates the smaller value of 10*Rdiff1 and 50Ω.

[0107] For example, under a target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 under a bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the range of the target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 satisfies max(0.2*Rdiff1,0.1Ω)≦Rdiff≦min(5*Rdiff1,50Ω), where max(0.2*Rdiff1,0.1Ω) indicates the larger value of 0.2*Rdiff1 and 0.1Ω, and min(5*Rdiff1,50Ω) indicates the smaller value of 5*Rdiff1 and 50Ω.

[0108] For example, under a target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 under a bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the range of the target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 satisfies max(0.5*Rdiff1,0.1Ω)≦Rdiff≦min(2*Rdiff1,50Ω), where max(0.5*Rdiff1,0.1Ω) indicates the larger value of 0.5*Rdiff1 and 0.1Ω, and min(2*Rdiff1,50Ω) indicates the smaller value of 2*Rdiff1 and 50Ω.

[0109] For example, under a target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 under a bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the range of the target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 satisfies max(0.8*Rdiff1,0.1Ω)≦Rdiff≦min(1.25*Rdiff1,50Ω), where max(0.8*Rdiff1,0.1Ω) indicates the larger value of 0.8*Rdiff1 and 0.1Ω, and min(1.25*Rdiff1,50Ω) indicates the smaller value of 1.25*Rdiff1 and 50Ω.

[0110] For example, under a target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 under a bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the range of the target optical power, the differential resistance value Rdiff of the opto-electrical semiconductor device 22 satisfies max(0.5*Rdiff1,0.1Ω)≦Rdiff≦min(4*Rdiff1,50Ω), where max(0.5*Rdiff1,0.1Ω) indicates the larger value of 0.5*Rdiff1 and 0.1Ω, and min(4*Rdiff1,50Ω) indicates the smaller value of 4*Rdiff1 and 50Ω.

[0111] In this embodiment of the present application, the relationship between the quantity P of the load links, the quantity N of the opto-electrical semiconductor devices 22, and the quantity W of the bias voltage output by the voltage conversion circuit 21 can be adjusted correspondingly based on different series-parallel connection relationships of the load links and the series-parallel connection relationships of different opto-electrical semiconductor devices 22 in the same load link. Typically, P=N=W, and specifically, each bias voltage output by the voltage conversion circuit 21 drives one load link, and each load link has one opto-electrical semiconductor device 22. In particular, if the opto-electrical semiconductor devices 22 have good device performance consistency, multiple load links can be driven in parallel on one voltage output terminal of the voltage conversion circuit 21, and each link has at least one opto-electrical semiconductor device 22. For example, one voltage output terminal of the voltage conversion circuit 21 drives two load links connected in parallel, and each load link includes one opto-electrical semiconductor device 22. In this case, W=P / 2 and P=N. In another example, one voltage output terminal of the voltage conversion circuit 21 drives two load links connected in parallel, and two optoelectronic semiconductor devices are connected in series to each of the links, where W=P / 2 and P=N / 2.

[0112] The optoelectric detection circuit 23 is configured to receive the light output by the optoelectric semiconductor device 22, detect the output optical power output by the optoelectric semiconductor device 22, and output a detection signal to the controller 24, where the detection signal may indicate the output optical power output by the optoelectric semiconductor device 22. The optoelectric detection circuit 23 typically detects the backlight optical power output by the optoelectric semiconductor device 22 in N detection links to detect the output optical power output by the optoelectric semiconductor device 22. As shown in FIG. 6 , the optoelectric detection circuit 23 includes a photoelectric detector 2301 and a sampling resistor 2302 connected in series. When illuminated by a backlight, the reverse-biased photoelectric detector 2301 generates a photocurrent. When the photocurrent passes through the sampling resistor 2302, a detection signal proportional to the photocurrent (a backlight sampling voltage Y is used as an example in this application, but is not intended to be limiting) is generated. The value of the photocurrent is proportional to the optical power of the backlight. Therefore, the backlight sampling voltage Y is proportional to the output optical power. The backlight sampling voltage Y output by the photoelectric detection circuit 23 is an analog signal.

[0113] The ADC 32 is configured to convert the backlight sampling voltage Y generated by the photoelectric detection circuit 23 from an analog signal to a digital signal. The ADC 32 may include a single ADC component or multiple ADC components, and the specifications of all the ADC components may be the same or different.

[0114] When ADC 32 includes a single ADC component, the quantity Q of input analog channels supported by the ADC component is greater than or equal to N, and the quantity R of output digital channels supported by the ADC component is greater than or equal to S, where S (S≧1) is the quantity of digital channels of controller 24 that are coupled to ADC 32. Specifically, the quantity Q of input analog channels supported by a single ADC component is N, and the quantity R of output digital channels supported is S=1.

[0115] When ADC 32 includes J (J≧2) ADC components, the amount of input analog channels supported by the ith (2≦i≦J) ADC component is Qi, and the amount of output digital channels supported by the ith ADC component is Ri. In this case, Q1+...+Qi+...+QJ≧N and R1+...+Ri+...+RJ≧S must be satisfied. Specifically, the amount of input analog channels supported by each of the J ADC components satisfies Q1+...+Qi+...+QJ=N, and the amount of output digital channels supported by each of the J ADC components satisfies Ri=1 (2≦i≦J).

[0116] The controller 24 is configured to provide signal processing and control for the entire driving system according to a control processing algorithm to implement a control method for the photoelectric assembly. Specifically, the controller 24 may determine a control signal Z based on a detection signal (e.g., a backlight sampling voltage Y) output by the photoelectric detection circuit 23 and output the control signal Z to a feedback terminal of the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21, i.e., implement APC. The controller 24 may also be used for automatic gain control (AGC), optical pulse output control, etc. For example, the controller 24 may calculate the control signal Z according to the formula Z=B*Y+C or obtain the control signal Z through table lookup, where B is an adjustment rule corresponding to the backlight sampling voltage Y and C is an adaptation constant. The values ​​of B and C may be obtained by searching a pre-calibrated or pre-adapted table in the controller 24 or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-adapted table in the controller 24 can be corrected based on the actual accurate input. In other words, there is a linear relationship between the control signal Z and the detection signal (backlight sampling voltage Y). This simplifies the algorithm design of the controller 24 and facilitates the control on the bias voltage.

[0117] In addition, the controller 24 may further acquire load link information (how to acquire the load link information will be described below), where the load link information includes a value of the bias voltage. The load link information may be a digital signal or an analog signal. The controller 24 may determine a control signal Z based on the load link information X and the detection signal (e.g., a backlight sampling voltage Y), and output the control signal Z to a feedback end of the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21.

[0118] When the load link information indicates the actual value of the bias voltage, the deviation between the theoretical value and the actual value of the bias voltage caused by device parameter deviations and fluctuations in the feedback network 31 can be eliminated, and a more accurate input is provided for the controller 24 to obtain the control signal Z. For example, the controller 24 may calculate the control signal Z according to the formula Z=A*X+B*Y+C or obtain the control signal Z through table lookup, where A is an adjustment rule corresponding to the load link information X, B is an adjustment rule corresponding to the backlight sampling voltage Y, and C is an adaptation constant, and the values ​​of A, B, and C can be obtained by searching a pre-calibrated or pre-adapted table in the controller 24 or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-adapted table in the controller 24 can be corrected based on the actual accurate input.

[0119] The bit width of the digital signal processed by the controller 24 is at least 6 bits, and the voltage fluctuation corresponding to the least significant bit satisfies the requirement for fine adjustment of the bias voltage output by the voltage conversion circuit 21, enabling accurate control of the bias voltage output by the voltage conversion circuit 21. If the digital signal processed by the controller 24 has only 4 bits, e.g., if the internal reference voltage of the controller 24, 2.5V, corresponds to the maximum value of a 4-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller 24 is 2.5V / 2^4 ≒ 156 mV. This voltage adjustment precision is unacceptable. If the bit width of the digital signal processed by the controller 24 is 6 bits, e.g., if the internal reference voltage of the controller 24, 2.5V, corresponds to the maximum value of a 6-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller 24 is 2.5V / 2^6 ≒ 39 mV. Even if the precision of the bias voltage output by the voltage conversion circuit 21 is the same as the voltage fluctuation of 39 mV corresponding to the least significant bit of the control signal Z, when the differential resistance value Rdiff of the optoelectronic semiconductor device 22 within the target optical power range is 10 Ω and the bias voltage fluctuation output by the voltage conversion circuit 21 is 39 mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device 22 is 3.9 mA. This may be considered a case where the equivalent adjustment current step is large in APC loop control, but it is also acceptable. If the bit width of the digital signal processed by the controller 24 is 8 bits, for example, the internal reference voltage of the controller 24, 2.5 V, corresponds to the maximum value of an 8-bit binary number, the voltage fluctuation corresponding to the least significant bit of the control signal Z output by the controller 24 is 2.5 V / 2^8 = 9.8 mV.Even if the accuracy of the bias voltage output by the voltage conversion circuit 21 is the same as the voltage fluctuation of 9.8 mV corresponding to the least significant bit of the control signal Z, when the differential resistance value Rdiff of the optoelectronic semiconductor device 22 within the target optical power range is 10 Ω and the bias voltage fluctuation output by the voltage conversion circuit 21 is 9.8 mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device 22 is 0.98 mA. This may be considered as a case where the equivalent adjustment current step is small in APC loop control, which is acceptable. In combination with the feedback network 31, the accuracy of the control signal Z can be further improved, and the accuracy of the bias voltage output by the voltage conversion circuit 21 can be further improved, that is, the resolution of the analog-to-digital conversion interface in the DAC 33 or the controller 24 is equivalently improved.

[0120] The amount of digital channels of the controller 24 coupled to the ADC 32 is S (S≧1), and the amount of analog channels of the controller 24 coupled to the DAC 33 is T (T≧1). The controller 24 can be a micro-control unit (MCU), a field-programmable gate array (FPGA), etc.

[0121] The DAC 33 is configured to convert the control signal Z generated by the controller 24 from a digital signal to an analog signal. The DAC 33 may include a single DAC component or multiple DAC components, all of which may have the same or different specifications.

[0122] When DAC 33 includes a single DAC component, the amount of input digital channels U supported by the DAC component is greater than or equal to T, and the amount of output analog channels V supported by the DAC component is greater than W. T (T≧1) is the amount of digital channels of controller 24 that are coupled to DAC 33. Specifically, the amount of input digital channels U supported by the single DAC component is T=1, and the amount of output analog channels V supported by the single DAC component is W.

[0123] When DAC 33 includes L (L≧2) DAC components, the amount of input digital channels supported by the i-th (2≦i≦L) DAC component is Ui, and the amount of output analog channels supported by the i-th DAC component is Vi. In this case, U1+...+Ui+...+UL≧T and V1+...+Vi+...+VL≧W must be satisfied. In particular, the amount of input digital channels supported by each of the above L DAC components satisfies Ui=1 (2≦i≦L), and the amount of output analog channels supported by each of the above L DAC components satisfies V1+...+Vi+...+VL=W.

[0124] It should be noted that in order to match the bit width of the digital signal processed by the controller 24, i.e., at least 6 bits, the bit width of the DAC 33 and the ADC 32 can match the bit width of the digital signal processed by the controller 24 to ensure adjustment accuracy. Therefore, the bit width of the DAC 33 and the ADC 32 is also at least 6 bits.

[0125] The feedback network 31 is configured to increase or decrease the voltage range of the control signal Z to obtain a feedback control signal F, and output the feedback control signal F to the voltage conversion circuit 21 to meet the requirements for the range of the signal input by the voltage conversion circuit 21 and improve the accuracy of the control signal Z. Therefore, the feedback control signal F can be expressed as F=E*Z+G, where E is the corresponding adjustment rule of the feedback network 31 for the control signal Z, and G is an adaptation constant. In addition, when the voltage conversion circuit 21 is a DC-DC conversion circuit, the DC-DC conversion circuit usually includes an operational amplifier, and the feedback network 31 is coupled to the output end and feedback end of the operational amplifier to form a feedback path of the operational amplifier. The feedback network 31 can provide W feedback control signals F corresponding to W output voltages to the voltage conversion circuit 21.

[0126] In particular, when the voltage conversion circuit 21 has a voltage regulation and transformation frequency input end or control end, the controller 24 can further provide another feedback control signal F2 to the voltage conversion circuit 21 based on the circuit status and characteristics of the voltage conversion circuit 21 to change the voltage regulation and transformation frequency of the voltage conversion circuit 21, which can improve the voltage conversion efficiency of the voltage conversion circuit 21.

[0127] The feedback network 31 may be a voltage divider network including resistors. For example, as shown in FIG. 6, the feedback network includes a resistor Ra, a resistor Rb, and a resistor Rc. A second end of the resistor Ra is grounded, a first end of the resistor Ra, a second end of the resistor Rb, and a first end of the resistor Rc are coupled to a feedback end of the voltage conversion circuit 21, a first end of the resistor Rb is coupled to a bias voltage output end of the voltage conversion circuit 21, and a second end of the resistor Rc is coupled to an output end of the controller 24.

[0128] It is assumed that there is a functional relationship Vout=f(Vfb) between the bias voltage Vout output by the voltage conversion circuit 21 and the feedback voltage Vfb (i.e., the voltage of the feedback control signal F) input from the feedback terminal of the voltage conversion circuit 21, where f() represents a function, and this functional relationship is related to the design of the voltage conversion circuit 21. If this functional relationship is linear, it can be further expressed as Vout=a*Vfb+c, where a and c are constant coefficients related to the design of the voltage conversion circuit 21. When the voltage conversion circuit 21 is a DC-DC conversion circuit, a reference voltage Vref (which is usually a fixed value) inside the DC-DC conversion circuit is input from an input terminal of an operational amplifier in the DC-DC conversion circuit, and a voltage Vfb is input from another input terminal of the operational amplifier. The voltages Vout, Vfb, and the reference voltage Vref have the following relationship when Rc is off: Vfb=Vref Equation 1 Vout=Vfb*(Ra+Rb) / Rb Equation 2

[0129] Specifically, in combination with the resistor voltage divider network of feedback network 31, the following can be obtained: Vout=(Vref / Ra-(Vadj-Vref) / Rc)*Rb+Vref Equation 3

[0130] Vadj is the voltage of the control signal Z output by the DAC 33.

[0131] From Equation 3, it can be seen that for a given resistance Ra, a given resistance Rb, and a given resistance Rc, the output voltage Vout of the DC-DC conversion circuit can be adjusted based on the voltage Vadj of the control signal Z, that is, Vout=f(Vadj), and the control signal Z and the feedback control signal F have a linear relationship. Therefore, different resistance Ra, resistance Rb, resistance Rc, voltage Vadj, and reference voltage Vref are set to obtain different voltage Vout.

[0132] The feedback network based on the resistor voltage divider network implements a linear increase or decrease of the control signal Z based on the feedback control signal F, thereby meeting the requirements for the range of the signal input by the voltage conversion circuit 21 and improving the accuracy of the control signal. In addition, the feedback network is simple in design and compact in structure, which facilitates the miniaturization of the entire optoelectronic assembly.

[0133] It should be noted that in the present application, only one feedback network based on a resistor voltage divider network is provided, and various functional relationships Vout=f(Vadj) can be further designed in combination with other devices such as digital circuits and analog circuits. In addition, in combination with the controller 24 and based on the backlight sampling voltage Y, the functional relationship Z=g(Y) of the control signal Z can be further determined to obtain Vout=f(Vadj)=f(g(Y)).

[0134] For example, using an example in which the controller 24 determines the control signal Z based on the detection signal (e.g., the backlight sampling voltage Y) output by the photoelectric detection circuit 23, it will be described how the controller 24 calibrates each of the parameters in the equation Z=B*Y+C.

[0135] Step 1: The controller 24 outputs a control signal Z. If a feedback network 31 is present, the feedback network 31 converts the control signal Z into a feedback control signal F and outputs the feedback control signal F to the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21. If a feedback network 31 is not present, the control signal Z is output to the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21. The bias voltage output by the voltage conversion circuit 21 correspondingly generates a driving current (also called a bias current), and the optoelectronic semiconductor device 22 outputs light (major power) and backlight (minor power) under the action of the driving current. The output optical power measured by an external optical power detector is P. The optoelectronic detection circuit 23 outputs a backlight sampling voltage Y. The backlight sampling voltage Y, the control signal Z, and the optical power P are stored in the controller 24 as a parameter combination (Y, Z, P).

[0136] Within the target optical power range, the ratio of the backlight optical power output by the optoelectric semiconductor device 22 to the output optical power P is essentially stable, and the backlight optical power is proportional to the backlight sampling voltage Y. Therefore, the output optical power P is proportional to the backlight sampling voltage Y. Therefore, the parameter combination (Y, Z, P) can be expressed as (Y, Z, P(Y)).

[0137] Step 2: The controller 24 changes the output control signal Z, obtains more parameter combinations (Yi, Zi, Pi(Yi)) in step 1, and stores the parameter combinations in the controller 24, where i is a positive integer. Alternatively, the controller 24 may obtain new parameter combinations through fitting based on multiple existing parameter combinations. After obtaining multiple combined parameters, the controller 24 may establish a mapping relationship between B, C, Y, and Z in the equation Z=B*Y+C according to a specific algorithm and rule.

[0138] Step 3: The controller 24 sets a default parameter combination (Yo, Zo, Po(Y)) based on the target optical power Pg, and the controller 24 is configured to output a control signal Z based on the default parameter combination during initialization, where Po≧Pg.

[0139] In the actual system operation process, the controller 24 performs APC to maintain the output optical power within a preset range. The controller 24 obtains the backlight sampling voltage Y in real time and obtains the control signal Z according to the calibrated formula Z=B*Y+C. Usually, the backlight sampling voltage Y obtained by the controller 24 is stable, and therefore the control signal Z is also stable.

[0140] When the output optical power of the optoelectronic semiconductor device 22 decreases due to aging of the device or an increase in ambient temperature, the backlight sampling voltage Yo decreases to Y'. In this case, the controller 24 adjusts the control signal Z according to Z = B * Y + C established in the calibration process so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, increases the carrier density, increases the output optical power, and further increases the backlight sampling voltage to Yt. The controller 24 compares Yt with Yo. When Yt < Yo, the adjustment of the control signal Z is continued so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, and increases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. When Yt > Yo, the controller continues to adjust the control signal Z so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, and decreases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. The adjustment direction and step of the control signal Z can be dynamically adjusted based on the change trend of the backlight sampling voltage Yt and according to the formula Z = B * Y + C. Finally, the entire system operates under the new parameter combination (Yo, Zt, Po(Yo)).

[0141] When the output optical power output by the optoelectronic semiconductor device 22 increases due to the decrease in the ambient temperature, the backlight sampling voltage Yo increases to Y'. In this case, the controller 24 adjusts the control signal Z according to the formula Z = B * Y + C established in the calibration process so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, reduces the carrier density, and further needs to reduce the backlight sampling voltage to Yt. The controller 24 compares Yt with Yo. When Yt > Yo, the adjustment of the control signal Z is continued so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, and reduces the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. When Yt < Yo, the controller continues to adjust the control signal Z so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, and increases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. The adjustment direction and step of the control signal Z can be dynamically adjusted based on the change trend of the backlight sampling voltage Yt and according to the formula Z = B * Y + C. Finally, the entire system operates under the new parameter combination (Yo, Zt, Po(Yo)).

[0142] According to the opto-electric assembly, the light source pool, and the control method for the opto-electric assembly provided in the embodiments of the present application, the efficiency of the opto-electric assembly is improved. The voltage conversion circuit provides a bias voltage to the opto-electric semiconductor device to adjust the output optical power output by the opto-electric semiconductor device. The opto-electric detection circuit receives the light output by the opto-electric semiconductor device, detects the output optical power output by the opto-electric semiconductor device, and outputs a detection signal to the controller. The controller can determine a control signal used to adjust the bias voltage based on the detection signal and send the control signal to the voltage conversion circuit. There is no need to couple a separate detection circuit between the voltage conversion circuit and the opto-electric semiconductor device, and additional power output by the voltage conversion circuit is not consumed. Most of the power output by the voltage conversion circuit is converted into output optical power output by the opto-electric semiconductor device. This can therefore improve the efficiency of the opto-electric assembly.

[0143] The power supply 25, the voltage conversion circuit 21, and the opto-electrical semiconductor device 22 can be coupled in multiple ways. The coupling methods between the power supply 25, the voltage conversion circuit 21, and the opto-electrical semiconductor device 22 will be described below with reference to Figures 7A, 7B, 7C, 7D, 7E, and 7F. For ease of explanation, please refer to the descriptions in other accompanying drawings for the configurations, functions, and coupling methods of other functional modules.

[0144] 7A, the power supply 25 outputs two voltages Vcc1 and Vcc2, which are output to a first voltage conversion circuit 211 and a second voltage conversion circuit 212, respectively. Vcc1 and Vcc2 may be the same or different. The bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by a controller to adjust the output optical power output by the opto-electrical semiconductor device in load link 1. The bias voltage output by the second voltage conversion circuit 212 is controlled by a control signal Z output by a controller to adjust the output optical power output by the opto-electrical semiconductor device in load link 2.

[0145] 7B, the power supply 25 outputs a voltage Vcc1 to the first voltage conversion circuit 211 and the second voltage conversion circuit 212. The bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by the controller to adjust the output optical power output by the opto-electrical semiconductor device in the load link 1. The bias voltage output by the second voltage conversion circuit 212 is controlled by a control signal Z output by the controller to adjust the output optical power output by the opto-electrical semiconductor device in the load link 2.

[0146] As shown in FIG. 7C, the power supply 25 outputs two voltages Vcc1 and Vcc2, which are connected to a first voltage conversion circuit 211 and the second voltage conversion circuit 212, respectively. Vcc1 and Vcc2 can be the same or different. Load link 1 and load link 2 are coupled in parallel to the voltage output terminals of the first voltage conversion circuit 211, and the bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by a controller to adjust the output optical power output by the opto-electrical semiconductor device in load link 1 and the opto-electrical semiconductor device in load link 2. Load link 3 and load link 4 are coupled in parallel to the first voltage conversion circuit 211, and the bias voltage output by the opto-electrical semiconductor device in load link 1 and the opto-electrical semiconductor device in load link 2 is controlled by a control signal Z output by a controller to adjust the output optical power output by the opto-electrical semiconductor device in load link 1 and the opto-electrical semiconductor device in load link 2. 2 Voltage conversion circuit 212The bias voltage output by the second voltage conversion circuit 212 is controlled by the control signal Z output by the controller, so that the photoelectric semiconductor device in the load link 3 and the load link 4 and an optoelectronic semiconductor device therein, and adjusts the output optical power output by the optoelectronic semiconductor device.

[0147] 7D, the power supply 25 outputs a voltage Vcc1 to the first voltage conversion circuit 211 and the second voltage conversion circuit 212. The load link 1 and the load link 2 are coupled in parallel to the voltage output terminal of the first voltage conversion circuit 211, and the bias voltage output by the first voltage conversion circuit 211 is controlled by the control signal Z output by the controller to adjust the output optical power output by the opto-electrical semiconductor device in the load link 1 and the opto-electrical semiconductor device in the load link 2. The load link 3 and the load link 4 are coupled in parallel to the first voltage conversion circuit 211 and the second voltage conversion circuit 212. 2 Voltage conversion circuit 212 The bias voltage output by the second voltage conversion circuit 212 is controlled by the control signal Z output by the controller, so that the photoelectric semiconductor device in the load link 3 and the load link 4 and an optoelectronic semiconductor device therein, and adjusts the output optical power output by the optoelectronic semiconductor device.

[0148] As shown in Figure 7E, multiple opto-electrical semiconductor devices (e.g., a first opto-electrical semiconductor device 221 and a second opto-electrical semiconductor device 222) may be connected in series to the load link, or as shown in Figure 7F, multiple opto-electrical semiconductor devices (e.g., a first opto-electrical semiconductor device 221 and a second opto-electrical semiconductor device 222) may be connected in parallel to the load link. That is, Figures 7E and 7F can be freely combined with Figures 7A to 7D. It should be noted that in this case, each of the opto-electrical semiconductor devices is paired with an independent opto-electrical detection circuit.

[0149] In the case of FIGS. 7E and 7F, the first opto-electrical semiconductor device 221 is paired with a first opto-electrical detection circuit, and the first opto-electrical detection circuit detects the output optical power output by the first opto-electrical semiconductor device 221 and determines the first detection The second opto-electrical semiconductor device 222 is configured to output a signal to the controller 24. The second opto-electrical semiconductor device 222 is paired with a second opto-electrical detection circuit, and the second opto-electrical detection circuit detects the output optical power output by the second opto-electrical semiconductor device 222 and outputs a second detection The first and second detection signals are configured to output a control signal to the controller 24. The controller 24 may determine a control signal based on the first and second detection signals and send the control signal to the voltage conversion circuit 21. Because the first and second opto-electrical semiconductor devices 221 and 222 are coupled to the voltage conversion circuit 21 through a load link, the bias voltages provided to the first and second opto-electrical semiconductor devices 221 and 222 can be adjusted based on the control signal.

[0150] Whether the first opto-electrical semiconductor device 221 and the second opto-electrical semiconductor device 222 are connected in series or in parallel, if the first detection signal is less than the second detection signal and the first detection signal is less than the first threshold (in other words, the output optical power output by the opto-electrical semiconductor devices is too low), the controller 24 determines a control signal based on the first detection signal, where the control signal may indicate the voltage conversion circuit 21 to increase the bias voltage to increase the output optical power output by the first opto-electrical semiconductor device 221 and the second opto-electrical semiconductor device 222. That is, if the output optical power output by the opto-electrical assembly needs to be increased, the control signal is determined based on the detection signal corresponding to the smaller of the output optical powers output by the two opto-electrical semiconductor devices.

[0151] Whether the first opto-electrical semiconductor device 221 and the second opto-electrical semiconductor device 222 are connected in series or in parallel, if the first detection signal is less than the second detection signal and the second detection signal is greater than the second threshold (in other words, the output optical power output by the opto-electrical semiconductor devices is too high), the controller 24 determines a control signal based on the second detection signal, where the control signal may indicate the voltage conversion circuit 21 to decrease the bias voltage to decrease the output optical power output by the first opto-electrical semiconductor device 221 and the second opto-electrical semiconductor device 222. That is, if the output optical power output by the opto-electrical assembly needs to be decreased, the control signal is determined based on the detection signal corresponding to the larger of the output optical power output by the two opto-electrical semiconductor devices.

[0152] Various coupling methods between the power supply 25, the voltage conversion circuit 21 and the optoelectronic semiconductor device 22 provide more flexibility for the design of the optoelectronic assembly, which can further reduce the number of devices, reduce costs and improve integration.

[0153] It should be noted that various combinations of Figures 7A, 7B, 7C, 7D, 7E, and 7F may be implemented by those skilled in the art, and all combinations are considered to be embodiments of the present application and fall within the scope of protection of the present application. In addition, the various combination schemes in Figures 7A, 7B, 7C, 7D, 7E, and 7F require that all load links in the same voltage conversion circuit have good consistency, and that all optoelectronic semiconductor devices in the same load link have good consistency. Otherwise, the adjustment trends of the two optoelectronic semiconductor devices may be inconsistent, or power fluctuations may be likely to occur. In addition, when the first threshold and the second threshold coexist, it is also required that the first threshold and the second threshold cannot be too close to each other. Otherwise, the adjustment trends of the two optoelectronic semiconductor devices may be inconsistent, or power fluctuations may be likely to occur.

[0154] The ADC 32, the DAC 33, and the controller 24 can be coupled in multiple ways. Below, the coupling methods between the ADC 32 and the controller 24 will be described with reference to Figures 8A, 8B, 8C, and 8D, and the coupling method between the controller 24 and the DAC 33 will be described with reference to Figures 9A, 9B, 9C, and 9D. For ease of explanation, please refer to the descriptions in other accompanying drawings for the configurations, functions, and coupling methods of other functional modules.

[0155] As shown in FIG. 8A , the ADC 32 includes four analog input ports (in1 to in4) and one digital output port (out1). The controller 24 includes one digital input port (in5), which is coupled to the digital output port out1 of the ADC 32. The four analog input ports (in1 to in4) of the ADC 32 respectively receive four analog signals (backlight sampling voltage 1 to backlight sampling voltage 4) from the photoelectric detection circuit. The ADC 32 separately performs analog-to-digital conversion on the four analog signals to obtain four digital signals and outputs the four digital signals sequentially in a specific order to the controller 24 through the digital output port out1 of the ADC 32. After receiving the four digital signals, the controller 24 analyzes the four digital signals in a specific order to obtain the values ​​of four backlight sampling voltages. The controller 24 may obtain one control signal based on each of the four backlight sampling voltages and send the four control signals to corresponding voltage conversion circuits to adjust the output bias voltages.

[0156] 8B, the first ADC 321 includes two analog input ports (in1 and in2) and one digital output port (out1), and the second ADC 322 includes two analog input ports (in3 and in4) and one digital output port (out2). The controller 24 includes two digital input ports (in5 and in6). The digital input port in5 of the controller 24 is coupled to the digital output port out1 of the first ADC 321, and the digital input port in6 of the controller 24 is coupled to the digital output port out2 of the second ADC 322. The two analog input ports (in1 and in2) of the first ADC 321 respectively receive two analog signals (backlight sampling voltage 1 and backlight sampling voltage 2) from the photoelectric detection circuit. The first ADC 321 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals, and outputs the two digital signals consecutively in a specific order to the controller 24 through the digital output port out1 of the first ADC 321. After receiving the two digital signals, the controller 24 analyzes the two digital signals in a specific order to obtain two backlight sampling voltage values. The two analog input ports (in3 and in4) of the second ADC 322 respectively receive two analog signals (backlight sampling voltage 3 and backlight sampling voltage 4) from the photoelectric detection circuit. The second ADC 322 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals, and outputs the two digital signals consecutively in a specific order to the controller 24 through the digital output port out2 of the second ADC 322. After receiving the two digital signals, the controller 24 analyzes the two digital signals in a specific order to obtain two backlight sampling voltage values. The controller 24 may obtain one control signal based on each of the four backlight sampling voltages, and send the four control signals to corresponding voltage conversion circuits respectively to adjust the output bias voltages.

[0157] As shown in Figure 8C, the ADC32 has four analog input ports (in1 to in4) and 2 One digital output port (out1 and out2). The controller 24 includes two digital input ports (in5 and in6). The digital input port in5 of the controller 24 is coupled to the digital output port out1 of the ADC 32, and the digital input port in6 of the controller 24 is coupled to the digital output port out2 of the ADC 32. The two analog input ports (in1 and in2) of the ADC 32 respectively receive two analog signals (backlight sampling voltage 1 and backlight sampling voltage 2) from the photoelectric detection circuit. The ADC 32 separately performs analog-to-digital conversion on the two analog signals to obtain two digital signals and outputs the two digital signals sequentially in a specific order to the controller 24 through the digital output port out1 of the ADC 32. After receiving the two digital signals, the controller 24 analyzes the two digital signals in a specific order to obtain the values ​​of the two backlight sampling voltages. The two analog input ports (in3 and in4) of the ADC 32 respectively receive two analog signals (backlight sampling voltage 3 and backlight sampling voltage 4) from the photoelectric detection circuit. The ADC 32 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals, which are then output to the controller 24 in a specific order via the digital output port out2 of the ADC 32. After receiving the two digital signals, the controller 24 analyzes the two digital signals in a specific order to obtain the values ​​of two backlight sampling voltages. The controller 24 can obtain one control signal based on each of the four backlight sampling voltages and send the four control signals to corresponding voltage conversion circuits to adjust the output bias voltages. While the total number of digital signals output from the output ports out1 and out2 of the ADC 32 is typically four, the number of digital signals output from the output ports out1 and out2, respectively, and the correspondence between this number and the corresponding backlight sampling voltages 1 to 4, are not limited.

[0158] 8D , the first ADC 321 includes four analog input ports (in1 to in4) and one digital output port (out1), and the second ADC 322 includes two analog input ports (in5 and in6) and one digital output port (out2). The controller 24 includes two digital input ports (in7 and in8). The digital input port in7 of the controller 24 is coupled to the digital output port out1 of the first ADC 321, and the digital input port in8 of the controller 24 is coupled to the digital output port out2 of the second ADC 322. The four analog input ports (in1 to in4) of the first ADC 321 receive four analog signals (backlight sampling voltage 1 to backlight sampling voltage 4) from the photoelectric detection circuit, respectively. The first ADC 321 performs analog-to-digital conversion on the four analog signals separately to obtain four digital signals, and outputs the four digital signals consecutively in a specific order to the controller 24 through the digital output port out1 of the first ADC 321. After receiving the four digital signals, the controller 24 analyzes the four digital signals in a specific order to obtain four backlight sampling voltage values. The two analog input ports (in5 and in6) of the second ADC 322 respectively receive two analog signals (backlight sampling voltage 5 and backlight sampling voltage 6) from the photoelectric detection circuit. The second ADC 322 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals, and outputs the two digital signals consecutively in a specific order to the controller 24 through the digital output port out2 of the second ADC 322. After receiving the two digital signals, the controller 24 analyzes the two digital signals in a specific order to obtain two backlight sampling voltage values.

[0159] As shown in FIG. 9A, the DAC33 includes four analog output ports (out1 to out4) and one digital input port (in1). The controller 24 includes one digital output port (out5). The digital output port out5 of the controller 24 is coupled to the digital input port in1 of the DAC33. The controller 24 outputs four control signals (control signal 1 to control signal 4) to the DAC33 sequentially in a specific order through the digital output port out5 of the controller 24. After receiving the four digital signals, the DAC33 analyzes the four digital signals in a specific order to obtain the four control signals, and outputs the four control signals separately. Digital Analog The conversion is performed to obtain four analog signals, which are then output separately through the four analog output ports (out1 to out4) of the DAC33.

[0160] As shown in FIG. 9B , the first DAC 331 includes two analog output ports (out1 and out2) and one digital input port (in1). The second DAC 332 includes two analog output ports (out3 and out4) and one digital input port (in2). The controller 24 includes two digital output ports (out5 and out6). The digital output port out5 of the controller 24 is coupled to the digital input port in1 of the first DAC 331, and the digital output port out6 of the controller 24 is coupled to the digital input port in2 of the second DAC 332. The controller 24 outputs two control signals (control signal 1 and control signal 2) to the first DAC 331 sequentially in a specific order through the digital output port out5 of the controller 24. After receiving the two digital signals, the first DAC 331 analyzes the two digital signals in a specific order to obtain the two control signals, and outputs the two control signals separately. Digital Analog Perform a conversion to obtain two analog signals, the first DAC 331The controller 24 outputs two control signals (control signal 3 and control signal 4) to the second DAC 332 in a specific order through the digital output port out6 of the controller 24. After receiving the two digital signals, the second DAC 332 analyzes the two digital signals in a specific order to obtain the two control signals, and outputs two analog signals separately for the two control signals. Digital Analog The conversion is performed to obtain two analog signals, and the two analog signals are output separately through the two analog output ports (out3 and out4) of the second DAC 332.

[0161] As shown in FIG. 9C, the DAC33 includes four analog output ports (out1 to out4) and two digital input ports (in1 and in2). The controller 24 includes two digital output ports (out5 and out6). The digital output port out5 of the controller 24 is coupled to the digital input port in1 of the DAC33, and the digital output port out6 of the controller 24 is coupled to the digital input port in2 of the DAC33. The controller 24 outputs two control signals (control signal 1 and control signal 2) to the DAC33 sequentially in a specific order through the digital output port out5 of the controller 24. After receiving the two digital signals, the DAC33 analyzes the two digital signals in a specific order to obtain the two control signals, and outputs the control signals separately for the two control signals. Digital Analog The controller 24 performs conversion to obtain two analog signals, and outputs the two analog signals separately through two analog output ports (out1 and out2) of the DAC 33. The controller 24 outputs two control signals (control signal 3 and control signal 4) to the DAC 33 in a specific order successively through a digital output port out6 of the controller 24. After receiving the two digital signals, the DAC 33 analyzes the two digital signals in a specific order to obtain two control signals, and outputs the two control signals separately. Digital AnalogConversion is performed to obtain two analog signals, which are then output separately through two analog output ports (out3 and out4) of the DAC 33. It is more common for the total number of digital signals input from the input ports in1 and in2 of the DAC 33 to be four, but the number of digital signals input from the input ports in1 and in2, respectively, and the correspondence between this number and the corresponding control signals 1 to 4 are not limited.

[0162] As shown in FIG. 9D , the first DAC 331 includes four analog output ports (out1 to out4) and one digital input port (in1). The second DAC 332 includes two analog output ports (out5 and out6) and one digital input port (in2). The controller 24 includes two digital output ports (out7 and out8). The digital output port out7 of the controller 24 is coupled to the digital input port in1 of the first DAC 331, and the digital output port out8 of the controller 24 is coupled to the digital input port in2 of the second DAC 332. The controller 24 outputs four control signals (control signal 1 to control signal 4) to the first DAC 331 sequentially in a specific order through the digital output port out7 of the controller 24. After receiving the four digital signals, the first DAC 331 analyzes the four digital signals in a specific order to obtain the four control signals and outputs the four control signals separately. Digital Analog The controller 24 performs conversion to obtain four analog signals, and outputs the four analog signals separately through four analog output ports (out1 to out4) of the first DAC 331. The controller 24 outputs two control signals (control signal 5 and control signal 6) to the second DAC 332 in a specific order consecutively through the digital output port out8 of the controller 24. After receiving the two digital signals, the second DAC 332 analyzes the two digital signals in a specific order to obtain two control signals, and outputs the two control signals separately. Digital AnalogThe conversion is performed to obtain two analog signals, and the two analog signals are output separately through the two analog output ports (out5 and out6) of the second DAC 332.

[0163] The coupling schemes shown in Figures 8A, 8B, 8C, 8D, 9A, 9B, 9C, and 9D improve the design flexibility of the optoelectronic assembly, and further reduce the resource requirements for the analog-to-digital conversion interface and the digital-to-analog conversion interface, reducing the number of ADCs and DACs, reducing costs, improving integration, and facilitating the miniaturization of the optoelectronic assembly. For example, when an ADC converts two analog signals into one digital signal, 50% of the ADCs can be reduced. When an ADC can convert more analog signals into one digital signal, more ADCs can be reduced. When a DAC converts two digital signals into one analog signal, 50% of the DACs can be reduced. When a DAC can convert more digital signals into one analog signal, more DACs can be reduced.

[0164] A specific coupling scheme between the ADC 32, the DAC 33 and the controller 24 will be described below with reference to FIG.

[0165] 10 , the power supply 25 provides power supply voltages Vcc1 and Vcc2 to the entire opto-electrical assembly. The first voltage conversion circuit 211 converts the voltage Vcc1 into a bias voltage 1 and provides the bias voltage 1 to the first opto-electrical semiconductor device 221. The bias voltage 1 output by the first voltage conversion circuit 211 can be adjusted based on a control signal Z1 output by the controller 24. The second voltage conversion circuit 212 converts the voltage Vcc2 into a bias voltage 2 and provides the bias voltage 2 to the second opto-electrical semiconductor device 222. The bias voltage 2 output by the second voltage conversion circuit 212 can be adjusted based on a control signal Z2 output by the controller 24. At least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212 can be a DC-DC conversion circuit. For example, 0.9*Vcc1>bias voltage 1>1.0V, and Vcc1>1.3V, 0.9*Vcc2>bias voltage 2>1.0V, and Vcc2>1.3V.

[0166] It should be noted that although this embodiment of the present application is described using an example in which two voltage conversion circuits respectively provide bias voltages to two opto-electrical semiconductor devices, this is not intended to be limiting. For example, more voltage conversion circuits may respectively provide bias voltages to more opto-electrical semiconductor devices.

[0167] The output light of the first opto-electrical semiconductor device 221 includes two portions. The first portion is output light 1, and the second portion (backlight 1) is output to a first opto-electrical detection circuit 231 for detecting the optical power of the first opto-electrical semiconductor device 221. The output light of the second opto-electrical semiconductor device 222 includes two portions. The first portion is output light 2, and the second portion (backlight 2) is output to a second opto-electrical detection circuit 232 for detecting the optical power of the second opto-electrical semiconductor device 222. The resistance values ​​of the first opto-electrical semiconductor device 221 and the second opto-electrical semiconductor device 222 within the target optical power range are both less than or equal to 60 Ω, and the differential resistance values ​​Rdiff of the first opto-electrical semiconductor device and the second opto-electrical semiconductor device within the target optical power range satisfy 0.1 Ω≦Rdiff≦50 Ω.

[0168] The first opto-electrical detection circuit 231 is configured to detect the output optical power output by the first opto-electrical semiconductor device 221, and the second opto-electrical detection circuit 232 is configured to detect the output optical power output by the second opto-electrical semiconductor device 222.

[0169] The ADC 32 includes two analog input ports, which respectively receive the backlight sampling voltage Y1 (analog signal) from the first photoelectric detection circuit 231 and the backlight sampling voltage Y2 (analog signal) from the second photoelectric detection circuit 232. The ADC 32 converts the backlight sampling voltage Y1 (analog signal) into a backlight sampling voltage Y1 (digital signal) and converts the backlight sampling voltage Y2 (analog signal) into a backlight sampling voltage Y2 (digital signal), and outputs the two digital signals to the controller 24 sequentially in a specific order through a digital output port. The ADC converts the two signals into one signal, which can reduce ADC resources by 50%.

[0170] The controller 24 analyzes the backlight sampling voltage (digital signal) by the ADC 32 in a specific order according to the rule to output the backlight sampling voltage Y1 (digital signal). signal ) and a backlight sampling voltage Y2 (digital signal). The controller 24 generates a control signal Z1 (digital signal) based on the backlight sampling voltage Y1 (digital signal), generates a control signal Z2 (digital signal) based on the backlight sampling voltage Y2 (digital signal), and outputs the two control signals to the DAC 33 through a digital output port in a specific order.

[0171] The DAC33 obtains the control signal Z1 (digital signal) and the control signal Z2 (digital signal) in a specific order according to the corresponding rule of outputting the control signal by the controller 24. The DAC33 performs digital-to-analog conversion on the control signal Z1 (digital signal) to obtain the control signal Z1 (analog signal), and outputs the control signal Z1 (analog signal) to the first feedback network 311 through the analog output port. The DAC33 performs digital-to-analog conversion on the control signal Z2 (digital signal) to obtain the control signal Z2 (analog signal), and outputs the control signal Z2 (analog signal) to the second feedback network 312 through the analog output port. The DAC converts one signal into two signals, which can reduce 50% of the DAC resources.

[0172] The first feedback network 311 is configured to increase or decrease the voltage range of the control signal Z1 to obtain a feedback control signal F1, and output the feedback control signal F1 to the feedback end of the first voltage conversion circuit 211 to meet the requirements for the range of the signal input by the first voltage conversion circuit 211 and equivalently improve the accuracy of the control signal Z1. The second feedback network 312 is configured to increase or decrease the voltage range of the control signal Z2 to obtain a feedback control signal F2, and output the feedback control signal F2 to the feedback end of the second voltage conversion circuit 212 to meet the requirements for the range of the signal input by the second voltage conversion circuit 212 and equivalently improve the accuracy of the control signal Z2. The bias voltage 1 output by the first voltage conversion circuit 211 can be adjusted based on the feedback control signal F1, and the bias voltage 2 output by the second voltage conversion circuit 212 can be adjusted based on the feedback control signal F2.

[0173] The following describes how the controller 24 obtains the load link information X.

[0174] In a possible implementation shown in FIG. 11 based on FIG. 2 , when the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input) and a digital-to-analog conversion interface (in other words, an analog signal can be directly output), or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are sufficient, the controller 24 can directly obtain the load link information X from the bias voltage output terminal of the voltage conversion circuit 21.

[0175] 12 based on FIG. 3 , when the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. The analog input port of the second ADC 34 is coupled to the bias voltage output terminal of the voltage conversion circuit 21, and the digital output port of the second ADC 34 is coupled to the input terminal of the controller 24. The controller 24 may use the second ADC 34 to obtain the load link information X from the bias voltage output terminal of the voltage conversion circuit 21. When the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input), or when the resources of the analog-to-digital conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. The analog input port of the second ADC 34 is coupled to the bias voltage output terminal of the voltage conversion circuit 21, and the digital output port of the second ADC 34 is coupled to the input terminal of the controller 24. The controller 24 may use the second ADC 34 to obtain the load link information X from the bias voltage output terminal of the voltage conversion circuit 21. When the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input), or when the analog-to-digital conversion interface of the controller 24 is insufficient, the optoelectric assembly may further include a second ADC 34. Resources is sufficient, the second ADC 34 can be the analog-to-digital conversion interface of the controller 24.

[0176] In addition, the second ADC 34 and the ADC 32 may be ADCs with two analog inputs and one digital output, and the two analog input ports of the ADCs may be respectively coupled to the bias voltage output terminal of the voltage conversion circuit 21 and the output terminal of the photoelectric detection circuit 23. The ADCs may successively output the load link information X and the backlight sampling voltage Y to the controller 24 in a specific order, and the controller 24 may obtain the load link information X and the backlight sampling voltage Y by analyzing them in a specific order. This can reduce the quantity of ADCs, reduce costs, improve integration, and facilitate the miniaturization of the photoelectric assembly.

[0177] 10 , when the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. Two analog input ports of the second ADC 34 are respectively coupled to the output terminal of the first voltage conversion circuit 211 and the output terminal of the second voltage conversion circuit 212, and a digital output port of the second ADC 34 is coupled to the controller 24. The controller 24 may use the second ADC 34 to obtain load link information X1 from the output terminal of the first voltage conversion circuit 211 and may use the second ADC 34 to obtain load link information X2 from the output terminal of the second voltage conversion circuit 212. The second ADC 34 performs analog-to-digital conversion on the load link information X1 and the load link information X2 separately to obtain two digital signals, and outputs the two digital signals to the controller 24 successively in a specific order through the digital output port of the second ADC 34. The controller 24 may obtain the load link information X1 and the load link information X2 through analysis in a specific order. The controller 24 may determine a control signal Z1 based on the load link information X1 and the backlight sampling voltage Y1, and output the control signal Z1 to the first voltage conversion circuit 211. The controller 24 may determine a control signal Z2 based on the load link information X2 and the backlight sampling voltage Y2, and output the control signal Z2 to the second voltage conversion circuit 212. When the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input), or when the analog-to-digital conversion interface of the controller 24 is Resources is sufficient, the second ADC 34 can be the analog-to-digital conversion interface of the controller 24.

[0178] Additionally, the second ADC 34 and the ADC 32 may be ADCs with four analog inputs and one digital output. The four analog input ports of the ADCs may be coupled to the output terminals of the first voltage conversion circuit 211, the second voltage conversion circuit 212, the first photoelectric detection circuit 231, and the second photoelectric detection circuit 232, respectively. 32 teeth, Second ADC3 4 Through the digital output ports, the load link information X1, the load link information X2, the backlight sampling voltage Y1, and the backlight sampling voltage Y2 can be output to the controller 24 in a specific order. The controller 24 can obtain the load link information X1, the load link information X2, the backlight sampling voltage Y1, and the backlight sampling voltage Y2 through analysis in a specific order. This can reduce the number of ADCs, reduce costs, improve integration, and facilitate miniaturization of the photoelectric assembly.

[0179] In yet another possible implementation shown in FIG. 14 based on FIG. 2, the voltage conversion circuit 21 further has an information output terminal, which is coupled to the information input terminal of the controller 24, and the information output terminal is configured to output the load link information X to the controller 24.

[0180] In yet another possible implementation shown in FIG. 15 based on FIG. 3 , the voltage conversion circuit 21 further has an information output end, which is configured to output the load link information X, where the load link information X is an analog signal. When the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. An analog input port of the second ADC 34 is coupled to the information output end of the voltage conversion circuit 21, and a digital output port of the second ADC 34 is coupled to the input end of the controller 24. The second ADC 34 performs analog-to-digital conversion on the load link information X to obtain a digital signal and outputs the digital signal to the controller 24 through the digital output port of the second ADC 34.

[0181] In addition, the second ADC 34 and the ADC 32 may be ADCs with two analog inputs and one digital output, and the two analog input ports of the ADCs may be respectively coupled to the information output terminal of the voltage conversion circuit 21 and the output terminal of the photoelectric detection circuit 23. The ADCs may sequentially output the load link information X and the backlight sampling voltage Y to the controller 24 in a specific order, and the controller 24 may obtain the load link information X and the backlight sampling voltage Y through analysis in a specific order. This can reduce the number of ADCs, reduce costs, improve integration, and facilitate the miniaturization of the photoelectric assembly.

[0182] In addition, the optoelectric assembly may further include a temperature control drive circuit and a temperature control circuit. The temperature control drive circuit is configured to supply power to the temperature control circuit. The temperature control circuit is configured to perform temperature control (e.g., perform cooling or heating) on ​​the optoelectric semiconductor device 22, so that the optoelectric semiconductor device 22 operates at a preset operating temperature to increase output optical power or extend the service life of the optoelectric semiconductor device 22. For example, the temperature control circuit may be a thermoelectric cooler (TEC).

[0183] 2, in a possible implementation, the photoelectric assembly may further include a temperature control drive circuit 41 and a temperature control circuit 42. The power supply 25 is configured to supply power to the entire photoelectric assembly, and the power supply 25 may have at least three voltage output terminals for supplying a power supply voltage Vcc_a to the voltage conversion circuit 21, a power supply voltage Vcc_b to the temperature control drive circuit 41, and a power supply voltage Vcc_c to the controller 24. For example, the power supply 25 is installed outside the entire photoelectric assembly and has three voltage output terminals. Power supply voltage Power supply voltages Vcc_a, Vcc_b, and Vcc_c are supplied to the opto-electrical assembly. Power supply voltages Vcc_a, Vcc_b, and Vcc_c may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of devices coupled to power supply 25. In addition, power supply voltage Vcc_c may be used to power other devices such as ADCs and DACs.

[0184] In addition, the value of the power supply voltage Vcc_a may be optimized and set based on the input / output voltage change efficiency curve of the voltage conversion circuit 21 to improve the voltage conversion efficiency of the voltage conversion circuit 21 as much as possible. The value of the power supply voltage Vcc_b may be optimized and set based on the voltage, current, cooling capacity, heating capacity, cooling power consumption, heating power consumption, etc. of the temperature control drive circuit 41 and the temperature control circuit 42 to improve the power supply energy efficiency of the temperature control circuit 42. The value of the power supply voltage Vcc_c may be optimized and set based on the voltage, current, and power consumption of devices such as the controller 24, ADC, and DAC to ensure normal operation of the devices and improve system stability.

[0185] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0186] The power supply voltage Vcc_b may be in the range of 2V to 18V. For example, the power supply voltage Vcc_b may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0187] The power supply voltage Vcc_c may be in a range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in a range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0188] The voltage ripple obtained by filtering the bias voltage output from the voltage conversion circuit 21 is 50mV. V Further, the voltage ripple is less than or equal to 40 mV. Further, the voltage ripple is less than or equal to 30 mV. Further, the voltage ripple is less than or equal to 20 mV. Further, the voltage ripple is less than or equal to 10 mV. And further, the voltage ripple is less than or equal to 5 mV. A smaller voltage ripple indicates a smaller change in current in the optoelectronic semiconductor device caused by the voltage ripple and a smaller impact on the target optical power.

[0189] The following describes the coupling method between the power supply 25, the voltage conversion circuit 21, the temperature control drive circuit 41, and the controller 24 with reference to Fig. 17. For ease of explanation, please refer to the descriptions of other accompanying drawings for the configurations, functions, and coupling methods of other functional modules.

[0190] 17A, the power supply 25 is configured to supply power to the entire photoelectric assembly, and the power supply 25 may have at least one voltage output terminal for supplying a power supply voltage Vcc_a to the voltage conversion circuit 21, the temperature control drive circuit 41, and the controller 24. The value of the power supply voltage Vcc_a may be determined based on the current or voltage characteristics of devices coupled to the power supply 25. In addition, the power supply voltage Vcc_a may also be used to power other devices such as an ADC and a DAC.

[0191] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be in the range of 2V to 6V. Furthermore, the power supply voltage Vcc_a may be in the range of 2V to 3.6V. Furthermore, the power supply voltage Vcc_a may be 3.3V. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0192] 17B, ​​the power supply 25 is configured to supply power to the entire photoelectric assembly, and the power supply 25 may have at least two voltage outputs for supplying a power supply voltage Vcc_a to the voltage conversion circuit 21 and the temperature control drive circuit 41, and for supplying a power supply voltage Vcc_c to the controller 24. The power supply voltages Vcc_a and Vcc_c may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of devices coupled to the power supply 25. In addition, the power supply voltage Vcc_c may be used to power other devices, such as an ADC and a DAC.

[0193] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0194] The power supply voltage Vcc_c may be in a range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in a range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0195] 17C, the power supply 25 is configured to supply power to the entire photoelectric assembly, and the power supply 25 may have at least two voltage outputs for supplying a power supply voltage Vcc_a to the voltage conversion circuit 21 and the controller 24 and a power supply voltage Vcc_b to the temperature control drive circuit 41. The power supply voltages Vcc_a and Vcc_b may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of devices coupled to the power supply 25. In addition, the power supply voltage Vcc_a may be used to power other devices such as an ADC and a DAC.

[0196] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0197] The power supply voltage Vcc_b may be in the range of 2V to 18V. For example, the power supply voltage Vcc_b may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0198] 17D, the power supply 25 is configured to supply power to the entire photoelectric assembly, and the power supply 25 may have at least two voltage outputs for supplying a power supply voltage Vcc_c to the temperature control drive circuit 41 and the controller 24 and a power supply voltage Vcc_a to the voltage conversion circuit 21. The power supply voltages Vcc_a and Vcc_c may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of devices coupled to the power supply 25. In addition, the power supply voltage Vcc_c may be used to power other devices such as an ADC and a DAC.

[0199] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0200] The power supply voltage Vcc_c may be in a range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in a range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0201] In various coupling methods between the power supply 25, the voltage conversion circuit 21, the temperature control drive circuit 41, and the controller 24, the power supply voltage provided by the power supply 25 is determined based on the load characteristics of the device coupled to the power supply 25. This can improve power supply energy efficiency, reduce power consumption, and improve system stability.

[0202] In addition, the voltage conversion circuit 21 may further have an enable terminal. When an enable signal is input from the enable terminal, the voltage conversion circuit 21 is enabled and outputs a bias voltage to the opto-electrical semiconductor device 22 to drive the opto-electrical semiconductor device 22 to emit light or amplify light from a light source. When a disable signal is input from the enable terminal, the voltage conversion circuit 21 is disabled and does not output a bias voltage to the opto-electrical semiconductor device 22, so that the opto-electrical semiconductor device 22 does not emit light or cannot amplify light from a light source. It should be noted that the enable signal and the disable signal may be signals of different levels.

[0203] For example, as shown in FIG. 18 based on FIG. 10, each of the first voltage conversion circuit 211 and the second voltage conversion circuit 212 may further have an enable terminal, and the enable terminals of all the voltage conversion circuits 21 may be separately controlled by different pins of the controller 24 or may be centrally controlled by the same pin of the controller 24. When the enable terminals of all the voltage conversion circuits 21 are separately controlled by different pins of the controller 24, the controller 24 can enable or disable at least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212, that is, separate control can be implemented for different load links, so that all the optoelectronic semiconductor devices 22 are turned on or off separately. When the enable terminals of multiple voltage conversion circuits 21 are centrally controlled by the same pin of the controller 24, the multiple optoelectronic semiconductor devices 22 can be turned on or off together, which saves the pin resources of the controller 24.

[0204] When the entire optoelectronic assembly is initialized, the controller 24 outputs a disable signal to disable all voltage conversion circuits 21 (at least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212). After outputting a preset control signal, the controller 24 outputs an enable signal to enable all voltage conversion circuits 21. Alternatively, during the initialization process of the controller 24, the disable signal can be input from the enable terminal of the voltage conversion circuit 21 based on a fixed high / low level as an input or via another logic gate circuit, so that the voltage conversion circuit 21 is disabled during the initialization process of the controller 24. Alternatively, the enable terminal of the voltage conversion circuit 21 can be coupled to a soft start circuit. During the initialization process of the controller 24, after the soft start circuit is powered on for soft startup, the soft start circuit outputs an enable signal to enable the voltage conversion circuit 21, thereby turning on the optoelectronic semiconductor device 22. This can avoid an excessively large bias voltage output by the voltage conversion circuit 21 due to an unstable control signal Z in the initialization process. Otherwise, when the voltage conversion circuit 21 is enabled before the controller 24 outputs the control signal Z, the bias voltage output by the voltage conversion circuit 21 will not be controlled and may therefore become excessively large. As a result, the photoelectric semiconductor device 22 in the load link will be burned out. In addition, these methods can be combined.

[0205] As shown in FIG. 19, when the opto-electrical assembly shown in FIG. 3 includes one voltage conversion circuit 21, for example, when the controller 24 executes enable control to turn on or off the voltage conversion circuit 21, the controller 24 may execute the following control method for the opto-electrical assembly.

[0206] S101: The controller 24 performs initialization after the opto-electrical assembly is powered on.

[0207] S102: The controller 24 outputs a disable signal to the enable terminal of the voltage conversion circuit 21 to disable the voltage conversion circuit 21.

[0208] S103: The controller 24 outputs a preset control signal to the feedback terminal of the voltage conversion circuit 21.

[0209] The preset control signal may control the voltage conversion circuit 21 to output a default bias voltage to the opto-electrical semiconductor device 22. The DAC 33 may perform digital-to-analog conversion on the preset control signal, and the feedback network 31 may increase or decrease the preset control signal.

[0210] S104: The controller 24 outputs an enable signal to the enable terminal of the voltage conversion circuit 21 to enable the voltage conversion circuit 21.

[0211] The photoelectric semiconductor device 22 emits light or amplifies the light from the light source, and the photoelectric detection circuit 23 outputs a backlight sampling voltage Y.

[0212] S105: The controller 24 obtains the backlight sampling voltage Y from the photoelectric detection circuit 23, calculates the photocurrent of the photoelectric detection circuit 23 according to the backlight sampling voltage Y, and further calculates the optical power of the photoelectric semiconductor device 22 to determine whether the optical power meets the requirements.

[0213] If the requirements are met, step S106 is executed and then step S105 is executed again, or if the requirements are not met, step S107 is executed and then step S105 is executed again to implement dynamic real-time APC.

[0214] S106: The controller 24 maintains the control signal Z that was previously output.

[0215] In this step, the bias voltage output by the voltage conversion circuit 21 is stabilized within a specific range, and further, the output optical power output by the optoelectronic semiconductor device 22 is stabilized within a specific range.

[0216] S107: The controller 24 obtains the control signal Z based on the backlight sampling voltage Y, and outputs the control signal Z to the feedback terminal of the voltage conversion circuit 21.

[0217] In this step, the bias voltage output by the voltage conversion circuit 21 is changed to change the output optical power output by the optoelectronic semiconductor device 22 .

[0218] As shown in FIG. 20, when the opto-electrical assembly shown in FIG. 18 includes a plurality of voltage conversion circuits 21, the controller 24 can execute the following control method for the opto-electrical assembly.

[0219] S201: The controller 24 performs initialization after the opto-electrical assembly is powered on.

[0220] S202: The controller 24 outputs a disable signal 1 to the enable terminal of the first voltage conversion circuit 211 to disable the first voltage conversion circuit 211, and outputs a disable signal 2 to the enable terminal of the second voltage conversion circuit 212, thereby disabling the second voltage conversion circuit 212.

[0221] S203: The controller 24 outputs a preset control signal to the feedback terminal of the first voltage conversion circuit 211 and the feedback terminal of the second voltage conversion circuit 212.

[0222] The preset control signal output by the controller 24 to the feedback end of the first voltage conversion circuit 211 may control the first voltage conversion circuit 211 to output a preset bias voltage to the first optoelectric semiconductor device 221. The preset control signal output by the controller 24 to the feedback end of the second voltage conversion circuit 212 may control the second voltage conversion circuit 212 to output a preset bias voltage to the second optoelectric semiconductor device 222. The two preset control signals may be the same or different. The two preset control signals may be sent to the DAC 33 in a specific order, and the DAC 33 performs digital-to-analog conversion on the two preset control signals, or the two preset control signals may be increased or decreased by the first feedback network 311 and the second feedback network 312, respectively.

[0223] S204: The controller 24 outputs an enable signal 1 to the enable terminal of the first voltage conversion circuit 211 to enable the first voltage conversion circuit 211, and outputs an enable signal 2 to the enable terminal of the second voltage conversion circuit 212 to enable the second voltage conversion circuit 212.

[0224] The first optoelectric semiconductor device 221 emits light or amplifies light from the light source, and the first optoelectric detection circuit 231 outputs a backlight sampling voltage Y1. The second optoelectric semiconductor device 222 emits light or amplifies light from the light source, and the second optoelectric detection circuit 232 outputs a backlight sampling voltage Y2. The ADC 32 may perform analog-to-digital conversion on the backlight sampling voltage Y1 and the backlight sampling voltage Y2, and then the signals obtained through analog-to-digital conversion are output to the controller 24 in a specific order.

[0225] S205: The controller 24 obtains the backlight sampling voltage from the photoelectric detection circuit of the i-th APC loop, calculates the photocurrent of the photoelectric detection circuit of the i-th APC loop based on the backlight sampling voltage, and further calculates the optical power of the photoelectric semiconductor device of the i-th APC loop to determine whether the optical power meets the requirement.

[0226] 18 includes two APC loops, where the value of i may be 1 or 2. In the first APC loop, the controller 24 obtains a backlight sampling voltage Y1 from the first optoelectric detection circuit 231, calculates a photocurrent of the first optoelectric detection circuit 231 based on the backlight sampling voltage Y1, and further calculates the optical power of the first optoelectric semiconductor device 221 to determine whether the optical power meets the requirement. In the second APC loop, the controller 24 obtains a backlight sampling voltage Y2 from the second optoelectric detection circuit 232, calculates a photocurrent of the second optoelectric detection circuit 232 based on the backlight sampling voltage Y2, and further calculates the optical power of the second optoelectric semiconductor device 222 to determine whether the optical power meets the requirement.

[0227] If the requirement is met, step S206 is executed and then step S205 is executed again, or if the requirement is not met, step S207 is executed and then step S205 is executed again to implement dynamic real-time APC for the i-th APC loop.

[0228] It should be noted that if the output optical power output by one APC loop meets the requirement but the output optical power output by another APC loop does not meet the requirement, the controller 24 may set a software delay, and the two APC loops will enter step S205 again at the same time after different step procedures, to simplify the program control algorithm design and implement the synchronization of different APC loops.

[0229] Alternatively, the controller 24 may synchronize two APC loops when outputting the control signals Z of different APC loops to the DAC 33, and the controller 24 converts the two parallel control signals Z into serial signals according to a specific rule and outputs the serial signals to the DAC 33. The DAC 33 decomposes and converts the serial digital signal into two analog signals according to a corresponding rule and outputs the two analog signals to the feedback ends of the first feedback network 311 and the second feedback network 312, respectively.

[0230] S206: The controller 24 maintains the control signal Zi previously output to the i-th APC loop.

[0231] In this step, the bias voltage output by the voltage conversion circuit 21 of the i-th APC loop is stabilized within a specific range, and further, the output optical power output by the optoelectronic semiconductor device 22 of the i-th APC loop is stabilized within a specific range.

[0232] S207: The controller 24 obtains a control signal according to the backlight sampling voltage output by the photoelectric detection circuit of the i-th APC loop, and outputs the control signal Zi to the feedback end of the voltage conversion circuit of the i-th APC loop.

[0233] In this step, the bias voltage output by the voltage conversion circuit 21 of the i-th APC loop is changed to change the output optical power output by the optoelectronic semiconductor device 22 of the i-th APC loop.

[0234] For example, in the first APC loop, the controller 24 obtains a control signal Z1 based on the backlight sampling voltage Y1 and outputs the control signal Z1 to the feedback terminal of the first voltage conversion circuit 211. In the second APC loop, the controller 24 obtains a control signal Z2 based on the backlight sampling voltage Y2 and outputs the control signal Z2 to the feedback terminal of the second voltage conversion circuit 212.

[0235] The control method can be extended to scenarios with multiple APC loops, where independent control can be implemented for each APC loop.

[0236] According to the control method for an optoelectronic assembly provided in an embodiment of the present application, when the controller is initialized, the voltage conversion circuit is first disabled, and then the controller outputs a control signal to the voltage conversion circuit, after which the voltage conversion circuit is enabled. Alternatively, in the controller initialization process, the voltage conversion circuit may be disabled based on a fixed high / low level as an input or via another logic gate circuit. Alternatively, in the controller initialization process, the voltage conversion circuit may be enabled via a soft-start circuit to turn on the optoelectronic semiconductor device. In this way, the optoelectronic semiconductor device can be prevented from being burned out due to an unstable control signal in the initialization process and an excessively large bias voltage output by the voltage conversion circuit.

[0237] It should be understood that the sequence numbers of the above processes do not refer to the execution order in the embodiments of the present application, and the execution order of the processes should be determined based on the functions and internal logic of the processes, and should not constitute any limitation on the implementation method of the embodiments of the present application.

[0238] Those skilled in the art may recognize that, in combination with the examples described in the embodiments disclosed herein, the modules and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but this implementation should not be considered to exceed the scope of this application.

[0239] For the sake of convenience and conciseness, it can be clearly understood by those skilled in the art that for detailed operation processes of the aforementioned systems, devices, and modules, please refer to the corresponding processes in the aforementioned method embodiments, and the details will not be described again in this specification.

[0240] In some embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the described device embodiments are merely examples. For example, the division into modules is merely a logical division of function, and other divisions may be used in actual implementation. For example, multiple modules or components may be combined or integrated into another device, or some features may be omitted or not implemented. In addition, the shown or discussed mutual couplings or direct couplings or communication connections may be implemented via some interfaces. Indirect couplings or communication connections between devices or modules may be implemented in electrical, mechanical, or other forms.

[0241] Modules described as separate parts may or may not be physically separated, and parts shown as modules may or may not be physical modules, and may be located in one device or distributed across multiple devices. Some or all of the modules may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0242] In addition, the functional modules in the embodiments of the present application may be integrated into one device, or each of the modules may exist physically alone, or two or more modules may be integrated into one device.

[0243] All or part of the above-described embodiments may be implemented by software, hardware, firmware, or any combination thereof. When a software program is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, the procedures or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optics, or Digital Subscriber Line (DSL)) or wireless (e.g., infrared, radio, or microwave) techniques. A computer-readable storage medium may be any available medium that can be accessed by a computer, or may be a data storage device, such as a server or data center, that consolidates one or more available media. The available medium may be magnetic media (e.g., floppy disks, hard disk drives, or magnetic tapes), optical media (e.g., DVDs), semiconductor media (e.g., solid state drives (SSDs)), or the like.

[0244] The above description is merely a specific implementation of the present application and is not intended to limit the scope of protection of the present application. Any variations or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application shall fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of protection of the claims.

Claims

1. an opto-electric assembly comprising: a voltage conversion circuit; an opto-electric semiconductor device; an opto-electric detection circuit; and a controller; the voltage conversion circuit is configured to provide a bias voltage to the opto-electrical semiconductor device, and adjust the output optical power output by the opto-electrical semiconductor device by changing the bias voltage, wherein a differential resistance Rdiff of the opto-electrical semiconductor device within a target optical power range satisfies 0.1Ω≦Rdiff≦50Ω, and the differential resistance is a ratio of a voltage fluctuation to a current fluctuation corresponding to the voltage fluctuation; the opto-electrical detection circuit is configured to detect the output optical power output by the opto-electrical semiconductor device and output a detection signal to the controller; the controller is configured to determine a control signal based on the detection signal and output the control signal to the voltage conversion circuit, the control signal being used to adjust the bias voltage; the opto-electrical assembly further comprises a digital-to-analog converter and an analog-to-digital converter, wherein the bit widths of the digital-to-analog converter and the analog-to-digital converter respectively match the bit width of the digital signal processed by the controller; the opto-electrical assembly further comprises a feedback network, wherein the feedback network comprises a first resistor, a second resistor, and a third resistor, wherein a second end of the first resistor is grounded, a first end of the first resistor, a second end of the second resistor, and a first end of the third resistor are coupled to a feedback end of the voltage conversion circuit, a first end of the second resistor is coupled to an output end of the voltage conversion circuit, and a second end of the third resistor is coupled to an output end of the controller.

2. a differential resistance Rdiffsub of the opto-electrical semiconductor device within the sub-range of the target optical power and an average differential resistance Rdiffavg within the range of the target optical power satisfy max(0.02*Rdiffavg, 0.1Ω)≦Rdiffsub≦min(50*Rdiffavg, 50Ω); max(0.02*Rdiffavg, 0.1Ω) indicates the larger value of 0.02*Rdiffavg and 0.1Ω, and min(50*Rdiffavg, 50Ω) indicates the smaller value of 50*Rdiffavg and 50Ω.

2. The opto-electrical assembly of claim 1, wherein the average differential resistance Rdiffavg represents a ratio of a bias voltage fluctuation corresponding to a lower optical power limit and an upper optical power limit of the opto-electrical semiconductor device within the target optical power range to a corresponding current fluctuation.

3. 2. The opto-electrical assembly of claim 1, wherein the opto-electrical semiconductor device is a light source, the resistance of the light source being less than or equal to 60 ohms within the range of the target optical power.

4. 2. The opto-electrical assembly of claim 1, wherein the opto-electrical semiconductor device is an optical amplifier, and the resistance of the optical amplifier is less than or equal to 60 ohms within the range of the target optical power.

5. 4. The optoelectronic assembly of claim 3, wherein said voltage conversion circuit is a unique bias adjustment circuit for said optoelectronic semiconductor device.

6. 6. The opto-electrical assembly of claim 5, wherein the bit width of the digital signal processed by the controller is greater than or equal to 6 bits.

7. The controller The optoelectronic assembly of claim 1 , further configured to enable or disable the voltage conversion circuit.

8. The controller 2. The optoelectric assembly of claim 1, configured to obtain load link information and determine the control signal based on a value of the bias voltage and the detection signal, the load link information comprising the value of the bias voltage.

9. 10. The optoelectronic assembly of claim 1, further comprising a temperature control drive circuit and a temperature control circuit, the temperature control drive circuit configured to provide power to the temperature control circuit, and the temperature control circuit configured to perform temperature control on the optoelectronic semiconductor device.

10. 10. The optoelectronic assembly of claim 9, wherein the power supply voltage input by the temperature control drive circuit ranges from 2V to 18V.

11. 2. The optoelectronic assembly of claim 1, wherein the power supply voltage input by the voltage conversion circuit ranges from 1.8V to 18V.

12. 2. The optoelectronic assembly of claim 1, wherein the power supply voltage input by the controller ranges from 1.5V to 6V.

13. 2. The opto-electrical assembly according to claim 1, wherein a voltage ripple obtained by performing filtering on the bias voltage output by the voltage conversion circuit is less than or equal to 50 mV.

14. the voltage conversion circuit comprises a first voltage conversion circuit and a second voltage conversion circuit, the opto-electrical semiconductor device comprises a first opto-electrical semiconductor device and a second opto-electrical semiconductor device, and the opto-electrical detection circuit comprises a first opto-electrical detection circuit and a second opto-electrical detection circuit; the first opto-electrical detection circuit is configured to detect an output optical power output by the first opto-electrical semiconductor device and output a first detection signal to the controller; the second opto-electrical detection circuit is configured to detect an output optical power output by the second opto-electrical semiconductor device and output a second detection signal to the controller; 2. The opto-electrical assembly of claim 1, wherein the controller is configured to: determine a first control signal based on the first detection signal and send the first control signal to the first voltage conversion circuit, where the first control signal is used to adjust a bias voltage provided to the first opto-electrical semiconductor device; and determine a second control signal based on the second detection signal and send the second control signal to the second voltage conversion circuit, where the second control signal is used to adjust a bias voltage provided to the second opto-electrical semiconductor device.

15. the controller is configured to continuously send the first control signal and the second control signal to the digital-to-analog converter; 15. The optoelectronic assembly of claim 14, wherein the digital-to-analog converter is configured to perform digital-to-analog conversion on the first control signal and output a signal obtained through the digital-to-analog conversion to the first voltage conversion circuit, and to perform digital-to-analog conversion on the second control signal and output a signal obtained through the digital-to-analog conversion to the second voltage conversion circuit.

16. 16. The opto-electrical assembly of claim 15, wherein the bit width of the digital-to-analog converter is greater than or equal to 6 bits.

17. the opto-electrical semiconductor device comprises a first opto-electrical semiconductor device and a second opto-electrical semiconductor device, the opto-electrical detection circuit comprises a first opto-electrical detection circuit and a second opto-electrical detection circuit; the first opto-electrical detection circuit is configured to detect an output optical power output by the first opto-electrical semiconductor device and output a first detection signal to the controller; the second opto-electrical detection circuit is configured to detect an output optical power output by the second opto-electrical semiconductor device and output a second detection signal to the controller; 2. The opto-electrical assembly of claim 1, wherein the controller is configured to determine the control signal based on the first detection signal and the second detection signal and send the control signal to the voltage conversion circuit, the control signal being used to adjust a bias voltage provided to the first opto-electrical semiconductor device and a bias voltage provided to the second opto-electrical semiconductor device.

18. 15. The optoelectric assembly of claim 14, wherein the analog-to-digital converter is configured to perform analog-to-digital conversion on the first detection signal, perform analog-to-digital conversion on the second detection signal, and continuously output the first detection signal and the second detection signal obtained through analog-to-digital conversion to the controller.

19. 20. The opto-electrical assembly of claim 18, wherein the bit width of the analog-to-digital converter is greater than or equal to 6 bits.

20. An optoelectronic assembly as described in claim 1, wherein the feedback network is configured to increase or decrease the voltage range of the control signal.

21. 21. The opto-electrical assembly of claim 20, wherein the output end of the controller is configured to output the control signal, and the feedback end of the voltage conversion circuit is configured to input the control signal whose voltage range is increased or decreased.

22. 2. The optoelectronic assembly of claim 1, wherein the voltage conversion circuit is a DC-DC conversion circuit.

23. 10. The optoelectronic assembly of claim 1, wherein the optoelectronic assembly is a light source or an optical amplifier, separate from an optical modulator.

24. 24. A light source pool comprising at least one opto-electric assembly according to any one of the preceding claims.

25. 24. An opto-electrical switching device comprising at least one of the opto-electrical assemblies according to any one of claims 1 to 23, an optical modulator, and a switching chip, wherein the opto-electrical assembly is configured to output light, and the switching chip is configured to control the optical modulator to modulate the light.

26. 26. The opto-electrical switching device of claim 25, wherein the opto-electrical switching device comprises a first controller configured to output a signal to a controller in the opto-electrical assembly to adjust the output optical power output by the opto-electrical assembly.

27. 24. A control method for an opto-electric assembly applied to the opto-electric assembly according to any one of claims 1 to 23, said method comprising the steps of: receiving a detection signal from an opto-electrical detection circuit in the opto-electrical assembly, the detection signal indicative of an output optical power output by an opto-electrical semiconductor device in the opto-electrical assembly; determining a control signal based on the detection signal and sending the control signal to a voltage conversion circuit in the opto-electrical assembly, the control signal being used to adjust a bias voltage; A control method for an optoelectronic assembly, comprising:

28. Disabling the voltage conversion circuit, outputting a preset control signal to the voltage conversion circuit, and enabling the voltage conversion circuit.

28. The method of claim 27, further comprising:

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