Photoelectric conversion device, photoelectric conversion system

Abstract

To provide a structure suitable for a specific device structure.SOLUTION: Each of a plurality of avalanche photodiodes includes an avalanche multiplication unit formed by a first semiconductor region of a first conductivity type that is disposed at a first depth, and a second semiconductor region of a second conductivity type different from the first conductivity type that is disposed at a second depth deeper than the first depth. A fourth semiconductor region at least one of a conductivity type and an impurity concentration of which is different from those of a third semiconductor region of the second conductivity type is disposed at a position shallower than the third semiconductor region, and a depth of a boundary portion between the third semiconductor region and the fourth semiconductor region is deeper than that of the avalanche multiplication unit.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] There is a known photodetector device that uses avalanche photodiodes (APDs) that can detect weak light at the single-photon level by utilizing avalanche multiplication. An APD forms a high-electric field region (avalanche multiplication section) by using a first semiconductor region of a first conductivity type that has the same polarity as the signal charge and a second semiconductor region of a second conductivity type that has the opposite polarity to the signal charge. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-201005 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the third semiconductor region that separates the pixels is provided to a position that is the same depth as the avalanche multiplication section in a cross-sectional view, and is disposed so as to surround the avalanche multiplication section in a plan view.

[0005] As the pixel size becomes smaller, the distance between the third semiconductor region and the avalanche multiplication section becomes shorter, which results in the formation of a local high electric field region between the third semiconductor region and the first semiconductor region, resulting in an increase in the dark count rate (hereinafter referred to as DCR). [Means for solving the problem]

[0006] According to one aspect, a photoelectric conversion device includes a semiconductor layer, a plurality of avalanche photodiodes arranged in the semiconductor layer, the avalanche photodiodes including a first avalanche photodiode and a second avalanche photodiode, each of the plurality of avalanche photodiodes having a majority carrier of the same conductivity type as a signal charge, and an avalanche multiplication section formed by a first semiconductor region of a first conductivity type arranged at a first depth, and a second semiconductor region of a second conductivity type different from the first conductivity type arranged at a second depth deeper than the first depth, the second semiconductor region having a conductivity type different from the first conductivity type, a third semiconductor region of the second conductivity type arranged between the first avalanche photodiode and the second avalanche photodiode, a fourth semiconductor region different from the third semiconductor region in at least one of conductivity type and impurity concentration arranged between the first avalanche photodiode and the second avalanche photodiode and at a position shallower than the third semiconductor region, and the depth of a boundary between the third semiconductor region and the fourth semiconductor region is deeper than the avalanche multiplication section.

[0007] According to another aspect, a photoelectric conversion device includes a semiconductor layer including a plurality of photoelectric conversion elements and having a first surface and a second surface opposite to the first surface and through which light is incident, wherein each of the plurality of photoelectric conversion elements includes an avalanche photodiode, and the avalanche photodiode has a first semiconductor region of a first conductivity type having charges of the same polarity as signal charges as majority carriers, and a second semiconductor region of a second conductivity type, each of the plurality of photoelectric conversion elements is separated by an isolation portion including a third semiconductor region of the second conductivity type, and the second semiconductor region is arranged in contact with the third semiconductor region, and the plurality of photoelectric conversion elements include first photoelectric conversion elements and second photoelectric conversion elements arranged adjacent to the first photoelectric conversion elements, and the third semiconductor region is arranged between the first photoelectric conversion elements and the second photoelectric conversion elements so that one end of the third semiconductor region is located closer to the second surface than the first surface and closer to the first surface than the second semiconductor region. [Effects of the Invention]

[0008] According to the photoelectric conversion device of the present invention, it is possible to provide a photoelectric conversion device that can achieve miniaturization of pixel size. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 2] Sensor board layout example [Figure 3] Circuit board layout example [Figure 4] Block diagram including equivalent circuit of photoelectric conversion element [Figure 5] A diagram showing the relationship between APD operation and output signal [Figure 6] Pixel plan view according to the first embodiment [Figure 7] 1 is a cross-sectional view of a pixel according to a first embodiment; [Figure 8] Pixel plan view according to the second embodiment [Figure 9] 10 is a cross-sectional view of a pixel according to a second embodiment. [Figure 10] Pixel plan view according to the third embodiment [Figure 11] 10 is a cross-sectional view of a pixel according to a third embodiment. [Figure 12] Pixel plan view according to the fourth embodiment [Figure 13] 10 is a cross-sectional view of a pixel according to a fourth embodiment. [Figure 14] Pixel plan view according to the fifth embodiment [Figure 15] 10 is a cross-sectional view of a pixel according to a fifth embodiment; [Figure 16] Pixel plan view according to the sixth embodiment [Figure 17] 10 is a cross-sectional view of a pixel according to a sixth embodiment; [Figure 18] Pixel plan view according to the seventh embodiment [Figure 19] 13 is a cross-sectional view of a pixel according to the seventh embodiment; [Figure 20] Photoelectric conversion system according to the eighth embodiment [Figure 21]13 is a schematic plan view of a photoelectric conversion device according to a ninth embodiment. [Figure 22] 13 is a schematic cross-sectional view of a photoelectric conversion device according to a ninth embodiment. [Figure 23] 13 is a potential diagram of a pixel of a photoelectric conversion device according to a ninth embodiment. [Figure 24] 13 is a schematic plan view of a photoelectric conversion device according to a tenth embodiment. [Figure 25] 13 is a schematic cross-sectional view of a photoelectric conversion device according to a tenth embodiment. [Figure 26] 13 is a schematic cross-sectional view of a photoelectric conversion device according to a tenth embodiment. [Figure 27] 11 is a schematic plan view of a photoelectric conversion device according to an eleventh embodiment. [Figure 28] 11 is a schematic cross-sectional view of a photoelectric conversion device according to an eleventh embodiment. [Figure 29] 11 is a schematic plan view of a photoelectric conversion device according to an eleventh embodiment. [Figure 30] 11 is a schematic cross-sectional view of a photoelectric conversion device according to an eleventh embodiment. [Figure 31] 12 is a schematic plan view of a photoelectric conversion device according to a twelfth embodiment. [Figure 32] 12 is a schematic cross-sectional view of a photoelectric conversion device according to a twelfth embodiment. [Figure 33] 13 is a schematic cross-sectional view of a photoelectric conversion device according to a thirteenth embodiment. [Figure 34] Method for manufacturing a photoelectric conversion device according to the fourteenth embodiment [Figure 35] Block diagram of a photoelectric conversion system according to a fifteenth embodiment. [Figure 36] Block diagram of a photoelectric conversion system according to a sixteenth embodiment. [Figure 37] Block diagram of a photoelectric conversion system according to a seventeenth embodiment. [Figure 38] Block diagram of a photoelectric conversion system according to an eighteenth embodiment. [Figure 39] FIG. 20 is a diagram showing a specific example of a photoelectric conversion system according to a 19th embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The embodiments described below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be assigned the same numbers and their description may be omitted. Furthermore, the configurations described in each embodiment may be mutually substituted or combined with the configurations described in other embodiments, provided that no technical problems arise.

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms containing these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the invention with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0012] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and a signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is an N-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is a P-type semiconductor region. The present invention also applies when the cathode of the APD is set to a fixed potential and a signal is extracted from the anode side. In this case, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is a P-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is an N-type semiconductor region. While the following description focuses on a case where one node of the APD is set to a fixed potential, the potentials of both nodes may fluctuate.

[0013] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0014] In this specification, the term "planar view" refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer described below or the surface opposite to the light incident surface. Furthermore, the term "cross section" refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0015] The semiconductor layer 301 has a first surface and a second surface opposite to the first surface, through which light is incident. In this specification, the depth direction is the direction from the first surface of the semiconductor layer 301 on which the APD is disposed toward the second surface. Hereinafter, the "first surface" may be referred to as the "front surface," and the "second surface" may be referred to as the "rear surface." The direction from a predetermined position on the semiconductor layer 301 toward the rear surface of the semiconductor layer 301 may be referred to as "deep." Furthermore, the direction from a predetermined position on the semiconductor layer 301 toward the front surface of the semiconductor layer 301 may be referred to as "shallow."

[0016] First, the configuration common to each embodiment will be described with reference to FIGS.

[0017] FIG. 1 is a diagram showing the configuration of a stacked-type photoelectric conversion device 100. The photoelectric conversion device 100 is configured by stacking and electrically connecting two substrates, a sensor substrate 11 and a circuit substrate 21. The sensor substrate 11 has a first semiconductor layer (semiconductor layer 301) having photoelectric conversion elements 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric conversion device 100 is configured by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in this order. The photoelectric conversion device described in each embodiment is a back-illuminated photoelectric conversion device in which light is incident from the second surface and a circuit substrate is disposed on the first surface.

[0018] In the following description, the sensor substrate 11 and the circuit substrate 21 are described as diced chips, but are not limited to chips. For example, each substrate may be a wafer. Also, each substrate may be stacked in the wafer state and then diced, or each chip may be stacked and bonded after being chipped from the wafer state.

[0019] The sensor substrate 11 has a pixel region 12 arranged thereon, and the circuit substrate 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0020] 2 is a diagram showing an example of the arrangement of the sensor substrate 11. Pixels 104, each having a photoelectric conversion element 102 including an APD, are arranged in a two-dimensional array in plan view to form a pixel region 12.

[0021] The pixel 104 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image, i.e., the pixel 104 may be a pixel for measuring the time and amount of light that arrives.

[0022] 3 is a configuration diagram of the circuit board 21. It has a signal processing unit 103 that processes the charges photoelectrically converted by the photoelectric conversion element 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0023] The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0024] The vertical scanning circuit unit 110 receives a control pulse supplied from the control pulse generating unit 115 and supplies the control pulse to each pixel. The vertical scanning circuit unit 110 uses logic circuits such as a shift register and an address decoder.

[0025] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and the memory holds digital values.

[0026] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0027] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0028] The signal output to the signal line 113 is output via an output circuit 114 to a recording unit or a signal processing unit outside the photoelectric conversion device 100 .

[0029] 2, the photoelectric conversion elements in the pixel region may be arranged one-dimensionally. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element, and for example, one signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0030] 2 and 3, a plurality of signal processing units 103 are arranged in a region overlapping the pixel region 12 in a planar view. A vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, a readout circuit 112, an output circuit 114, and a control pulse generation unit 115 are arranged so as to overlap between an end of the sensor substrate 11 and an end of the pixel region 12 in a planar view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged around the pixel region 12. The vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the readout circuit 112, the output circuit 114, and the control pulse generation unit 115 are arranged in a region overlapping the non-pixel region in a planar view.

[0031] FIG. 4 is an example of a block diagram including the equivalent circuits of FIGS.

[0032] In FIG. 2, the photoelectric conversion element 102 having the APD 201 is provided on a sensor substrate 11, and the other members are provided on a circuit board 21.

[0033] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With this voltage supplied, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0034] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode are operated at a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode are operated at a potential difference close to or less than the breakdown voltage.

[0035] An APD operated in Geiger mode is called a SPAD (single photon avalanche diode). For example, the voltage VL (first voltage) is −30 V, and the voltage VH (second voltage) is 3 V. The APD 201 may be operated in either linear mode or Geiger mode.

[0036] The quench element 202 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The quench element 202 also functions to return the voltage supplied to the APD 201 to voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0037] The signal processing unit 103 has a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may have any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0038] The waveform shaping unit 210 shapes the potential change at the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While an example using one inverter as the waveform shaping unit 210 is shown in FIG. 4, a circuit in which multiple inverters are connected in series, or another circuit having a waveform shaping effect, may also be used.

[0039] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0040] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 3 via a drive line 214 (not shown in Fig. 3) in Fig. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0041] The electrical connection may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0042] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0043] FIG. 5 is a diagram showing a schematic diagram of the relationship between the operation of an APD and an output signal.

[0044] Fig. 5(a) is a diagram illustrating the APD 201, quench element 202, and waveform shaping unit 210 of Fig. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. Fig. 5(b) shows the waveform change at node A in Fig. 5(a), and Fig. 5(c) shows the waveform change at node B in Fig. 5(a).

[0045] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. As the voltage drop increases and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, as shown at time t2, and the voltage level at node A drops no more than a certain value. After that, between time t2 and time t3, a current flows through node A from voltage VL to compensate for the voltage drop, and at time t3, node A settles to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0046] The arrangement of the signal lines 113, the readout circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the signal lines 113 may be arranged to extend in the row direction, and the readout circuits 112 may be arranged at the ends of the signal lines 113.

[0047] The photoelectric conversion devices of the respective embodiments will be described below.

[0048] (First embodiment) FIG. 6 is an enlarged plan view of a pixel portion of a photoelectric conversion device according to the first embodiment. In FIG. 6, APDs are arranged in a two-dimensional plane. In this embodiment, each pixel has one APD, so FIG. 6 is a plan view of a pixel portion having a 2×2 pixel array. FIG. 7(a) shows a cross-sectional view taken along dashed line A-A' in FIG. 6, and FIG. 7(b) shows a cross-sectional view taken along dashed line B-B' in FIG. The numbers in FIG. 6 correspond to the numbers in FIGS. 7(a) and (b). Details of each component will be described with reference to FIGS. 7(a) and (b).

[0049] In a plan view, the first APD and the third APD are arranged in a first direction, and the third APD and the second APD are arranged in a second direction perpendicular to the first direction. In FIG. 4, the first APD and the third APD are arranged in the direction opposite to each other, and the first APD and the second APD are arranged in the diagonal direction. For example, in FIG. 6, the APD on the upper left is the first APD, the APD on the upper right is the third APD, and the APD on the lower left is the second APD. Also, in FIG. 6, the distance between the first semiconductor region 311 of the first APD and the first semiconductor region 311 of the second APD is longer than the distance between the first semiconductor region 311 of the first APD and the first semiconductor region 311 of the third APD.

[0050] In the semiconductor layer 301 of FIG. 7(a), a first semiconductor region 311 of a first conductivity type and a second semiconductor region 312 of a second conductivity type are arranged. The first semiconductor region 311 and the second semiconductor region 312 form a PN junction, constituting an APD that forms an avalanche multiplication section. A contact plug 341 that supplies a voltage VL is formed in the first semiconductor region 311. The semiconductor layer 301 has a surface (first surface) 302 on which the contact plug is formed and a surface (second surface) 303 facing the first surface 302. In this embodiment, the second surface 303 is the light incident surface. As described above, the light incident surface is a surface when viewed macroscopically, and the first surface 302 and the second surface 303 do not have to be parallel to each other.

[0051] An isolation region 331 for reducing avalanche crosstalk is formed between adjacent pixels in FIG. 7(a). The isolation region 331 includes a trench structure. The trench structure is preferably made of a material that increases the reflectivity of photons generated in the avalanche multiplication unit 314 or a material that absorbs the generated photons. The isolation region 331 is made of, for example, a deep trench isolation (DTI) and an insulating material disposed inside the DTI. The isolation region 331 made of this insulating material reduces the intrusion of photons emitted in the high electric field region of the avalanche multiplication unit 314 into adjacent pixels. However, the isolation region 331 may be made of a trench structure containing a metal material such as copper or tungsten. This improves the light-shielding performance between pixels. Alternatively, the isolation region 331 may include a trench structure containing air (e.g., a vacuum) inside the trench structure.

[0052] The DTI may penetrate from the first surface 302 to the second surface 303. Alternatively, if the DTI is formed from the second surface, the end of the DTI may be positioned midway through the semiconductor layer 301 before reaching the first surface 302. In this case, it is preferable that the end of the DTI is positioned at a position shallower than the depth of the avalanche multiplication section 314. In this specification, the depth direction refers to the direction from the first surface 302 toward the second surface 303. By positioning the end of the DTI in this manner, avalanche crosstalk can be reduced. Preferably, the DTI is provided so as to penetrate the semiconductor layer. Note that in this embodiment, an example has been described in which a trench structure including a DTI is provided as the isolation region 331. However, the isolation region 331 is a component that is selectively provided, and the present invention also encompasses a configuration in which the isolation region 331 is not provided.

[0053] A third semiconductor region 321 of the second conductivity type is disposed on the sidewall of the isolation region 331. The third semiconductor region 321 serves to separate adjacent pixels. When the isolation region 331 is provided, it also serves to reduce dark current generated on the sidewall of the isolation region 331.

[0054] In this embodiment, the third semiconductor region 321 is disposed on the second surface 303 side, with the depth 402 as the boundary. In this manner, the first semiconductor region 311 of the first conductivity type and the third semiconductor region 321 of the second conductivity type are formed at different depths. The third semiconductor region 321 is disposed from the second surface 303 to the depth 402 so as to contact the sidewall of the isolation region 331, but is not disposed from the depth 402 to the first surface 302.

[0055] When the first semiconductor region 311 of the first conductivity type and a part of the third semiconductor region 321 of the second conductivity type are formed at the same depth, as the pixel size becomes smaller, the distance between the first semiconductor region 311 and the third semiconductor region 321 becomes smaller, which causes electric field concentration between the first semiconductor region 311 and the third semiconductor region 321, increasing the DCR.

[0056] In contrast, in the structure of this embodiment, the first semiconductor region 311 of the first conductivity type and the third semiconductor region 321 of the second conductivity type are formed at different depths. For example, in FIG. 7(a), the top surface of the third semiconductor region 321 of the second conductivity type is located lower than the bottom surface of the first semiconductor region 311 of the first conductivity type. Therefore, even when the pixel size is miniaturized, the distance between the two semiconductor regions can be increased compared to when the two semiconductor regions are formed at the same depth. As a result, an increase in DCR due to electric field concentration between the first semiconductor region 311 and the third semiconductor region 321 can be reduced.

[0057] Depth 402 is located deeper than depth 401, which is the PN junction surface of the APD. On the other hand, depth 402 is located shallower than depth 403, where second semiconductor region 312 is disposed. Here, depth 403 indicates a position half the depth occupied by second semiconductor region 312.

[0058] Of the dark current generated in the sidewall portion of the separation region 331, dark current charges generated at a position shallower than the depth 402 flow into the first semiconductor region 311 through the fifth semiconductor region 313, which has a lower potential than the avalanche multiplication section 314. This dark current component does not pass through the avalanche multiplication section 314. Therefore, the dark current charges are not avalanche multiplied and are not detected as an APD signal, and therefore are not counted as DCR. Therefore, even if the top surface of the second semiconductor region 312 does not reach the first surface 302, no DCR problem occurs.

[0059] A fifth semiconductor region 313 of the first conductivity type or the second conductivity type is disposed on both ends of the first semiconductor region 311 to relieve electric field concentration. In this case, the impurity concentration of the fifth semiconductor region 313 is set to be lower than the impurity concentration of the first semiconductor region 311. For example, when the impurity concentration of the first semiconductor region 311 is 6.0×10 18 [atms / cm 3 ] or more, the impurity concentration of the fifth semiconductor region 313 is 1.0×10 16 [atms / cm 3 ] or more, 1.0 × 10 18 [atms / cm 3 In this specification, the impurity concentration refers to the net impurity concentration of a given impurity, or the so-called NET doping concentration.

[0060] Furthermore, a sixth semiconductor region 315 of the second conductivity type is disposed in a region deeper than the second semiconductor region 312, and a seventh semiconductor region 316 of the second conductivity type is disposed in a region deeper than the sixth semiconductor region 315. At this time, the seventh semiconductor region 316 is configured to have a higher impurity concentration of the second conductivity type than the sixth semiconductor region 315. This allows the charge photoelectrically converted in the sixth semiconductor region 315 to pass through the avalanche multiplication section 314 disposed on the first surface 302 side without passing through to the second surface 303 side. This allows the signal charge to be efficiently read out and counted as an APD signal.

[0061] FIG. 7(b) is a cross-sectional view taken along dashed line B-B' in the diagonal direction of FIG. 6. This differs from FIG. 7(a) in that no isolation region 331 is provided between adjacent avalanche multiplication sections. Because avalanche crosstalk increases as the distance between adjacent avalanche multiplication sections decreases, providing an isolation region between adjacent avalanche multiplication sections in the opposite side direction rather than in the diagonal direction is more effective in suppressing avalanche crosstalk. As described above, the isolation region 331 is an isolation region formed by an insulating film such as an oxide film. By eliminating the isolation region 331 between diagonally arranged avalanche multiplication sections, a contact plug 342 can be formed to supply a potential VH to the APD. Furthermore, the contact plug 342 can be shared between different avalanche multiplication sections.

[0062] When carriers are avalanche-multiplied, photons emitted in a high electric field region may leak into adjacent pixels, resulting in avalanche crosstalk. Patent Document 1 discloses a method for reducing avalanche crosstalk by providing a trench structure as an inter-pixel isolation region and arranging an insulator inside the trench structure. Patent Document 1 also discloses a method for forming a third semiconductor region of the second conductivity type on the sidewall of the inter-pixel isolation region and supplying a voltage to the third semiconductor region from a contact connected to the anode.

[0063] An eighth semiconductor region 323 of the second conductivity type is disposed below the contact plug 342 to reduce contact resistance with the semiconductor layer 301. The impurity concentration of the eighth semiconductor region 323 may be approximately the same as that of the third semiconductor region 321. Alternatively, the impurity concentration of the eighth semiconductor region 323 may be higher than that of the third semiconductor region 321. The distance between the eighth semiconductor region 323 and the first semiconductor region 311 is greater in the diagonal direction than in the opposite side direction. This reduces the likelihood of electric field concentration between the first semiconductor region 311 and the eighth semiconductor region 323, thereby reducing the resulting increase in DCR. Therefore, as shown in FIG. 6 , the contact plug 342 and the eighth semiconductor region 323 are disposed between the diagonal pixels in a plan view, rather than between the opposite side pixels.

[0064] 7(b), a voltage VL is applied to the first semiconductor region 1311 through a contact plug 341, and a voltage VH is applied to the eighth semiconductor region 323 through a contact plug 342. The potential applied to the eighth semiconductor region 323 is supplied to the second semiconductor region 312 through the third semiconductor region 321 and the sixth semiconductor region 315. As a result, a reverse bias voltage is applied to the first conductivity type first semiconductor region 1311 and the second conductivity type second semiconductor region 312, and an avalanche multiplication section 314 can be formed.

[0065] 7(b), the contact plug 342 is disposed on the first surface 302 side, but a potential may be supplied to the third semiconductor region 321 from the second surface 303 side. In this case, there is no need to dispose the eighth semiconductor region 323, and therefore the avalanche multiplication sections 314 can be closer to each other in the diagonal direction.

[0066] 6, the avalanche multiplication section is arranged in a circular shape, and the third semiconductor region 321 provided below the eighth semiconductor region 323 is arranged in a rectangular shape in a plan view, but this embodiment is not limited to this. For example, the first semiconductor region 311 and the third semiconductor region 321 may have the same shape in a plan view. In this case, it is preferable to arrange the contact plug 342 on the second surface 303 side.

[0067] Although not shown, a planarization layer, a filter layer, a microlens, etc. may be disposed on the back surface of the semiconductor layer 301. The filter layer may be a variety of optical filters such as a color filter, an infrared light cut filter, or a monochrome filter. The color filter may be an RGB color filter, an RGBW color filter, etc.

[0068] With the above configuration, according to the first embodiment, it is possible to realize an APD that achieves miniaturization of pixel size. Furthermore, since the isolation region 331 is provided, it is possible to reduce avalanche crosstalk.

[0069] (Second embodiment) A photoelectric conversion device according to a second embodiment will be described with reference to Fig. 8, Fig. 9(a), and Fig. 9(b). Fig. 8 is a plan view of the photoelectric conversion device according to this embodiment, in which APDs are arranged in a 2x2 array on a two-dimensional plane. Fig. 9(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 8, and Fig. 9(b) shows a cross-sectional view taken along dashed line B-B'.

[0070] The photoelectric conversion device according to this embodiment differs from the first embodiment in that a fourth semiconductor region 322 is disposed on the sidewall of the isolation region 331 between the first surface 302 and the depth 402. Other than this point and points described below, the photoelectric conversion device according to this embodiment is substantially the same as the first embodiment, and therefore description thereof will be omitted.

[0071] The fourth semiconductor region 322 is disposed on the first surface 302 side, with the depth 402 as the boundary. The fourth semiconductor region 322 differs from the third semiconductor region 321 in at least one of the conductivity type and the impurity concentration. The fourth semiconductor region 322 may be a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type, or an intrinsic semiconductor region. When the fourth semiconductor region 322 is a semiconductor region of a second conductivity type, the fourth semiconductor region 322 is set to have a lower impurity concentration of the second conductivity type than the third semiconductor region 321. For example, the impurity concentration of the third semiconductor region 321 differs by four times or more from the impurity concentration of the fourth semiconductor region 322. As an example, when the impurity concentration of the third semiconductor region 321 is 1.0×10 17 [atms / cm 3 ], the impurity concentration of the fourth semiconductor region 322 is 1.0×10 16 [atms / cm 3 In addition, when the fourth semiconductor region is of the first conductivity type, the fourth semiconductor region 322 is set to have a lower impurity concentration of the first conductivity type than the first semiconductor region 311. For example, the fourth semiconductor region 322 and the first semiconductor region 311 have a difference of 10 times or more. As an example, when the impurity concentration of the first semiconductor region 311 is 6.0×10 18 [atms / cm 3 ], the impurity concentration of the fourth semiconductor region 322 is 1.0×10 16[atms / cm 3 The impurity concentration of the fourth semiconductor region may be approximately the same as that of the semiconductor layer 301, regardless of the polarity.

[0072] The fourth semiconductor region 322 is preferably a semiconductor region of the second conductivity type. When the depth 402 is located at a position deeper than the depth 403, part of the dark current generated at the sidewall of the isolation region 331, which is generated at a depth where the third semiconductor region 321 is not located, passes through the avalanche multiplication section 314, causing an increase in DCR.

[0073] 9(a), by arranging the depth 402 at a position shallower than the depth 403, among the dark currents generated on the sidewalls of the isolation region 331, dark current charges generated at a position deeper than the depth 402 are recombined in the second conductivity type third semiconductor region 321. Therefore, it is possible to reduce the increase in DCR.

[0074] According to this embodiment, an APD that can reduce the pixel size can be realized. In addition, since the isolation region 331 is provided, avalanche crosstalk can also be reduced.

[0075] (Third embodiment) A photoelectric conversion device according to a third embodiment will be described with reference to Fig. 10, Fig. 11(a), and Fig. 11(b). Fig. 10 is a plan view of a photoelectric conversion device according to this embodiment, in which APDs are arranged in a two-dimensional, planar configuration of 2 x 2. Fig. 11(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 10, and Fig. 11(b) shows a cross-sectional view taken along dashed line B-B'.

[0076] The photoelectric conversion device according to this embodiment differs from the second embodiment in that, in plan view, the width of the fourth semiconductor region 322 is narrower than the width of the third semiconductor region 321. Other than this point and points described below, the photoelectric conversion device according to this embodiment is substantially the same as the second embodiment, and therefore description thereof will be omitted.

[0077] In this specification, the "width of a semiconductor region" refers to the length in a direction perpendicular to the depth direction. For example, the width of the fourth semiconductor region 322 in Fig. 11(a) is the length in a direction from the interface between the isolation region 331 and the fourth semiconductor region 322 toward the fifth semiconductor region 311 in a cross section in the depth direction.

[0078] 10 and 11(a), the width (extension amount) of the fourth semiconductor region 322 is smaller than the width (extension amount) of the third semiconductor region 321 relative to the isolation region 331 by an offset C. That is, in a plan view, the distance from the isolation region 331 to the end of the fourth semiconductor region 322 on the first semiconductor region 311 side is smaller than the distance from the isolation region 331 to the end of the third semiconductor region 321 on the first semiconductor region 311 side. Here, the end of the fourth semiconductor region 322 on the first semiconductor region 311 side refers to the interface between the fourth semiconductor region 322 and the semiconductor region 324 between the fifth semiconductor region 313 and the fourth semiconductor region 322. The semiconductor region 324 is a semiconductor region different in at least one of the conductivity type and impurity concentration from the fourth semiconductor region 322 and the fifth semiconductor region 313. For example, the semiconductor region 324 is a semiconductor region of the first conductivity type and having a lower impurity concentration than the fifth semiconductor region 313. Moreover, the end of the third semiconductor region 321 on the first semiconductor region 311 side refers to the interface between the third semiconductor region 321 and the sixth semiconductor region 315.

[0079] In this embodiment, when the fourth semiconductor region 322 is of the first conductivity type, the fourth semiconductor region 322 may have the same impurity concentration as the first semiconductor region 311. In addition, in this embodiment, when the fourth semiconductor region 322 is of the second conductivity type, the fourth semiconductor region 322 may have the same impurity concentration as the third semiconductor region 321.

[0080] Even if the impurity concentration of each semiconductor region is the same, if the distance E between the first semiconductor region 311 and the fourth semiconductor region 322 is the same as the distance D between the first semiconductor region 311 and the third semiconductor region 321, the same effect as in the first embodiment can be achieved.

[0081] The fourth semiconductor region 322 may be an intrinsic semiconductor region, a semiconductor region of a first conductivity type having a lower impurity concentration than the first semiconductor region 311, or a semiconductor region of a second conductivity type having a lower impurity concentration than the third semiconductor region 321.

[0082] According to this embodiment, an APD that can reduce pixel size can be realized. Furthermore, since the isolation region 331 is provided, avalanche crosstalk can also be reduced. Furthermore, since the width of the fourth semiconductor region 322 is reduced, the pixel size can be reduced more than in the second embodiment.

[0083] (Fourth embodiment) A photoelectric conversion device according to a fourth embodiment will be described with reference to Fig. 12, Fig. 13(a), and Fig. 13(b). Fig. 12 is a plan view of a photoelectric conversion device according to the fourth embodiment, in which APDs are arranged in a two-dimensional plane in a 2 × 2 array. Fig. 13(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 12, and Fig. 13(b) shows a cross-sectional view taken along dashed line B-B'. The numbers in Fig. 12 correspond to the numbers in Figs. 13(a) and 13(b).

[0084] The photoelectric conversion device according to this embodiment differs from the second embodiment in that isolation regions 331 are also arranged between adjacent pixels in the diagonal direction along dashed line B-B' in Fig. 12. Other than this point and points described below, the photoelectric conversion device according to this embodiment is substantially the same as the second embodiment, and therefore description thereof will be omitted.

[0085] In this embodiment, the isolation regions 331 are arranged all around the pixel in the diagonal direction as well as the opposite side direction in plan view. That is, the isolation regions 331 are also arranged between the APDs in the cross section taken along dashed line BB'.

[0086] In the second embodiment, the contact plug 342 disposed between diagonally adjacent pixels is shared by four pixels, and each pixel essentially has one contact plug for applying voltage VH. In contrast, in the present embodiment, an isolation region 331 in which an insulating film is embedded is disposed between diagonally adjacent pixels, and therefore, as shown in FIG. 12, the contact plugs must be disposed offset from the center between the diagonally adjacent pixels in a plan view. In the example of FIG. 12, four contact plugs 342 are allocated per pixel, but this number is not necessarily four; one contact plug for applying voltage VH may be sufficient per pixel. Alternatively, a single contact plug for applying voltage VH may be shared by multiple pixels.

[0087] In the second embodiment, among the photons emitted from the avalanche multiplication unit 314, photons traveling in the diagonal direction, i.e., along the dashed line B-B' in FIG. 12, may cause avalanche crosstalk. In this embodiment, the isolation region 331 is arranged around the pixel, including the diagonal direction. Therefore, it is possible to reduce avalanche crosstalk between diagonally adjacent pixels.

[0088] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. Furthermore, the provision of an isolation region can also reduce avalanche crosstalk. In particular, avalanche crosstalk between diagonally adjacent pixels can also be reduced.

[0089] (Fifth embodiment) A photoelectric conversion device according to a fifth embodiment will be described with reference to Fig. 14, Fig. 15(a), and Fig. 15(b). Fig. 14 is a plan view of a photoelectric conversion device according to the fifth embodiment, in which APDs are arranged in a two-dimensional plane in a 2 × 2 array. Fig. 15(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 14, and Fig. 15(b) shows a cross-sectional view taken along dashed line B-B'. The numbers in Fig. 14 correspond to the numbers in Figs. 15(a) and 15(b).

[0090] The photoelectric conversion device according to this embodiment differs from the second embodiment in that the separation region 331 does not reach the second surface 303. Other than this point and the points described below, the photoelectric conversion device according to this embodiment is substantially the same as the second embodiment, and therefore description thereof will be omitted.

[0091] 15(a), the isolation region 331 is disposed up to the boundary between the sixth semiconductor region 315 and the seventh semiconductor region 316. When the first plane 302 is used as the reference, the depth at which the seventh semiconductor region 316 is disposed is, for example, 2.5 μm or more.

[0092] The source of photons that cause avalanche crosstalk is the avalanche multiplication section 314, and the photons generated there are unlikely to leak into adjacent pixels via the seventh semiconductor region 316 arranged on the second surface 303 side. Therefore, the isolation region 331 does not need to reach the second surface 303, and may be formed partway in the depth direction as shown in FIG. 15(a). In this case, the difficulty of the process of forming the isolation region 331 and the third semiconductor region 321 can be reduced.

[0093] According to this embodiment, an APD that can reduce pixel size can be realized. In addition, the provision of the isolation region 331 can reduce avalanche crosstalk. In addition, the difficulty of the process can be reduced.

[0094] (Sixth embodiment) A photoelectric conversion device according to a sixth embodiment will be described with reference to Fig. 16, Fig. 17(a), and Fig. 17(b). Fig. 16 is a plan view of a photoelectric conversion device according to this embodiment, in which APDs are arranged in a two-dimensional plane in a 2 × 2 array. Fig. 17(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 16, and Fig. 17(b) shows a cross-sectional view taken along dashed line B-B'. The numbers in Fig. 16 correspond to the numbers in Figs. 17(a) and 17(b).

[0095] The photoelectric conversion device according to this embodiment differs from the fourth embodiment in that the contact plug that applies voltage VH to the APD is not arranged on the first surface 302 side, but is supplied through contact plug 343 arranged on the second surface 303 side. Other than this point and the points described below, the photoelectric conversion device according to this embodiment is substantially the same as the fourth embodiment, and therefore description thereof will be omitted.

[0096] The voltage VH applied from the contact plug 343 is supplied to the second semiconductor region 312 through the seventh semiconductor region 316 and the sixth semiconductor region 315. As a result, a reverse bias voltage is applied to the first semiconductor region 311 and the second semiconductor region 312, and the avalanche multiplication section 314 can be formed.

[0097] In this embodiment, since there is no contact plug for applying voltage VH on the first surface 302 side, there is no need to form the eighth semiconductor region 323 on the first surface 302 side. Therefore, in Figures 17(a) and 17(b), the fourth semiconductor region 322 is arranged instead of the eighth semiconductor region 323. If the isolation region 331 is not arranged, the fourth semiconductor region 322 may not be arranged.

[0098] Although the contact plugs 343 are provided in FIGS. 17(a) and 17(b), electrodes such as metal films may be formed instead of the contact plugs 343, and a potential may be supplied via the electrodes.

[0099] 17(a) and 17(b), the contact plug 343 is arranged at a position overlapping the avalanche multiplication section 314 in plan view, but the contact plug 343 may be arranged at a position not overlapping the avalanche multiplication section 314. This allows incident light from the second surface 303 side to be incident on the semiconductor layer without being blocked by the contact plug 343.

[0100] According to this embodiment, an APD that can reduce the pixel size can be realized. In addition, since the isolation region 331 is provided, avalanche crosstalk can also be reduced.

[0101] (Seventh embodiment) A photoelectric conversion device according to the seventh embodiment will be described with reference to Fig. 18, Fig. 19(a), and Fig. 19(b). Fig. 18 is a plan view of a photoelectric conversion device according to the seventh embodiment, in which APDs are arranged in a two-dimensional plane in a 2 × 2 array. Fig. 19(a) shows a cross-sectional view taken along dashed line A-A' in Fig. 18, and Fig. 19(b) shows a cross-sectional view taken along dashed line B-B'. The numbers in Fig. 18 correspond to the numbers in Figs. 19(a) and 19(b).

[0102] The photoelectric conversion device according to this embodiment differs from the first embodiment in the configuration of the semiconductor region for forming the avalanche multiplication section 314. Other than this point and points described below, the photoelectric conversion device according to this embodiment is substantially the same as the first embodiment, and therefore description thereof will be omitted.

[0103] In FIG. 19(a), a PN junction is formed between a ninth semiconductor region 351 of a first conductivity type and a tenth semiconductor region 352 of a second conductivity type, thereby forming an avalanche multiplication section 314. The impurity concentration of the ninth semiconductor region 351 is, for example, similar to that of the first semiconductor region 311 in FIG. 5(a), and the impurity concentration of the tenth semiconductor region 352 is, for example, similar to that of the second semiconductor region 312 in FIG. 5(a). In addition, in FIG. 19(a), an eleventh semiconductor region 353 is disposed at the same depth as the tenth semiconductor region 352. When the eleventh semiconductor region 353 is of the second conductivity type, its impurity concentration is lower than that of the tenth semiconductor region 352. When the eleventh semiconductor region 353 is of the first conductivity type, its impurity concentration is lower than that of the ninth semiconductor region 351. In addition, a twelfth semiconductor region 354 is disposed at the same depth as the ninth semiconductor region 351. When the twelfth semiconductor region 354 is of the first conductivity type, its impurity concentration is lower than that of the ninth semiconductor region 351. When the twelfth semiconductor region 354 is of the second conductivity type, its impurity concentration is lower than that of the tenth semiconductor region 352.

[0104] The avalanche multiplication section 314 is formed by an electric field between the ninth semiconductor region 351 and the tenth semiconductor region 352. According to the configuration of this embodiment, the area of ​​the ninth semiconductor region 351 can be kept constant regardless of the pixel size. The potential height for signal charges is set lower in the eleventh semiconductor region 353 than in the tenth semiconductor region 352. As a result, charges photoelectrically converted in the sixth semiconductor region 315 pass through the eleventh semiconductor region 353 and are collected in the avalanche multiplication section 314. This potential design makes it possible to minimize the area of ​​the avalanche multiplication section 314, which is a noise generation source.

[0105] In addition, in FIG. 19(a), the ninth semiconductor region 351 and the tenth semiconductor region 352 do not overlap each other in a plan view, but they may partially overlap each other.

[0106] Furthermore, if the potential height for signal charges is lower in the eleventh semiconductor region 353 than in the tenth semiconductor region 352, the tenth semiconductor region 352 and the eleventh semiconductor region 353 may have the same second conductivity type impurity concentration. This point will also be described in the ninth embodiment.

[0107] In addition, in Figure 19(a), if the PN junction depth of the ninth semiconductor region 351 and the tenth semiconductor region 352 is 401 and the depth at which the tenth semiconductor region 352 is arranged is 403, the relationship of each depth to the depth 402 is the same as in the first embodiment.

[0108] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. In addition, the provision of the isolation region 331 also makes it possible to reduce avalanche crosstalk. Furthermore, signal charges can be collected in the avalanche multiplication section 314 while reducing the area of ​​the avalanche multiplication section 314 compared to the first embodiment. Therefore, it is possible to increase the photodetection efficiency while reducing noise.

[0109] (Eighth embodiment) A photoelectric conversion device according to the eighth embodiment will be described with reference to Fig. 20. In the photoelectric conversion device according to this embodiment, an isolation region 331b that does not reach the first surface 302 is arranged between diagonally adjacent pixels. The isolation region 331 described in Fig. 13 for the fourth embodiment is also provided between diagonally adjacent pixels, but reaches the first surface 302, and differs from this embodiment in that the isolation region 331 does or does not reach the first surface 302. Other than this point and the points described below, this embodiment is substantially the same as the above embodiments, and therefore description thereof will be omitted.

[0110] The isolation region 331b is preferably formed to a depth close to the depth 401 at which the avalanche multiplication section 314 is disposed, thereby making it possible to reduce avalanche crosstalk between adjacent pixels in the opposite side direction.

[0111] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. Furthermore, the provision of an isolation region can also reduce avalanche crosstalk. In particular, avalanche crosstalk between diagonally adjacent pixels can also be reduced.

[0112] (Ninth embodiment) A photoelectric conversion device according to a ninth embodiment will be described with reference to FIGS.

[0113] 21 is a schematic plan view of four pixels in a 2×2 arrangement among the plurality of pixels included in the pixel region 12. FIG. 21 shows a plane of the first surface of the semiconductor layer 300.

[0114] Fig. 22(a) is a schematic cross-sectional view taken along line A-A' in Fig. 21, i.e., in a first direction, and Fig. 22(b) is a schematic cross-sectional view taken along line B-B' in Fig. 21, i.e., in a second direction intersecting the first direction. In Fig. 22, the first direction is the opposite side direction, and the second direction is the diagonal direction. Fig. 22 shows a semiconductor layer 300 included in the sensor substrate 11 and a portion of a contact plug connected to the semiconductor layer 300.

[0115] 21, each pixel 104 includes at least one APD. In the following description, a configuration in which the pixel 104 is configured with one APD will be described, but the pixel 104 may be configured with multiple APDs. For convenience, the APD arranged in the direction opposite the first APD will be referred to as the second APD, and the APD arranged in the diagonal direction of the first APD will be referred to as the third APD.

[0116] Although the details of each semiconductor region will be described later, Fig. 21 shows a first semiconductor region 1311 of a first conductivity type (e.g., N-type) for forming an avalanche multiplication region of the APD. A third semiconductor region 1313 is disposed around the first semiconductor region 1311.

[0117] In FIG. 21, a sixth semiconductor region 1316 of a second conductivity type (for example, P type) to which a contact plug is connected is disposed between the first semiconductor region 1311 of the first APD and the first semiconductor region 1311 of the third APD.

[0118] An isolation portion (isolation region) including a fourth semiconductor region 1314 of the second conductivity type is arranged between each pixel. In the above embodiment, an example in which the isolation portion (isolation region) is configured with a trench structure and a semiconductor region has been described. On the other hand, in the present embodiment, an example in which the isolation portion (isolation region) is configured with only a semiconductor region will be described. The fourth semiconductor region 1314 of the second conductivity type is arranged to separate the opposite side and diagonal directions. In a plan view, the sixth semiconductor region 1316 is arranged to overlap the fourth semiconductor region 1314.

[0119] As shown in FIG. 22(a), the semiconductor layer 300 is provided with semiconductor regions constituting the pixel 104. The APD includes at least a first semiconductor region 1311 of a first conductivity type and a second semiconductor region 1312 of a second conductivity type. The first semiconductor region 1311 and the second semiconductor region 1312 form a PN junction. The impurity concentration of the first semiconductor region 1311 is higher than the impurity concentration of the second semiconductor region 1312. An avalanche multiplication region 1302 is formed by applying a predetermined reverse bias voltage to the first semiconductor region 1311 and the second semiconductor region 1312. The first semiconductor region 1311 is connected to a contact plug 1130, and a voltage is applied via the contact plug 1130. Note that a plurality of contact plugs 1130 may be provided.

[0120] A semiconductor region 1301 of a first conductivity type having a lower impurity concentration than the first semiconductor region 1311 may be disposed between the first semiconductor region 1311 and the second semiconductor region 1312. The semiconductor region 1301 may be of either the first conductivity type or the second conductivity type.

[0121] A third semiconductor region 1313 of the first conductivity type is disposed at an end of the first semiconductor region 1311 to alleviate the electric field. The third semiconductor region 1313 may be composed of a semiconductor region of the second conductivity type as long as the purpose of alleviating the electric field can be achieved. The impurity concentration of the third semiconductor region 1313 is lower than that of the first semiconductor region 1311 if it is of the first conductivity type, and lower than that of the second semiconductor region 1312 if it is of the second conductivity type. The difference in impurity concentration between the third semiconductor region 1313 and the first semiconductor region 1311 or the second semiconductor region 1312 is two times or more. The third semiconductor region is an additional semiconductor region and may not be provided.

[0122] 22(a) and 22(b), a fourth semiconductor region 1314 of the second conductivity type is arranged to separate the pixels in the opposite side and diagonal directions. A second semiconductor region 1312 of the second conductivity type is arranged in contact with the fourth semiconductor region 1314.

[0123] A second conductivity type fifth semiconductor region 1315 is disposed at a position deeper than the second semiconductor region 1312. The second conductivity type fifth semiconductor region 1315 is disposed in contact with the fourth semiconductor region 1314. In a plan view, the fifth semiconductor region 1315 may be disposed over the entire surface of the pixel 104, with a portion of the fifth semiconductor region 1315 overlapping with the fourth semiconductor region 1314. In FIGS. 22(a) and 22(b), the fifth semiconductor region 1315 is disposed in contact with the rear surface of the semiconductor layer 300, but it may be disposed separately. Note that although FIGS. 22(a) and 22(b) show an example in which the second conductivity type fifth semiconductor region 1315 is formed by ion implantation, this is not limiting. For example, a pinning film may be disposed on the rear surface of the semiconductor layer 300, and the fifth semiconductor region 1315 may not be formed by ion implantation. A known material may be used for the pinning film.

[0124] Although not shown, a planarization layer, a filter layer, a microlens, etc. may be disposed on the back surface of the semiconductor layer 300. The filter layer may be a variety of optical filters such as a color filter, an infrared cut filter, or a monochrome filter. The color filter may be an RGB color filter, an RGBW color filter, etc.

[0125] A seventh semiconductor region 1317 of the first conductivity type is provided between the second semiconductor region 1312 and the fifth semiconductor region 1315. The impurity concentration of the seventh semiconductor region 1317 is higher than the impurity concentration of the semiconductor region 1301 provided around the seventh semiconductor region 1317. With this configuration, the potential of the seventh semiconductor region 1317 is lower than the potential of the semiconductor region 1301 for signal charges, allowing more charges to be collected in the avalanche multiplication region 1302. The seventh semiconductor region 1317 is a semiconductor region provided as needed and does not necessarily have to be provided. Furthermore, although a portion of the seventh semiconductor region 1317 and the second semiconductor region 1312 are in contact with each other in the cross-sectional view of FIG. 22 , the seventh semiconductor region 1317 may be provided spaced apart from the second semiconductor region 1312.

[0126] 22(a), one end (upper surface) of the second conductivity type fourth semiconductor region 1314 is disposed at a position shallower than the second semiconductor region 1312 and deeper than the first surface of the semiconductor layer 300. In other words, between the first photoelectric conversion element having the first APD and the second photoelectric conversion element having the second APD, one end of the fourth semiconductor region 1314 is disposed closer to the second surface than the first surface and closer to the first surface than the second semiconductor region 1312. As shown in FIG. 22(a), one end of the fourth semiconductor region 1314 is not disposed continuously from the second surface to the first surface in the opposite side direction, but is disposed spaced apart from the first surface.

[0127] If the fourth semiconductor region 1314 is disposed continuously from the second surface to the first surface between the first APD and the second APD, there is a possibility that electric field concentration will occur in the lateral direction between the first semiconductor region 1311 or the third semiconductor region 1313 and the fourth semiconductor region 1314. On the other hand, if one end of the fourth semiconductor region 1314 is located below the upper surface of the second semiconductor region 1312, a depletion layer may spread in the lateral direction between the first semiconductor region 1311 of the first APD and the first semiconductor region 1311 of the second APD. As a result, the depletion layers may connect, which may cause punch-through between pixels.

[0128] In contrast, according to this embodiment, in the opposite side direction, the upper end of the fourth semiconductor region 1314 is disposed at a position deeper than the first surface and shallower than the second semiconductor region 1312. Therefore, it is possible to reduce the electric field concentration in the lateral direction while making punch-through less likely to occur.

[0129] As shown in FIG. 22(b), in the diagonal direction, the fourth semiconductor region 1314 is continuously disposed from the first surface to the same depth as the depth at which the fifth semiconductor region 1315 is disposed. In the diagonal direction, it is easier to ensure a distance between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313 compared to the opposite side direction. Therefore, the distance between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313 is longer in the diagonal direction compared to the opposite side direction. Therefore, even if the fourth semiconductor region 1314 is disposed up to the first surface, electric field concentration in the lateral direction is less likely to occur in the diagonal direction compared to the opposite side direction. As shown in FIG. 22(b), in the diagonal direction, a voltage needs to be applied to the second semiconductor region 1312 via the contact plug 131, as described below. Therefore, in the diagonal direction, the fourth semiconductor region 1314 is continuously disposed up to the first surface. The fourth semiconductor region 1314 does not need to be formed continuously up to the first surface as long as it is in contact with the sixth semiconductor region 1316. At least, it is sufficient that the fourth semiconductor region 1314 and the sixth semiconductor region 1316 are in contact with each other.

[0130] A sixth semiconductor region 1316 of the second conductivity type is provided on the first surface side of the semiconductor layer 300. As shown in Figures 21 and 22(b), the sixth semiconductor region 1316 is included in the fourth semiconductor region 1314 of the second conductivity type.

[0131] The impurity concentration of the sixth semiconductor region 1316 is higher than the impurity concentration of the fourth semiconductor region 1314. With this configuration, by connecting the sixth semiconductor region 1316 and the contact plug 131, it is possible to make the contact resistance between the metal and the semiconductor lower than the contact resistance when the fourth semiconductor region 1314 and the contact plug 131 are connected.

[0132] By applying a predetermined reverse bias voltage between the contact plug 131 connected to the sixth semiconductor region 1316 and the contact plug 130 connected to the first semiconductor region 1311, the avalanche multiplication region 302 can be formed.

[0133] (Organization of semiconductor regions at each position and relationship with potential) At the first depth D1, a first semiconductor region 1311 of a first conductivity type, a third semiconductor region 1313 of a first conductivity type or a second conductivity type, a semiconductor region 1301 of a first conductivity type or a second conductivity type, a fourth semiconductor region 1314 of a second conductivity type, and a sixth semiconductor region 1316 of a second conductivity type are arranged.

[0134] The first semiconductor region 1311 and the third semiconductor region 1313 are in contact with each other in a planar view. Also, the third semiconductor region 1313 and the semiconductor region 1301 are in contact with each other in a planar view.

[0135] Here, each semiconductor region being disposed at the first depth D1 means, for example, that the concentration peak of the ion-implanted impurity is disposed at the first depth D1. However, the peak does not necessarily have to be disposed at the first depth D1, as long as a region in which the impurity is recognized as having been diffused is provided at the first depth D1.

[0136] The second depth D2 is deeper than the first depth D1. In other words, the second depth D2 is closer to the back surface of the semiconductor layer 300 than the first depth D1. The second semiconductor region 1312 and the fourth semiconductor region 1314 are disposed at the second depth D.

[0137] The third depth D3 is deeper than the second depth D2. In other words, the third depth D3 is closer to the back surface of the semiconductor layer 300 than the second depth D2. The seventh semiconductor region 1317, the semiconductor region 1301, and the fourth semiconductor region 1314 are disposed at the third depth D3.

[0138] The fourth depth D4 is located deeper than the third depth D3. In other words, the fourth depth D4 is located closer to the back surface of the semiconductor layer 300 than the third depth D3. A fifth semiconductor region 1315 and a fourth semiconductor region 1314 are disposed at the fourth depth D4.

[0139] FIG. 23 shows a potential diagram for the APDs of FIGS.

[0140] 23, dotted line 20 indicates the potential distribution of line segment DD', and solid line 30 indicates the potential distribution of line segment CC'. D1 to D4 in the depth direction on the horizontal axis in Fig. 23 correspond to D1 to D4 in Fig. 22, respectively.

[0141] 23, the potential gradually decreases from depth D4 toward depth D3. The seventh semiconductor region 1317 disposed at depth D3 is of the first conductivity type, and the second semiconductor region 1312 disposed at depth D2 is of the second conductivity type, so the potential gradually increases from depth D3 toward depth D2. On the other hand, the third semiconductor region 1313 disposed at depth D1 is either of the first conductivity type or of the second conductivity type with a lower impurity concentration than the second semiconductor region 1312. Therefore, the potential decreases from depth D2 toward depth D1.

[0142] On the other hand, the dotted line 20 and the solid line 30 show the same tendency of gradually decreasing potential from depth D4 to depth D3. However, in the solid line 30, the potential gradually decreases from depth D3 to depth D2. Furthermore, the potential decreases sharply from depth D2 to depth D1. From depth D4 to D3, the potential gradients of the dotted line 20 and the solid line 30 show almost the same tendency, and the potential gradient decreases gradually. Therefore, the charge generated in the photodetector moves to the front surface side (first surface side) of the semiconductor layer 300 due to the gentle potential gradient.

[0143] As described above, the first semiconductor region 1311 and the second semiconductor region 1312 form a PN junction, but the impurity concentration of the second semiconductor region 1312 is lower than that of the first semiconductor region 1311. Therefore, when a reverse bias potential is applied to the first semiconductor region 1311 and the second semiconductor region 1312, a depletion layer region is formed toward the second semiconductor region 1312. In this case, a strong electric field is applied to the center of the second semiconductor region 1312 around the avalanche multiplication region 302, whereas only a weak electric field is applied to the peripheral portion of the second semiconductor region 1312. Therefore, at the position of depth D2, the potential of the solid line 30 is significantly reduced, and at depth D2, the potential of the solid line 30 is lower than the potential of the dotted line 20. On the other hand, because only a weak electric field is applied to the peripheral portion of the second semiconductor region 1312, the potential relationship corresponding to the difference in conductivity type or impurity concentration of each semiconductor region is maintained.

[0144] 23, the potential height for electrons, which are signal charges, is lower in the center of the second semiconductor region 1312 than in the peripheral portion. This makes it easier for photoelectrically converted charges to move toward the center of the second semiconductor region 1312.

[0145] The charges that have moved to the vicinity of the center of the second semiconductor region 1312 are accelerated by the steep potential gradient from depth D2 to depth D1 of the solid line 30 in FIG.

[0146] In contrast, the potential distribution does not cause avalanche multiplication from depth D2 to depth D1 of the dotted line 20 in Fig. 23. Therefore, the generated charges can be counted as signal charges without increasing the area of ​​the avalanche multiplication region 1302 relative to the pixel size.

[0147] An example of the impurity concentration of each semiconductor region will be specifically described below. Here, the first conductivity type is defined as N-type, and the second conductivity type is defined as P-type.

[0148] The impurity concentration of the sixth semiconductor region 1316 in FIG. 19 ~10 20 [atoms / cm 3 ] is about that level.

[0149] The N-type first semiconductor region 1311 has a higher impurity concentration than the N-type seventh semiconductor region 1317. For example, the impurity concentration of the N-type first semiconductor region 1311 is 1×10 18 [atoms / (cm 3 ) and a potential that is a reverse bias with respect to the fourth semiconductor region 1314 is supplied to the N-type first semiconductor region 1311 .

[0150] The N-type third semiconductor region 1313 has an impurity concentration lower than that of the N-type first semiconductor region 1311. For example, the impurity concentration of the N-type third semiconductor region 1313 is 1×10 16 ~5×10 17 [atoms / cm 3 If the third semiconductor region 1313 is P-type, an avalanche multiplication field may be formed between the first semiconductor region 1311 and the third semiconductor region 1313 depending on the impurity concentration of the third semiconductor region 1313, which may cause an increase in noise.

[0151] The impurity concentration of the P-type second semiconductor region 1312 is set to be lower than the impurity concentration of the P-type fourth semiconductor region 1314. For example, the impurity concentration of the P-type second semiconductor region 1312 is set to be 1×10 16 ~5×10 17 [atoms / cm 3 ] is about that level.

[0152] 22, it is assumed that the P-type second semiconductor region 1312 is not provided, and an N-type seventh semiconductor region 1317 having a lower impurity concentration than the N-type first semiconductor region 1311 is disposed immediately below the N-type first semiconductor region 1311. In this case, it is possible to generate charges in the seventh semiconductor region 1317 and read out the charges from the N-type first semiconductor region 1311.

[0153] However, it is difficult to achieve avalanche multiplication under voltage conditions equivalent to those of this embodiment. This is because a large portion of the reverse bias potential difference is applied to the depletion layer region of the N-type seventh semiconductor region 1317, thereby reducing the potential difference applied to the avalanche multiplication region near the N-type first semiconductor region 1311. On the other hand, in this embodiment, the N-type seventh semiconductor region 1317 is surrounded by P-type semiconductor regions in all directions, so the potential of the N-type seventh semiconductor region 1317 is closer to the surrounding P-type semiconductor region than to the N-type first semiconductor region 1311. In other words, by suppressing excessive expansion of the depletion layer deep into the semiconductor layer using the P-type second semiconductor region 1312, it is possible to concentrate a large portion of the applied potential difference in the avalanche multiplication region near the N-type first semiconductor region 1311. As a result, photocharges can be avalanche multiplied at a lower voltage. In this case, the impurity concentration of the N-type seventh semiconductor region 1317 needs to be lower than that of the N-type first semiconductor region 1311.

[0154] 22, the N-type seventh semiconductor region 1317 is shown as a region having the same impurity concentration as an example. However, it is preferable that the N-type seventh semiconductor region 1317 has an impurity concentration gradient so as to create a potential structure in which charges move toward the first surface side of the semiconductor layer 300. By providing such an impurity concentration gradient, it is possible to make it easier for charges to move to the N-type seventh semiconductor region 1317.

[0155] 22 shows the P-type second semiconductor region 1312 as an impurity region having the same impurity concentration. However, any configuration may be adopted as long as the potential of the central portion of the second semiconductor region 1312 is lower than the potential of the peripheral portion. For example, a configuration may be adopted in which the impurity concentration of the peripheral portion of the second semiconductor region 1312 is higher than the impurity concentration of the central portion of the P-type second semiconductor region 1312. Furthermore, the central portion of the second semiconductor region 1312 may be an N-type semiconductor region.

[0156] According to this embodiment, it is possible to realize an APD that allows for miniaturization of pixel size. Furthermore, it is possible to reduce punch-through between the first semiconductor region 1311 of the first APD and the first semiconductor region 1311 of the second APD while reducing the generation of an electric field between the first semiconductor region 1311 or the third semiconductor region 1313 and the fourth semiconductor region 1314.

[0157] (Tenth embodiment) A photoelectric conversion device according to the tenth embodiment will be described with reference to FIG. 24 and FIGS. 25(a) and 25(b). FIG. 24 is a schematic plan view of a semiconductor layer 300 in which an APD of the photoelectric conversion device according to this embodiment is disposed. FIG. 25(a) is a schematic cross-sectional view taken along line A-A' in FIG. 24, and FIG. 25(b) is a schematic cross-sectional view taken along line B-B' in FIG. 24. The photoelectric conversion device according to this embodiment differs from the tenth embodiment in that a ninth semiconductor region 1319 of the first conductivity type is disposed near the first surface of the semiconductor layer 300. Other than this point and matters described below, the photoelectric conversion device according to this embodiment is substantially the same as the tenth embodiment. Therefore, the same reference numerals are used to designate components similar to those of the tenth embodiment, and descriptions thereof may be omitted.

[0158] 24, the ninth semiconductor region 1319 is arranged to surround the first semiconductor region 313 and the third semiconductor region 1313 in a plan view. The ninth semiconductor region 1319 desirably has an impurity concentration equal to or lower than that of the third semiconductor region 1313. For example, if the ninth semiconductor region 1319 and the third semiconductor region 1313 have different impurity concentrations, the ninth semiconductor region 1319 desirably has an impurity concentration at least two times lower than that of the third semiconductor region 1313.

[0159] By providing the ninth semiconductor region 1319, it is possible to reduce noise in signals due to dark electrons that may be generated by defect levels at the interface of the first surface of the semiconductor layer 300 or near the first surface. When the ninth semiconductor region 1319 is provided, a region in which the potential with respect to dark electrons is lowered from the ninth semiconductor region 1319 toward the first semiconductor region 1311 is formed. In other words, dark electrons generated at the interface of the first surface of the semiconductor layer 300 or the like are more likely to move toward the first semiconductor region 1311 and less likely to move toward the semiconductor region 1301 or the seventh semiconductor region 1317. This reduces the number of dark electrons passing through the avalanche multiplication region 1302, thereby reducing noise. Note that dark electrons that move to the first semiconductor region 1311 via the third semiconductor region 1313 are read out without passing through the avalanche multiplication region 1302 and are not determined as a signal. Therefore, they do not become noise even when read out.

[0160] The ninth semiconductor region 1319 may be arranged so that the impurity concentration decreases with increasing distance from the first semiconductor region 1311, or may be arranged to have the same impurity concentration. Also, the ninth semiconductor region 1319 may have a concentration gradient in the depth direction.

[0161] 25(a), the ninth semiconductor region 1319 is preferably arranged continuously in the opposite side direction between adjacent pixels, from the third semiconductor region 1313 of a pixel 104 to the third semiconductor region 1313 of the adjacent pixel. As shown in FIG. 9, the ninth semiconductor region 1319 is preferably arranged so as to surround the first semiconductor region 1311, the third semiconductor region 1313, the sixth semiconductor region 1316, and the fourth semiconductor region 1314 in a planar view. For example, the ninth semiconductor region 1319 is preferably arranged in a region excluding the first semiconductor region 1311, the third semiconductor region 1313, the sixth semiconductor region 1316, and the fourth semiconductor region 1314 in a planar view. This makes it easier to reduce the effect of increased signal noise due to dark electrons.

[0162] The ninth semiconductor region 1319 is preferably disposed at a position shallower than the lower end of the first semiconductor region 1311. Furthermore, the vertical length of the ninth semiconductor region 1319 is preferably shorter than the vertical length of the third semiconductor region 1313. Furthermore, the vertical length of the ninth semiconductor region 1319 is preferably shorter than the vertical length of the first semiconductor region 1311. This can reduce the unintended movement of dark electrons into the avalanche multiplication region 1302.

[0163] In the opposite side direction, the ninth semiconductor region 1319 and the fourth semiconductor region 1314 may be in contact with each other or may be separated as shown in FIG. 25(a). When the ninth semiconductor region 1319 and the fourth semiconductor region 1314 are in contact with each other, charge is less likely to move to adjacent pixels, and when they are separated, electric field concentration is less likely to occur between the fourth semiconductor region 1314 and the first semiconductor region 1311. Furthermore, in the diagonal direction, as shown in FIG. 25(b), the ninth semiconductor region 1319 and the fourth semiconductor region 1314 are in contact with each other, but they may also be separated. However, as described above, in order to obtain the noise reduction effect achieved by disposing the ninth semiconductor region 1319, it is preferable that the ninth semiconductor region 1319 be disposed in contact with the fourth semiconductor region 1314.

[0164] 24, in this embodiment, the ninth semiconductor region 1319 is arranged so as to constitute a part of the first surface of the semiconductor layer 300, but this is not essential. For example, the ninth semiconductor region 1319 may be arranged at a position away from the first surface.

[0165] The third semiconductor region 1313 may be disposed in contact with the second semiconductor region 1312, as shown in FIG. 26. The third semiconductor region 1313 is disposed in a torus shape in FIGS. 24 and 25, but is disposed in a circular shape in FIG. 26. For example, as shown in FIG. 26, a first conductivity type third semiconductor region 1313 is disposed between the first semiconductor region 1311 and the second semiconductor region 1312. This deepens the PN junction surface, and reduces local concentration of the electric field in the avalanche multiplication region 1302. Note that the schematic plan view is the same as FIG. 9, and the schematic cross-sectional view in the diagonal direction is omitted because it is the same except that the third semiconductor region 1313 is disposed between the first semiconductor region 1311 and the second semiconductor region 1312.

[0166] 26, the impurity concentration of the third semiconductor region 1313 near the side surface of the first semiconductor region 1311 may be the same as the impurity concentration of the third semiconductor region 1313 near the bottom surface of the first semiconductor region 1311. However, the impurity concentration of the third semiconductor region 1313 may be arranged to decrease as it approaches the second semiconductor region 1312 from the first semiconductor region 1311.

[0167] Furthermore, the third semiconductor region 1313 may have a lower impurity concentration in the vicinity of the first semiconductor region 1311 than in the vicinity of the ninth semiconductor region 1319. For example, the third semiconductor region 1313 may have an impurity concentration that decreases stepwise from the side closer to the first semiconductor region 1311 to the side farther from the first semiconductor region 1311. This makes it possible to alleviate electric field concentration in the lateral direction.

[0168] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. Furthermore, punch-through between pixels can be reduced while reducing the generation of electric fields in the lateral direction. Furthermore, the electric field distribution in the avalanche multiplication region 1302 can be more easily formed spatially uniformly, thereby reducing noise caused by electric field concentration.

[0169] (Eleventh embodiment) A photoelectric conversion device according to the eleventh embodiment will be described with reference to FIG. 27 and FIGS. 28(a) and 28(b). FIG. 27 is a schematic plan view of a semiconductor layer 300 in which an APD of a photoelectric conversion device according to this embodiment is disposed. FIG. 28(a) is a schematic cross-sectional view taken along line A-A' in FIG. 27, and FIG. 28(b) is a schematic cross-sectional view taken along line B-B' in FIG. 27. The photoelectric conversion device according to this embodiment differs from the tenth embodiment in that the isolation portion has a trench structure 1321 in the direction opposite sides between pixels. Other than this point and matters described below, the eleventh embodiment is substantially the same as the eleventh embodiment. Therefore, the same reference numerals are used to designate the same components as those of the tenth embodiment, and descriptions thereof may be omitted.

[0170] The trench structure 1321 is not disposed on the first surface of the semiconductor layer 300, but in order to make the planar arrangement of the trench structure 1321 easier to understand, in Figure 27, the position where the trench structure 1321 is disposed is shown by a dashed line.

[0171] The trench structure 1321 preferably includes a material different from that of the semiconductor layer 300. The trench structure 1321 preferably includes a reflective material or a light-absorbing material. The reflective or absorbing material is, for example, a material that reflects or absorbs 20% or more. For example, the trench structure 1321 includes at least one of an insulating material, air, and a metal. When the semiconductor layer 300 is made of silicon, examples of the insulating material include a silicon oxide film and a silicon nitride film. This reduces crosstalk to adjacent APDs. More preferably, the trench structure 1321 includes at least one of an insulating material and a metal. A phenomenon called avalanche emission may occur in the avalanche multiplication region 1302. This is a phenomenon in which photons are generated when electrons, which are hot carriers generated by avalanche multiplication, recombine with holes. When photons from this avalanche emission leak into adjacent pixels and undergo photoelectric conversion, electron-hole pairs are generated. In other words, photons generated by avalanche emission, rather than incident light, are read out as signals from adjacent pixels, resulting in false signals. By including a metal or the like in the trench structure 1321, it is possible to reduce the intrusion of photons into adjacent pixels even when avalanche emission occurs.

[0172] The trench structure 1321 is preferably arranged from the second surface of the semiconductor layer 300 to the same depth as the second semiconductor region 1312 or to a depth shallower than the second semiconductor region 1312. This is because crosstalk, in which photons generated by avalanche emission mix with adjacent pixels, can be easily reduced. However, the trench structure 1321 may also be arranged from the second surface to a position deeper than the second semiconductor region 1312. This is because crosstalk caused by avalanche emission can still be more easily reduced in this case than when the trench structure 1321 is not arranged.

[0173] 28(a), a trench structure 1321 is formed from the back surface side of the semiconductor layer 300. The trench structure 1321 is provided so as to be contained within the fourth semiconductor region 1314. That is, in the opposite side direction, pixels are separated by both the trench structure 1321 and the second conductivity type fourth semiconductor region 1314.

[0174] On the other hand, referring to FIG. 28(b), no trench structure 1321 is provided in the diagonal direction, and pixels are separated only by the fourth semiconductor region 1314.

[0175] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. Furthermore, punch-through between pixels can be reduced while reducing the generation of electric fields in the lateral direction. Furthermore, the electric field distribution in the avalanche multiplication region 1302 can be more easily formed spatially uniformly, reducing noise caused by electric field concentration. Additionally, crosstalk due to avalanche light emission can be more easily reduced.

[0176] Since the trench structure 1321 is not disposed between pixels in the diagonal direction, it is possible to reduce the electrical resistance from the contact plug 1131 to the fifth semiconductor region 1315. This makes it easier to form a potential gradient in a direction perpendicular to the semiconductor layer 300, and it is possible to shorten the time required to collect signal charges in the avalanche multiplication region 1302.

[0177] 29 and 30(a) and (b), trench structures 1321 may be arranged between pixels in the opposite side direction and the diagonal direction. As in FIG. 27, in FIG. 29, the positions where the trench structures 1321 are arranged are indicated by dashed lines to make the planar arrangement of the trench structures 1321 easier to understand. In this case, as shown in FIG. 29, the trench structures 1321 are arranged so as to surround the entire periphery of the first semiconductor region 1311 in plan view.

[0178] According to FIGS. 29 and 30, crosstalk due to avalanche light emission in the diagonal direction can also be reduced.

[0179] (Twelfth embodiment) A photoelectric conversion device according to the twelfth embodiment will be described with reference to FIG. 31 and FIGS. 32(a) and 32(b). FIG. 31 is a schematic plan view of a semiconductor layer 300 in which an APD of a photoelectric conversion device according to this embodiment is disposed. FIG. 32(a) is a schematic cross-sectional view taken along line A-A' in FIG. 31, and FIG. 32(b) is a schematic cross-sectional view taken along line B-B' in FIG. 31. The photoelectric conversion device according to this embodiment has trench structures 1321 penetrating the semiconductor layer 300 to separate pixels in opposite side directions. Furthermore, trench structures 1321 that do not penetrate the semiconductor layer 300 are also provided to separate pixels in diagonal directions. Except for these points and those described below, the present embodiment is substantially similar to the eleventh embodiment. Therefore, the same reference numerals are used to designate components similar to those of the eleventh embodiment, and descriptions thereof may be omitted.

[0180] In the direction opposite to each other between pixels, a fourth semiconductor region 1314 of the second conductivity type is arranged in contact with a portion of a trench structure 1321 penetrating the semiconductor layer 300, but the fourth semiconductor region 1314 is not arranged in other portions. For example, as shown in FIG. 32( a), a first portion of the trench structure 1321 is in contact with the fourth semiconductor region 1314 at a position shallower than the second semiconductor region 1312. The second portion is in contact with the semiconductor region 1301 of the first conductivity type, and the third portion is in contact with the ninth semiconductor region 1319. The first portion, the second portion, and the third portion are closer to the first surface of the semiconductor layer 300 in this order. Note that it is not essential that a portion of the trench structure 1321 be in contact with the semiconductor region 1301; it is sufficient that the trench structure 1321 be in contact with at least the fourth semiconductor region 1314 and the ninth semiconductor region 1319. In this way, the trench structure 1321 has a portion in contact with the semiconductor region of the second conductivity type and a portion in contact with the semiconductor region of the first conductivity type. 32(a), even if unwanted charges are generated due to the trench structure 1321, the second semiconductor region 1312 and the fourth semiconductor region 1314, which have high potential, are arranged below the trench structure 1321. Furthermore, the third semiconductor region 1313 and the ninth semiconductor region 1319, which have low potential, are arranged above the trench structure 1321. In other words, the potential makes it difficult for unwanted charges to move to the avalanche multiplication region 1302, so even if unwanted charges are generated, they have little effect on the readout signal.

[0181] The trench structure 1321 can be made of the same material as that described in the above embodiment. Furthermore, if the trench structure 1321 has a portion in contact with a semiconductor region of the first conductivity type, it is preferable that a pinning film be disposed at least in the region in contact with the semiconductor region of the first conductivity type. This allows holes to be concentrated in the vicinity of the trench structure 1321 by the pinning film, making it more difficult for unwanted charges to be read out as signals even if they are generated due to the formation of the trench structure 1321. The pinning film may be disposed continuously from the lower end to the upper end of the trench structure 1321.

[0182] The configuration between pixels in the diagonal direction is the same as that described with reference to Fig. 30(b) in the description of the eleventh embodiment, and therefore the description will be omitted. Note that, in the diagonal direction between pixels, trench structures 1321 may not be provided as described with reference to Fig. 28(b).

[0183] According to this embodiment, an APD that allows for miniaturization of pixel size can be realized. Furthermore, punch-through between pixels can be reduced while reducing the generation of electric fields in the lateral direction. Furthermore, the electric field distribution in the avalanche multiplication region 1302 is more likely to be formed spatially uniformly, thereby reducing noise caused by electric field concentration. Additionally, trench structures 1321 that penetrate the semiconductor layer 300 in the direction opposite each pixel are provided, further reducing crosstalk caused by avalanche light emission.

[0184] (Thirteenth embodiment) A photoelectric conversion device according to the thirteenth embodiment will be described with reference to Figures 33(a) and (b). Figure 33(a) is a modified example of Figure 22(a), and Figure 32(b) is a modified example of Figure 25(a).

[0185] This embodiment differs from the above-described embodiment in that the upper surface of the second conductivity type fourth semiconductor region 1314 is provided at the same position as the second semiconductor region 1312. Even with this configuration, the upper surface of the second conductivity type fourth semiconductor region 1314 is located lower than the lower surface of the first conductivity type first semiconductor region 1311, thereby suppressing electric field concentration in the lateral direction. This makes it possible to realize an APD that allows for miniaturization of pixel size.

[0186] Other matters are substantially the same as those in the ninth and tenth embodiments, so the same components as those in these embodiments are given the same reference numerals and the description thereof will be omitted.

[0187] (Fourteenth embodiment) A manufacturing method for a photoelectric conversion device according to the fourteenth embodiment will be described with reference to FIG. 34. For convenience of explanation, the manufacturing method for the second embodiment will be described, but other embodiments can also be manufactured using a similar manufacturing method. Also, in FIG. 34, a cross-sectional view of the diagonal direction of adjacent pixels will be used for the explanation, but cross sections in the diagonal direction can also be manufactured using the same concept. Furthermore, well-known manufacturing methods can be applied to the steps whose explanation is omitted in FIG. 34.

[0188] First, as shown in FIG. 34(a), a semiconductor layer 301 is prepared.

[0189] 34(b), impurities of the second conductivity type are ion-implanted into a region that will become the seventh semiconductor region 316 from the normal direction to the first surface 302. As a result, the seventh semiconductor region 316 is formed at a position deep relative to the first surface 302 of the semiconductor layer 301. Similarly, impurities of the second conductivity type are ion-implanted into a region that will become the sixth semiconductor region 315. As a result, the sixth semiconductor region 315 is formed at a depth shallower than the seventh semiconductor region 316 of the semiconductor layer 301.

[0190] 34(c), impurities of the second conductivity type are ion-implanted into regions that will become the third semiconductor regions 321 from the normal direction to the first surface 302. In this way, the third semiconductor regions 321 are formed.

[0191] 34(d), an isolation region 331 is formed between adjacent pixels. The isolation region 331 is formed in the region where the third semiconductor region 321 is to be disposed. In this way, the sidewall portion of the isolation region 331 is covered with the third semiconductor region 321.

[0192] Next, as shown in FIG. 34( e), impurities of the second conductivity type are ion-implanted into a region that will become the second semiconductor region 312 from the normal direction to the first surface 302. This forms the second semiconductor region 312. Similarly, impurities of the first conductivity type are ion-implanted into a region that will become the first semiconductor region 311 from the normal direction to the first surface 302 so as to contact the second semiconductor region 312 in the depth direction. This forms the first semiconductor region 311. As a result, a PN junction is formed between the first semiconductor region 311 and the second semiconductor region 312. When the voltages VL and VH described in the first embodiment are applied to this PN junction, it becomes an avalanche multiplication section 314.

[0193] 34(f), impurity ions are implanted into the region that will become the third semiconductor region 313 from the normal direction to the first surface 302. In this way, the third semiconductor region 313 is formed.

[0194] Next, as shown in FIG. 34(g), a contact plug 341 is formed in the first semiconductor region 311.

[0195] The pixel of this embodiment can be produced by such a manufacturing method.

[0196] (Fifteenth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 35. Fig. 35 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0197] The photoelectric conversion device described in the above embodiment can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. Figure 35 illustrates a block diagram of a digital still camera as an example of such systems.

[0198] 35 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The photoelectric conversion system further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0199] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary and outputs image data. The signal processing unit 1007 may be formed in the same semiconductor layer as the imaging device 1004, or may be formed in a different semiconductor layer from the imaging device 1004. Furthermore, the imaging device 1004 and the signal processing unit 1007 may be formed in the same semiconductor layer.

[0200] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0201] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0202] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0203] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0204] (16th embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 36. Fig. 36 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0205] FIG. 36(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 2300 includes an imaging device 2310. The imaging device 2310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 2300 includes an image processing unit 2312 that performs image processing on multiple pieces of image data acquired by the imaging device 2310. The photoelectric conversion system 2300 also includes a parallax acquisition unit 2314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 2300. The photoelectric conversion system 2300 also includes a distance acquisition unit 2316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 2314 and the distance acquisition unit 2316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 2318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0206] The photoelectric conversion system 2300 is connected to a vehicle information acquisition device 2320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2300 is also connected to a control ECU 2330, which is a control device (control unit) that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 2318. The photoelectric conversion system 2300 is also connected to an alarm device 2340 that issues an alarm to the driver based on the determination result of the collision determination unit 2318. For example, if the determination result of the collision determination unit 2318 indicates a high collision possibility, the control ECU 2330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 2340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0207] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 2300. Fig. 36(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 2350). A vehicle information acquisition device 2320 sends instructions to the photoelectric conversion system 2300 or the imaging device 2310. Such a configuration can further improve the accuracy of distance measurement.

[0208] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0209] (16th embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 37. Fig. 37 is a block diagram showing an example of the configuration of a range image sensor that is a photoelectric conversion system.

[0210] 37, the range image sensor 401 is configured to include an optical system 402, a photoelectric conversion device 403, an image processing circuit 404, a monitor 405, and a memory 406. The range image sensor 401 can obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 411 and reflected from the surface of the subject.

[0211] The optical system 402 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 403 , forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 403 .

[0212] The photoelectric conversion device 403 is the photoelectric conversion device described in the above-mentioned embodiment, and a distance signal indicating the distance determined from the light receiving signal output from the photoelectric conversion device 403 is supplied to the image processing circuit 404.

[0213] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 403. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0214] In the range image sensor 401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0215] (17th embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 38. Fig. 38 is a diagram showing an example of the schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0216] 38 shows an operator (doctor) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1003. As shown in the figure, the endoscopic surgery system 1003 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0217] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the example shown, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0218] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0219] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be the photoelectric conversion device described in the above-described embodiment. The image signal is sent to a camera control unit (CCU) 1135 as RAW data.

[0220] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0221] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0222] The light source device 1203 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0223] The input device 1137 is an input interface for the endoscopic surgery system 1003. A user can input various information and instructions to the endoscopic surgery system 1003 via the input device 1137.

[0224] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0225] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 1203. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0226] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0227] The light source device 1203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, specific tissue, such as blood vessels on the surface of the mucous membrane, can be photographed with high contrast by irradiating light with a narrower band than the light (i.e., white light) used in normal observation. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0228] (17th embodiment) The photoelectric conversion system of this embodiment will be described with reference to FIG. 39. FIG. 39(a) is a diagram showing an example of the configuration of glasses 1600 (smart glasses) which are the photoelectric conversion system. The glasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in the above-mentioned twelfth embodiment. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. Furthermore, multiple types of photoelectric conversion devices may be used in combination. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 39(a).

[0229] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0230] FIG. 22(b) illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0231] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0232] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0233] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0234] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0235] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0236] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0237] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0238] The above-described embodiments can be modified as appropriate without departing from the scope of the technical concept. Furthermore, examples in which part of the configuration of one embodiment is added to another embodiment, or examples in which part of the configuration of another embodiment is replaced with another embodiment, are also included in the embodiments of the present invention. [Explanation of symbols]

[0239] 300 Semiconductor layer 311 First semiconductor region 312 Second semiconductor region 314 Avalanche multiplier 321 Third Semiconductor Region 322 Fourth Semiconductor Region 331 Separation area 401 Depth 402 depth 403 Depth 1311 First semiconductor region 1312 Second semiconductor region 1314 Fourth semiconductor region (third semiconductor region included in the isolation portion) 1319 9th semiconductor region (4th semiconductor region of the 1st conductivity type)

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface; a plurality of avalanche photodiodes disposed in the semiconductor layer, the avalanche photodiodes including a first avalanche photodiode, a second avalanche photodiode, and a third avalanche photodiode; each of the plurality of avalanche photodiodes includes an avalanche multiplication section formed by a first semiconductor region of a first conductivity type, which has majority carriers of the same conductivity type as the signal charge and is arranged at a first depth relative to the first surface, and a second semiconductor region of a second conductivity type that is a conductivity type different from the first conductivity type and is arranged at a second depth deeper than the first depth relative to the first surface, In a plan view, the first avalanche photodiode and the second avalanche photodiode are arranged adjacent to each other in a first direction, and the second avalanche photodiode and the third avalanche photodiode are arranged adjacent to each other in a second direction perpendicular to the first direction, a third semiconductor region of the second conductivity type is disposed between the first avalanche photodiode and the second avalanche photodiode; a fourth semiconductor region is disposed between the first avalanche photodiode and the second avalanche photodiode and at a position shallower than the third semiconductor region; a fifth semiconductor region of the second conductivity type electrically connected to the second semiconductor region is disposed at the first depth between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the third avalanche photodiode; a surface of the third semiconductor region on the first surface side is disposed deeper than a surface of the first semiconductor region on the second surface side with respect to the first surface, a first contact plug to which a potential is supplied is connected to the first semiconductor region; a second contact plug to which a potential different from that of the first contact plug is supplied is connected to the fifth semiconductor region; the fourth semiconductor region is a semiconductor region of the second conductivity type in which the impurity concentration of the second conductivity type is lower than the impurity concentration of the second conductivity type in the third semiconductor region, or the semiconductor region of the first conductivity type, The photoelectric conversion device according to claim 1, wherein the impurity concentration of the fifth semiconductor region is the same as or higher than the impurity concentration of the third semiconductor region.

2. The photoelectric conversion device according to claim 1 , wherein the second semiconductor region is in contact with the third semiconductor region.

3. the fourth semiconductor region is a semiconductor region of the second conductivity type, 3. The photoelectric conversion device according to claim 1, wherein the width of the fourth semiconductor region is narrower than the width of the third semiconductor region.

4. 3. The photoelectric conversion device according to claim 1, wherein the fourth semiconductor region is a semiconductor region of the first conductivity type.

5. The photoelectric conversion device described in claim 3, characterized in that the depth of the boundary between the third semiconductor region and the fourth semiconductor region is shallower than the surface of the second semiconductor region on the first surface side relative to the first surface, or is the same as the depth at which the second semiconductor region is provided.

6. 4. The photoelectric conversion device according to claim 3, wherein a depth of a boundary between the third semiconductor region and the fourth semiconductor region is shallower than a surface of the second semiconductor region on the first surface side relative to the first surface.

7. 7. The photoelectric conversion device according to claim 1, wherein a distance between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the third avalanche photodiode is longer than a distance between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the second avalanche photodiode.

8. 8. The photoelectric conversion device according to claim 1, wherein the fifth semiconductor region has a higher impurity concentration of the second conductivity type than the third semiconductor region.

9. 9. The photoelectric conversion device according to claim 1, wherein each of the plurality of avalanche photodiodes is arranged at a third depth relative to the first surface that is deeper than the second depth, and includes a sixth semiconductor region that performs photoelectric conversion.

10. 10. The photoelectric conversion device according to claim 9, wherein the third semiconductor region is disposed between the sixth semiconductor region of the first avalanche photodiode and the sixth semiconductor region of the second avalanche photodiode.

11. the second semiconductor region has a first portion located between the first semiconductor region and the sixth semiconductor region and a second portion disposed around the first portion, 11. The photoelectric conversion device according to claim 10, wherein a potential level of the signal charge in the first portion of the second semiconductor region is lower than that in the second portion of the second semiconductor region.

12. 12. The photoelectric conversion device according to claim 9, wherein each of the plurality of avalanche photodiodes includes a seventh semiconductor region of the second conductivity type arranged at a fourth depth relative to the first surface, the fourth depth being deeper than the third depth.

13. The photoelectric conversion device according to claim 12 , wherein the seventh semiconductor region and the third semiconductor region are in contact with each other.

14. an isolation region including a trench structure disposed between the first avalanche photodiode and the second avalanche photodiode; 14. The photoelectric conversion device according to claim 1, wherein the third semiconductor region and the fourth semiconductor region are disposed on a sidewall of the trench structure.

15. 15. The photoelectric conversion device according to claim 14, wherein the trench structure penetrates from the second surface of the semiconductor layer to the first surface of the semiconductor layer.

16. 16. The photoelectric conversion device according to claim 14, wherein the trench structure is formed from the first surface of the semiconductor layer.

17. 17. The photoelectric conversion device according to claim 14, wherein the trench structure is formed from the second surface of the semiconductor layer.

18. 18. The photoelectric conversion device according to claim 14, wherein the trench structure is not arranged between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the third avalanche photodiode.

19. 18. The photoelectric conversion device according to claim 14, wherein the trench structure is arranged between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the third avalanche photodiode.

20. 20. The photoelectric conversion device according to claim 19, wherein the length of the trench structure in the depth direction of a cross section passing through the first avalanche photodiode and the third avalanche photodiode is different from the length of the trench structure in the depth direction of a cross section passing through the first avalanche photodiode and the second avalanche photodiode.

21. 21. The photoelectric conversion device according to claim 14, wherein at least one of a metal material, an insulating material, and air is disposed inside the trench structure.

22. The photoelectric conversion device according to any one of claims 1 to 21, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

23. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 21, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

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