Conversion program and conversion processing method

Abstract

To provide a conversion program and a conversion processing method for allocating processing to an appropriate accelerator.SOLUTION: In an information processing system including a management server, a node, an NW device, a storage device, a memory device, an FPGA device and a GPU device, a management server 100 being a computer for performing compilation of a source code of an application includes a program division part 121 for dividing the source program into a plurality of program blocks, an analysis part 122 for acquiring a result of analysis of access frequency to each of a plurality of accelerators by each of the plurality of program blocks, an arrangement destination determination part 123 for selecting a first program block among the plurality of program blocks and an accelerator to be an arrangement destination of the first program block from among the plurality of accelerators on the basis of the analysis result, and a logic conversion part 124 for converting the first program block into a hardware logic that operates in the accelerator of the arrangement destination.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a conversion program and a conversion processing method. [Background technology]

[0002] Computer systems with heterogeneous environments, where different types of computing units coexist, are in use. In heterogeneous environments, for example, offloading the processing of the CPU (Central Processing Unit) to an accelerator can improve computational performance. Accelerators such as FPGAs (Field Programmable Gate Arrays) and GPUs (Graphics Processing Units) are used.

[0003] Furthermore, the technology for converting source programs written in high-level languages ​​such as C or C++ into accelerator logic is called high-level synthesis. For example, a high-level synthesis system has been proposed that automatically generates the optimal hardware description language for hardware that adds external memory to an integrated circuit. Another proposal has been a parameter optimization system that determines the optimal combination of loop unrolling and circuit parallelism in high-level synthesis. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-2185 [Patent Document 2] Japanese Patent Application Publication No. 2019-215697 [Patent Document 3] US Patent Application Publication No. 2020 / 0225922 [Patent Document 4] U.S. Patent No. 8,739,102 [Patent Document 5] U.S. Patent Application Publication No. 2021 / 0116882 Summary of the Invention [Problem to be solved by the invention]

[0005] A node including a CPU may be connected to multiple accelerators, making it possible to offload processing from the CPU to multiple accelerators. For example, accelerators may be installed in various devices connected to the node, such as external storage devices, memory devices, and network devices. In this case, the problem is how to appropriately determine which parts of a source program should be allocated to which accelerators.

[0006] In one aspect, the present invention aims to allocate processing to an appropriate accelerator. [Means for solving the problem]

[0007] In one embodiment, a conversion program is provided that causes a computer to execute the following process: divide a source program into a plurality of program blocks, select a first program block from the plurality of program blocks and an accelerator from the plurality of accelerators in which to place the first program block based on a result of analyzing the number of times each of the plurality of program blocks accesses each of a plurality of accelerators, and convert the first program block into hardware logic that operates on the accelerator in which the first program block is placed.

[0008] Also, in one aspect, a conversion processing method is provided. [Effects of the Invention]

[0009] In one aspect, processing can be assigned to an appropriate accelerator. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an information processing apparatus according to a first embodiment. [Figure 2] FIG. 10 illustrates an example of an information processing system according to a second embodiment. [Figure 3] FIG. 2 illustrates an example of hardware of a management server. [Figure 4] FIG. 1 illustrates an example of hardware of an information processing system. [Figure 5] FIG. 2 illustrates an example of functions of a management server. [Figure 6] FIG. 10 is a diagram illustrating an example of source code. [Figure 7] FIG. 10 is a diagram illustrating an example of a loop description. [Figure 8] FIG. 10 is a diagram illustrating an example of interactions between program blocks. [Figure 9] FIG. 10 is a diagram illustrating an example of an interaction number table. [Figure 10] 10 is a flowchart illustrating an example of processing by a management server. [Figure 11] 10 is a flowchart illustrating an example of selecting a placement destination accelerator. [Figure 12] 10 is a flowchart illustrating an example of logic conversion. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present embodiment will be described below with reference to the drawings. [First embodiment] A first embodiment will be described.

[0012] FIG. 1 is a diagram illustrating an information processing apparatus according to a first embodiment. The information processing device 10 is connected to an information processing system 20 via a network. The information processing system 20 has a node 21 and accelerators 22, 23, and 24. The node 21 is connected to the accelerators 22, 23, and 24. The node 21 has a CPU and a RAM. The accelerators 22, 23, and 24 are realized by, for example, an FPGA, a GPU, a TPU (Tensor Processing Unit), and a DPU (Data Processing Unit). The information processing system 20 may have individual RAMs connected to the accelerators 22, 23, and 24, respectively. Furthermore, the information processing device 10 may be included in the information processing system 20.

[0013] The accelerators 22, 23, and 24 may be mounted in different types of devices, such as shared storage, shared memory, network (NW) devices, FPGA devices, and GPU devices.

[0014] The shared storage provides external storage shared by multiple nodes including node 21 in the information processing system 20. The shared memory provides external memory shared by the multiple nodes. The NW device relays communications between nodes. The FPGA device provides an external FPGA to node 21. The GPU device provides an external GPU to node 21.

[0015] The accelerators 22, 23, and 24 execute predetermined functions of devices such as shared storage and network devices, and can also be used as a destination to offload processing from the CPU of the node 21. An example of such an accelerator is a smart NIC (Network Interface Card) in a network device, which is realized by an FPGA or the like.

[0016] For example, the accelerator 22 may be mounted in a shared storage, the accelerator 23 may be mounted in a shared memory, the accelerator 24 may be mounted in a network device, or the accelerators 22, 23, and 24 may be mounted in an FPGA device or a GPU device.

[0017] The node 21 and the accelerators 22, 23, and 24 may be connected via an interconnect such as CXL (Compute Express Link, registered trademark) or a network such as Ethernet (registered trademark) or Infiniband. In the following description, the identifier of the accelerator 22 is X. The identifier of the accelerator 23 is Y. The identifier of the accelerator 24 is Z.

[0018] The information processing device 10 compiles a source program 30 written in a high-level language such as C or C++ to generate an executable file to be executed by the information processing system 20. In the information processing system 20, calculations are executed by the CPU of the node 21 and at least some of the accelerators 22, 23, and 24. An environment in which multiple types of calculation units coexist, such as the information processing system 20, is called a heterogeneous environment.

[0019] The information processing device 10 has a storage unit 11 and a processing unit 12. The storage unit 11 may be a volatile storage device such as a random access memory (RAM), or a non-volatile storage device such as a hard disk drive (HDD) or flash memory. The storage unit 11 stores a source program 30 and data used in processing by the processing unit 12.

[0020] The processing unit 12 may include a CPU, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA, etc. The processing unit 12 may also be a processor that executes a program. The term "processor" may include a collection of multiple processors (multiprocessor).

[0021] During compilation, the processing unit 12 converts at least a portion of the description of the source program 30 into hardware logic that runs on one of the accelerators, enabling the processing related to the description to be offloaded from the node 21 to the accelerator. High-level synthesis technology is used to convert the description of the source program 30 into hardware logic that runs on the accelerator. High-level synthesis may be performed based on a coarse-grained reconfigurable architecture (CGRA). Tools that perform high-level synthesis, i.e., high-level synthesis tools, include, for example, Vivado (registered trademark) HLS and Intel (registered trademark) HLS Compiler. HLS stands for High-Level Synthesis.

[0022] First, the processing unit 12 divides the source program 30 into a plurality of program blocks. A program block is a set of functions. For example, the processing unit 12 divides the source program 30 into a predetermined number of program blocks so that the number of functions included in each program block is approximately the same. The processing unit 12 may also divide the source program 30 into a predetermined number of program blocks so that the number of lines of code included in each program block is approximately the same. For example, the plurality of program blocks includes program blocks 31, 32, .... The identifier of program block 31 is A. The identifier of program block 32 is B.

[0023] The processing unit 12 analyzes the number of times each of the program blocks accesses each of the accelerators. The number of times each program block accesses each of the accelerators corresponds to, for example, the number of times the program block calls the accelerator.

[0024] The number of calls to an accelerator can be obtained by counting the number of calls to a predetermined function included in a program block that corresponds to the type of device on which the accelerator is installed. Taking the C language as an example, the predetermined functions according to the device type include the following: For shared storage, for example, the ftputc function, ftputs function, and ftprintf function; For shared memory, for example, the mmap function; For network devices, for example, the ioctl function, socket function, and connect function; For GPU devices, for example, CUDA (registered trademark); For FPGA devices, for example, the fftw function and the GROMACS gmx_fft library function.

[0025] For example, for program block 31, processing unit 12 obtains the number of accesses to accelerator 22 as "1" and the number of accesses to other accelerators as "0." Also, for program block 32, processing unit 12 obtains the number of accesses to accelerator 23 as "1," the number of accesses to accelerator 24 as "2," and the number of accesses to other accelerators as "0."

[0026] The processing unit 12 selects a first program block from among the multiple program blocks based on the results of the access count analysis. For example, the processing unit 12 selects a program block for which the number of accesses to at least one accelerator is equal to or greater than one as the first program block. The processing unit 12 also selects an accelerator from among the multiple accelerators to which the first program block is to be placed. For example, for each program block, the processing unit 12 selects the accelerator with the highest number of accesses from that program block as the accelerator to which that program block is to be placed.

[0027] For example, program block 31 has the most number of accesses to accelerator 22. Therefore, processing unit 12 places program block 31 in accelerator 22. Also, for example, program block 32 has the most number of accesses to accelerator 24. Therefore, processing unit 12 places program block 32 in accelerator 24. The placement accelerators for other program blocks are determined in a similar manner. Note that a program block that does not access any accelerator is not placed in any accelerator and is assigned to node 21. Also, if there are two or more accelerators that have the most number of accesses for a certain program block, processing unit 12 may preferentially select an accelerator installed in a data storage device such as a shared memory from among the two or more accelerators.

[0028] Table 40 indicates the accelerator to which each program block is to be placed. For example, table 40 indicates that program block 31 with identifier A is to be placed in accelerator 22 corresponding to identifier X. Table 40 also indicates that program block 32 with identifier B is to be placed in accelerator 24 corresponding to identifier Z. Both program blocks 31 and 32 are examples of first program blocks.

[0029] The processing unit 12 converts the first program block into hardware logic that operates on the accelerator where the first program block is to be placed. The processing unit 12 can use an existing high-level synthesis tool that corresponds to the accelerator to convert the first program block into hardware logic. The hardware logic may also be logic specialized for specific hardware, such as a GPU.

[0030] For example, the processing unit 12 converts the program block 31 into logic 51 that operates on the accelerator 22 based on the table 40. The identifier "AX" of the logic 51 indicates that the logic 51 is obtained by converting the program block 31 into hardware logic that operates on the accelerator 22. The processing unit 12 also converts the program block 32 into logic 52 that operates on the accelerator 24 based on the table 40. The identifier "BZ" of the logic 52 indicates that the logic 52 is obtained by converting the program block 32 into hardware logic that operates on the accelerator 24.

[0031] The processing unit 12 offloads processing corresponding to a part of the source program 30 from the node 21 to the accelerator. That is, the processing unit 12 compiles a main application to be executed on the node 21 based on the source program 30 and performs high-level synthesis of program blocks to be offloaded to the accelerator. Then, the processing unit 12 generates an executable file including an executable program of the main application that cooperates with the accelerator and synthesized hardware logic information (for example, circuit information of an FPGA, etc.).

[0032] The processing unit 12 causes the node 21 to execute the generated executable file. The node 21 then configures the corresponding accelerator using the hardware logic information, and executes processing in cooperation with the accelerator using the main application.

[0033] As described above, according to the information processing device 10, a source program is divided into a plurality of program blocks. The results of an analysis of the number of accesses by each of the plurality of program blocks to each of a plurality of accelerators are obtained. Based on the results of the analysis of the number of accesses, a first program block from the plurality of program blocks and an accelerator from the plurality of accelerators in which the first program block is to be placed are selected. The first program block is converted into hardware logic that operates on the accelerator in which the first program block is to be placed.

[0034] This allows the information processing device 10 to assign processing to an appropriate accelerator. Specifically, the information processing device 10 preferentially allocates each program block of the source program 30 to an accelerator that has a high number of accesses for that program block. This reduces data transfer between the CPU of the node 21 and the accelerator when executing processing related to that program block. As a result, overhead related to the data transfer is reduced. In this way, the information processing device 10 can improve the processing performance of the information processing system 20.

[0035] The processing unit 12 may use the results of simulating the operation of the logic 51, 52, ... corresponding to the program blocks 31, 32, ... to calculate performance indicators such as the calculation time and power consumption required to execute the processing corresponding to the source program 30. The processing unit 12 may then similarly re-arrange the program blocks on each accelerator to generate hardware logic and calculate the performance indicators even when the source program 30 is divided into different division units. The processing unit 12 may thus try dividing the source program 30 into several division units, select the division unit with the best performance indicator, and compile the source program 30. This allows the information processing device 10 to further improve the processing performance of the information processing system 20 that executes the processing corresponding to the source program 30.

[0036] [Second embodiment] Next, a second embodiment will be described. FIG. 2 illustrates an example of an information processing system according to the second embodiment.

[0037] The information processing system of the second embodiment includes a management server 100, nodes 200, a network device 300, a storage device 400, a memory device 500, an FPGA device 600, and a GPU device 700. The management server 100 and the nodes 200 are connected to the network device 300. The storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700 are connected to the node 200. For example, CXL is used as an interface for connecting the node 200 with the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700.

[0038] The management server 100 is a computer that compiles application source code. The source code is written in a high-level language such as C or C++. The source code may also be referred to as a source program. The management server 100 causes the node 200 to execute the executable file generated by the compilation. Multiple accelerators are connected to the node 200. The accelerators are realized, for example, by FPGAs, GPUs, TPUs, and DPUs. The accelerators may also be referred to as hardware accelerators. The management server 100 offloads some processing to the accelerators so that the node 200 executes the application in cooperation with the multiple accelerators. The management server 100 uses high-level synthesis technology to convert the source code description into accelerator logic. The high-level synthesis may be performed based on CGRA.

[0039] The node 200 is a computer that executes an application in cooperation with multiple accelerators. The node 200 offloads part of the application processing to the accelerators installed in the network device 300, the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700.

[0040] The network device 300 is a communication device that relays communication between the management server 100 and the node 200. The network device 300 has a network accelerator realized by, for example, an FPGA. The network accelerator may be what is called a smart NIC. Although not shown in FIG. 2, multiple nodes including the node 200 and other network devices may be connected to the network device 300.

[0041] The storage device 400 is an external storage externally attached to the node 200. The storage device 400 has a shared storage shared by a plurality of nodes including the node 200. The storage device 400 has a storage accelerator realized by, for example, an FPGA.

[0042] The memory device 500 is an external memory attached to the node 200. The memory device 500 has a shared memory shared by a plurality of nodes including the node 200. The memory device 500 has a memory accelerator realized by, for example, an FPGA.

[0043] The FPGA device 600 is an arithmetic device external to the node 200. The FPGA device 600 includes an FPGA as an accelerator that can be used by the node 200. The GPU device 700 is an external computing device attached to the node 200. The GPU device 700 includes a GPU as an accelerator that can be used by the node 200.

[0044] In this way, the information processing system according to the second embodiment has a heterogeneous environment or a heterogeneous network. FIG. 3 illustrates an example of hardware of the management server.

[0045] The management server 100 includes a CPU 101, a RAM 102, a HDD 103, a GPU 104, an input interface 105, a media reader 106, and a NIC 107. The CPU 101 is an example of the processing unit 12 of the first embodiment. The RAM 102 or the HDD 103 is an example of the storage unit 11 of the first embodiment.

[0046] The CPU 101 is a processor that executes program instructions. The CPU 101 loads at least a portion of the programs and data stored in the HDD 103 into the RAM 102 and executes the programs. The CPU 101 may include multiple processor cores. The management server 100 may also have multiple processors. The processing described below may be executed in parallel using multiple processors or processor cores. A set of multiple processors may also be called a "multiprocessor" or simply a "processor."

[0047] The RAM 102 is a volatile semiconductor memory that temporarily stores programs executed by the CPU 101 and data used in calculations by the CPU 101. The management server 100 may be provided with a type of memory other than RAM, or may be provided with multiple memories.

[0048] The HDD 103 is a nonvolatile storage device that stores software programs such as an OS (Operating System), middleware, and application software, as well as data. The management server 100 may also be provided with other types of storage devices, such as flash memory or an SSD (Solid State Drive), or may be provided with multiple nonvolatile storage devices.

[0049] The GPU 104 outputs an image to a display 61 connected to the management server 100 in accordance with an instruction from the CPU 101. The display 61 may be any type of display, such as a CRT (Cathode Ray Tube) display, a liquid crystal display (LCD: Liquid Crystal Display), a plasma display, or an organic EL (OEL: Organic Electro-Luminescence) display.

[0050] The input interface 105 acquires input signals from input devices 62 connected to the management server 100 and outputs them to the CPU 101. The input devices 62 may be pointing devices such as a mouse, a touch panel, a touch pad, or a trackball, a keyboard, a remote controller, or a button switch. In addition, multiple types of input devices may be connected to the management server 100.

[0051] The medium reader 106 is a reading device that reads programs and data recorded on the recording medium 63. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO: Magneto-Optical disk), a semiconductor memory, etc. can be used as the recording medium 63. Magnetic disks include flexible disks (FD: Flexible Disks) and HDDs. Optical disks include compact discs (CDs) and digital versatile discs (DVDs).

[0052] The medium reader 106 copies programs and data read from the recording medium 63 to another recording medium such as the RAM 102 or the HDD 103. The read programs are executed by the CPU 101, for example. The recording medium 63 may be a portable recording medium, which may be used to distribute programs and data. The recording medium 63 and the HDD 103 may also be referred to as computer-readable recording media.

[0053] The NIC 107 is connected to the network device 300 and is an interface for communicating with other computers including the node 200 via the network device 300. The NIC 107 is connected to the network device 300 by a cable, for example.

[0054] FIG. 4 is a diagram illustrating an example of hardware of an information processing system. The node 200 includes a CPU 201, a memory 202, a storage 203, and a CXL switch 204. The CPU 201 is the processor of the node 200. The CPU 201 executes programs stored in the memory 202. The memory 202 is the main storage device of the node 200. The memory 202 stores the programs executed by the CPU 201. The memory 202 is, for example, a RAM such as a DRAM (Dynamic RAM). The same applies to the memories described below.

[0055] The storage 203 is an auxiliary storage device of the node 200. For example, the storage 203 stores an executable file of an application generated by the management server 100. The CPU 201 loads the executable file stored in the storage 203 into the memory 202 and executes it.

[0056] The CXL switch 204 is an interconnect that connects the node 200 with the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700.

[0057] The NW device 300 has a NW accelerator 301 and a switch 302. The NW accelerator 301 is an accelerator that can be used to offload processing from the node 200. The NW accelerator 301 is realized by, for example, an FPGA. The switch 302 determines the transfer destination of received data and transmits the data to the determined transfer destination based on layer 3 or layer 2 protocols. For example, an example of a layer 3 protocol is IP (Internet Protocol). An example of a layer 2 protocol is Ethernet. Although not shown, the NW device 300 has a memory that stores data to be processed by the NW accelerator 301.

[0058] The storage device 400 has a storage accelerator 401 and a shared storage 402. The storage accelerator 401 is an accelerator that can be used as an offload destination for processing of the node 200. The storage accelerator 401 is realized by, for example, an FPGA. The shared storage 402 is storage shared by multiple nodes including the node 200. The shared storage 402 is realized by, for example, an HDD or an SSD. Although not shown in the figure, the storage device 400 has a memory that holds data to be processed by the storage accelerator 401.

[0059] The memory device 500 includes a memory accelerator 501 and a shared memory 502. The memory accelerator 501 is an accelerator that can be used as an offload destination for processing of the node 200. The memory accelerator 501 is realized by, for example, an FPGA. The shared memory 502 is a memory shared by multiple nodes including the node 200. At least a portion of the storage area of ​​the shared memory 502 may be used to hold data to be processed by the memory accelerator 501.

[0060] For example, the storage device 400 and the memory device 500 may be connected to other nodes (not shown) via a CXL interface. The FPGA device 600 includes an FPGA 601 and a memory 602. The FPGA 601 is an accelerator that can be used to offload processing from the node 200. The memory 602 holds data to be processed by the FPGA 601.

[0061] The GPU device 700 includes a GPU 701 and a memory 702. The GPU 701 is an accelerator that can be used to offload processing from the node 200. The memory 702 holds data to be processed by the GPU 701.

[0062] FIG. 5 illustrates an example of functions of the management server. The management server 100 includes a storage unit 110 and a control unit 120. The storage unit 110 uses storage areas of the RAM 102 and the HDD 103. The control unit 120 is realized by the CPU 101 executing a program stored in the RAM 102.

[0063] The storage unit 110 stores source code of an application to be executed by the node 200. The storage unit 110 also stores executable files that are the result of the control unit 120 compiling the source code.

[0064] The control unit 120 compiles the source code. The control unit 120 generates an executable file so as to offload part of the processing related to the source code to one of the accelerators connected to the node 200. The control unit 120 includes a program dividing unit 121, an analyzing unit 122, a placement determining unit 123, a logic converting unit 124, a performance evaluating unit 125, and a compiling processing unit 126.

[0065] The program division unit 121 divides the source code into a plurality of program blocks. The program block divisions are function divisions. A program block may also be called a task block. One or more functions belong to one program block. The division unit is determined by the number of main functions and the code capacity (number of lines) included in one program block. Multiple patterns of division units are prepared in advance.

[0066] For example, when classifying division units by the number of main functions, the following three types of granularity of division units are predefined: Large granularity means that the number of main functions is about 20 or more; Medium granularity means that the number of main functions is about 5 to 20; and Small granularity means that the number of main functions is less than about 5.

[0067] Furthermore, for example, when classifying division units by code size, the following three types of division unit granularity are predefined: Large granularity means that the number of lines is approximately 1000 or more; Medium granularity means that the number of lines is approximately 500 to 1000; and Small granularity means that the number of lines is approximately less than 500.

[0068] The analysis unit 122 analyzes interactions between program blocks and between program blocks and accelerators. The interactions between program blocks indicate the order in which each program block is executed relative to other program blocks, and whether or not it can be executed in parallel with other program blocks.

[0069] An interaction between a program block and an accelerator indicates an access from the program block to the accelerator. The analysis unit 122 counts the number of interactions between the program block and the accelerator. Specifically, the analysis unit 122 counts the number of times the accelerator is called by a predetermined function included in the program block (the number of calls) as the number of interactions between the program block and the accelerator. The analysis unit 122 acquires the number of interactions for each pair of a program block and an accelerator.

[0070] If the number of interactions between a program block and an accelerator is 1 or more, the program block is said to have an interaction with the accelerator. If the number of interactions between a program block and an accelerator is 0, the program block is said to have no interaction with the accelerator.

[0071] The placement destination determination unit 123 determines an accelerator to which the program block should be placed based on the number of interactions acquired by the analysis unit 122 for each pair of program block and accelerator. Specifically, if a program block has only interactions with a single accelerator, the placement destination determination unit 123 determines the program block as the placement destination of the accelerator. If a program block has interactions with multiple accelerators, the placement destination determination unit 123 determines the accelerator with the largest number of interactions as the placement destination of the program block. If a program block has no interactions with any accelerators, the placement destination determination unit 123 assigns the program block to the CPU 201 of the node 200.

[0072] The logic conversion unit 124 converts each program block into hardware logic that operates on the accelerator at the placement destination determined by the placement destination determination unit 123. An existing high-level synthesis tool can be used for the logic conversion by the logic conversion unit 124. Examples of existing high-level synthesis tools include Vivado HLS and Intel HLS Compiler.

[0073] The performance evaluation unit 125 evaluates the runtime performance of the application based on performance information for each program block obtained from the results of an operation simulation using the hardware logic generated by the logic conversion unit 124. The performance evaluation unit 125 evaluates the runtime performance of the application for the results of dividing the source code into multiple patterns of division units, and selects the division unit that provides the best performance.

[0074] The compilation processing unit 126 compiles the source code so that each program block is offloaded to the accelerator where it is to be placed when the source code is divided into division units selected by the performance evaluation unit 125, and generates an executable file.

[0075] The control unit 120 tries division into a plurality of patterns of division units such as large granularity, medium granularity, and small granularity, selects the division unit with the best performance index, and compiles the source code. FIG. 6 is a diagram illustrating an example of source code.

[0076] The source code 111 is stored in the storage unit 110. The source code 111 is written in C language and is the source code of an application to be executed by the node 200. Each line of the source code 111 is assigned a line number for convenience. In the example of the source code 111, the definition of the structure gmx_many_fft on lines 1 to 6 marks the delimiter of the first main function. The definition of the function gmx_fft_init_many_1d on the following lines 8 to 18 marks the delimiter of the second main function. The description on line 8 at the delimiter of the second main function corresponds to a call of the fft function.

[0077] FIG. 7 is a diagram showing an example of a loop description. Code 111c shows an example of a loop description that may be included in source code 111. Code 111c is an example of a description of matrix product c of matrices a and b. a, b, and c are all square matrices with n rows and n columns. Code 111c includes a loop description that is repeatedly executed using a for statement. Calculations related to such loop descriptions are well suited to accelerators such as FPGAs, and can be processed efficiently by offloading them to an accelerator.

[0078] FIG. 8 is a diagram showing an example of interactions between program blocks. The source code 111 is divided into a plurality of program blocks by the program division unit 121. The plurality of program blocks includes program blocks A, B, C, .... The analysis unit 122 obtains the order relationship of the program blocks A, B, C, ... as the interactions between the program blocks. For example, the analysis unit 122 can obtain the order relationship by analyzing the dependency relationships of the variables included in each program block using existing technology.

[0079] For example, sequence 71 shows a case where program blocks A, B, and C are executed serially in this order, such that program block A is followed by program block B, and program block B is followed by program block C. Sequence 72 shows a case where program blocks B and C can be executed in parallel after program block A. The analysis results of the interactions between program blocks are used to evaluate the time required to execute the calculation corresponding to source code 111 (computation time).

[0080] FIG. 9 is a diagram illustrating an example of the interaction number table. The interaction number table 112 is a table that holds the analysis results of the number of interactions between program blocks and accelerators. The interaction number table 112 is generated by the analysis unit 122 and stored in the memory unit 110. The interaction number table 112 includes the following items: program block ID (IDentifier), number of storage interactions, number of NW interactions, number of memory interactions, number of FPGA interactions, and number of GPU interactions.

[0081] The program block ID field contains the program block ID, which is identification information for the program block. The number of storage interactions is registered in the item of the number of storage interactions. The number of storage interactions corresponds to the number of calls from the node 200 to the storage device 400 based on the corresponding program block.

[0082] The number of NW interactions is registered in the item of the number of NW interactions. The number of NW interactions corresponds to the number of calls from the node 200 to the NW device 300 based on the corresponding program block.

[0083] The number of memory interactions is registered in the memory interaction number field. The number of memory interactions corresponds to the number of calls from the node 200 to the memory device 500 based on the corresponding program block.

[0084] The number of FPGA interactions is registered in the field of the number of FPGA interactions. The number of FPGA interactions corresponds to the number of calls from the node 200 to the FPGA device 600 based on the corresponding program block.

[0085] The number of GPU interactions is registered in the GPU Interaction Count field. The number of GPU interactions corresponds to the number of calls from the node 200 to the GPU device 700 based on the corresponding program block.

[0086] The number of interactions for a device indicates the number of accesses from the corresponding program block to the accelerator installed in the device. For example, the analysis unit 122 obtains the number of interactions for the device by counting the number of calls to a predetermined function included in the corresponding program block and corresponding to the device.

[0087] Taking the C language as an example, the following functions are specific to the device type, i.e., specific functions corresponding to the accelerator installed in the device. For the shared storage (storage device 400), functions for writing to files include the ftputc function, ftputs function, and ftprintf function. For the shared memory (memory device 500), functions include the mmap function. For the NW device 300, functions include the ioctl function, socket function, and connect function. For the GPU device 700, functions include the CUDA function. For the FPGA device 600, functions include the fftw function, which is a Fourier transform function, and the gmx_fft library function of GROMACS. Other computational functions that FPGAs excel at include matrix multiplication, multiplication, multiply-and-accumulate operations, barrel shifters, complex number operations, and trigonometric function operations, as shown in Figure 7. Note that the computational functions that FPGAs excel at differ depending on the environment and application, and therefore may be other functions.

[0088] For example, the interaction number table 112 has a record with a program block ID of "A," a storage interaction count of "4," a network interaction count of "0," a memory interaction count of "0," a FPGA interaction count of "0," and a GPU interaction count of "0." This record indicates that the storage interaction count of program block A is 4, the network interaction count is 0, the memory interaction count is 0, the FPGA interaction count is 0, and the GPU interaction count is 0. The interaction number table 112 also has records for other program blocks, including program blocks B and C.

[0089] Next, the processing procedure performed by the management server 100 will be described. FIG. 10 is a flowchart illustrating an example of processing by the management server. (S10) The program division unit 121 divides the source code 111 into a plurality of program blocks using a predetermined division unit. The plurality of program blocks includes, for example, program blocks A, B, C, .... Here, the program division unit 121 changes the division unit from large granularity to medium granularity to small granularity each time step S10 is executed. As described above, each granularity of the division unit is determined in advance based on the number of main functions and the number of lines of code included in one program block.

[0090] (S11) The analysis unit 122 analyzes the interactions between the program blocks obtained in step S10. Specifically, as illustrated in Fig. 8, the analysis unit 122 analyzes the context of each program block and the possibility of parallel execution.

[0091] (S12) The analysis unit 122 analyzes the interactions of each program block with the accelerator. Specifically, based on the description of the program block, the analysis unit 122 obtains the number of calls to a predetermined function corresponding to the device equipped with the accelerator as the number of interactions, and records the number of interactions in the interaction number table 112.

[0092] (S13) The placement destination determination unit 123 determines an accelerator to which the program block is to be placed based on the interaction number table 112, which is the analysis result of the analysis unit 122. Details of the processing by the placement destination determination unit 123 will be described later.

[0093] (S14) The logic conversion unit 124 performs logic conversion. Specifically, the logic conversion unit 124 uses an existing high-level synthesis tool to convert the program block into logic that operates in the accelerator at the placement destination. Details of the processing by the logic conversion unit 124 will be described later. In addition, the logic conversion unit 124 performs an operation simulation of the converted logic, and acquires the calculation time and power consumption required for the operation corresponding to each program block.

[0094] (S15) The performance evaluation unit 125 calculates the calculation time and power consumption required to execute the entire application corresponding to the source code 111 based on the calculation time and power consumption obtained in step S14. For example, the performance evaluation unit 125 may calculate the calculation time of the entire application based on the analysis results of the interactions between program blocks analyzed in step S11 and the calculation time of each program block in each accelerator. Specifically, for a portion of the source code 111 where the execution order of each program block is serial, the performance evaluation unit 125 adds up the calculation times corresponding to each program block. Furthermore, for a portion of the source code 111 where two or more program blocks can be executed in parallel, the performance evaluation unit 125 determines the longest calculation time among the two or more program blocks. Furthermore, the performance evaluation unit 125 calculates the overall power consumption by summing the power consumption of each accelerator and the power consumption of the CPU 201. The performance evaluation unit 125 can also evaluate the calculation time and power consumption of the portion of the source code 111 assigned to the CPU 201 using existing techniques such as static analysis, simulation, or machine learning model for that portion.

[0095] (S16) The performance evaluation unit 125 determines whether performance evaluation has been completed for all division units prepared in advance. If performance evaluation has been completed for all division units, the process proceeds to step S17. If performance evaluation has not been completed for all division units, the process proceeds to step S10. In step S10, the program division unit 121 divides the source code 111 into unprocessed division units, and the subsequent steps are executed.

[0096] (S17) The compilation processing unit 126 compiles the source code 111 by adopting the accelerator placement of each program block in the division unit that yields the best performance evaluation result by the performance evaluation unit 125. The compilation processing unit 126 generates an executable file based on the source code 111. The executable file includes an executable program that causes the CPU 201 to execute calculations in cooperation with each accelerator, and hardware logic information for configuring each accelerator. The hardware logic information is, for example, information used to configure the circuit of the accelerator. For example, the hardware logic information may be an RTL (Register Transfer Level) description of an FPGA or the like. The hardware logic information may also be information indicating logic specialized for specific hardware such as a GPU. Then, the processing of the management server 100 ends.

[0097] In addition, in the selection criteria for the division unit that has the best performance evaluation result in step S17, for example, the division unit with the shortest calculation time and power consumption is selected with the highest priority. If there is no division unit with the shortest calculation time and power consumption, for example, the division unit with the shortest calculation time or power consumption is selected with the highest priority. However, this selection criteria is just an example, and other selection criteria may be used.

[0098] For example, the management server 100 causes the CPU 201 of the node 200 to execute the generated executable file. The CPU 201 then configures the corresponding accelerator using the hardware logic information included in the executable file, and executes the application processing in cooperation with the accelerator.

[0099] FIG. 11 is a flowchart showing an example of selecting a destination accelerator. The selection of the accelerator to be placed corresponds to step S13. (S20) The placement destination determination unit 123 obtains the number of interactions for each program block based on the interaction count table 112. The placement destination determination unit 123 extracts program blocks whose interaction counts recorded in the interaction count table 112 are not all 0, and executes the following steps from step S21 onwards for each of these program blocks.

[0100] (S21) The placement destination determination unit 123 determines whether there are multiple interaction types in the same program block. If there are multiple interaction types in the same program block, processing proceeds to step S22. If there are not multiple interaction types in the same program block, processing proceeds to step S23. Here, "there are multiple interaction types" corresponds to "there are multiple items in the interaction count table 112 with the number of interactions being 1 or more for the corresponding program block." "There are not multiple interaction types" corresponds to "there is only one item in the interaction count table 112 with the number of interactions being 1 or more for the corresponding program block."

[0101] (S22) The placement destination determination unit 123 compares the number of interactions and determines to place the corresponding program block in the accelerator with the largest number of interactions. Note that if the numbers are the same, i.e., if there are multiple accelerators with the largest number of interactions, the placement destination determination unit 123 determines to place the corresponding program block in the accelerator closest to the read data. For example, if the number of NW interactions and the number of memory interactions are the same, the placement destination determination unit 123 prioritizes and selects the memory accelerator 501 closest to the data as the placement destination. Then, the placement destination determination unit 123 ends processing for the corresponding program block.

[0102] (S23) The placement destination determination unit 123 determines to place the program block in the accelerator whose interaction count is equal to or greater than 1. Then, the placement destination determination unit 123 ends the processing for the program block.

[0103] The placement destination determination unit 123 assigns to the CPU 201 of the node 200 a program block whose interaction count recorded in the interaction count table 112 is all 0.

[0104] FIG. 12 is a flowchart illustrating an example of logic conversion. The logic conversion corresponds to step S14. The logic conversion is performed for each accelerator.

[0105] (S30) The logic conversion unit 124 extracts loops from the program block in which the accelerator is to be placed. (S31) The logic conversion unit 124 converts the corresponding program block into hardware logic that operates on the accelerator by reconfiguring the PE (Processing Element) in the accelerator. For example, a description of a loop or the like extracted in step S30 is converted into hardware logic. The logic conversion unit 124 generates hardware logic information that indicates the hardware logic.

[0106] The logic conversion unit 124 can convert the program block description into hardware logic using an existing high-level synthesis tool. (S32) The logic conversion unit 124 simulates the operation of the accelerator based on the hardware logic information generated in step S31, and calculates performance. In step S32, the logic conversion unit 124 calculates, as performance, for example, the calculation time for each hardware logic corresponding to the program block.

[0107] (S33) The logic conversion unit 124 determines whether the calculation time is the shortest. If the calculation time is the shortest, the process proceeds to step S34. If the calculation time is not the shortest, the process proceeds to step S31, and the process starts again from reconfiguring the PE. The calculation time in step S33 is the total calculation time in the accelerator. Note that when step S33 is executed for a certain accelerator for the first time, there is no calculation time to compare, so the logic conversion unit 124 proceeds to step S34 without making a determination in step S33.

[0108] (S34) The logic conversion unit 124 calculates the power consumption of the accelerator. For example, the logic conversion unit 124 may calculate the power consumption based on the catalog value of the accelerator's power consumption and the total calculation time of the accelerator. Alternatively, the logic conversion unit 124 may calculate the power consumption using a machine learning model that outputs power consumption in response to input hardware logic information. For example, the initial value of power consumption may be calculated based on the catalog value of power consumption, or power consumption data may be accumulated while being corrected and learned from an operation log.

[0109] (S35) The logic conversion unit 124 determines whether the power consumption is minimum. If the power consumption is minimum, the logic conversion for the accelerator is completed. If the power consumption is not minimum, the process proceeds to step S31, and the process starts again from the reconfiguration of the PE. Note that when step S35 is executed for a certain accelerator for the first time, there is no power consumption to compare, so the logic conversion unit 124 proceeds to step S31 without making the determination in step S35.

[0110] It should be noted that there may be cases where a final hardware logic conversion result cannot be obtained even after repeating the procedure of steps S31 to S35 a predetermined number of times. In this case, the logic conversion unit 124 may select, as the final conversion result, a conversion result that has the best priority on calculation time and power consumption among conversion results that have both calculation time and power consumption better than the target values.

[0111] This completes the description of the processing procedure performed by the management server 100. The technology that converts application programs into accelerator logic is called high-level synthesis (CGRA). CGRA involves the consideration of the number of function repetitions (loop extraction) and microarchitectural optimization of wiring. Generally, CGRA reconfiguration involves reducing the granularity (unit of division) to a smaller function, etc., and then arranging the function repetition and microarchitecture in consideration of the function repetition. This allows, for example, repetitive processing parts that were previously performed only by the CPU to be placed in the accelerator, improving computational speed and energy efficiency through microarchitectural efficiency. In addition, Just-in-Time high-level synthesis, which reconfigures CGRAs during compilation, reduces compilation time and improves performance by mapping loops.

[0112] However, in a heterogeneous environment, accelerators targeted by CGRA are located in various locations. For example, accelerators such as FPGAs and GPUs are not limited to within the chip of the node 200, but are also located in various locations, such as near external storage via an interconnect or near the network. For this reason, existing high-level synthesis techniques alone can only locally optimize specific accelerators, but global optimization is difficult.

[0113] In this way, when the granularity of the reconfiguration is finer, ease of compilation and local optimization can be achieved, but the overall optimization may not be achieved. This is because the locations of accelerators (targets of CGRA) are scattered, such as near the core, near the memory, near the network, and near the storage, and the interactions between each of these locations affect the overall optimization.

[0114] Therefore, the management server 100 considers the interaction with each accelerator in the program block and prioritizes compositing accelerators with more interactions, thereby achieving not only local optimization but also global optimization. In other words, it is possible to achieve CGRA conversion that is optimized for the entire system including multiple accelerators.

[0115] Specifically, the management server 100 prioritizes allocation of each program block of the source code 111 to an accelerator that has a high number of accesses for that program block. This reduces data transfer between the CPU 201 and the accelerator when executing processing related to that program block. As a result, overhead related to the data transfer is reduced. In this way, the management server 100 can improve processing performance during application execution through cooperation between the node 200 and the accelerator.

[0116] Furthermore, the management server 100 can execute a program at an optimal execution speed while reducing power consumption in the entire system by selecting the optimal division unit in consideration of calculation time and power consumption.

[0117] As described above, the management server 100 executes the following processes. The control unit 120 divides the source program into multiple program blocks. The control unit 120 acquires the results of an analysis of the number of accesses by each of the multiple program blocks to each of the multiple accelerators. Based on the analysis results, the control unit 120 selects a first program block from the multiple program blocks and an accelerator from the multiple accelerators on which to place the first program block. The control unit 120 converts the first program block into hardware logic that operates on the accelerator on which to place it.

[0118] This allows the management server 100 to assign processing to an appropriate accelerator. For example, data transfer between the CPU 201 and the accelerator during execution of processing related to a program block allocated to the accelerator is reduced. As a result, overhead related to the data transfer is reduced. In this way, the management server 100 can improve processing performance during application execution through cooperation between the node 200 and the accelerator. Note that the source code 111 is an example of a source program. The number of storage interactions, the number of network interactions, the number of memory interactions, the number of FPGA interactions, and the number of GPU interactions are examples of the number of accesses to each of multiple accelerators.

[0119] Furthermore, when selecting an accelerator for placement, the control unit 120 may select, from among multiple accelerators, the accelerator that has been accessed the most by the first program block as the accelerator for placement. This allows the management server 100 to efficiently reduce data transfer between the CPU 201 and the accelerator when executing processing related to the program block placed in the accelerator.

[0120] The multiple accelerators may also include a first accelerator provided in the memory device 500. When selecting an accelerator for placement, if two or more accelerators with the same number of accesses by the first program block include the first accelerator, the control unit 120 may preferentially select the first accelerator as the accelerator for placement. This allows the management server 100 to efficiently reduce data transfer between the CPU 201 and the accelerator when executing processing related to the program block placed in the accelerator. Note that the memory accelerator 501 is an example of a first accelerator.

[0121] The control unit 120 may also analyze the number of accesses to each of the accelerators by each of the program blocks. In this analysis, the control unit 120 may obtain the number of accesses based on the number of calls to functions corresponding to each of the accelerators included in the program blocks. This allows the management server 100 to efficiently obtain the number of accesses to each of the accelerators by each of the program blocks.

[0122] The functions corresponding to each of the multiple accelerators may be functions according to the device in which the accelerator is installed or the type of device. The network device 300, the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700 are examples of devices in which accelerators are installed. That is, each of the multiple accelerators may be installed in any of the network device 300, the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700.

[0123] Furthermore, in selecting the first program block, the control unit 120 may select a program block that has accessed at least one of the multiple accelerators one or more times as the first program block. This allows the management server 100 to appropriately identify a program block to be assigned to one of the accelerators.

[0124] Furthermore, the control unit 120 may select multiple first program blocks when selecting a first program block. The control unit 120 may select an accelerator for each first program block when selecting an accelerator for placement. This allows the management server 100 to assign processing to an appropriate accelerator.

[0125] Furthermore, the control unit 120 may divide the source program into a plurality of program blocks using each of a plurality of division units. In a system having a plurality of accelerators, the control unit 120 may acquire, for each division unit, an index value indicating system performance when at least some of the processing of the plurality of program blocks is executed by at least some of the plurality of accelerators. The control unit 120 may select one of the plurality of division units based on the index value for each division unit.

[0126] More specifically, the control unit 120 may acquire the index value indicating the performance of the system for each of a plurality of division units indicating the granularity of division of the plurality of program blocks based on the result of analyzing the execution order of the plurality of program blocks and the hardware logic. Then, the control unit 120 may select one of the plurality of division units based on the index value acquired for each division unit.

[0127] This allows the management server 100 to execute programs while further improving the performance of the entire system. The information processing system 20 and the information processing system of the second embodiment are examples of such systems. The results of analyzing the execution order of multiple program blocks may include information such as the chronological relationship between the program blocks at execution time and the possibility of parallel execution of two or more program blocks.

[0128] Furthermore, when acquiring an index value indicating system performance, the control unit 120 may acquire the calculation time and power consumption required to execute operations corresponding to the source program. This allows the management server 100 to allocate processing to an appropriate accelerator while increasing the execution speed of operations and reducing power consumption throughout the system.

[0129] Furthermore, the control unit 120 may generate an executable file that causes a system having multiple accelerators to execute operations corresponding to the source program, based on the hardware logic obtained by converting the program blocks. This allows the management server 100 to cause the system to execute the executable file, thereby allowing the system to efficiently execute operations using the accelerators.

[0130] The information processing of the first embodiment can be realized by causing the processing unit 12 to execute a program. The information processing of the second embodiment can be realized by causing the CPU 101 to execute a program. The program can be recorded on a computer-readable recording medium 113.

[0131] For example, the program can be distributed by distributing recording medium 113 on which the program is recorded. Alternatively, the program may be stored in another computer and distributed via a network. For example, a computer may store (install) a program recorded on recording medium 113 or a program received from another computer in a storage device such as RAM 102 or HDD 103, and read and execute the program from the storage device. [Explanation of symbols]

[0132] 10. Information processing equipment 11 Storage section 12 Processing section 20 Information Processing Systems 21 nodes 22,23,24 Accelerator 30 Source Program 31,32 Program Block 40 tables 51,52 Logic

Claims

1. On the computer, Divide the source program into multiple program blocks, selecting a first program block from the plurality of program blocks and an accelerator from the plurality of accelerators in which the first program block is to be placed based on an analysis result of the number of times each of the plurality of program blocks accesses each of the plurality of accelerators; converting the first program block into hardware logic that operates in the accelerator where the first program block is to be placed; A conversion program that performs the processing.

2. In selecting the accelerator to be placed, an accelerator having the largest number of accesses by the first program block is selected from among the plurality of accelerators as the accelerator to be placed.

2. The conversion program according to claim 1, which causes the computer to execute a process.

3. the plurality of accelerators includes a first accelerator provided in a memory device; In selecting the accelerator to be placed, if the first accelerator is included in two or more accelerators having the same number of accesses by the first program block, the first accelerator is preferentially selected as the accelerator to be placed.

2. The conversion program according to claim 1, which causes the computer to execute a process.

4. In the analysis, the number of accesses is acquired based on the number of calls of functions included in the plurality of program blocks and corresponding to each of the plurality of accelerators.

2. The conversion program according to claim 1, which causes the computer to execute a process.

5. In selecting the first program block, a program block having an access count of one or more to at least one accelerator among the plurality of accelerators is selected as the first program block.

2. The conversion program according to claim 1, which causes the computer to execute a process.

6. The selection of the first program blocks includes selecting a plurality of the first program blocks; In the selection of the accelerator to be placed, the accelerator to be placed is selected for each of the first program blocks.

2. The conversion program according to claim 1, which causes the computer to execute a process.

7. acquire, for each of a plurality of division units indicating a granularity of division of the plurality of program blocks, an index value indicating the performance of the system having the plurality of accelerators when at least a portion of the processing of at least a portion of the plurality of program blocks is executed by at least a portion of the plurality of accelerators, based on a result of analyzing the execution order of the plurality of program blocks and the hardware logic; selecting one of the plurality of division units based on the index value acquired for each division unit; 2. The conversion program according to claim 1, which causes the computer to execute a process.

8. The acquisition of the index value involves acquiring a calculation time and power consumption required to execute an operation corresponding to the source program.

8. The conversion program according to claim 7, which causes the computer to execute a process.

9. generating an executable file that causes the system having the plurality of accelerators to execute operations corresponding to the source program based on the hardware logic; 2. The conversion program according to claim 1, which causes the computer to execute a process.

10. The computer Divide the source program into multiple program blocks, selecting a first program block from the plurality of program blocks and an accelerator from the plurality of accelerators in which the first program block is to be placed based on an analysis result of the number of times each of the plurality of program blocks accesses each of the plurality of accelerators; converting the first program block into hardware logic that operates in the accelerator where the first program block is to be placed; Conversion process method.

Images