Solar cell and its manufacturing method, solar power generation module

Abstract

To provide a solar cell and a manufacturing method thereof, and a photovoltaic module.SOLUTION: A solar cell includes: a semiconductor substrate; an emitter electrode and a first passivation layer; a tunneling layer; a block layer and a first doped conductive layer positioned on a surface of the tunneling layer; a second doped conductive layer positioned on the surface the tunneling layer; a second passivation layer positioned on a surface of the second doped conductive layer; a second electrode penetrating through the second passivation layer to form contact with the second doped conductive layer; and a first electrode penetrating through the first passivation layer to form contact with the emitter electrode. The first doped conductive layer is positioned between the tunneling layer and the block layer. The first doped conductive layer and the block layer correspond to a metallization region. The second doped conductive layer covers the tunneling layer in a non-metallization region and the block layer. The block layer is used to block migration of a doped element in the second doped conductive layer to the first doped conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to the technical field of solar cells, and more particularly to solar cells and their manufacturing methods, and photovoltaic power generation modules. [Background technology]

[0002] With the continuous development of solar cell technology, recombination loss at the metal contact region has become one of the key factors limiting further improvement of solar cell conversion efficiency. To improve the conversion rate of solar cells, solar cells are generally passivated using a passivation contact to reduce recombination between the interior and surface of the solar cell. Common passivation contact cells include heterojunction (heterojunction with intrinsic thin-layer, HIT) cells and tunnel oxide passivated contact (TOPCon) cells. However, the passivation structure of conventional cells has limitations in improving passivation performance, so there is a need to improve the conversion efficiency of passivation contact cells, while making them difficult to mass-produce.

[0003] Therefore, how to improve the passivation performance of passivated contact cells has become the most urgent issue to be solved in the photovoltaic power generation industry. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, the present application provides a solar cell, a manufacturing method thereof, and a photovoltaic module that can improve the poor passivation performance of the metallized region and ensure the lateral transport ability of carriers. [Means for solving the problem]

[0005] According to a first aspect, the present application provides a solar cell, the solar cell comprising: a semiconductor substrate having a first surface and a second surface disposed opposite to each other; an emitter electrode and a first passivation layer located on a first surface of the semiconductor substrate; a tunnel layer located on a second surface of the semiconductor substrate; a first doped conductive layer and a blocking layer located on a surface of the tunnel layer; a second doped conductive layer located on a surface of the tunnel layer; a second passivation layer located on a surface of the second doped conductive layer; a second electrode penetrating the second passivation layer and making contact with the second doped conductive layer, and a first electrode penetrating the first passivation layer and making contact with the emitter electrode; the first doped conductive layer is located between the tunnel layer and the block layer, and the first doped conductive layer and the block layer correspond to a metallized region; The second doped conductive layer covers the tunnel layer and the block layer in the non-metallized region, and the doping concentration of the second doped conductive layer is greater than the doping concentration of the first doped conductive layer.

[0006] According to a second aspect, the present application provides a method for manufacturing a solar cell, the method comprising: providing a semiconductor substrate having opposed first and second surfaces; forming an emitter electrode on the textured first surface of the semiconductor substrate; forming a tunnel layer on a second surface of the semiconductor substrate; forming a first non-conductive layer on a surface of the tunneling layer, the first non-conductive layer corresponding to the metallized and non-metallized regions; forming a blocking layer on a surface of the first non-conductive layer, the blocking layer corresponding to a metallized region; forming a second non-conductive layer on a surface of the first non-conductive layer and the blocking layer, and performing a doping process on the second non-conductive layer to convert the second non-conductive layer and the first non-conductive layer located in the non-metallized area into a second doped conductive layer and to convert the first non-conductive layer located in the metallized area into a first doped conductive layer, so that the doping concentration of the second doped conductive layer is greater than the doping concentration of the first doped conductive layer; forming a second passivation layer on a surface of the second doped conductive layer and a first passivation layer on a surface of the emitter electrode; forming a second electrode on a surface of the second passivation layer and a first electrode on a surface of the first passivation layer.

[0007] According to a third aspect, an embodiment of the present application provides a photovoltaic module, the photovoltaic module including a cover plate, an encapsulant layer, and a solar cell string, the solar cell string including a plurality of solar cells according to the first aspect or solar cells manufactured by the manufacturing method according to the second aspect. [Effects of the Invention]

[0008] The technical solution of the present application has at least the following beneficial effects: The present application provides a low-concentration first doped conductive layer and a blocking layer only in the metallized region of the second surface of the battery, and a high-concentration second doped conductive layer over the entire second surface of the battery. On the other hand, the low-concentration first doped conductive layer contacts the tunnel layer, reducing the passivation effect of the doping element on the tunnel layer, and reducing the recombination current density J in the metallized region. 0,metalAt the same time, the difference in quasi-Fermi levels qVD between the low-concentration first doped conductive layer and the semiconductor substrate is small, which is advantageous for improving the theoretical open circuit voltage and the photoelectric conversion efficiency of the solar cell. Furthermore, the presence of the high-concentration second doped conductive layer in the metallized region and the non-metallized region ensures the lateral transport speed of carriers on the back surface of the cell. Furthermore, since the distance between the second doped conductive layer in the non-metallized region and the semiconductor substrate is short, the provision of the low-concentration first doped conductive layer and blocking layer prevents the band bending effect of the second doped conductive layer from being too far away, which would otherwise occur, and ensures selective carrier transport. [Brief explanation of the drawings]

[0009] In order to more clearly explain the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without any creative work. [Figure 1] 1 is a schematic diagram 1 of the configuration of a solar cell of the present invention. [Figure 2] 2 is a schematic diagram illustrating the configuration of the solar cell of the present invention. [Figure 3] 1 is a flowchart for manufacturing a solar cell according to the present invention. [Figure 4] 1 is a schematic diagram illustrating a configuration in which a first emitter electrode is formed on a semiconductor substrate according to the present application. [Figure 5] FIG. 2 is a schematic diagram of a configuration in which a tunnel layer is formed on a second surface of a semiconductor substrate according to the present application. [Figure 6] FIG. 2 is a schematic diagram of a configuration in which a first non-conductive layer is formed on the surface of a tunnel layer according to the present application. [Figure 7] FIG. 2 is a schematic diagram illustrating a configuration in which a blocking layer is formed on the surface of a first non-conductive layer according to the present application. [Figure 8]FIG. 2 is a schematic diagram of a configuration according to the present application in which a second non-conductive layer is formed on the surface of a first non-conductive layer and a block layer located in a non-metallized region. [Figure 9] 9 is a schematic diagram of the structure formed in FIG. 8 after doping according to the present application. [Figure 10] 1 is a schematic diagram of a semiconductor substrate according to the present application after a first passivation layer and a second passivation layer are formed thereon. FIG. [Figure 11] 1 is a schematic diagram illustrating the configuration of a photovoltaic power generation module according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to better understand the technical solution of the present application, the following detailed description of the embodiments of the present application is given with reference to the accompanying drawings.

[0011] It should be understood that the described embodiments are only some of the embodiments of the present application, and do not include all of the embodiments. Based on the embodiments of the present application, other embodiments that a person skilled in the art can obtain without creative work shall all fall within the scope of protection of the present application.

[0012] The terms used in the examples of this application are merely for the purpose of describing particular examples and are not intended to limit the present application. As used in the examples of this application and the appended claims, the singular forms "a kind," "one," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0013] It should be understood that the term "and / or" used in this specification is merely a relational relationship that describes related objects and indicates that three relationships may exist, for example, A and / or B can indicate three situations: A exists alone, A and B exist simultaneously, and B exists alone. Also, the character " / " in the text generally indicates that the related objects before and after it are in an "or" relationship.

[0014] Optimizing the surface passivation of crystalline silicon solar cells is one of the key ways to improve their efficiency. In recent years, with the development of theoretical technology and people's pursuit of better passivation effects, the tunnel oxide passivated contact (TOPCon) structure has attracted attention due to its higher theoretical efficiency. The TOPCon structure consists of an ultra-thin silicon oxide and a highly doped silicon thin film, and has excellent passivation effect, forming an electric field passivation effect. Crystalline silicon cells manufactured using TOPCon technology have an efficiency of over 26%.

[0015] Conventional TOPCon cells often use polycrystalline silicon (ploy-Si) as the doped layer. This involves first depositing a layer of amorphous silicon (a-Si:H) by chemical vapor deposition (CVD) and then converting the a-Si:H to ploy-Si through annealing, significantly improving crystallinity and further doping and activating the ploy-Si, thereby improving the cell's conductivity. Researchers have found that the difference in quasi-Fermi levels (qVD) between the silicon substrate and the collection layer determines the upper limit of the cell's open-circuit voltage (Voc). The higher the qVD, the higher the upper limit of the cell's open-circuit voltage (Voc). While the doping concentration of the conventional doped polycrystalline silicon layer must be high enough to form good contact with the metal electrode, a highly doped polycrystalline silicon layer also has two problems: phosphorus diffusion into the oxide layer can affect the passivation effect of the tunnel layer; and the low qVD between the doped polycrystalline silicon and the silicon substrate limits the upper limit of the theoretical open-circuit voltage, limiting the improvement of the cell's conversion efficiency.

[0016] In view of this, an embodiment of the present application provides a solar cell. FIG. 1 is a schematic diagram of the solar cell according to the embodiment of the present application, and the solar cell comprises: a semiconductor substrate 1 having a first surface and a second surface disposed opposite to each other; an emitter electrode 2 and a first passivation layer 3 located on a first surface of a semiconductor substrate 1; a tunnel layer 4 located on the second surface of the semiconductor substrate 1; a first doped conductive layer 5 and a blocking layer 6 located on the surface of the tunnel layer 4; a second doped conductive layer 7 located on the surface of the tunnel layer 4; a second passivation layer 8 located on the surface of the second doped conductive layer 7; a first electrode 9 in contact with the emitter electrode 2 and a second electrode 10 in contact with the second doped conductive layer 7; the first doped conductive layer 5 is located between the tunnel layer 4 and the block layer 6, and the first doped conductive layer 5 and the block layer 6 correspond to a metallized region; The second doped conductive layer 7 covers the tunnel layer 4 and the block layer 6 in the non-metallized region, and the doping concentration of the second doped conductive layer 7 is greater than the doping concentration of the first doped conductive layer 5.

[0017] In the above technical solution, the present application provides a low-concentration first doped conductive layer 5 and a blocking layer 6 only in the metallized region of the second surface of the battery, and a high-concentration second doped conductive layer 7 on the entire second surface of the battery. On the one hand, the low-concentration first doped conductive layer 5 contacts the tunnel layer 4, reducing the passivation effect of the doping element on the tunnel layer 4, and reducing the recombination current density J in the metallized region. 0,metalAt the same time, the difference qVD of the quasi-Fermi levels between the low-concentration first doped conductive layer 5 and the semiconductor substrate 1 is small, which is advantageous for improving the theoretical open-circuit voltage and the photoelectric conversion efficiency of the solar cell. Furthermore, the presence of the high-concentration second doped conductive layer 7 in both the metallized and non-metallized regions ensures the lateral transport speed of carriers on the back surface of the cell. Furthermore, since the distance between the second doped conductive layer 7 in the non-metallized region and the semiconductor substrate 1 is short, the provision of the low-concentration first doped conductive layer 5 and the blocking layer 6 prevents the band bending effect of the second doped conductive layer 7 from being too great, which would otherwise occur when the distance between the second doped conductive layer 7 and the semiconductor substrate 1 is too great, and ensures selective transport of carriers. Compared to improving the passivation effect by sequentially providing a lightly doped conductive layer on the entire surface, a blocking layer 6 on the entire surface, and a highly doped conductive layer on the entire surface of the tunnel layer 4 on the back side of the solar cell, the design of the localized doped conductive layer of the present application can not only improve the passivation effect of the metallization region, but also ensure the lateral transport efficiency of carriers, thereby effectively improving the cell efficiency.

[0018] In some embodiments, the first surface of the semiconductor substrate 1 may be the front surface of the solar cell or the back surface of the solar cell; when the first surface of the semiconductor substrate 1 is the front surface of the solar cell, the second surface of the semiconductor substrate 1 is the back surface of the solar cell; conversely, when the first surface of the semiconductor substrate 1 is the back surface of the solar cell, the second surface of the semiconductor substrate 1 is the front surface of the solar cell; as will be understood, the front surface of the solar cell is the surface facing the sun (i.e., the light-receiving surface), and the back surface of the solar cell is the surface facing away from the sun (i.e., the non-light-receiving surface). In the following, in both cases, an example will be described in which the first surface of the semiconductor substrate 1 is the front surface of the solar cell and the second surface of the semiconductor substrate 1 is the back surface of the solar cell.

[0019] For those skilled in the art, the metallized region refers to the region where the second electrode 10 of the solar cell penetrates the second passivation layer 8 to form contact (direct or indirect contact) with the doped conductive layer, and in some cases, conductive metal particles during the electrode formation process may become liberated into the main electrode structure and form an indirect contact, while the non-metallized region refers to other regions other than the region where the second electrode 10 penetrates the second passivation layer 8 to form contact with the doped conductive layer or regions other than the metallized region.

[0020] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the embodiments of the present application are not limited to the specific type of the semiconductor substrate 1. The doping element of the semiconductor substrate 1 may be phosphorus, nitrogen, etc.

[0021] In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and specifically may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, or 240 μm, etc., but is not limited thereto.

[0022] In some embodiments, the emitter electrode 2 may be an emitter electrode structure having a uniform doping depth, or may be a selective emitter electrode structure having different doping concentrations and doping depths. Specifically, the selective emitter electrode 2 is a highly doped emitter electrode region corresponding to a metal electrode, and other regions are lightly doped emitter electrode regions. The emitter electrode 2 region may be located within the surface of the semiconductor substrate 1, or may be located outside the surface of the semiconductor substrate 1 to form an independent emitter electrode 2 structure. When the semiconductor substrate 1 is N-type, the emitter electrode 2 is P-type, and the semiconductor substrate 1 and the emitter electrode 2 form a PN junction.

[0023] In some embodiments, the material of first passivation layer 3 may include, but is not limited to, a single oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc., and first passivation layer 3 can provide good passivation effect to semiconductor substrate 1, contributing to improving the cell's conversion efficiency. Note that first passivation layer 3 can also serve to reduce reflection of incident light, and in some embodiments may be referred to as an anti-reflection layer.

[0024] In some embodiments, the thickness of the first passivation layer 3 ranges from 10 nm to 120 nm, and may be, specifically, 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or 120 nm, etc., and of course, may be other values ​​within the above range and is not limited thereto.

[0025] In some embodiments, the tunnel layer 4 is a thin oxide layer, such as silicon oxide or a metal oxide, and may contain other additional elements, such as nitrogen. Exemplarily, the tunnel layer 4 may be a stacked structure of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other examples, the tunnel layer 4 may be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, or the like. The tunnel layer 4 may not effectively provide a perfect tunnel barrier, and may contain defects such as pinholes, which may cause other charge carrier transport mechanisms (e.g., drift, diffusion) to dominate the tunneling effect.

[0026] In some embodiments, the thickness of the tunnel layer 4 is 0.5 nm to 2 nm, and may be, for example, 0.5 nm, 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, or 2 nm, and the thin tunnel layer 4 of the present application is advantageous in blocking the transport of majority carriers and promoting the tunneling collection of minority carriers.

[0027] In some embodiments, the material of the first doped conductive layer 5 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the embodiments of the present application are not limited to the specific type of the first doped conductive layer 5. Preferably, the material of the first doped conductive layer 5 includes polycrystalline silicon, i.e., the first doped conductive layer 5 is a first doped polycrystalline silicon layer, and the second doped conductive layer 7 is a second doped polycrystalline silicon layer.

[0028] In some embodiments, the doping elements in the first doped conductive layer 5 include at least one of boron, phosphorus, gallium, and arsenic.

[0029] In some embodiments, the doping concentration of the first doped conductive layer 5 is 1E18 cm -3 ~1.5E21cm -3 Specifically, 1E18cm -3 , 3E18cm -3 , 8E18cm -3 , 1E19cm -3 , 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 1.5E21cm -3 etc. may also be used.

[0030] Specifically, when the doping element in the first doped conductive layer 5 is phosphorus and the material is polycrystalline silicon, the first doped conductive layer 5 is a phosphorus-doped polycrystalline silicon layer, and the concentration of the phosphorus element in the phosphorus-doped polycrystalline silicon layer is 1E19 cm -3 ~1.5E21cm -3 Specifically, 1E19cm -3 , 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 1.5E21cm -3Controlling the phosphorus concentration in the phosphorus-doped polycrystalline silicon layer within the above range is advantageous for obtaining excellent passivation and metal contact performance, and as will be understood, the phosphorus concentration in the phosphorus-doped polycrystalline silicon layer refers to the concentration of the doping element phosphorus occupying only silicon lattice sites in the phosphorus-doped polycrystalline silicon layer.

[0031] When the doping element in the first doped conductive layer 5 is arsenic and the material is polycrystalline silicon, the first doped conductive layer 5 is an arsenic-doped polycrystalline silicon layer, and the concentration of the arsenic element in the arsenic-doped polycrystalline silicon layer is 1E19 cm -3 ~1.5E21cm -3 Specifically, 1E19cm -3 , 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 1.5E21cm -3 Controlling the arsenic concentration in the arsenic-doped polycrystalline silicon layer within the above range is advantageous in obtaining excellent passivation and metal contact performance.

[0032] When the doping element in the first doped conductive layer 5 is boron and the material is polycrystalline silicon, the first doped conductive layer 5 is a boron-doped polycrystalline silicon layer, and the concentration of the boron element in the boron-doped polycrystalline silicon layer is 1E18 cm -3 ~4.5E19cm -3 Specifically, 1E18cm -3 , 5E18cm -3 , 1E19cm -3 , 2E19cm -3 , 3E19cm -3 , 4E19cm -3 or 4.5E19cm -3 Controlling the boron concentration in the boron-doped polycrystalline silicon layer within the above range is advantageous in obtaining excellent passivation performance and in ensuring contact with the metal electrode.

[0033] When the doping element in the first doped conductive layer 5 is gallium and the material is polycrystalline silicon, the first doped conductive layer 5 is a gallium-doped polycrystalline silicon layer, and the concentration of the gallium element in the gallium-doped polycrystalline silicon layer is 1E18 cm -3 ~4.5E19cm -3 Specifically, 1E18cm -3 , 5E18cm -3 , 1E19cm -3 , 2E19cm -3 , 3E19cm -3 , 4E19cm -3 or 4.5E19cm -3 Controlling the gallium concentration in the gallium-doped polycrystalline silicon layer within the above range is advantageous in obtaining excellent passivation performance and in ensuring contact with the metal electrode.

[0034] In some embodiments, the thickness of the first doped conductive layer 5 is 20 nm to 150 nm, and specifically may be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, etc.

[0035] In some embodiments, the blocking layer 6 of the present application is a film layer structure for blocking the transition of doping elements in the second doped conductive layer 7 to the first doped conductive layer 5 located in the metallized region, thereby reducing the diffusion of the doping elements into the tunnel layer 4 in the metallized region, improving the doping concentration of the doping elements in the second doped conductive layer 7, and further improving the field passivation capability. The material of the blocking layer 6 is silicon oxide (e.g., SiO x silicon carbide (for example, SiC), silicon nitride (for example, SiN xThe diffusion rate of dopant ions in the above materials is much lower than that in polycrystalline silicon. Specifically, the polycrystalline silicon has many grain boundaries and the tetrahedral lattice structure of the polycrystalline silicon body Si-Si is more suitable for the diffusion of impurity atoms in the block layer. For example, in the block layer, SiC has a slow diffusion rate of impurity elements due to its amorphous nature, and SiO x Since the diffusion of impurity elements is slow due to the lattice characteristics of the blocking layer, the impurity elements stay in the blocking layer for a long time and diffuse slowly, thereby achieving a blocking effect.

[0036] In this embodiment, the blocking ability of the blocking layer 6 is defined as the longest distance that the thermally diffused doped ions can travel in the direction from the first doped conductive layer toward the tunnel layer. The shorter the longest distance that the doped ions can travel, the stronger the blocking ability of the blocking layer 6. Conversely, the longer the longest distance that the doped ions can travel, the weaker the blocking ability of the blocking layer 6.

[0037] In some embodiments, the ratio of the width of the first doped conductive layer 5 to the width of the blocking layer 6 in the direction parallel to the tunnel layer 4, i.e., along the X-axis direction in FIG. 1, is 1:(1 to 2), and specifically may be 1:1, 1:1.2, 1:1.5, 1:1.7, or 1:2, etc., and preferably the ratio of the width of the first doped conductive layer 5 to the width of the blocking layer 6 is 1:1.2. FIG. 2 is a schematic diagram of the configuration of a solar cell according to an example of the present application, in which the ratio of the width of the first doped conductive layer 5 to the width of the blocking layer 6 is 1:1.2. It can be seen that in some embodiments, the orthogonal projection of the blocking layer 6 on the tunnel layer 4 overlaps with the orthogonal projection of the first doped conductive layer 5 on the tunnel layer 4, and in other embodiments, the orthogonal projection of the blocking layer 6 on the tunnel layer 4 partially overlaps with the orthogonal projection of the first doped conductive layer 5 on the tunnel layer 4. Within the above ratio constraints, the doping concentration in the first doped conductive layer 5 can be ensured to be within a low range, which can reduce the passivation effect of the doping elements on the tunnel layer 4, which is beneficial to improving the theoretical open circuit voltage and further improving the conversion efficiency of the solar cell.

[0038] In some embodiments, the thickness of the blocking layer 6 is 0.5 nm to 4 nm, and may be, for example, 0.5 nm, 1 nm, 2 nm, 3 nm, or 4 nm. The thickness direction of the blocking layer 6 is the direction from the first doped conductive layer 5 toward the tunnel layer 4. By controlling the thickness of the blocking layer 6 within the above range, it is possible to block the doping element along the direction perpendicular to the surface on which the tunnel layer 4 is located from entering the first doped conductive layer 5 so that the doping concentration in the first doped conductive layer 5 is low. If the thickness of the blocking layer 6 is less than 0.5 nm, the blocking ability of the blocking layer 6 is poor, making it impossible to obtain a first doped conductive layer 5 with a low doping concentration. If the thickness of the blocking layer 6 is greater than 4 nm, the blocking layer 6 significantly blocks carrier transport in the Z-axis direction, making it impossible to ensure efficient carrier transport.

[0039] In some embodiments, the second doped conductive layer 7 covers the tunnel layer 4 and the block layer 6 in the non-metallized region, and the material of the second doped conductive layer 7 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the embodiments of the present application are not limited to the specific type of the second doped conductive layer 7. Preferably, the material of the second doped conductive layer 7 includes polycrystalline silicon.

[0040] In some embodiments, the doping elements in the second doped conductive layer 7 include at least one of boron, phosphorus, gallium, and arsenic.

[0041] In some embodiments, the doping concentration of the second doped conductive layer 7 is 5E18 cm -3 ~2E21cm -3 Specifically, 5E18cm -3 , 8E18cm -3 , 1E19cm -3 , 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 2E21cm -3 etc. may also be used.

[0042] Specifically, when the doping element in the second doped conductive layer 7 is phosphorus and the material is polycrystalline silicon, the second doped conductive layer 7 becomes a phosphorus-doped polycrystalline silicon layer, and the concentration of the phosphorus element in the phosphorus-doped polycrystalline silicon layer is 5E19 cm -3 ~2E21cm -3 Specifically, 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 2E21cm -3Controlling the phosphorus concentration in the phosphorus-doped polycrystalline silicon layer within the above range can ensure lateral transport of carriers, which is advantageous for improving the fill factor, and as will be understood, the phosphorus concentration in the phosphorus-doped polycrystalline silicon layer refers to the concentration of the doping element phosphorus occupying only silicon lattice sites in the phosphorus-doped polycrystalline silicon layer.

[0043] When the doping element in the second doped conductive layer 7 is arsenic and the material is polycrystalline silicon, the second doped conductive layer 7 becomes an arsenic-doped polycrystalline silicon layer, and the concentration of the arsenic element in the arsenic-doped polycrystalline silicon layer is 5E19 cm -3 ~2E21cm -3 Specifically, 5E19cm -3 , 1E20cm -3 , 5E20cm -3 , 8E20cm -3 , 1E21cm -3 or 2E21cm -3 By controlling the arsenic concentration in the arsenic-doped polycrystalline silicon layer within the above range, lateral transport of carriers can be ensured, which is advantageous for improving the fill factor.

[0044] When the doping element in the second doped conductive layer 7 is boron and the material is polycrystalline silicon, the second doped conductive layer 7 becomes a boron-doped polycrystalline silicon layer, and the concentration of the boron element in the boron-doped polycrystalline silicon layer is 5E18 cm -3 ~5E19cm -3 Specifically, 5E18cm -3 , 1E19cm -3 , 2E19cm -3 , 3E19cm -3 , 4E19cm -3 or 5E19cm -3 Controlling the boron concentration in the boron-doped polycrystalline silicon layer within the above range is advantageous in obtaining excellent passivation performance and in ensuring contact with the metal electrode.

[0045] When the doping element in the second doped conductive layer 7 is gallium and the material is polycrystalline silicon, the second doped conductive layer 7 becomes a gallium-doped polycrystalline silicon layer, and the concentration of the gallium element in the gallium-doped polycrystalline silicon layer is 5E18 cm -3 ~5E19cm -3 Specifically, 5E18cm -3 , 1E19cm -3 , 2E19cm -3 , 3E19cm -3 , 4E19cm -3 or 5E19cm -3 Controlling the gallium concentration in the gallium-doped polycrystalline silicon layer within the above range is advantageous in obtaining excellent passivation performance and in ensuring contact with the metal electrode.

[0046] In some embodiments, the thickness of the second doped conductive layer 7 is between 20 nm and 200 nm, and may be, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm. As will be appreciated, the thickness of the first doped conductive layer 5 is smaller than the thickness of the second doped conductive layer 7 because the first doped conductive layer 5 corresponds only to the localized metallized areas, and the second doped conductive layer 7 covers the first doped conductive layer 5 and corresponds to the entire back surface of the battery (i.e., corresponds to both the metallized and non-metallized areas).

[0047] In some embodiments, when the surface area of ​​the tunnel layer 4 in contact with the first doped conductive layer 5 is S1 and the sum of the surface area of ​​the tunnel layer 4 in contact with the first doped conductive layer 5 and the surface area of ​​the tunnel layer 4 in contact with the second doped conductive layer 7 is S2, S1:S2=1:(5 to 50), specifically, it may be 1:5, 1:10, 1:20, 1:30, 1:40, 1:45, or 1:50, etc. Within the above range, passivation performance in the metallized region of the doped conductive layer can be ensured, and lateral transport of carriers in other regions of the doped conductive layer can be ensured, which is advantageous for improving the photoelectric conversion efficiency of the battery. If the S1:S2 ratio is greater than 1:5, the ratio of the first doped conductive layer 5 is too high, which significantly impedes the lateral transport of carriers in the polycrystalline silicon layer, impacting the fill factor of the cell and reducing the photoelectric conversion efficiency. If the S1:S2 ratio is less than 1:50, the ratio of the second doped conductive layer 7 is too high, which increases the carrier recombination rate in the metal region, significantly reducing the passivation effect, impacting the open circuit voltage of the cell and reducing the photoelectric conversion efficiency.

[0048] In some embodiments, the present invention further provides a method for manufacturing a solar cell according to the present invention, in which the doped conductive layer is formed by first forming a first non-conductive layer 11 covering the tunnel layer 4, then forming a block layer 6 in the metallized region, then forming a second non-conductive layer 12 on the surface of the tunnel layer 4 and the block layer 6 covering the non-metallized region, and finally performing a doping process to convert the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized region into a second doped conductive layer 7. , the first non-conductive layer 11 located in the metallized region is converted into the first doped conductive layer 5. Due to the presence of the blocking layer 6, as the doping process progresses, the resistance of the doping element entering the first non-conductive layer 11 and transforming into the first doped conductive layer 5 increases, and the doping concentration of the first doped conductive layer 5 gradually decreases along the direction from the first doped conductive layer 5 to the tunnel layer 4. This can minimize the diffusion of the doping element into the tunnel layer 4, which is advantageous to improving the passivation performance of the metallized region.

[0049] In some embodiments, during the doping process, the presence of the blocking layer 6 in the metallized region prevents the transport of the doping element toward the first non-conductive layer 11, and the second non-conductive layer 12 located in the metallized region has a large amount of doping element. In the non-metallized region, the blocking layer 6 does not block the doping element, allowing the doping element to diffuse uniformly throughout the non-metallized region. The first non-conductive layer 11 and the second non-conductive layer 12 located in the non-metallized region have a small amount of doping element. That is, the doping concentration of the second doped conductive layer 7 located in the non-metallized region is higher than that of the second doped conductive layer 7 located in the metallized region. This increases the concentration in the region of the second doped conductive layer 7 that contacts the second electrode 10, which is beneficial for lateral carrier transport and for forming a good contact between the second doped conductive layer 7 and the second electrode 10.

[0050] In some embodiments, the first doped conductive layer 5 is bordered on both sides by the second doped conductive layer 7 along a direction parallel to the plane layer on which the tunnel layer 4 is located, so that during the doping process, the doping elements in the second doped conductive layer 7 also diffuse into the first doped conductive layer 5 along a direction parallel to the plane layer on which the tunnel layer 4 is located, making the doping concentration of the first doped conductive layer 5 toward the second doped conductive layer 7 greater than the doping concentration of the first doped conductive layer 5 away from the second doped conductive layer 7.

[0051] The solar cell manufacturing method according to the embodiments of the present application is used to manufacture TOPCon batteries. Hereinafter, the manufacturing method of the TOPCon batteries according to the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. It should be understood that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments.

[0052] An embodiment of the present application provides a method for manufacturing a solar cell, as shown in FIG. 3, and the method for manufacturing a solar cell according to the present application includes the following steps:

[0053] In step S100, a semiconductor substrate 1 is provided, and the semiconductor substrate 1 includes a first surface and a second surface opposite to each other.

[0054] In step S200, an emitter electrode 2 is formed on a first surface of the textured semiconductor substrate 1.

[0055] In step S300, a tunnel layer 4 is formed on the second surface of the semiconductor substrate 1.

[0056] In step S400, a first non-conductive layer 11 is formed on the surface of the tunnel layer 4, and the first non-conductive layer 11 corresponds to the metallized area and the non-metallized area.

[0057] In step S500, a blocking layer 6 is formed on the surface of the first non-conductive layer 11, and the blocking layer 6 corresponds to the metallized region.

[0058] In step S600, a second non-conductive layer 12 is formed on the surface of the first non-conductive layer 11 and the block layer 6, and the second non-conductive layer 12 is doped, thereby converting the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized area into a second doped conductive layer 7, and converting the first non-conductive layer 11 located in the metallized area into a first doped conductive layer 5, and the doping concentration of the second doped conductive layer 7 is greater than the doping concentration of the first doped conductive layer 5.

[0059] In step S700, a second passivation layer 8 is formed on the surface of the second doped conductive layer 7, and a first passivation layer 3 is formed on the surface of the emitter electrode 2.

[0060] In step S800, the second electrode 10 is formed on the surface of the second passivation layer 8, and the first electrode 9 is formed on the surface of the first passivation layer 3.

[0061] In the above technical solution, the present application forms a first non-conductive layer 11, a blocking layer 6, and a second non-conductive layer 12 in this order on the second surface of the semiconductor substrate 1, and then performs a doping process. Due to the presence of the blocking layer 6, less doping elements enter the first non-conductive layer 11 between the blocking layer 6 and the tunnel layer 4 during the doping process, thereby converting the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized region into a second doped conductive layer 7, and the first non-conductive layer 11 located in the metallized region into a first doped conductive layer 5, with the doping concentration of the second doped conductive layer 7 being greater than that of the first doped conductive layer 5. On the one hand, the lightly doped first conductive layer 5 is in contact with the tunnel layer 4, thereby reducing the passivation effect of the doping element on the tunnel layer 4. Furthermore, the difference in quasi-Fermi levels qVD between the lightly doped first conductive layer 5 and the semiconductor substrate 1 is small, which is advantageous for improving the theoretical open-circuit voltage and the photoelectric conversion efficiency of the solar cell. Furthermore, the heavily doped second conductive layer 7 is present in both the metallized and non-metallized regions, which ensures the lateral transport speed of carriers at the back surface of the cell. Furthermore, since the second doped conductive layer 7 located in the non-metallized region is close to the semiconductor substrate 1, the provision of the lightly doped first conductive layer 5 and the blocking layer 6 can avoid excessive reduction in the band bending effect of the second doped conductive layer 7 due to an excessive distance between the second doped conductive layer 7 and the semiconductor substrate 1, thereby ensuring selective carrier transport.

[0062] In some embodiments, the method for manufacturing a solar cell of the present application will be clearly and completely described using the example where the first surface of the semiconductor substrate 1 is the front surface of the solar cell and the second surface of the semiconductor substrate 1 is the back surface of the solar cell.

[0063] In step S100, a semiconductor substrate 1 is provided, and the semiconductor substrate 1 includes a first surface and a second surface opposite to each other.

[0064] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the embodiments of the present application are not limited to the specific type of the semiconductor substrate 1. The doping element of the semiconductor substrate 1 may be phosphorus, nitrogen, etc.

[0065] In some embodiments, the thickness of the semiconductor substrate 1 is 110 μm to 250 μm. Specifically, the thickness of the semiconductor substrate 1 may be 110 μm, 120 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, 210 μm, 220 μm, 230 μm, 240 μm, or 250 μm, etc., and examples of the present application are not limited with respect to the thickness of the semiconductor substrate 1.

[0066] In step S200, an emitter electrode 2 is formed on a first surface of the textured semiconductor substrate 1, as shown in FIG.

[0067] In some embodiments, a texturing process may be performed on the front surface of the semiconductor substrate 1 to form a texture or a surface texture structure (e.g., a pyramidal structure). The texturing process may be performed by chemical etching, laser etching, mechanical etching, plasma etching, etc., but is not limited thereto. For example, the front surface of the semiconductor substrate 1 may be textured using an NaOH solution, and a pyramidal texture structure may be produced due to the anisotropy of the corrosion of the NaOH solution.

[0068] As can be seen, the texturing process provides a textured structure on the surface of the semiconductor substrate 1, which creates a light trapping effect, increases the number of light rays absorbed by the solar cell, and improves the conversion efficiency of the solar cell.

[0069] In some embodiments, the method may further comprise cleaning the semiconductor substrate 1 to remove surface metal and organic contaminants prior to the texturing process.

[0070] In some embodiments, the emitter electrode 2 can be formed on the front surface of the semiconductor substrate 1 by one or more of high-temperature diffusion, paste doping, or ion implantation. Specifically, the emitter electrode 2 is formed by diffusing boron atoms using a boron source. The boron source, for example, boron tribromide, can be used for the diffusion process to convert the microcrystalline silicon phase of crystalline silicon into a polycrystalline silicon phase. Due to the relatively high concentration of boron on the surface of the semiconductor substrate 1, a borosilicate glass layer (BSG) is typically formed. This borosilicate glass layer has a metal gettering effect and must be removed later because it affects the normal operation of the solar cell.

[0071] In some embodiments, the emitter electrode 2 may be an emitter electrode 2 structure with a uniform doping depth, or may be a selective emitter electrode 2 structure with different doping concentrations and doping depths.

[0072] In step S300, a tunnel layer 4 is formed on the second surface of the semiconductor substrate 1, as shown in FIG.

[0073] In some embodiments, the examples of the present application are not limited to a specific operation method for forming the tunnel layer 4. For example, the rear surface of the semiconductor substrate 1 can be oxidized and tunneled using any one of an ozone oxidation method, a high-temperature thermal oxidation method, and a nitric acid oxidation method. The tunnel layer 4 may be one or more of a silicon oxide layer, an aluminum oxide layer, and a silicon oxynitride layer.

[0074] In step S400, as shown in FIG. 6, a first non-conductive layer 11 is formed on the surface of the tunnel layer 4, and the first non-conductive layer 11 corresponds to the metallized region and the non-metallized region.

[0075] In some embodiments, the first non-conductive layer 11 is formed by low-temperature deposition, specifically, the amorphous silicon layer may be manufactured by any one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and the present application is not limited to the manufacturing method of the doped amorphous silicon layer 400. Accordingly, the apparatus used for deposition may be a CVD apparatus, a PVD apparatus, an ALD apparatus, etc.

[0076] In some embodiments, the low-temperature deposition temperature is 100°C to 300°C, and the low-temperature deposition temperature may be specifically 100°C, 110°C, 120°C, 150°C, 170°C, 200°C, 220°C, 250°C, or 300°C, etc. Limiting the low-temperature deposition temperature within the above range is advantageous for the formation of a non-conductive film layer, and can also crystallize the local non-conductive material, thereby improving the photoelectric performance of the cell.

[0077] In some embodiments, the thickness of the first non-conductive layer 11 is 20 nm to 150 nm, and specifically may be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, etc.

[0078] In step S500, as shown in FIG. 7, a blocking layer 6 is formed on the surface of the first non-conductive layer 11, and the blocking layer 6 corresponds to the metallized region.

[0079] In some embodiments, a localized laser treatment is performed on the surface of the first non-conductive layer 11 in a gas atmosphere containing silicon oxide, silicon carbide, silicon nitride, magnesium fluoride, or the like to form a blocking layer 6 corresponding to the metallized region. Compared to conventional mask treatment methods, the localized laser treatment process of the present application is simpler, has higher productivity, and is easier to mass-produce. Of course, the localized blocking layer 6 may be formed by other methods, and the present application is not particularly limited thereto. During the process of forming the blocking layer 6, the blocking layer 6 may be located entirely within the metallized region, or a portion of the blocking layer 6 may be located within the non-metallized region to achieve a strong blocking effect.

[0080] In some embodiments, the pulse width of the laser light used in the laser processing may be 1 ps to 100 ns, and specifically may be 1 ps, 100 ps, ​​500 ps, ​​1 ns, 5 ns, 10 ns, 50 ns, or 100 ns.

[0081] In some embodiments, the wavelength of the laser light is between 250 nm and 532 nm, and specifically may be 250 nm, 280 nm, 300 nm, 350 nm, 400 nm, 480 nm, 500 nm, or 532 nm.

[0082] In some embodiments, the power of the laser treatment is 20 mJ / cm 2 ~500mJ / cm 2 Specifically, 20 mJ / cm 2 , 50mJ / cm 2 , 80mJ / cm 2 , 100mJ / cm 2 , 150 mJ / cm 2 , 200mJ / cm 2 , 300mJ / cm 2 , 400mJ / cm 2 or 500mJ / cm 2 For materials such as silicon nitride, which have good absorption in the blue-green wavelength region, it is possible to process them with a low-power laser beam, whereas for materials with a wide band gap such as silicon oxide, it is necessary to process them with a high-power laser beam.

[0083] In some embodiments, the frequency of the laser treatment is between 100 kHz and 160 kHz, and may be specifically 100 kHz, 300 kHz, 800 kHz, 1000 kHz, 1300 kHz, or 1600 kHz.

[0084] In some embodiments, the number of pulse irradiations in the laser treatment is 1 to 5.

[0085] In step S600, a second non-conductive layer 12 is formed on the surface of the first non-conductive layer 11 and the blocking layer 6, the resulting structure being shown in FIG. 8, and the second non-conductive layer 12 is doped, the resulting structure being shown in FIG. 9.

[0086] In the above step, during the doping process of the second non-conductive layer 12, the doping elements diffuse along the Z-axis direction shown in FIG. 1 . That is, in the metallized region, the doping elements are transported in the order of the second non-conductive layer 12 → the blocking layer 6 → the first non-conductive layer 11. During the transport process, the existence of the blocking layer 6 makes it difficult for the doping elements to diffuse from the second non-conductive layer 12 to the first non-conductive layer 11. However, due to the effect of the doping pressure, some of the doping elements can still diffuse into the first non-conductive layer 11. In this way, the second non-conductive layer 12 and the first non-conductive layer 11 located in the non-metallized region are transformed into the second doped conductive layer 7, and the first non-conductive layer 11 located in the metallized region is transformed into the first doped conductive layer 5, and the doping concentration of the second doped conductive layer 7 is greater than that of the first doped conductive layer 5. As will be understood, the thickness of the first doped conductive layer 5 is the thickness of the first non-conductive layer 11, and the thickness of the second doped conductive layer 7 is the thickness of the first non-conductive layer 11 plus the thickness of the second non-conductive layer 12.

[0087] In some embodiments, during the doping process, the resistance of the doping element to enter the first non-conductive layer 11 and become the first doped conductive layer 5 becomes increasingly greater as the doping process progresses, thereby causing the doping concentration of the first doped conductive layer 5 to decrease sequentially along the direction from the first doped conductive layer 5 to the tunnel layer 4.

[0088] In some embodiments, during the doping process, the presence of the metallized region blocking layer 6 prevents the transport of the doping element toward the first non-conductive layer 11, so that more doping elements are present in the second amorphous silicon located in the metallized region, and in the non-metallized region, due to the absence of blocking by the blocking layer 6, the doping elements can diffuse uniformly throughout the non-metallized region, resulting in fewer doping elements in the first non-conductive layer 11 and the second non-conductive layer 12 located in the non-metallized region, i.e., the doping concentration of the second doped conductive layer 7 located in the non-metallized region is greater than the doping concentration of the second doped conductive layer 7 located in the metallized region.

[0089] In some embodiments, the first doped conductive layer 5 is bordered on both sides by the second doped conductive layer 7 along a direction parallel to the plane layer on which the tunnel layer 4 is located, so that during the doping process, the doping elements in the second doped conductive layer 7 also diffuse into the first doped conductive layer 5 along a direction parallel to the plane layer on which the tunnel layer 4 is located, making the doping concentration of the first doped conductive layer 5 toward the second doped conductive layer 7 greater than the doping concentration of the first doped conductive layer 5 away from the second doped conductive layer 7.

[0090] In some embodiments, the doping process employs a high-temperature deposition and diffusion method, the specific manufacturing process being as follows: Nitrogen gas is introduced into the high-temperature equipment for 20 minutes, the air in the furnace tube is completely removed, the high-temperature equipment is heated to 600°C to 1100°C, an inert gas containing a doping source, such as Ar / N2, is introduced, and a high-temperature reaction is carried out for 5 to 50 minutes, and oxygen gas is further introduced, followed by an oxidation reaction at 600°C to 1100°C for 5 to 60 minutes, and after the oxidation, the high-temperature equipment is cooled to room temperature.

[0091] In some embodiments, the doping element for the doping process includes at least one of boron, gallium, phosphorus, and arsenic. The doping source for the doping process includes at least one of a boron source, a gallium source, a phosphorus source, and an arsenic source. Typically, the boron source may be, for example, at least one of BCl, BBr, BH, an organic boron source, and solid silicon containing a high concentration of elemental boron. The gallium source may be, for example, trimethylgallium, and solid silicon containing a high concentration of elemental gallium. The phosphorus source may be, for example, but not limited to, at least one of POCl, PH, an organic phosphorus source, and solid silicon containing a high concentration of elemental phosphorus. The arsenic source may be, for example, AsH, and solid silicon containing a high concentration of elemental arsenic.

[0092] In some embodiments, the conductivity type of the doped element is the same as the conductivity type of the doped element of the semiconductor substrate 1. For example, if the semiconductor substrate 1 is an N-type substrate, the doped element may be an N-type doped element, such as phosphorus or arsenic, and the formed doped layer may be a phosphorus-doped layer or an arsenic-doped silicon layer; if the semiconductor substrate 1 is a P-type substrate, the doped element may be a P-type doped element, such as boron or gallium, and the formed doped layer may be a boron-doped layer or a gallium-doped layer.

[0093] In step S700, as shown in FIG. 10, a second passivation layer 8 is formed on the surface of the second doped conductive layer 7, and a first passivation layer 3 is formed on the surface of the emitter electrode 2.

[0094] In some embodiments, the first passivation layer 3 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may be used for the first passivation layer 3, and the present application is not limited to the specific material of the first passivation layer 3. The first passivation layer 3 can provide good passivation and anti-reflection effects for the semiconductor substrate 1, thereby contributing to improving the conversion efficiency of the battery.

[0095] In some embodiments, the second passivation layer 8 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. For example, the second passivation layer 8 may be made of silicon nitride, where the silicon nitride thin film layer can act as an anti-reflection film and has good insulating properties, compactness, stability, and the ability to shield impurity ions. The silicon nitride thin film layer provides passivation to the semiconductor substrate 1, thereby significantly improving the photoelectric conversion efficiency of the solar cell.

[0096] In step S800, the second electrode 10 is formed on the surface of the second passivation layer 8, and the first electrode 9 is formed on the surface of the first passivation layer 3.

[0097] In some embodiments, a front main grid and a front sub-grid are printed on the front side of the semiconductor substrate 1 using paste and dried to form corresponding first electrodes 9, a back main grid and a back sub-grid are printed on the back side of the semiconductor substrate 1 using paste and dried to form corresponding second electrodes 10, and finally the dried battery cell is sintered to produce a solar cell.

[0098] In the embodiments of the present application, there is no limitation on the specific materials of the first electrode 9 and the second electrode 10. For example, the first electrode 9 is a silver electrode or a silver / aluminum electrode, and the second electrode 10 is a silver electrode or a silver / aluminum electrode.

[0099] In a third aspect, an embodiment of the present application provides a photovoltaic module 1000 including a cell string formed by electrically connecting the solar cells described above.

[0100] Specifically, as shown in FIG. 11, the photovoltaic module 1000 includes a first cover plate 200, a first sealing adhesive layer 300, a solar cell string, a second sealing adhesive layer 400, and a second cover plate 500.

[0101] In some embodiments, a solar cell string includes a plurality of the solar cells 100 connected via conductive tape, and the solar cells 100 may be connected in a partially stacked manner or joined together.

[0102] In some embodiments, the first cover plate 200, the second cover plate 500 may be a transparent or opaque cover plate, for example, a glass cover plate, a plastic cover plate.

[0103] Both sides of the first sealing adhesive layer 300 are in contact with and attached to the first cover plate 200 and the battery string, respectively, and both sides of the second sealing adhesive layer 400 are in contact with and attached to the second cover plate 500 and the battery string, respectively. The first sealing adhesive layer 300 and the second sealing adhesive layer 400 may be an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film, respectively.

[0104] In order to prevent the occurrence of stacking misalignment during stacking of the photovoltaic module 1000, the photovoltaic module 1000 may adopt a method of completely enclosing the sides, i.e., using sealing tape to completely cover and seal the sides of the photovoltaic module 1000.

[0105] The photovoltaic module 1000 further includes an edge sealing member fixed and sealed to a portion of the edge of the photovoltaic module 1000. The edge sealing member can be fixed and sealed to an edge near a corner of the photovoltaic module 1000. The edge sealing member can be a high-temperature resistant tape. The high-temperature resistant tape has excellent high-temperature resistance and will not decompose or fall off during the lamination process, ensuring reliable sealing of the photovoltaic module 1000. Both ends of the high-temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. Both ends of the high-temperature resistant tape can be bonded to the second cover plate 500 and the first cover plate 200, respectively, and the center of the high-temperature resistant tape can limit the position of the tape relative to the side of the photovoltaic module 1000, preventing misalignment during lamination of the photovoltaic module 1000.

[0106] The above are only preferred embodiments of the present application, and do not limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application should be included within the protection scope of the present application. [Explanation of symbols]

[0107] 1-Semiconductor substrate 2-Emitter electrode 3-First passivation layer 4-Tunnel Layer 5-First doped conductive layer 6-Block Layer 7-Second doped conductive layer 8-Second passivation layer 9-1st electrode 10-Second electrode 11-First non-conductive layer 12-Second non-conductive layer 1000-Photovoltaic Module 100-solar cell 200-1st cover plate 300-1st sealing adhesive layer 400-Second sealing adhesive layer 500-Second cover plate

Claims

1. A solar cell, a semiconductor substrate; a tunnel layer located on one surface of the semiconductor substrate; an emitter electrode and a first passivation layer located on the other surface of the semiconductor substrate; a first doped conductive layer and a blocking layer located on a surface of the tunnel layer; a second doped conductive layer located on a surface of the tunnel layer; the first doped conductive layer is located between the tunnel layer and the block layer, and the first doped conductive layer and the block layer correspond to a metallized region; the second doped conductive layer covers the tunnel layer and the blocking layer in the non-metallized region, and the blocking layer is used to block the transition of the doping element in the second doped conductive layer to the first doped conductive layer; the doping concentration of the second doped conductive layer is greater than the doping concentration of the first doped conductive layer; the doping concentration of the first doped conductive layer is between 1E18 cm −3 and 1.5E21 cm −3 , and the doping concentration of the second doped conductive layer is between 5E18 cm −3 and 2E21 cm −3 ; a material of the blocking layer containing at least one of silicon oxide, silicon carbide, silicon nitride, and magnesium fluoride, and a thickness of the blocking layer ranging from 0.5 nm to 4 nm;

2. 2. The solar cell according to claim 1, wherein the ratio of the width of the first doped conductive layer to the width of the blocking layer is 1:(1 to 2).

3. The first doped conductive layer is a phosphorus-doped polycrystalline silicon layer, and the concentration of phosphorus in the phosphorus-doped polycrystalline silicon layer is 1E19 cm －３ ~1.5E21cm －３ Alternatively, the first doped conductive layer is an arsenic-doped polycrystalline silicon layer, and the concentration of arsenic in the arsenic-doped polycrystalline silicon layer is 1E19 cm －３ ~1.5E21cm －３ 2. The solar cell according to claim 1, wherein:

4. The first doped conductive layer is a boron-doped polycrystalline silicon layer, and the concentration of boron element in the boron-doped polycrystalline silicon layer is 1E18 cm －３ ~4.5E19cm －３ Alternatively, the first doped conductive layer is a gallium-doped polycrystalline silicon layer, and the concentration of gallium element in the gallium-doped polycrystalline silicon layer is 1E18 cm －３ ~4.5E19cm －３ 2. The solar cell according to claim 1, wherein:

5. The second doped conductive layer is a phosphorus-doped polycrystalline silicon layer, and the concentration of phosphorus in the phosphorus-doped polycrystalline silicon layer is 5E19 cm －３ ~2E21cm －３ Alternatively, the second doped conductive layer is an arsenic-doped polycrystalline silicon layer, and the concentration of arsenic in the arsenic-doped polycrystalline silicon layer is 5E19 cm －３ ~2E21cm －３ 2. The solar cell according to claim 1, wherein:

6. The second doped conductive layer is a boron-doped polycrystalline silicon layer, and the concentration of boron element in the boron-doped polycrystalline silicon layer is 5E18 cm －３ ~5E19cm －３ Alternatively, the second doped conductive layer is a gallium-doped polycrystalline silicon layer, and the concentration of gallium element in the gallium-doped polycrystalline silicon layer is 5E18 cm －３ ~5E19cm －３ 2. The solar cell according to claim 1, wherein:

7. 2. The solar cell of claim 1, wherein the doping concentration of the second doped conductive layer located in the non-metallized region is greater than the doping concentration of the second doped conductive layer located in the metallized region.

8. A photovoltaic module, A photovoltaic module comprising a cover plate, an encapsulant layer, and a solar cell string, the solar cell string including the solar cell according to any one of claims 1 to 7.

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