Display panel, gate drive circuit driving method, and display device

Abstract

This application discloses a display panel, a gate drive circuit driving method, and a display device, which includes a pixel drive circuit and a gate drive circuit, and the gate drive circuit is connected to a first voltage terminal for turning off a drive transistor in the pixel drive circuit, which is connected to an output terminal of the gate drive circuit, and a second voltage terminal, thereby suppressing threshold voltage drift of the drive transistor and improving reliability of the drive transistor and fault tolerance of the display panel.

Description

[Technical Field]

[0001] The present application relates to the field of display technology, and more particularly to a display panel, a gate driving circuit driving method, and a display device. [Background technology]

[0002] The backplate fabricated using low-temperature polycrystalline oxide technology combines the advantages of low-temperature polysilicon and oxide backplate technologies, enabling the resulting display device to achieve high- and low-frequency switching, which is beneficial for achieving the goals of power saving and improving display quality. However, there are differences in electrical properties between low-temperature polysilicon and oxide. When oxide transistors are biased for a long time or operated at high temperatures, threshold voltage drift occurs. To suppress threshold voltage drift, it is necessary to adjust the gate voltage. However, adjusting the gate voltage affects the characteristics of the surrounding low-temperature polysilicon transistors, which is detrimental to the normal operation of the display device. Summary of the Invention [Problem to be solved by the invention]

[0003] According to the embodiments of the present application, a display panel, a gate driving circuit driving method, and a display device are provided that can suppress the drift of the threshold voltage of the driving transistor in the pixel driving circuit, thereby improving the reliability of the driving transistor and the fault tolerance of the display panel. [Means for solving the problem]

[0004] According to an embodiment of the present application, A display area; A hidden area, a pixel driving circuit located in the display area and a gate driving circuit located in the non-display area, The gate driving circuit is provided with a display panel connected to a first voltage terminal for turning off a driving transistor in the pixel driving circuit, which is connected to an output terminal of the gate driving circuit, and a second voltage terminal for turning off an output transistor in the gate driving circuit.

[0005] In the display panel, the gate drive circuit includes cascaded multi-stage sub-circuits; The n-th stage sub-circuit in the multi-stage sub-circuit is a scan control module for implementing forward scanning or reverse scanning based on the scan control signal; a pull-down control module connected to the scan control module for controlling an operation state of a pull-down module based on the scan control module; a pull-down module connected to the pull-down control module and the output module, accessing the first voltage end and the second voltage end, for turning off the output transistor located in the output module through the second voltage end in a reset stage, and accessing the output end of the output module through the first voltage end, thereby pulling down the output end of the output module and turning off the driving transistor in the pixel driving circuit; an output module connected to the scan control module and the pull-down module for accessing an N-th stage clock signal and outputting a gate driving signal.

[0006] In the display panel, The pull-down module includes: a pull-down transistor having a gate connected to the pull-down control module, a first pole connected to the output module, and a second pole connected to the second voltage terminal, for turning off the output transistor in the reset stage to stop writing the N-stage clock signal to the output terminal of the output module; a reset transistor, the reset transistor having a gate connected to the gate of the pull-down transistor, a first pole connected to the output terminal of the output module, and a second pole connected to the first voltage terminal, for pulling down the output terminal of the output module in the reset stage to turn off the driving transistor in the pixel driving circuit; a first storage capacitor having one end connected to the gate of the pull-down transistor and the other end accessing the second voltage terminal, for maintaining the gate voltages of the pull-down transistor and the reset transistor;

[0007] In the display panel, The pull-down control module: a first transistor having a gate connected to the scan control module, a first pole connected to a third voltage terminal, and a second pole connected to the gate of the pull-down transistor, for operating the pull-down module in the reset stage; a second transistor having a gate connected to the first electrode of the pull-down transistor, a first electrode connected to the second electrode of the first transistor, and a second electrode accessing the second voltage terminal, for holding the pull-down module in an off state during the input stage, the output stage, and the pull-down stage, thereby writing the N-stage clock signal to the output terminal of the output module.

[0008] In the display panel, the scan control signals include a forward scan control signal and a reverse scan control signal; The scan control module a third transistor, the third transistor having a gate connected to an activation signal or an (N-2)th stage gate driving signal, a first pole connected to the forward scanning control signal, and a second pole connected to the gate of the second transistor, for operating the pull-down control module and the output module in the input stage, thereby writing the Nth stage clock signal to the output end of the output module; a fourth transistor, the fourth transistor having a gate connected to an N+2 stage gate driving signal, a first pole connected to the second pole of the third transistor, and a second pole connected to the reverse scan control signal, for causing the pull-down control module to control the operation of the pull-down module during the reset stage; a fifth transistor having a gate connected to the forward scan control signal, a first pole connected to the N+2 stage clock signal, and a second pole connected to the gate of the first transistor; a sixth transistor having a gate accessing the reverse scan control signal, a first pole accessing the N-2 stage clock signal, and a second pole connected to the second pole of the fifth transistor;

[0009] In the display panel, The output module includes: a seventh transistor having a gate accessing the third voltage terminal and a first pole connected to the second pole of the third transistor; the output transistor having the gate connected to the second pole of the seventh transistor, a first pole accessing an N-stage clock signal, and a second pole connected to the first pole of the reset transistor; a second storage capacitor having one end connected to the first pole of the seventh transistor and the other end accessing the second voltage end, for keeping the output transistor on in the input stage, the output stage and the pull-down stage, thereby writing the N-stage clock signal to the output end of the output module.

[0010] In the display panel, The gate drive circuit The display device further includes a blacking module, connected to the pull-down module and the output module, for accessing a blacking control signal and blacking the display screen at the moment of shutdown.

[0011] In the display panel, The blackening module comprises: a ninth transistor having a gate connected to the blackening control signal, a first pole connected to the pull-down module, and a second pole connected to the second voltage terminal; a tenth transistor having a gate and a first pole connected to the gate of the ninth transistor, and a second pole connected to the output end of the output module;

[0012] In the display panel, a first electrode of the ninth transistor is connected to the gate of the reset transistor in the pull-down module; The second pole of the tenth transistor is connected to the second pole of the output transistor in the output module.

[0013] In the display panel, The first voltage terminal is a DC low voltage power supply; The second voltage terminal is a DC low voltage power supply.

[0014] In the display panel, The third voltage terminal is a high voltage DC power supply.

[0015] In the display panel, the forward scanning control signal is a high level signal, The reverse scan control signal is a low level signal.

[0016] In the display panel, the plurality of transistors located in the pixel driving circuit are oxide transistors; The plurality of transistors in the gate driver circuit are low temperature polysilicon transistors.

[0017] According to the present application: A gate drive circuit driving method for driving the gate drive circuit in the display panel, comprising: In the input stage, the output module and the pull-down control module in the gate driving circuit are operated by the scan control signal connected to the scan control module in the gate driving circuit, and the pull-down control module keeps the pull-down module in the gate driving circuit in an OFF state, and writes the N-th stage clock signal to the output terminal of the output module in the gate driving circuit; In an output stage, the N-stage clock signal is used to generate a bootstrap effect in the output module, and the output end of the output module outputs a gate driving signal that drives the operation of the driving transistor in the pixel driving circuit; In a pull-down stage, maintaining the operation of the output module, and causing the pull-down control module and the N-stage clock signal to write the N-stage clock signal to the output end of the output module; The method for driving a gate driving circuit further includes: in a reset stage, operating the pull-down control module according to the scanning control signal, the pull-down control module controlling the pull-down module to an active state, turning off the output transistor located in the output module by the second voltage end, allowing the output end of the output module to access the first voltage end, and turning off the driving transistor.

[0018] The present application further provides a display device including the display panel. [Effects of the Invention]

[0019] Compared with the prior art, embodiments of the present application provide a display panel, a gate drive circuit driving method, and a display device, wherein the display panel includes a display area, a non-display area, a pixel drive circuit located in the display area, and a gate drive circuit located in the non-display area, the gate drive circuit being connected to a first voltage terminal for turning off a drive transistor in the pixel drive circuit, which is connected to an output terminal of the gate drive circuit, and a second voltage terminal for turning off an output transistor in the gate drive circuit, thereby suppressing threshold voltage drift of the drive transistor in the pixel drive circuit and improving reliability of the drive transistor and fault tolerance of the display panel. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a schematic diagram illustrating a structure of a display panel according to an embodiment of the present application. [Figure 2A] 1 is a diagram illustrating the principle of a gate drive circuit according to an embodiment of the present application. [Figure 2B] 1 is a diagram illustrating the principle of a gate drive circuit according to an embodiment of the present application. [Figure 3A] FIG. 1 is a schematic diagram illustrating a structure of a gate drive circuit according to an embodiment of the present application. [Figure 3B] FIG. 1 is a schematic diagram illustrating a structure of a gate drive circuit according to an embodiment of the present application. [Figure 3C] 4 is an operation timing chart of the gate drive circuit according to the embodiment of the present application. [Figure 4] FIG. 1 is a schematic diagram illustrating a structure of a gate drive circuit according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0021] In order to clarify the purpose, technical means, and effects of the present application, the present application will be described in more detail below with reference to the drawings and examples. Note that the specific examples described in this specification are for the purpose of illustrating the present application, and are not intended to limit the present application.

[0022] Specifically, Fig. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present application. Figs. 2A and 2B are diagrams showing the principle of a gate drive circuit according to an embodiment of the present application. Figs. 3A and 3B are schematic diagrams showing the structure of a gate drive circuit according to an embodiment of the present application. Fig. 3C is an operation timing chart of the gate drive circuit according to an embodiment of the present application.

[0023] The display panel includes a display area 100a, a non-display area 100b, a pixel driving circuit located in the display area 100a, and a gate driving circuit located in the non-display area 100b.

[0024] Here, the gate driving circuit is connected to a first voltage terminal VSS for turning off the driving transistor in the pixel driving circuit, which is connected to the output terminal Gate(N) of the gate driving circuit, and a second voltage terminal VGL for turning off the output transistor T8 in the gate driving circuit, thereby suppressing threshold voltage drift of the driving transistor in the pixel driving circuit, and improving the reliability of the driving transistor and the fault tolerance of the display panel.

[0025] Specifically, referring to FIGS. 2A and 2B and 3A to 3C, the gate driving circuit includes a cascaded multi-stage sub-circuit, The n-th stage sub-circuit in the multi-stage sub-circuit is a scan control module 100 for implementing forward scanning or reverse scanning based on a scan control signal; a pull-down control module 200 connected to the scan control module 100, for controlling the operation state of the pull-down module 300 according to the scan control module 100; a pull-down module 300 connected to the pull-down control module 200 and the output module 400, accessing the first voltage end VSS and the second voltage end VGL, for turning off the output transistor T8 located in the output module 400 by the second voltage end VGL in a reset step S4, and for pulling down the output end Gate(N) of the output module 400 by accessing the output end Gate(N) of the output module 400 by the first voltage end VSS, thereby turning off the driving transistor in the pixel driving circuit; the output module 400, connected to the scan control module 100 and the pull-down module 300, for accessing the N-th stage clock signal CK(N) and outputting the gate driving signal;

[0026] In the reset step S4, the pull-down module 300 connects the output terminal Gate(N) of the output module 400 to the first voltage terminal VSS, so that the output terminal Gate(N) of the output module 400 is pulled down, thereby adjusting the gate voltage of the driving transistor in the pixel driving circuit located in the display area, avoiding the problem of threshold voltage drift caused by long-term bias in the driving transistor, and improving the reliability of the driving transistor. The threshold voltage drift of the driving transistor is suppressed, and at the same time, its influence on the gate driving circuit is avoided.

[0027] Here, the first voltage terminal VSS can be modulated by a central control panel, and the voltage value of the first voltage terminal VSS can be determined through a reliability experiment, thereby obtaining a suitable voltage value for turning off the driving transistor.

[0028] The plurality of transistors in the pixel driving circuit located within the display area are field effect transistors, and further, the plurality of transistors in the pixel driving circuit located within the display area are thin film transistors, and further, the plurality of transistors in the pixel driving circuit located within the display area are oxide thin film transistors.

[0029] According to the present application, there is provided a gate drive circuit driving method for driving the gate drive circuit in the display panel, comprising: In an input stage S1, the scan control signal connected to the scan control module 100 in the gate driving circuit is used to operate the output module 400 and the pull-down control module 200, the pull-down control module 200 keeps the pull-down module 300 in an OFF state, and the N-th stage clock signal CK(N) is written to the output terminal Gate(N) of the output module 400; In an output stage S2, the N-stage clock signal CK(N) generates a bootstrap effect in the output module 400, and the output end Gate(N) of the output module 400 outputs a gate driving signal for driving the operation of the driving transistor in the pixel driving circuit; In a pull-down step S3, the operation of the output module 400 is maintained, and the N-stage clock signal CK(N) is written to the output terminal Gate(N) of the output module 400 according to the pull-down control module 200 and the N-stage clock signal CK(N); In a reset step S4, the pull-down control module 200 is operated by the scanning control signal, the pull-down control module 200 controls the pull-down module 300 to an active state, the output transistor T8 located in the output module 400 is turned off by the second voltage end VGL, and the output end Gate(N) of the output module 400 is connected to the first voltage end to turn off the driving transistor.

[0030] Continuing to refer to FIGS. 2A and 2B and FIGS. 3A to 3C, the pull-down module 300 includes: a pull-down transistor T11, the pull-down transistor T11 having a gate connected to the pull-down control module 200, a first pole connected to the output module 400, and a second pole connected to the second voltage end VGL, for turning off the output transistor T8 in the reset step S4 to stop writing the N-stage clock signal CK(N) to the output end Gate(N) of the output module 400; a reset transistor T12, the reset transistor T12 having a gate connected to the gate of the pull-down transistor T11, a first pole connected to the output terminal Gate(N) of the output module 400, and a second pole connected to the first voltage terminal VSS, for pulling down the output terminal Gate(N) of the output module 400 in the reset stage S4 to turn off the driving transistor in the pixel driving circuit; a first storage capacitor C1 having one end connected to the gate of the pull-down transistor T11 and the other end connected to the second voltage end VGL for maintaining the gate voltages of the pull-down transistor T11 and the reset transistor T12;

[0031] The pull-down control module 200 includes: a first transistor T1, the first transistor T1 having a gate connected to the scan control module 100, a first terminal connected to a third voltage terminal VGH, and a second terminal connected to the gate of the pull-down transistor T11, for operating the pull-down module 300 in the reset stage S4; a second transistor T2 having a gate connected to a first electrode of the pull-down transistor T11, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the second voltage end VGL, for keeping the pull-down module 300 in an off state during the input stage S1, the output stage S2, and the pull-down stage S3, thereby writing the N-stage clock signal to the output end Gate(N) of the output module 400;

[0032] The scanning control signals include a forward scanning control signal U2D and a reverse scanning control signal D2U; The scan control module 100 a third transistor T3, the third transistor T3 having a gate connected to the (N-2)th stage gate driving signal Gate(N-2), a first pole connected to the forward scanning control signal U2D, and a second pole connected to the gate of the second transistor T2, for operating the pull-down control module 200 and the output module 400 in the input stage S1 to write the Nth stage clock signal to the output terminal Gate(N) of the output module 400; a fourth transistor T4, the fourth transistor T4 having a gate connected to an N+2 stage gate driving signal Gate(N+2), a first pole connected to the second pole of the third transistor T3, and a second pole connected to the reverse scan control signal D2U, for causing the pull-down control module 200 to control the operation of the pull-down module 300 in the reset stage S4; a fifth transistor T5 having a gate connected to the forward scanning control signal U2D, a first pole connected to the (N+2)th stage clock signal CK(N+2), and a second pole connected to the gate of the first transistor T1; a sixth transistor T6 having a gate accessing the reverse scan control signal D2U, a first pole accessing the N-2-th stage clock signal CK(N-2), and a second pole connected to the second pole of the fifth transistor T5;

[0033] The output module 400 includes: a seventh transistor T7 having a gate connected to the third voltage terminal VGH and a first pole connected to the second pole of the third transistor T3; the output transistor T8, having a gate connected to the second pole of the seventh transistor T7, a first pole for accessing the N-th stage clock signal CK(N), and a second pole connected to the first pole of the reset transistor T12; a second storage capacitor C2, one end of which is connected to the first pole of the seventh transistor T7 and the other end of which is connected to the second voltage end VGL, for keeping the output transistor T8 turned on in the input stage S1, the output stage S2 and the pull-down stage S3, thereby writing the N-stage clock signal CK(N) to the output end Gate(N) of the output module 400;

[0034] Here, the first voltage end VSS is a DC low power supply, the second voltage end VGL is a DC low power supply, and the third voltage end VGH is a DC high power supply.

[0035] The plurality of transistors located in the gate drive circuit are field-effect transistors, and the plurality of transistors located in the gate drive circuit are thin film transistors, and the plurality of transistors located in the gate drive circuit are low-temperature polysilicon thin film transistors. In order to distinguish between the source and drain other than the gate in a transistor, the first pole in this application may be either the drain or the source, and accordingly, the second pole may be the other of the source or the drain.

[0036] Continuing to refer to FIGS. 3A to 3C, taking as an example that each transistor in the gate driving circuit is an N-type transistor, the forward scanning control signal U2D is at a high level, the reverse scanning control signal D2U is at a low level, the first voltage end VSS is a DC low power supply, the second voltage end VGL is a DC low power supply, and the third voltage end VGH is a DC high power supply, the operating principle of the gate driving circuit includes:

[0037] In the input stage S1, when the N-2 stage gate driving signal Gate(N-2) is at a high level, the third transistor T3 in the scan control module 100 is turned on, and the second transistor T2 in the pull-down control module 200 is turned on. At the same time, the seventh transistor T7 in the output module 400 is turned on because the third voltage terminal VGH is a high DC power supply, causing the forward scan control signal U2D to be written to the first pole and charging the second storage capacitor C2, so that the forward scan control signal U2D is written to both the first pole and the second pole (i.e., point Q1 and point Q2), and the output transistor T8 is turned on, and the N stage clock signal CK(N) is written to the output terminal Gate(N) of the output module 400. The second transistor T2 in the pull-down control module 200 is turned on, so that the signal of the second voltage terminal VGL is written to the gates of the pull-down transistor T11 and the reset transistor T12 in the pull-down module 300, and the pull-down transistor T11 and the reset transistor T12 are turned off.

[0038] When the N-2 stage gate driving signal Gate(N-2) is at a low level, the third transistor T3 in the scan control module 100 is turned off, and the third voltage end VGH is a high DC power supply, so the seventh transistor T7 in the output module 400 remains turned on, the potentials of points Q1 and Q2 are maintained by the signal stored in the second storage capacitor C2, and the output transistor T8 is maintained on. At the same time, the second transistor T2 in the pull-down control module 200 is maintained on by the signal stored in the second storage capacitor C2. The N stage clock signal CK(N) continues to be written to the output end Gate(N) of the output module 400. The signal from the second voltage end VGL continues to be written to the gates of the pull-down transistor T11 and the reset transistor T12 in the pull-down module 300, so the pull-down transistor T11 and the reset transistor T12 are turned off.

[0039] During the output stage S2, the potentials of points Q1 and Q2 are maintained by the signal stored in the second storage capacitor C2, so that the output transistor T8 is maintained on. At the same time, the signal stored in the second storage capacitor C2 maintains the second transistor T2 in the pull-down control module 200 on. The signal from the second voltage terminal VGL continues to be written to the gates of the pull-down transistor T11 and the reset transistor T12 in the pull-down module 300, so that the pull-down transistor T11 and the reset transistor T12 are turned off. Since the output transistor T8 is maintained on, when the N-stage clock signal CK(N) is at a high level, a bootstrap effect occurs at the gate (i.e., point Q2), and the potential of point Q2 is pulled up to 2*VGH-VGL. The output transistor T8 is fully turned on, and the high-level signal loaded into the N-stage clock signal CK(N) is written to the output terminal Gate(N) of the output module 400, thereby providing a gate driving signal to the driving transistor of the pixel driving circuit in the display area.

[0040] In the pull-down stage S3, the Nth stage clock signal CK(N) changes from high to low, the bootstrap effect at the gate of the output transistor T8 (i.e., point Q2) disappears, the potentials at points Q1 and Q2 are maintained by the signal stored in the second storage capacitor C2, the output transistor T8 remains on, and the second transistor T2 in the pull-down control module 200 remains on. The pull-down transistor T11 and the reset transistor T12 in the pull-down module 300 remain off. The low-level signal loaded to the Nth stage clock signal CK(N) is written to the output terminal Gate(N) of the output module 400.

[0041] In the reset stage S4, when the N+2 stage gate driving signal Gate(N+2) is at a high level, the fourth transistor T4 in the scan control module 100 is turned on. At the same time, the N-2 stage clock signal CK(N-2) and the N+2 stage clock signal CK(N+2) are at a high level, and the forward scan control signal U2D is at a high level, so the fifth transistor T5 in the scan control module 100 is turned on. By turning on the fourth transistor T4, the low-level signal loaded into the reverse scan control signal D2U is written to the gate of the second transistor T2 in the pull-down control module 200, and the second transistor T2 is turned off. By turning on the fourth transistor T4, the low-level signal loaded into the reverse scan control signal D2U is written to the first pole of the seventh transistor T7 in the output module 400. When the fifth transistor T5 is turned on, the first transistor T1 in the pull-down control module 200 is turned on, and the gates of the pull-down transistor T11 and the reset transistor T12 in the pull-down module 300 access the third voltage terminal VGH, turning on the pull-down transistor T11 and the reset transistor T12. The first storage capacitor C1 charges and maintains the gate potentials of the pull-down transistor T11 and the reset transistor T12. When the seventh transistor T7 in the output module 400 has its first and second poles (i.e., Q1 and Q2 points) connected to the second voltage terminal VGL, the output transistor T8 is turned off.When the reset transistor T12 is turned on, the output terminal Gate(N) of the output module 400 is pulled down to the same potential as the first voltage terminal VSS, so that the gate voltage of the driving transistor in the pixel driving circuit in the display area is adjusted by the gate driving signal output from the output terminal Gate(N) of the output module 400, thereby avoiding the problem of threshold voltage drift caused by long-term bias in the transistors located in the display area, and improving the reliability of the driving transistor and other transistors in the pixel driving circuit.

[0042] Here, the gate of the third transistor T3 of the scan control module 100 may be connected to the activation signal STV instead of the N-2-th stage gate driving signal Gate(N-2). When the gate of the third transistor T3 is connected to the activation signal STV, the operating principle of the gate driving circuit is the same as when the gate of the third transistor T3 is connected to the N-2-th stage gate driving signal Gate(N-2), and the description thereof will be omitted here.

[0043] Continuing to refer to FIG. 2B and FIG. 3B, the gate driving circuit includes: The display device further includes a blacking module 500, which is connected to the pull-down module 300 and the output module 400, and which receives a blacking control signal GAS and blackens the display screen at the moment of shutdown.

[0044] Furthermore, the blackening module 500 a ninth transistor T9, having a gate connected to the blackening control signal GAS, a first pole connected to the pull-down module 300, and a second pole connected to the second voltage terminal VGL; a tenth transistor T10 having a gate and a first pole connected to the gate of the ninth transistor T9 and a second pole connected to the output terminal Gate(N) of the output module 400;

[0045] Furthermore, the first electrode of the ninth transistor T9 is connected to the gate of the reset transistor T12 in the pull-down module 300; The second pole of the tenth transistor T10 is connected to the second pole of the output transistor T8 in the output module 400.

[0046] At the moment of shutdown, the blackening control signal GAS becomes a high level signal, and the remaining input signals (e.g., the N-2 stage clock signal CK(N-2), the forward scanning control signal U2D, etc.) are all controlled to be low level, so that the ninth transistor T9 and the tenth transistor T10 in the blackening module 500 are turned on, and the gate driving signal output from the output terminal Gate(N) of the output module 400 causes the display panel to blacken the display screen.

[0047] 3A and 3B are described as examples in which each transistor is an N-type transistor, but those skilled in the art may replace the N-type transistors with P-type transistors and obtain analysis results by inverting the signal phase accordingly. Therefore, in the embodiments of the present application, a description of a gate drive circuit and a driving method thereof using P-type transistors will be omitted.

[0048] 4, which is a schematic diagram showing the structure of a gate driving circuit according to an embodiment of the present application. According to the present application, there is provided a gate driving circuit including cascaded multi-stage sub-circuits, wherein the n-th stage sub-circuit in the multi-stage sub-circuit comprises: a first transistor T1 having a drain D1 connected to a third voltage terminal VGH; a second transistor T2 having a drain D2 connected to the source S1 of the first transistor T1 and a source S2 connected to a second voltage end VGL; a third transistor T3, the third transistor T3 having a gate connected to the (N-2)th stage gate driving signal Gate(N-2) or the activation signal STV, a drain D3 connected to the forward scanning control signal U2D, and a source S3 connected to the gate of the second transistor T2; a fourth transistor T4 having a gate connected to the (N+2)th stage gate driving signal Gate(N+2), a drain D4 connected to the source S3 of the third transistor T3, and a source S4 connected to the reverse scan control signal D2U; a fifth transistor T5 having a gate connected to the forward scan control signal U2D, a drain D5 connected to the (N+2)-th stage clock signal CK(N+2), and a source S5 connected to the gate of the first transistor T1; a sixth transistor T6 having a gate connected to the reverse scan control signal D2U, a drain connected to the N-2-th stage clock signal CK(N-2), and a source connected to the source of the fifth transistor T5; a seventh transistor T7 having a gate connected to the third voltage terminal VGH and a drain D7 connected to the source S3 of the third transistor T3; an eighth transistor T8 having a gate connected to the source S7 of the seventh transistor T7 and a drain D8 accessing the N-th stage clock signal CK(N); a ninth transistor T9 having a gate connected to the blackening control signal GAS and a source S9 connected to the second voltage terminal VGL; a tenth transistor T10 having a gate and a drain D10 connected to the gate of the ninth transistor T9 and a source S10 connected to the source S8 of the eighth transistor T8; an eleventh transistor T11 having a gate connected to the drain D9 of the ninth transistor T9 and to the source S1 of the first transistor T1, a drain D11 connected to the drain D7 of the seventh transistor T7, and a source S11 accessing the second voltage end VGL; a twelfth transistor T12 having a gate connected to the gate of the eleventh transistor T11, a drain D12 connected to the source S8 of the eighth transistor T8, and a source S12 connected to the first voltage end VSS; a first storage capacitor C1, one end of which is connected to the gate of the eleventh transistor T11 and the other end of which is connected to the second voltage terminal VGL; and a second storage capacitor C2, one end of which is connected to the drain D7 of the seventh transistor T7 and the other end of which is connected to the second voltage terminal VGL.

[0049] In the gate driving circuit of this application, only the n-th stage sub-circuit in the multi-stage sub-circuit will be described as an example, but the multi-stage sub-circuits of the remaining stages in the gate driving circuit are similar to the n-th stage sub-circuit, and therefore will not be described here.

[0050] The present application further provides a display device including the display panel.

[0051] The display device may be a liquid crystal display device, a flexible display device, etc. Furthermore, the gate driving circuit is suitable for a high-resolution display device. Furthermore, the flexible display device includes a light-emitting element. Furthermore, the light-emitting element includes an organic light-emitting diode, a submillimeter light-emitting diode, and a micro light-emitting diode.

[0052] Specifically, the display device may be a mobile display device or a fixed display device, including display devices of mobile phones, tablets, desktop computers, handheld devices, learning machines, etc.

[0053] In the display device, by driving the driving transistor in the pixel driving circuit with the gate driving circuit, the driving transistor can be prevented from being in a bias state for a long period of time, the threshold voltage drift of the driving transistor can be improved, and the reliability of the multiple transistors located in the display area can be improved. In addition, since the first voltage terminal VSS is adjustable as needed, the bias voltage of the multiple transistors in the display area can be adjusted, thereby improving the fault tolerance of the display device.

[0054] According to the display panel, gate drive circuit driving method, and display device of the present application, the display panel includes a display area 100a, a non-display area 100b, a pixel drive circuit located in the display area 100a, and a gate drive circuit located in the non-display area 100b, and the gate drive circuit is connected to a first voltage terminal VSS for turning off a drive transistor in the pixel drive circuit connected to an output terminal Gate(N) of the gate drive circuit, and a second voltage terminal VGL for turning off an output transistor T8 in the gate drive circuit, thereby suppressing threshold voltage drift of the drive transistor and improving the reliability of the drive transistor and the fault tolerance of the display panel.

[0055] In the above embodiments, the description of each embodiment is focused on its own particular point, and for parts not described in detail in one embodiment, reference can be made to the relevant descriptions of other embodiments.

[0056] The display panel, the gate driving circuit driving method, and the display device according to the embodiments of the present application have been described in detail above. In this specification, the principles and embodiments of the present application have been described using specific examples. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Those skilled in the art may still modify the technical solutions described in the above embodiments or replace some of these technical features with equivalents, but it should be understood that such modifications or replacements do not deviate from the essence of the corresponding technical solutions and the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display area; A hidden area, a driving transistor in a pixel driving circuit in the display area and a gate driving circuit located in the non-display area; the gate drive circuit drives the drive transistor in the pixel drive circuit; the driving transistor is an oxide thin film transistor; the gate drive circuit includes a first voltage terminal connected to a gate of the drive transistor connected to an output terminal of the gate drive circuit, and a second voltage terminal connected to an output transistor in the gate drive circuit; a DC low-voltage power supply is connected to the first voltage terminal, a DC low-voltage power supply is connected to the second voltage terminal, the first voltage terminal is used to turn off a driving transistor in the pixel driving circuit, the driving transistor being connected to an output terminal of the gate driving circuit, and the second voltage terminal is used to turn off the output transistor in the gate driving circuit; the gate drive circuit includes cascaded multi-stage sub-circuits; The n-th stage sub-circuit in the multi-stage sub-circuit is a scan control module for implementing forward scanning or reverse scanning based on the scan control signal; a pull-down control module connected to the scan control module for controlling an operation state of a pull-down module based on the scan control module; a pull-down module connected to the pull-down control module and the output module, accessing the first voltage terminal and the second voltage terminal, for turning off the output transistor located in the output module through the second voltage terminal in a reset stage, and accessing the output terminal of the output module through the first voltage terminal, thereby pulling down the output terminal of the output module and turning off the driving transistor; an output module connected to the scan control module and the pull-down module, for accessing an N-stage clock signal and outputting a gate drive signal; The pull-down module includes: a pull-down transistor having a gate connected to the pull-down control module, a first pole connected to the output module, and a second pole connected to the second voltage terminal, for turning off the output transistor in the reset stage to stop writing the N-stage clock signal to the output end of the output module; a reset transistor having a gate connected to the gate of the pull-down transistor, a first pole connected to the output end of the output module, and a second pole accessing the first voltage terminal, for pulling down the output end of the output module in the reset stage to turn off the drive transistor; a first storage capacitor having one end connected to the gate of the pull-down transistor and the other end connected to the second voltage terminal, for maintaining gate voltages of the pull-down transistor and the reset transistor; The pull-down control module: a first transistor for operating the pull-down module in the reset phase, the first transistor having a gate connected to the scan control module, a first pole accessing a third voltage terminal, and a second pole connected to the gate of the pull-down transistor; a second transistor having a gate connected to the first pole of the pull-down transistor, a first pole connected to the second pole of the first transistor, and a second pole accessing the second voltage terminal, for holding the pull-down module in an off state during the input stage, the output stage, and the pull-down stage, thereby writing the N-stage clock signal to the output end of the output module; the scan control signals include a forward scan control signal and a reverse scan control signal; The scan control module a third transistor, the third transistor having a gate connected to an activation signal or an (N-2)th stage gate driving signal, a first pole connected to the forward scanning control signal, and a second pole connected to the gate of the second transistor, for operating the pull-down control module and the output module in the input stage, thereby writing the Nth stage clock signal to the output end of the output module; a fourth transistor, the fourth transistor having a gate connected to an (N+2)th stage gate driving signal, a first pole connected to the second pole of the third transistor, and a second pole connected to the reverse scan control signal, for causing the pull-down control module to control the operation of the pull-down module in the reset stage; a fifth transistor having a gate connected to the forward scan control signal, a first pole connected to the N+2 stage clock signal, and a second pole connected to the gate of the first transistor; a sixth transistor having a gate connected to the reverse scan control signal, a first pole connected to the N-2 stage clock signal, and a second pole connected to the second pole of the fifth transistor; The output module includes: a seventh transistor having a gate accessing the third voltage terminal and a first pole connected to the second pole of the third transistor; the output transistor has a gate connected to the second pole of the seventh transistor, a first pole for accessing an N-stage clock signal, and a second pole connected to the first pole of the reset transistor, the second pole of the output transistor being connected to the output end of the output module; a second storage capacitor, one end of which is connected to the first pole of the seventh transistor and the other end of which is connected to the second voltage terminal, for maintaining the output transistor turned on in the input stage, the output stage and the pull-down stage, thereby writing the N-stage clock signal to the output end of the output module; a high DC power supply is connected to the third voltage terminal; Display panel.

2. The gate drive circuit a blacking module coupled to the pull-down module and the output module and accessing a blacking control signal; The blackening module comprises: a ninth transistor having a gate connected to the blackening control signal, a first pole connected to the pull-down module, and a second pole connected to the second voltage terminal; a tenth transistor having a gate and a first pole connected to the gate of the ninth transistor and a second pole connected to the output end of the output module; a first electrode of the ninth transistor is connected to the gate of the reset transistor in the pull-down module; a second pole of the tenth transistor is connected to a second pole of an output transistor in the output module; At the moment of shutdown, the ninth transistor and the tenth transistor are turned on, and the gate driving signal output from the output terminal of the output module causes the display panel to blacken the display screen. The display panel according to claim 1 .

3. the forward scanning control signal is a high level signal, the reverse scanning control signal is a low level signal; The display panel according to claim 1 .

4. The plurality of transistors located in the gate driving circuit are low-temperature polysilicon transistors; The display panel according to claim 1 .

5. 2. A gate drive circuit driving method for driving the gate drive circuit in the display panel according to claim 1, comprising: In an input stage, the output module and the pull-down control module in the gate driving circuit are operated by a scanning control signal connected to the scanning control module in the gate driving circuit, and the pull-down control module keeps the pull-down module in the gate driving circuit in an OFF state, and writes an N-stage clock signal to the output terminal of the output module in the gate driving circuit; In an output stage, the N-stage clock signal generates a bootstrap effect in the output module, and the output end of the output module outputs a gate driving signal for driving the operation of the driving transistor; In a pull-down stage, maintaining the operation of the output module, and causing the pull-down control module and the N-stage clock signal to write the N-stage clock signal to the output end of the output module; In a reset stage, the pull-down control module is operated by the scanning control signal, and the pull-down control module controls the pull-down module to an active state, and the second voltage terminal is used to turn off the output transistor located in the output module, and the output end of the output module is connected to the first voltage terminal, and the driving transistor is turned off. Gate drive circuit driving method.

6. A display panel comprising the display panel according to any one of claims 1 to 4. Display device.

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