Image sensor

Abstract

To provide an image sensor that can relieve an electric field concentration phenomenon.SOLUTION: An image sensor is provided. A substrate having a first surface and a second surface, which face each other, and a pixel separation pattern provided in the substrate and defining a unit pixel region are provided. The unit pixel region includes a first unit pixel region and a second unit pixel region that are adjacent in a first direction and include a first transfer gate and a second transfer gate. The pixel separation pattern includes a first pixel separation part between the first unit pixel region and the second unit pixel region, and a second pixel separation part apart from the first pixel separation part in the first direction through the second transfer gate. The upper surface of the first pixel separation part is lower than the upper surface of the second pixel separation part.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to image sensors, and more particularly to conductive structures in image sensors. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are abbreviated as CIS (CMOS image sensor). The CIS has a plurality of unit pixel regions arranged two-dimensionally. Each unit pixel region includes a photodiode. The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 10,074,678 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor capable of reducing the electric field concentration phenomenon.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor that can ensure a patterning margin for forming a transfer gate.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] An image sensor according to the concept of the present invention includes a substrate having a first surface and a second surface facing each other, and a pixel isolation pattern provided in the substrate and defining a unit pixel region, the unit pixel region including a first unit pixel region and a second unit pixel region adjacent to each other in a first direction and each including a first transfer gate and a second transfer gate, the pixel isolation pattern including a first pixel isolation portion between the first unit pixel region and the second unit pixel region and a second pixel isolation portion spaced apart from the first pixel isolation portion in the first direction via the second transfer gate, and a top surface of the first pixel isolation portion may be lower than a top surface of the second pixel isolation portion.

[0008] An image sensor according to the present invention includes a substrate having a first surface and a second surface facing each other, the first surface including an active region defined by an isolation layer, and a pixel isolation pattern provided within the substrate and defining unit pixel regions, the unit pixel regions including first and second unit pixel regions spaced apart in a first direction, the first unit pixel region including a first floating diffusion region and a first transfer gate, the second unit pixel region including a second floating diffusion region and a second transfer gate, and a first top surface of the isolation layer between the first and second transfer gates may be lower than a second top surface of the isolation layer between the first and second floating diffusion regions.

[0009] An image sensor according to the concept of the present invention includes a substrate having a first surface and a second surface facing each other, a pixel separation pattern provided in the substrate and defining a unit pixel region, an anti-reflection film provided on the second surface of the substrate, a color filter and a microlens provided on the anti-reflection film, and a wiring layer on the first surface of the substrate, wherein the unit pixel region includes a first unit pixel region and a second unit pixel region adjacent to each other in a first direction and each unit pixel region includes a first transfer gate and a second transfer gate, and the pixel separation pattern includes a first pixel separation portion between the first unit pixel region and the second unit pixel region and a second pixel separation portion spaced apart from the first pixel separation portion in the first direction via the second transfer gate, and an upper surface of the first pixel separation portion may be lower than an upper surface of the second pixel separation portion. [Effects of the Invention]

[0010] In the image sensor according to the present invention, first recess portions for forming adjacent transfer gates are formed based on a layout in which the first recess portions are connected to each other, thereby ensuring a patterning margin for forming the transfer gates and mitigating electric field concentration between the transfer gates and the floating diffusion region. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Figure 2] 1 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention; [Figure 3] FIG. 1 is a plan view showing an image sensor according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5] FIG. 4 is an enlarged plan view of a region Q in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line II' in FIG. 5. [Figure 7]FIG. 6 is a cross-sectional view taken along line II-II' in FIG. 5. [Figure 8] FIG. 6 is a cross-sectional view taken along line III-III' in FIG. 5. [Figure 9] FIG. 6 is an enlarged plan view of a region R in FIG. 5. [Figure 10] FIG. 7 is an enlarged view of the S1 region in FIG. [Figure 11] FIG. 8 is an enlarged view of the S2 region in FIG. [Figure 12] 6 is a cross-sectional view showing an image sensor according to an embodiment of the present invention, taken along line II' of FIG. 5. FIG. [Figure 13] 6 is a cross-sectional view showing an image sensor according to an embodiment of the present invention, taken along line II-II' of FIG. 5. FIG. [Figure 14] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 15] 5A and 5B are cross-sectional views taken along line II-II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 16] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17] 5A and 5B are cross-sectional views taken along line II-II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 18] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 19] 5A and 5B are cross-sectional views taken along line II-II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 20] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 21]5A and 5B are cross-sectional views taken along line II-II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 22] 6 is a cross-sectional view taken along line II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 23] 5A and 5B are cross-sectional views taken along line II-II' of FIG. 5, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 24] FIG. 4 is an enlarged plan view of a region Q in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the image sensor may include an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog to digital converter (ADC) 7, and an input / output buffer 8.

[0014] The active pixel sensor array 1 may include a plurality of pixels arranged two-dimensionally and may convert optical signals into electrical signals. The active pixel sensor array 1 may be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, provided by a row driver 3. The electrical signals converted by the active pixel sensor array 1 may be provided to a correlated double sampler 6.

[0015] The row driver 3 can provide a number of drive signals to the active pixel sensor array 1 for driving the pixels according to the results of decoding by the row decoder 2. If the pixels are arranged in a matrix, a drive signal can be provided for each row. The timing generator 5 can provide timing signals and control signals to the row decoder 2 and the column decoder 4. The correlated double sampler 6 (CDS) can receive, hold, and sample electrical signals generated by the active pixel sensor array 1. The correlated double sampler 6 can double sample a specific noise level and a signal level based on an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0016] The analog-to-digital converter 7 (ADC) can convert an analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and output the digital signal. The input / output buffer 8 can latch the digital signal and sequentially output the latched signal to a video signal processor (not shown) according to the decoding result of the column decoder 4.

[0017] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention.

[0018] 1 and 2, the active pixel sensor array 1 may include a plurality of pixels PX, which may be arranged in a matrix. Each of the pixels PX may include a transfer transistor TX and logic transistors RX, SX, and AX. The logic transistor may include a reset transistor RX, a select transistor AX, and a source follower transistor SX. The transfer transistor TX, the reset transistor RX, and the select transistor AX may each include a transfer gate TG, a reset gate RG, and a select gate SEL. Each of the pixels PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

[0019] The photoelectric conversion element PD can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion element PD can be a photodiode including a P-type impurity region and an N-type impurity region. The transfer transistor TX can transfer the charges generated in the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD can transfer and cumulatively store the charges generated in the photoelectric conversion element PD. The source follower transistor SX can be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0020] The reset transistor RX can periodically reset the charge accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode of the reset transistor RX can be connected to a power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX can be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be discharged, resetting the floating diffusion region FD.

[0021] The source follower transistor SX may function as a source follower buffer amplifier. The source follower transistor SX may amplify a potential change in the floating diffusion region FD and output it to an output line (Vout). The selection transistor AX may select a pixel PX to be read out row by row. When the selection transistor AX is turned on, a power supply voltage VDD may be applied to the drain electrode of the source follower transistor SX.

[0022] 2 illustrates a unit pixel PX including one photoelectric conversion element PD and four transistors TX, RX, AX, and SX, but the image sensor according to the present invention is not limited thereto. For example, the reset transistor RX, the source follower transistor SX, or the selection transistor AX may be shared by adjacent pixels PX. Also, a unit pixel PX may include multiple photoelectric conversion elements PD. Multiple adjacent pixels PX may share one floating diffusion region FD.

[0023] 3 is a plan view showing an image sensor according to an embodiment, and FIG 4 is a cross-sectional view taken along line AA' in FIG 3.

[0024] 3 and 4, the image sensor may include a sensor chip 1000 and a logic chip 2000. The sensor chip 1000 may include a photoelectric conversion layer 10, a first wiring layer 21, and a light-transmitting layer 30. The photoelectric conversion layer 10 may include a first substrate 100, a pixel isolation pattern 150, an element isolation pattern 103, and a photoelectric conversion region 110 provided within the first substrate 100. Light incident from the outside may be converted into an electrical signal in the photoelectric conversion region 110.

[0025] The first substrate 100 may include a pixel array region AR, an optical black region OB, and a pad region PAD in a plan view. The pixel array region AR may be disposed in a center portion of the first substrate 100 in a plan view. The pixel array region AR may include a plurality of unit pixel regions PX. The unit pixel regions PX may output photoelectric signals from incident light. The unit pixel regions PX may be arranged two-dimensionally in columns and rows. The columns may be parallel to a first direction D1. The rows may be parallel to a second direction D2. In this specification, the first direction D1 may be parallel to a first surface 100a of the first substrate 100. The second direction D2 may be parallel to the first surface 100a of the first substrate 100 and may be different from the first direction D1. For example, the second direction D2 may be substantially perpendicular to the first direction D1. The third direction D3 may be substantially perpendicular to the first surface 100a of the first substrate 100.

[0026] The pad area PAD may be provided at an edge portion of the first substrate 100 and may surround the pixel array area AR in a plan view. A second pad terminal 83 may be provided on the pad area PAD. The second pad terminal 83 may output an electrical signal generated in the unit pixel area PX to the outside, or an external electrical signal or voltage may be transmitted to the unit pixel area PX through the second pad terminal 83.

[0027] The optical black area OB may be disposed between the pixel array area AR and the pad area PAD of the first substrate 100. The optical black area OB may surround the pixel array area AR in a plan view. The optical black area OB may include a plurality of dummy areas 111 that do not include a photoelectric conversion area 110. The photoelectric conversion area 110' of the optical black area OB has a similar structure to the photoelectric conversion area 110 of the pixel array area AR, but may not perform an operation of receiving light and generating an electrical signal. The signals generated in the photoelectric conversion area 110' and the dummy areas 111 of the optical black area OB may be used as information for removing noise in subsequent processes.

[0028] The circuit chip 2000 may be stacked on the sensor chip 1000. The circuit chip 2000 may include a second substrate 40 and a second wiring layer 23. The second wiring layer 23 may be interposed between the first wiring layer 21 and the second substrate 40. The second wiring layer 23 and the first wiring layer 21 may form a wiring structure 20. The second substrate 40 may include a plurality of transistors for components other than the active pixel sensor array 1 of FIG. 1.

[0029] A first connecting structure 50, a first pad terminal 81, and a bulk color filter 90 may be provided on the first substrate 100 in the optical black region OB. The first connecting structure 50 may include a first light-shielding pattern 51, a first insulating pattern 53, and a first capping pattern 55. The first light-shielding pattern 51 may be provided on the second surface 100b of the first substrate 100. The first light-shielding pattern 51 may cover the second surface 100b and conformally cover the inner walls of the third trench TR3 and the fourth trench TR4. The first light-shielding pattern 51 may penetrate the photoelectric conversion layer 10 and the first wiring layer 21 to electrically connect the photoelectric conversion layer 10 and the first wiring layer 21. More specifically, the first light-shielding pattern 51 may contact the wiring in the first wiring layer 21 and the pixel separating pattern 150 in the photoelectric conversion layer 10. Therefore, the first connecting structure 50 may be electrically connected to the wiring in the first wiring layer 21. The first light-blocking pattern 51 can block light incident into the optical black area OB.

[0030] A first pad terminal 81 may be provided inside the third trench TR3 and fill the remaining portion of the third trench TR3. The first pad terminal 81 may include a metal material, such as aluminum. The first pad terminal 81 may be connected to the pixel isolation pattern 150. Therefore, a negative voltage may be applied to the pixel isolation pattern 150 through the first pad terminal 81.

[0031] A first insulating pattern 53 may be provided on the first light-shielding pattern 51 to fill the remaining portion of the fourth trench TR4. The first insulating pattern 53 may penetrate the photoelectric conversion layer 10 and the first wiring layer 21. A first capping pattern 55 may be provided on the first insulating pattern 53. The first capping pattern 55 may be provided on the first insulating pattern 53.

[0032] A bulk color filter 90 may be provided on the first pad terminal 81, the first light-shielding pattern 51, and the first capping pattern 55. The bulk color filter 90 may cover the first pad terminal 81, the first light-shielding pattern 51, and the first capping pattern 55. A first protective film 71 may be provided on the bulk color filter 90 to cover the bulk color filter 90.

[0033] In the pad area PAD, a second connecting structure 60, a second pad terminal 83, and a second protective film 73 may be provided on the first substrate 100. The second connecting structure 60 may include a second light-shielding pattern 61, a second insulating pattern 63, and a second capping pattern 65.

[0034] A second light-shielding pattern 61 may be provided on the second surface 100b of the first substrate 100. More specifically, the second light-shielding pattern 61 may cover the second surface 100b and conformally cover the inner walls of the fifth trench TR5 and the sixth trench TR6. The second light-shielding pattern 61 may penetrate the photoelectric conversion layer 10 and a portion of the first wiring layer 21. More specifically, the second light-shielding pattern 61 may contact the wirings 231 and 232 in the second wiring layer 23. The second light-shielding pattern 61 may include a metal material such as tungsten (W).

[0035] A second pad terminal 83 may be provided inside the fifth trench TR5. The second pad terminal 83 may be provided on the second light-shielding pattern 61 and fill the remaining portion of the fifth trench TR5. The second pad terminal 83 may include a metal material, such as aluminum. The second pad terminal 83 may serve as an electrical connection path between the image sensor device and the outside. A second insulating pattern 63 may fill the remaining portion of the sixth trench TR6. The second insulating pattern 63 may fully or partially penetrate the photoelectric conversion layer 10 and the first wiring layer 21. A second capping pattern 65 may be provided on the second insulating pattern 63. A second passivation film 73 may cover a portion of the second light-shielding pattern 61 and the second capping pattern 65.

[0036] A current applied through the second pad terminal 83 can flow to the pixel separation pattern 150 through the second light-shielding pattern 61, the wires 231 and 232 in the second wiring layer 23, and the first light-shielding pattern 51. An electrical signal generated from the photoelectric conversion regions 110 and 110′ and the dummy region 111 can be transmitted to a logic transistor in the second substrate 40 of the circuit chip 2000 through the wires of the first wiring layer 21, the wires 231 and 232 in the second wiring layer 23, the second light-shielding pattern 61, and the second pad terminal 83.

[0037] The pixel array area AR of the image sensor will be described in more detail below with reference to FIGS.

[0038] FIG. 5 is an enlarged plan view of region Q in FIG. 3. FIG. 6 is a cross-sectional view taken along line I-I' in FIG. 5. FIG. 7 is a cross-sectional view taken along line II-II' in FIG. 5. FIG. 8 is a cross-sectional view taken along line III-III' in FIG. 5. FIG. 9 is an enlarged plan view of region R in FIG. 5. FIG. 10 is an enlarged view of region S1 in FIG. 6. FIG. 11 is an enlarged view of region S2 in FIG. 7. For ease of explanation, the following description will focus on the sensor chip 1000 of the image sensor.

[0039] 5 to 11, the image sensor according to the embodiment of the present invention may include a photoelectric conversion layer 10, gate electrodes TG, RG, SEL, and SF, a first wiring layer 21, and a light transmission layer 30. The photoelectric conversion layer 10 may include a first substrate 100, a pixel isolation pattern 150, and an element isolation pattern 103.

[0040] The first substrate 100 may have a first surface 100a (or front surface) and a second surface 100b (or rear surface) facing each other. Light may be incident on the second surface 100b of the first substrate 100. The first wiring layer 21 may be disposed on the first surface 100a of the first substrate 100, and the light-transmitting layer 30 may be disposed on the second surface 100b of the first substrate 100. The first substrate 100 may be a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 100 may include impurities of a first conductivity type. For example, the impurities of the first conductivity type may include P-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0041] The first substrate 100 may include a plurality of unit pixel regions PX defined by pixel isolation patterns 150. The plurality of unit pixel regions PX may be arranged in a matrix shape along first and second directions D1 and D2 that intersect with each other. The first substrate 100 may include photoelectric conversion regions 110. The photoelectric conversion regions 110 may be provided in the first substrate 100 in each of the unit pixel regions PX. The photoelectric conversion regions 110 are regions in the first substrate 100 doped with second conductive impurities. The second conductive impurities may have an opposite conductivity type to the first conductive impurities. The second conductive impurities may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. The photoelectric conversion regions 110 may be disposed closer to the first surface 100a than the second surface 100b. For example, each photoelectric conversion region 110 may include a first region adjacent to the first surface 100a and a second region adjacent to the second surface 100b. There may be a difference in impurity concentration between the first region and the second region of the photoelectric conversion region 110. Therefore, the photoelectric conversion region 110 may have a potential gradient between the first surface 100a and the second surface 100b of the first substrate 100. As another example, the photoelectric conversion region 110 may not have a potential gradient between the first surface 100a and the second surface 100b of the first substrate 100.

[0042] The first substrate 100 and the photoelectric conversion region 110 may form a photodiode. That is, the photodiode may be formed by a pn junction between the first substrate 100 of the first conductivity type and the photoelectric conversion region 110 of the second conductivity type. The photoelectric conversion region 110 constituting the photodiode may generate and accumulate photocharges in proportion to the intensity of incident light.

[0043] The pixel isolation pattern 150 may extend between the unit pixel regions PX of the first substrate 100. The pixel isolation pattern 150 may have a lattice structure. In a plan view, the pixel isolation pattern 150 may completely surround each unit pixel region PX. The pixel isolation pattern 150 may be provided in a first trench TR1, which may be a region recessed from the first surface 100a of the first substrate 100. The pixel isolation pattern 150 may extend from the first surface 100a to the second surface 100b of the first substrate 100. The pixel isolation pattern 150 is a deep trench isolation layer. The pixel isolation pattern 150 may penetrate the first substrate 100. The vertical height of the pixel isolation pattern 150 may be substantially the same as the vertical thickness of the first substrate 100. For example, the width of the pixel separating pattern 150 may gradually decrease from the first surface 100a to the second surface 100b of the first substrate 100.

[0044] The pixel isolation pattern 150 may include a first isolation pattern 151, a second isolation pattern 153, and a capping pattern 155. The first isolation pattern 151 may be provided along a sidewall of the first trench TR1. For example, the first isolation pattern 151 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide). As another example, the first isolation pattern 151 may include multiple layers, and the layers may include different materials. The first isolation pattern 151 may have a lower refractive index than the first substrate 100. Therefore, crosstalk between the unit pixel regions PX of the first substrate 100 may be prevented or reduced.

[0045] The second isolation pattern 153 may be provided within the first isolation pattern 151. For example, a sidewall of the second isolation pattern 153 may be surrounded by the first isolation pattern 151. The first isolation pattern 151 may be interposed between the second isolation pattern 153 and the first substrate 100. The second isolation pattern 153 may be separated from the first substrate 100 by the first isolation pattern 151. Therefore, the second isolation pattern 153 may be electrically isolated from the first substrate 100 during operation of the image sensor. The second isolation pattern 153 may include a crystalline semiconductor material, such as polycrystalline silicon. For example, the second isolation pattern 153 may further include a dopant, and the dopant may include impurities of a first conductivity type or a second conductivity type. For example, the second isolation pattern 153 may include doped polycrystalline silicon. For example, the second isolation pattern 153 may include an undoped crystalline semiconductor material. For example, the second isolation pattern 153 may include undoped polycrystalline silicon. The term "undoped" may refer to a state in which no intentional doping process is performed. The dopant may include an N-type dopant and a P-type dopant.

[0046] A capping pattern 155 may be provided on an upper surface of the second isolation pattern 153. The capping pattern 155 may be disposed adjacent to the first surface 100a of the first substrate 100. The upper surface of the capping pattern 155 may be coplanar with the first surface 100a of the first substrate 100. The capping pattern 155 may include a non-conductive material. For example, the capping pattern 155 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-dielectric material (e.g., hafnium oxide and / or aluminum oxide). Therefore, the pixel isolation pattern 150 may prevent photocharges generated by incident light incident on each unit pixel region PX from being incident on an adjacent unit pixel region PX due to random drift. That is, the pixel isolation pattern 150 may prevent crosstalk between the unit pixel regions PX.

[0047] An isolation pattern 103 may be provided in the first substrate 100. For example, the isolation pattern 103 may be provided in a second trench TR2, which may be recessed from the first surface 100a of the first substrate 100. The isolation pattern 103 may be a shallow isolation STI film. The isolation pattern 103 may define first and second active patterns ACT1 and ACT2. A lower surface of the isolation pattern 103 may be provided in the first substrate 100. The width of the isolation pattern 103 may gradually decrease from the first surface 100a to the second surface 100b of the first substrate 100. The lower surface of the isolation pattern 103 may be vertically spaced apart from the photoelectric conversion region 110. A pixel isolation pattern 150 may be connected to the isolation pattern 103. At least a portion of the isolation pattern 103 may be disposed on an upper sidewall of the pixel isolation pattern 150 and connected to the upper sidewall of the pixel isolation pattern 150. The sidewalls and bottom surface of the device isolation pattern 103 and the sidewalls of the pixel isolation pattern 150 may have a stepped structure. The depth of the device isolation pattern 103 may be smaller than the depth of the pixel isolation pattern 150. The device isolation pattern 103 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0048] Each unit pixel region PX may include a first active pattern ACT1 and a second active pattern ACT2 defined by an isolation pattern 103. The planar shapes of the first and second active patterns ACT1 and ACT2 are not limited to those shown in FIG.

[0049] 2 may be provided on the first surface 100a of the first substrate 100. Gate electrodes TG, SEL, SF, and RG of each transistor may be provided on the first surface 100a of the first substrate 100. The gate electrodes TG, SEL, SF, and RG may include a transfer gate TG, a select gate SEL, a source follower gate SF, and a reset gate RG.

[0050] A transfer transistor TX may be provided on the first active pattern ACT1 of each unit pixel region PX. The transfer transistor TX may be electrically connected to the photoelectric conversion region 110. The transfer transistor TX may include a transfer gate TG and a floating diffusion region FD on the first active pattern ACT1. The transfer gate TG may include a buried portion VP recessed in the first substrate 100 and a protruding portion PP protruding above the first surface 100a of the first substrate 100. A gate spacer GS may be provided on a sidewall of the protruding portion PP. A gate dielectric layer GI may be interposed between the transfer gate TG and the first substrate 100. The floating diffusion region FD may be located in the first active pattern ACT1 on one side of the transfer gate TG. The floating diffusion region FD may have a second conductivity type (e.g., n-type) opposite to that of the first substrate 100. The gate spacer GS may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate dielectric layer GI may include a silicon oxide layer or a high-k layer having a dielectric constant higher than that of a silicon oxide layer.

[0051] The source follower transistor SX and the selection transistor AX may be provided on the first active pattern ACT1 of the unit pixel region PX. The reset transistor RX may be provided on the second active pattern ACT2 of the unit pixel region PX. A gate dielectric layer may be interposed between the first substrate 100 and each of the transfer gate TG, the selection gate SEL, the source follower gate SF, and the reset gate RG.

[0052] The first wiring layer 21 may include insulating layers 221, 222, and 223, a conductive structure 200, wires 212 and 213, and a via 215. The insulating layers 221 and 222 may include a first insulating layer 221 and a second insulating layer 222 and 223. The first insulating layer 221 may cover the first surface 100a of the first substrate 100. The first insulating layer 221 may be provided between the wires 212 and 213 and the first surface 100a of the first substrate 100 and may cover the gate electrodes TG, SEL, SF, and RG. The second insulating layers 222 and 223 may be stacked on the first insulating layer 221. The first and second insulating layers 212, 222, and 223 may include a non-conductive material. For example, the first and second insulating layers 212, 222, and 223 may include a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0053] An etch stop layer 204 may be provided between the first insulating layer 221 and the first surface 100a of the first substrate 100. The etch stop layer 204 may cover the gate electrodes TG, SEL, SF, and RG. The etch stop layer 204 may include at least one of silicon nitride, silicon oxynitride, or silicon carbonitride. For example, the etch stop layer 204 may include two layers of silicon nitride having different densities.

[0054] The wirings 212 and 213 may be provided on the first insulating layer 221. More specifically, the wirings 212 and 213 may be disposed in second insulating layers 222 and 223 stacked on the first surface 100a of the first substrate 100. The wirings 212 and 213 may be vertically connected to the transfer transistor TX, the source follower transistor SX, the reset transistor RX, and the selection transistor AX through vias 215. An electrical signal converted in the photoelectric conversion region 110 may be transmitted to the circuit chip through the first wiring layer 21. The vias 215 may include a lower via 205 connected to the transfer gate TG or the floating diffusion region FD. The first and second wirings 212 and 213 and the via 215 may include a metal material such as copper (Cu). The first and second wirings 212 and 213 and the via 215 may include a material different from that of the conductive structure 200. The first and second wirings 212 and 213 and the via 215 may be electrically connected to the conductive structure.

[0055] The light-transmitting layer 30 may include a color filter 303 and a microlens 307. The light-transmitting layer 30 may collect and filter light incident from the outside and provide the light to the photoelectric conversion layer 10. Specifically, the color filter 303 and the microlens 307 may be provided on the second surface 100b of the first substrate 100. The color filters 303 may be disposed on the unit pixel regions PX, respectively. The microlenses 307 may be disposed on the color filters 303, respectively. An anti-reflection film 132 and first and second lower insulating films 134 and 136 may be disposed between the second surface 100b of the first substrate 100 and the color filters 303. The anti-reflection film 132 may prevent reflection of light so that light incident on the second surface 100b of the first substrate 100 can smoothly reach the photoelectric conversion region 110. A third lower insulating film 305 may be disposed between the color filters 303 and the microlenses 307. Each of the first and second lower insulating layers 134 and 136 may include at least one of a fixed charge layer, an adhesion layer, and a protection layer.

[0056] The color filter 303 may include a primary color filter. The color filter 303 may include first to third color filters having different colors. For example, the first to third color filters may include green, red, and blue color filters, respectively. The first to third color filters may be arranged in a Bayer pattern. For another example, the first to third color filters may include other colors such as cyan, magenta, or yellow.

[0057] The microlenses 307 may have a convex shape to condense light incident on the unit pixel region PX. In a plan view, the microlenses 307 may overlap the photoelectric conversion regions 110, but are not limited to this.

[0058] Referring to FIG. 5, the first substrate 100 may include pixel groups PG, each including a plurality of unit pixel regions PX. The pixel groups PG may be arranged two-dimensionally along rows and columns in a plan view. One pixel group PG may include a first unit pixel region PX1, a second unit pixel region PX2, a third unit pixel region PX3, and a fourth unit pixel region PX4. The first to fourth unit pixel regions PX1, PX2, PX3, and PX4 may be separated by a pixel separation pattern 150. The first to fourth unit pixel regions PX1, PX2, PX3, and PX4 may be arranged two-dimensionally, forming two rows and two columns. According to the embodiment, the first unit pixel region PX1 may be spaced apart from the second unit pixel region PX2 in a first direction D1, and the third unit pixel region PX3 may be spaced apart from the first unit pixel region PX1 in a second direction D2. The fourth unit pixel region PX4 may be spaced apart from the second unit pixel region PX2 in the second direction D2. The pixel isolation pattern 150 may include a first pixel isolation portion 150P1 between the first unit pixel region PX1 and the second unit pixel region PX2. The first pixel isolation portion 150P1 may extend between the third unit pixel region PX3 and the fourth unit pixel region PX4. The device isolation pattern 103 may include a first portion 103P1 adjacent to the first pixel isolation portion 150P1.

[0059] The pixel isolation pattern 150 may include a third pixel isolation portion 150P3 between the first unit pixel region PX1 and the fourth unit pixel region PX4. The third pixel isolation portion 150P3 may extend between the second unit pixel region PX2 and the third unit pixel region PX3. The third pixel isolation portion 150P3 extending in the first direction D1 may intersect with the first pixel isolation portion 150P1 extending in the second direction D2.

[0060] The pixel isolation pattern 150 may include a second pixel isolation portion 150P2 spaced apart from the first pixel isolation portion 150P1 in the first direction D1 (or the opposite direction to the first direction D1) across the first unit pixel region PX1 or the second unit pixel region PX2. Similarly, the second pixel isolation portion 150P2 may include a portion spaced apart from the first pixel isolation portion 150P1 in the first direction D1 (or the opposite direction to the first direction D1) across the third unit pixel region PX3 or the fourth unit pixel region PX4. For example, the second pixel isolation portion 150P2 may surround the pixel group PG.

[0061] The device isolation pattern 103 may include a second portion 103P2 and a third portion 103P3 adjacent to the second pixel isolation portion 150P2 and the third pixel isolation portion 150P3, respectively.

[0062] The first unit pixel region PX1 may have a mirror-symmetric structure with the second unit pixel region PX2 across the first pixel isolation portion 150P1. The third unit pixel region PX3 may have a mirror-symmetric structure with the first unit pixel region PX1 across the third pixel isolation portion 150P3. For example, the first transfer gate TG1 of the first unit pixel region PX1 may have a mirror-symmetric shape with the second transfer gate TG2 of the second unit pixel region PX2, as shown in FIG.

[0063] The transmission gates TG arranged along the first direction D1 may be arranged in pairs, with adjacent two transmission gates TG forming a pair. For example, the first transmission gate TG1 and the second transmission gate TG2 may be the nearest pair. That is, the distance between the first transmission gate TG1 and the second transmission gate TG2 may be closer than the distance between the fifth transmission gate TG5 and the second transmission gate TG2 of the fifth unit pixel region PX5 illustrated in FIG. 5.

[0064] A recess region RR may be provided between the first transmission gate TG1 and the second transmission gate TG2, recessed in the third direction D3 from the first surface 100a of the first substrate 100. For example, the first surface 100a of the first substrate 100 may have a second height H2, and the bottom surface of the recess region RR may have a first height H1 that is lower than the second height H2. Hereinafter, the height of the recess region RR may be referred to as the height of the bottom surface. In this embodiment, the bottom surface of the recess region RR may be defined as the top surface of the first pixel isolation portion 150P1 and the top surface of the first portion 103P1 of the device isolation pattern 103. That is, the top surface of the first pixel isolation portion 150P1 and the top surface of the first portion 103P1 of the device isolation pattern 103 may each include a portion having the first height H1. The etch stop layer 204 may substantially conformally cover the sidewalls and bottom surface of the recess region RR.

[0065] As shown in FIG. 5, the recess region RR may be provided between two adjacent transfer gates TG in the first direction D1. For example, the recess region RR may be provided between the first transfer gate TG1 and the second transfer gate TG2. Similarly, the recess region RR may be provided between the third transfer gate TG3 of the third unit pixel region PX3 and the fourth transfer gate TG4 of the fourth unit pixel region PX4. As described above, the recess region RR is provided between two adjacent transfer gates TG among the transfer gates TG arranged along the first direction D1, but it does not have to be provided between two non-adjacent transfer gates TG. For example, the recess region RR may not be provided between the second transfer gate TG2 of the second unit pixel region PX2 and the fifth transfer gate TG5 of the fifth unit pixel region PX5. Furthermore, the recess region RR may not be provided between adjacent transfer gates TG in the second direction D2.

[0066] The recess region RR may not be provided on the second pixel isolation portion 150P2 and the third pixel isolation portion 150P3. That is, the top surface of the second pixel isolation portion 150P2 may be disposed at a second height H2 that is higher than the first height H1 and is substantially the same as the height of the first surface 100a of the first substrate 100. In addition, the top surface of the second portion 103P2 of the device isolation pattern 103 may be disposed at the second height H2.

[0067] Similarly, the top surface of the third pixel isolation portion 150P3 may be disposed at a third height H3 that is higher than the first height H1 and is substantially the same as the height of the first surface 100a of the first substrate 100. The third height H3 may be substantially the same as the second height H2. In addition, the top surface of the third portion 103P3 of the device isolation pattern 103 may be disposed at the third height H3.

[0068] Between unit pixel regions PX adjacent to each other in the first direction D1, the recess region RR may be limited to between two transfer gates TG adjacent to each other in the first direction D1, and may not be provided in other regions. For example, the recess region RR may not be provided in a region between the first floating diffusion region FD1 of the first unit pixel region PX1 and the second floating diffusion region FD2 of the second unit pixel region PX2 (hereinafter referred to as a non-recessed region NR). Similarly, the recess region RR may not be provided between the floating diffusion region FD of the third unit pixel region PX3 and the floating diffusion region FD of the fourth unit pixel region PX4. Therefore, the top surface of the first pixel isolation portion 150P1 in the non-recessed region NR between the first floating diffusion region FD1 and the second floating diffusion region FD2 and the top surface of the first portion 103P1 of the element isolation pattern 103 can be positioned at a second height H2 that is higher than the first height H1 and is substantially the same as the height of the first surface 100a of the first substrate 100.

[0069] 10, the thickness t1 of the buried portion VP of the transfer gate TG may be greater than the thickness t2 of the protruding portion PP. For example, the thickness t1 of the buried portion VP may be about 3500 Å to about 5000 Å, and the thickness t2 of the protruding portion PP may be about 1000 Å to about 1400 Å. The depth of the recessed region RR, i.e., the distance D1 from the second height H2 of the first surface 100a of the first substrate 100 to the first height H1 of the upper surface of the third portion 103P3 of the device isolation pattern 103, defining the bottom surface of the recessed region RR, is about 15% to about 35% of the thickness t1 of the buried portion VP. For example, the depth of the recessed region RR may be about 600 Å to about 1200 Å.

[0070] 9, the floating diffusion region FD may be adjacent to the transfer gate TG in the second direction D2. The buried portion VP of the transfer gate TG includes a first sidewall TS1 adjacent to the floating diffusion region FD, and the first sidewall TS1 may intersect with the second sidewall TS2 of the floating diffusion region FD at an angle α of 90° or more. The second sidewall TS2 of the floating diffusion region FD may be the same as the sidewall of the device isolation pattern 103 that defines it. The sidewall of the buried portion VP of the transfer gate TG may be spaced a predetermined distance DS from the sidewall of the protrusion portion PP in the region where it contacts the floating diffusion region FD. The shape of the transfer gate TG as described above may mitigate the phenomenon of electric field concentration at the point where the transfer gate TG and the floating diffusion region FD meet.

[0071] 12 and 13 are cross-sectional views showing an image sensor according to an embodiment of the present invention, taken along lines II' and II-II' in Fig. 5. Hereinafter, any content that overlaps with what has been described above will be omitted.

[0072] 12 and 13, a pixel isolation pattern 150 may be provided in a first trench TR1. The first trench TR1 may be a region recessed from the second surface 100b of the first substrate 100. A width W2 of the lower surface of the pixel isolation pattern 150 may be greater than a width W1 of the upper surface of the pixel isolation pattern 150. The lower surface of the pixel isolation pattern 150 may be substantially coplanar with the second surface 100b. The pixel isolation pattern 150 may penetrate the second surface 100b of the first substrate 100. The upper surface of the pixel isolation pattern 150 may be disposed within the first substrate 100. Therefore, the pixel isolation pattern 150 may be vertically separated from the first surface 100a of the first substrate 100. Alternatively, the pixel isolation pattern 150 may be connected to the first surface 100a. Unlike the configuration described with reference to FIGS. 6 to 8, the pixel isolation pattern 150 may not include a second isolation pattern 153. The pixel isolation pattern 150 may not include a crystalline semiconductor material, such as polysilicon.

[0073] 14 to 23 are views explaining a method for manufacturing an image sensor according to an embodiment of the present invention, and FIGS. 14, 16, 18, 20, and 22 are cross-sectional views taken along line II' of FIG. 5, and FIGS. 15, 17, 19, 21, and 23 are cross-sectional views taken along line II-II' of FIG. 5.

[0074] 5, 14, and 15, a first substrate 100 having a first surface 100a and a second surface 100b facing each other may be prepared. The first substrate 100 may contain impurities of a first conductivity type (e.g., p-type). As an example, the first substrate 100 may be a substrate in which a first conductivity type epitaxial layer is formed on a first conductivity type bulk silicon substrate. As another example, the first substrate 100 may be a bulk substrate including a first conductivity type well.

[0075] A pixel isolation pattern 150 and a device isolation pattern 103 may be formed on a first surface 100a of the first substrate 100. The device isolation pattern 103 may be formed in a second trench TR2. The pixel isolation pattern 150 may be formed in a first trench TR1. The first trench TR1 may be formed after an insulating film for forming the device isolation pattern 103 is formed to cover the second trench TR2. As a result, the pixel isolation pattern 150 may be formed to penetrate the device isolation pattern 103. The device isolation pattern 103 may include silicon oxide or silicon oxynitride. A bottom surface TR1b of the first trench TR1 may be spaced apart from a second surface 100b of the first substrate 100.

[0076] The pixel isolation pattern 150 may be formed by sequentially depositing layers for forming the first isolation pattern 151, the second isolation pattern 153, and the capping pattern 155, followed by a planarization process. For example, the first isolation pattern 151 may include silicon oxide, silicon nitride, and / or silicon oxynitride. The second isolation pattern 153 may include polysilicon. The process of forming the second isolation pattern 153 may include performing a doping process such as a beam line ion implantation process or a plasma doping process (PLAD). The capping pattern 155 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0077] 5, 16, and 17, impurities may be doped into each unit pixel region PX to form a photoelectric conversion region 110. The photoelectric conversion region 110 may have a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type). A thinning process may be performed to remove a portion of the first substrate 100, thereby reducing the vertical thickness of the first substrate 100. The thinning process may include grinding or polishing the second surface 100b of the first substrate 100 and anisotropic or isotropic etching. Subsequently, an anisotropic or isotropic etching process may be performed to remove any remaining surface defects of the first substrate 100.

[0078] By performing a thinning process on the second surface 100b of the first substrate 100, the lower surfaces of the first and second separated patterns 151 and 153 may be exposed. The lower surfaces of the first and second separated patterns 151 and 153 may be located at substantially the same level as the second surface 100b of the first substrate 100.

[0079] A transistor may be formed in each unit pixel region PX. The transistor formation process may include a process of forming a gate electrode such as a transfer gate TG. To form the transfer gate TG, a recess portion RS may be formed in the first surface 100a of the first substrate 100. The process of forming the recess portion RS may include forming a hard mask pattern HM on the first surface 100a of the first substrate 100. The hard mask pattern HM may expose a region where the transfer gate TG is to be formed and a region between a pair of adjacent transfer gates TG. For example, the hard mask pattern HM may include a silicon nitride layer or a silicon oxynitride layer. The formation of the hard mask pattern HM may include forming a hard mask layer covering the first surface 100a of the first substrate 100 and then patterning the hard mask layer into a photoresist pattern. Therefore, the formed recess portion RS may include a first recess portion RP1, which is a region where the transfer gate TG is to be formed, and a second recess portion RP2 between the first recess portion RP1. The first recess portion RP1, which is a region where the transfer gate TG is to be formed, may be deeper than the second recess portion RP2. The second recess portion RP2 may be no deeper than the first recess portion RP1 in the region where the upper portion of the device isolation pattern 103 and the upper portion of the first pixel isolation portion 150P1 are etched. The first recess portion RP1 and the second recess portion RP2 may be formed together using the same etching process. The difference in depth between the first recess portion RP1 and the second recess portion RP2 may be due to the difference in etch rate of the etched materials. That is, the first recess portion RP1 is formed by etching the silicon layer constituting the first substrate 100, and the second recess portion RP2 is formed by etching the first isolation pattern 151, the capping pattern 155, and the device isolation pattern 103, which are formed of a silicon-based insulating material. This etching process may be performed using a recipe with a relatively high etch rate for the silicon layer. The etching process for forming the recess portion RS may include multiple etching processes. For example, after forming the hard mask pattern HM, a dry etching process and a wet etching process may be performed sequentially.The top surface of the first portion 103P1 of the isolation pattern 103, which forms the bottom surface of the second recess portion RP2, the top surface of the first isolation pattern 151, and the top surface of the capping pattern 155 may be substantially coplanar.

[0080] 5, 18, and 19, after removing the hard mask pattern HM, a preliminary gate dielectric layer 171 and a preliminary gate layer 172 may be formed to sequentially fill the recess portion RS. The preliminary gate dielectric layer 171 may be formed substantially conformally along the first surface 100a of the first substrate 100 exposed by removing the hard mask pattern HM and the sidewalls and bottom surfaces of the recess portion RS. The preliminary gate dielectric layer 171 may be a silicon oxide layer or a high-k layer having a dielectric constant greater than that of a silicon oxide layer. The preliminary gate layer 172 may be formed on the preliminary gate dielectric layer 171 to completely fill the recess portion RS. For example, the preliminary gate layer 172 may be formed of a semiconductor material such as polycrystalline silicon. The process of forming the preliminary gate layer 172 may include multiple deposition and doping processes. For example, after forming a first polycrystalline silicon layer, a first impurity implantation process may be performed, and then a second polycrystalline silicon layer may be formed and a second impurity implantation process may be performed. In this case, a native oxide film may be formed between the first polycrystalline silicon layer and the second polycrystalline silicon layer, but is not limited thereto.

[0081] 5, 20, and 21, a patterning process may be performed on the preliminary gate layer 172 to form a gate electrode including a transfer gate TG. The preliminary gate layer 172 may be removed at the second recess portion RP2 to form a recess region RR exposing the preliminary gate dielectric layer 171. The transfer gate TG may be formed to include a buried portion VP filling the first recess portion RP1 and a protruding portion PP protruding above the first surface 100a of the first substrate 100. The buried portion VP may include a step structure ST formed thereon by a patterning process.

[0082] 5, 22, and 23, a gate spacer GS may be formed on a sidewall of the protrusion PP of the transfer gate TG. The gate spacer GS may be formed by depositing a spacer insulating film and an anisotropic etching process. During the anisotropic etching process, the preliminary gate dielectric film 171 may also be patterned to form the gate dielectric film GI. The gate spacer GS may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0083] An impurity implantation process may be performed on the resultant structure on which the gate electrode is formed to form first and second active patterns ACT1 and ACT2 including floating diffusion regions FD, thereby completing the formation of the transfer transistor TX and the logic transistor.

[0084] An etch stop layer 204 may be formed covering the first surface 100a of the first substrate 100 and the recess region RR. The etch stop layer 204 may be formed of at least one of silicon nitride, silicon oxynitride, or silicon carbonitride. The etch stop layer 204 may contact the top surfaces of the first pixel isolation portion 150P1 and the device isolation pattern 103 in the recess region RR, but instead, a gate dielectric layer GI may remain between the etch stop layer 204 and the first pixel isolation portion 150P1 and between the etch stop layer 204 and the device isolation pattern 103. Then, a first insulating layer 221 may be formed covering the etch stop layer 204.

[0085] 5, 6 to 8, a lower via 205 may be formed through the first insulating layer 221 to be connected to the transfer gate TG or the floating diffusion region FD. Then, second insulating layers 222 and 223 may be sequentially formed on the first insulating layer 221. Wirings 212 and 213 and a via 215 may be formed in the second insulating layers 222 and 223, completing the formation of the first wiring layer 21.

[0086] An anti-reflection layer 132, a first lower insulating layer 134, and a second lower insulating layer 136 may be sequentially formed on the second surface 100b of the first substrate 100. A color filter 303 may be formed on each unit pixel region PX. A microlens 307 may be formed on each color filter 303, thereby completing the formation of the light-transmitting layer 30.

[0087] As the integration density of image sensors increases, if first recess portions RP1 for forming adjacent transfer gates TG are formed based on a layout in which the adjacent transfer gates TG are separated from each other, the adjacent transfer gates TG may not be separated from each other or the sidewalls of the transfer gates TG in contact with the floating diffusion regions FD may be excessively rounded, resulting in electric field concentration. According to an embodiment of the present invention, first recess portions RP1 for forming adjacent transfer gates TG may be formed based on a layout in which the adjacent transfer gates TG are connected to each other. As a result, the first recess portions RP1 for providing adjacent transfer gates TG may be formed in a shape connected by the second recess portions RP2. Therefore, a patterning margin for forming the transfer gates TG may be secured, and the electric field concentration phenomenon may be alleviated where the transfer gates TG are connected to the floating diffusion regions FD.

[0088] Fig. 24 is an enlarged plan view of the Q region of Fig. 3. For simplicity of explanation, explanation of overlapping components will be omitted.

[0089] 24, in the image sensor according to the embodiment of the present invention, a first substrate 100 may include pixel groups PG each including a plurality of unit pixel regions PX. One pixel group PG may include a first unit pixel region PX1, a second unit pixel region PX2, a third unit pixel region PX3, and a fourth unit pixel region PX4. The first to fourth unit pixel regions PX1, PX2, PX3, and PX4 may be separated by pixel isolation patterns 150. The pixel isolation patterns 150 may extend between the unit pixel regions PX of the first substrate 100. The pixel isolation patterns 150 may have a lattice structure. In a plan view, the pixel isolation patterns 150 may completely surround each of the unit pixel regions PX. Element isolation patterns 103 defining first and second active patterns ACT1 and ACT2 may be provided within the first substrate 100.

[0090] The pixel isolation pattern 150 may include a first pixel isolation portion 150P1, a second pixel isolation portion 150P2, and a third pixel isolation portion 150P3. The first pixel isolation portion 150P1 may be disposed between the first unit pixel region PX1 and the second unit pixel region PX2 and between the third unit pixel region PX3 and the fourth unit pixel region PX4, and may extend in the second direction D2. The third pixel isolation portion 150P3 may be disposed between the first unit pixel region PX1 and the fourth unit pixel region PX4 and between the second unit pixel region PX2 and the third unit pixel region PX3, and may extend in the first direction D1. The second pixel isolation portion 150P2 may surround the pixel group PG.

[0091] The first, second, third, and fourth unit pixel regions PX1, PX2, PX3, and PX4 may each include a first, second, third, and fourth transfer gates TG1, TG2, TG3, and TG4. In this embodiment, the distance between the first and third transfer gates TG1 and TG3 may be substantially the same as the distance between the first and second transfer gates TG1 and TG2. For example, the first through fourth transfer gates TG1-TG4 may be formed in a first recess portion RP1 connected by a second recess portion RP2 when forming the recess portion RS described with reference to FIGS. 16 and 17. That is, the first through fourth transfer gates TG1-TG4 may be formed based on a layout in which the first recess portion RP1 for forming the transfer gates is connected to one another.

[0092] In this embodiment, recess regions RR may be provided in the first pixel isolation portion 150P1 and the third pixel isolation portion 150P3. The second pixel isolation portion 150P2 may be a non-recessed region NR. For example, as shown in FIG. 24, the recess regions RR may have a cross shape in the regions between the first through fourth transfer gates TG1-TG4. In the first pixel isolation portion 150P1, the region between the first floating diffusion region FD1 of the first unit pixel region PX1 and the second floating diffusion region FD2 of the second unit pixel region PX2 may be a non-recessed region NR. Similarly, in the first pixel isolation portion 150P1, the region between the third floating diffusion region FD3 of the third unit pixel region PX3 and the fourth floating diffusion region FD4 of the fourth unit pixel region PX4 may be a non-recessed region NR.

[0093] Although the present invention has been described above with reference to the accompanying drawings, the present invention may be embodied in other specific forms without modifying the technical concept or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0094] 100 boards 110 Photoelectric conversion region 200 Conductive Structure 204 Etch stop film 205 bottom via 215 Beer 212, 213 wiring 221, 222, 223 Insulating layer 1000 sensor chips 2000 logic chips GI gate dielectric film GS Gate Spacer PP protrusion RR recess area TG Transmission Gate VP embedding part

Claims

1. a substrate having a first surface and a second surface facing each other; a pixel separating pattern provided in the substrate and defining a unit pixel area; The unit pixel regions include a first unit pixel region and a second unit pixel region adjacent to each other in a first direction, the first unit pixel region and the second unit pixel region including a first transfer gate and a second transfer gate, respectively; the pixel separation pattern includes a first pixel separation portion between the first unit pixel region and the second unit pixel region, and a second pixel separation portion spaced apart from the first pixel separation portion in the first direction with the second transmission gate interposed therebetween, the first pixel separation portion being interposed between the first transmission gate and the second transmission gate adjacent to each other; an upper surface of the first pixel isolation portion between the first transmission gate and the second transmission gate is lower than an upper surface of the second pixel isolation portion; The first unit pixel region and the second unit pixel region each include a first floating diffusion region and a second floating diffusion region disposed adjacent to the first surface, the first pixel isolation portion includes a first upper surface between the first transmission gate and the second transmission gate and a second upper surface between the first floating diffusion region and the second floating diffusion region; The first top surface is lower than the second top surface.

2. the unit pixel region includes a third unit pixel region adjacent to the first unit pixel region in a second direction perpendicular to the first direction, the pixel separation pattern further includes a third pixel separation portion between the first unit pixel region and the third unit pixel region, The image sensor of claim 1 , wherein a top surface of the first pixel isolation portion is lower than a top surface of the third pixel isolation portion.

3. the unit pixel region includes a fourth unit pixel region spaced apart from the first unit pixel region via the second unit pixel region, the fourth unit pixel region including a fourth transfer gate; the second pixel isolation portion is disposed between the second transmission gate and the fourth transmission gate; 3. The image sensor of claim 1, wherein the distance between the first transmission gate and the second transmission gate is shorter than the distance between the second transmission gate and the fourth transmission gate.

4. the first transmission gate includes a buried portion recessed into the first surface of the substrate and a protruding portion protruding above the first surface; The image sensor according to claim 1 , wherein a distance from the first surface to an upper surface of the first pixel isolation portion is 15% to 35% of a thickness of the buried portion.

5. a distance from an upper surface of the second pixel isolation portion to an upper surface of the first pixel isolation portion is 600 Å (angstroms) to 1200 Å; The thickness of the buried portion is 3500 Å to 5000 Å; 5. The image sensor of claim 4, wherein the thickness of the protrusion is between 1000 Å and 1400 Å.

6. the first unit pixel region includes a first floating diffusion region disposed adjacent to the first surface; the first floating diffusion region is adjacent to the first transmission gate in a second direction perpendicular to the first direction; 6. The image sensor of claim 1, wherein a first sidewall of the first transfer gate adjacent to the first floating diffusion region intersects with a second sidewall of the first floating diffusion region at an angle of 90° or more.

7. the substrate further includes an isolation layer defining an active region; 7. The image sensor of claim 1, wherein a first upper surface of the isolation film between the first and second transfer gates is disposed at a level lower than the first surface of the substrate.

8. The first unit pixel region and the second unit pixel region each include a first floating diffusion region and a second floating diffusion region disposed adjacent to the first surface, 8. The image sensor of claim 7, wherein the first upper surface of the isolation layer is disposed at a level lower than a second upper surface of the isolation layer between the first floating diffusion region and the second floating diffusion region.

9. The image sensor of claim 8 , wherein the first upper surface of the device isolation layer is substantially flush with an upper surface of the first pixel isolation portion.

10. a substrate having a first surface and a second surface facing each other, the first surface and the second surface including an active region defined by an isolation film; a pixel separating pattern provided within the substrate and defining a unit pixel area, the unit pixel area including a first unit pixel area and a second unit pixel area spaced apart in a first direction; the first unit pixel region includes a first floating diffusion region and a first transfer gate, and the second unit pixel region includes a second floating diffusion region and a second transfer gate; a first upper surface of the isolation layer between the first and second transfer gates being lower than a second upper surface of the isolation layer between the first and second floating diffusion regions;

11. the unit pixel region includes a third unit pixel region adjacent to the first unit pixel region in a second direction perpendicular to the first direction and including a third transfer gate; 11. The image sensor of claim 10, wherein a third top surface of the isolation layer between the third transfer gate and the first transfer gate is higher than the first top surface and is substantially flush with the second top surface.

12. the unit pixel region includes a fourth unit pixel region spaced apart from the first unit pixel region via the second unit pixel region, the fourth unit pixel region including a fourth transfer gate; 12. The image sensor of claim 10, wherein a fourth top surface of the isolation layer between the fourth transfer gate and the first transfer gate is higher than the first top surface and is substantially at the same level as the second top surface.

13. 13. The image sensor of claim 12, wherein a distance between the first transmission gate and the second transmission gate is closer than a distance between the second transmission gate and the fourth transmission gate.

14. the first transmission gate includes a buried portion recessed into the first surface of the substrate and a protruding portion protruding above the first surface; The image sensor of claim 12 , wherein a distance from the first surface to a first upper surface of the isolation layer is 15% to 35% of a thickness of the buried portion.

15. a distance from the first surface to a first upper surface of the isolation film is 600 Å to 1200 Å; The thickness of the buried portion is 3500 Å to 5000 Å; 15. The image sensor of claim 14, wherein the thickness of the protrusion is between 1000 Å and 1400 Å.

16. the pixel separating pattern further includes a first pixel separating pattern between the first unit pixel region and the second unit pixel region, The image sensor of claim 10 , wherein the first and second transmission gates are mirror-symmetric with respect to the first pixel separation pattern.

17. a substrate having a first surface and a second surface facing each other; a pixel separating pattern provided in the substrate and defining a unit pixel area; an anti-reflective coating provided on the second surface of the substrate; a color filter and a microlens provided on the anti-reflection film; a wiring layer on the first surface of the substrate; The unit pixel regions include a first unit pixel region and a second unit pixel region adjacent to each other in a first direction, the first unit pixel region and the second unit pixel region including a first transfer gate and a second transfer gate, respectively; the pixel separation pattern includes a first pixel separation portion between the first unit pixel region and the second unit pixel region, and a second pixel separation portion spaced apart from the first pixel separation portion in the first direction with the second transmission gate interposed therebetween, the first pixel separation portion being interposed between the first transmission gate and the second transmission gate adjacent to each other; an upper surface of the first pixel isolation portion between the first transmission gate and the second transmission gate is lower than an upper surface of the second pixel isolation portion; The first unit pixel region and the second unit pixel region each include a first floating diffusion region and a second floating diffusion region disposed adjacent to the first surface, the first pixel isolation portion includes a first upper surface between the first transmission gate and the second transmission gate and a second upper surface between the first floating diffusion region and the second floating diffusion region; The first top surface is lower than the second top surface.

18. the unit pixel region includes a third unit pixel region adjacent to the first unit pixel region in a second direction perpendicular to the first direction, the pixel separation pattern further includes a third pixel separation portion between the first unit pixel region and the third unit pixel region, The image sensor of claim 17 , wherein a top surface of the first pixel isolation portion is lower than a top surface of the third pixel isolation portion.

19. the unit pixel region includes a fourth unit pixel region spaced apart from the first unit pixel region via the second unit pixel region, the fourth unit pixel region including a fourth transfer gate; the second pixel isolation portion is disposed between the second transmission gate and the fourth transmission gate; 19. The image sensor of claim 17, wherein the distance between the first transmission gate and the second transmission gate is closer than the distance between the second transmission gate and the fourth transmission gate.

Images