Semiconductor Devices

Abstract

To provide a transistor with excellent electric characteristics.SOLUTION: A semiconductor device includes a semiconductor, a first insulator provided in contact with the semiconductor, a first conductor provided in contact with the first insulator and overlapping with the semiconductor through the first insulator, and a second conductor and a third conductor provided in contact with the semiconductor. Any one or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention may be applied to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a camera, It relates to image devices, processors, electronic devices, display devices, liquid crystal display devices, light emitting devices, The present invention relates to a method for manufacturing a storage device, an imaging device, and an electronic device. The present invention relates to a method for driving a liquid crystal display device, a light emitting device, a storage device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the (object of matter).

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. may have semiconductor devices. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. It is known that transistors have extremely small leakage currents when they are in a non-conducting state. For example, low-power transistors using oxide semiconductors, which have low leakage current, are being developed. A power CPU and the like have been disclosed (see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to reduce impurities such as water and hydrogen in transistors using oxide semiconductors, Therefore, the gate electrode and the semiconductor device used in the transistor may be subjected to a high-temperature heat treatment. The source electrode or the drain electrode is formed of a material having heat resistance and oxidation resistance. is preferred.

[0007] In view of the above, one embodiment of the present invention is a transistor using a heat-resistant and oxidation-resistant conductor. One of our goals is to provide the following.

[0008] Another object is to provide a transistor with stable electrical characteristics. An object of the present invention is to provide a transistor with low leakage current when off. Another object is to provide a transistor having high frequency characteristics. An object of the present invention is to provide a transistor having marrow-off electrical characteristics. An object of the present invention is to provide a transistor with a small subthreshold swing value. Another object is to provide a highly reliable transistor.

[0009] Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. It is an object of the present invention to provide a device or an electronic device having the module. It is an object of the present invention to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device including a first insulator in contact with the semiconductor, and a second insulator in contact with the first insulator. A first conductor overlaps the semiconductor via an insulator, a second conductor and a and a third conductor, and at least one of the first to third conductors is made of tungsten ( W), silicon (Si), carbon (C), germanium (Ge), tin (Sn), and aluminum and one or more elements selected from aluminum (Al) and nickel (Ni). This is a semiconductor device.

[0012] In one embodiment of the present invention, at least one of the first to third conductors is a Rutherford backscattering conductor. Analysis(RBS: Rutherford Backscattering Spectrom The silicon concentration obtained by the method is between 5 atomic % and 70 atomic %. The semiconductor device has a region in which

[0013] In one embodiment of the present invention, at least one of the first to third conductors has silicon and an oxide on the surface. The semiconductor has a region containing an element, and the thickness of the region is 0.2 nm or more and 20 nm or less. It is a device.

[0014] One aspect of the present invention is a semiconductor device including a second insulator in contact with the semiconductor, and a second insulator in contact with the second insulator. and a fourth conductor overlapping the semiconductor via the fourth conductor, the fourth conductor being made of tungsten and silicon. one or more selected from silicon, carbon, germanium, tin, aluminum, and nickel and a region having the element.

[0015] In one aspect of the present invention, the fourth conductor is silicon obtained by Rutherford backscattering analysis. The semiconductor device having a region in which the concentration is 5 atomic % or more and 70 atomic % or less. It is a location.

[0016] In one aspect of the present invention, the fourth conductor has a region having silicon and oxygen on the surface thereof, In the semiconductor device, the thickness of the region is 0.2 nm or more and 20 nm or less.

[0017] One embodiment of the present invention is the above semiconductor device, in which the semiconductor includes an oxide semiconductor. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a transistor using a heat-resistant and oxidation-resistant conductor is provided. It can be provided.

[0019] Furthermore, a transistor having stable electrical characteristics can be provided. It is possible to provide a transistor with low leakage current at high frequency. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. It is possible to provide a low-cost transistor. It is possible.

[0020] Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module having the semiconductor device or the module may be provided. It is possible to provide an electronic device having a module. Or, a new module can be provided. Or, a new electronic Equipment can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 2] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 3] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 4] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 5] Cross-sectional TEM image of a-like OS. [Figure 6] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 7] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are a schematic view and a cross-sectional view illustrating a film forming apparatus. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] FIG. 1 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention. [Figure 21] FIG. 1 is a cross-sectional view showing a chamber according to one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view showing a chamber according to one embodiment of the present invention. [Figure 23] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 25]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 31] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 32] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 33] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 36] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 40] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 42] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 43] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 44] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 45] FIG. 1 is a diagram illustrating the XPS results of a sample. [Figure 46] Schematic diagram illustrating the STEM results of the sample. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0024] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. The above-mentioned embodiments can be combined or substituted to form one embodiment of the present invention.

[0025] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0026] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0027] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative and is expressed in terms of its magnitude relative to a reference potential. Therefore, even if it is described as "ground potential," For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined.

[0028] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, ordinal numbers described in this specification and the like can be replaced with other numbers as appropriate. and the ordinal numbers used to identify an aspect of the present invention may not match.

[0029] Impurities in semiconductors are substances other than the main components that make up the semiconductor. For example, impurities with a concentration of 0. Elements present in amounts less than 1 atomic % (also called atomic %) are impurities. This can result in the formation of DOS (Density of State) in semiconductors, for example. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen In addition, if the semiconductor is a silicon layer, oxygen vacancies may occur. In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0030] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the source and drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0031] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0032] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width that is The larger the

[0033] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0034] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area where the source and drain face each other The channel width of the In this specification, it is sometimes referred to as "channel width." In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the embedded channel can be determined by taking a cross-sectional TEM image and analyzing the image. The value can be determined by

[0035] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0036] In this specification, when it is stated that A has a shape that protrudes more than B, it is not limited to a top view. In the cross-sectional view, at least one end of A is located outside at least one end of B. Therefore, it may be stated that A has a shape that protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0037] In this specification, when simply referring to a semiconductor, it can be replaced with various semiconductors. For example, Group 14 semiconductors such as silicon and germanium, and oxide semiconductors Conductors, silicon carbide, germanium silicide, gallium arsenide, indium phosphide, selenide Can be replaced by compound semiconductors such as zinc and cadmium sulfide, and organic semiconductors .

[0038] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0040] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be used to explain.

[0041] <Transistor configuration> The structure of a transistor will be described below as an example of a semiconductor device according to one embodiment of the present invention. Reveal.

[0042] The structure of the transistor 10 will be described with reference to FIGS. 1A to 1C. 1B is a top view of the transistor 10. 1(C) is a cross-sectional view corresponding to the dashed line A3-A4 in FIG. 1(A). In the region indicated by the dashed line A1-A2, the channel length direction of the transistor 10 is In the region indicated by the dashed line A3-A4, the transistor 10 The channel width direction of the transistor is the direction of the Source (source region or source electrode) and drain (drain region or drain electrode) ) between the substrate and the horizontal plane, the channel width direction is the direction in which the carriers move. In FIG. 1(A), the insulating film The insulating material 106a, the semiconductor 106b, and the insulator 106c are almost the same as the conductors 108a and 108b. However, since this is difficult to see in a top view, the insulators 106a and 106b are not shown. The semiconductor 106b and the insulator 106c are shown slightly offset by thin dashed lines.

[0043] The transistor 10 is made up of an insulator 101 on a substrate 100, a conductor 102, an insulator 105, and an insulating layer. The semiconductor 103 and the insulator 104, the insulator 106a on the insulator 104, the semiconductor 106b and and insulator 106c, conductor 108a and conductor 108b on semiconductor 106b, and insulator The insulator 112 on the body 106c, the conductor 114 on the insulator 112, and the insulator on the conductor 114 The electrode includes an edge 116, an insulator 118, a conductor 120a, and a conductor 120b.

[0044] Here, the insulator 101, the insulator 103, the insulator 104, the insulator 105, the insulator 106a, The insulators 106c, 112, 116 and 118 are insulating films or insulating The conductor 102, the conductor 108a, the conductor 108b, and the conductor 114, the conductor 120a and the conductor 120b can also be called a conductive film or a conductive layer. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.

[0045] Note that the insulator 106a and / or the insulator 106c may not be provided.

[0046] In addition, one or more of the insulators 105, 103, and 104 may be provided. For example, a single layer structure of only the insulator 104 may be used, or the insulator 103 and the insulating layer 104 may be used. The edge 104 may have a laminated structure of two layers.

[0047] Furthermore, as will be described in detail later, when the insulator 106a and the insulator 106c are used alone, Materials that can function as conductors or semiconductors may be used. When a transistor is formed by stacking the conductor 106b, the carrier is the semiconductor 106b. The vicinity of the interface between the conductor 106b and the insulator 106a, and the boundary between the semiconductor 106b and the insulator 106c The insulators 106a and 106c function as the channel of the transistor. Therefore, in this specification and the like, the insulators 106a and The insulator 106c will not be described as a conductor or a semiconductor, but as an insulator.

[0048] A conductor 102 is formed on an insulator 101 formed on a substrate 100. At least a portion of the insulating layer 106a overlaps with the semiconductor 106b and the insulating layer 106c. In addition, an insulator 105 is provided on the conductor 102 so as to be in contact with the conductor 102 and cover the conductor 102. An insulator 103 is formed on the insulator 105, and an insulator 104 is formed on the insulator 103. A body 104 is formed.

[0049] An insulator 106a is formed on the insulator 104, and a semiconductor 1 is formed in contact with the upper surface of the insulator 106a. In FIG. 1B, the edge of the insulator 106a and the semiconductor 106b is The insulator 106a and the semiconductor 106b are formed so that their portions are roughly aligned. The configuration of the semiconductor device shown in the embodiment is not limited to this.

[0050] The conductor 108a and the conductor 108b are formed in contact with the semiconductor 106b. The conductor 108a and the conductor 108b are formed apart from each other, and the source of the transistor 10 It can function as a gate electrode and a drain electrode.

[0051] The insulator 106c is formed in contact with the semiconductor 106b. It is preferable that the semiconductor 106b is in contact with the region sandwiched between the semiconductor 106a and the conductor 108b. In FIG. 1(B), the insulator 106c is located approximately on the upper surfaces of the conductors 108a and 108b. However, the structure of the semiconductor device described in this embodiment is not limited to this. .

[0052] An insulator 112 is formed on the insulator 106c. A conductor 114 is formed on the insulator 112. In FIG. 1B, the ends of the insulator 112 and the insulator 106c are approximately aligned. Insulators 112 and 106c are formed as shown in FIG. The structure of the conductor device is not limited to this. It can function as a pole.

[0053] An insulator 116 is formed on the conductor 114 and the insulator 112, and an insulating layer is formed on the insulator 116. An insulator 118 is formed. A conductor 120a and a conductor 120b are formed on the insulator 118. The conductor 120a and the conductor 120b are formed between the insulator 106c and the insulator 112. , the conductor 108a and the conductor 108b pass through openings formed in the insulators 116 and 118. It is connected to the electric body 108b.

[0054] In addition, any one of the conductor 102, the conductor 114, the conductor 108a, and the conductor 108b The above is a combination of tungsten and silicon, carbon, germanium, tin, aluminum or nickel. and one or more elements selected from nickel.

[0055] In particular, the conductor in this embodiment has a region containing tungsten and silicon. It is preferable to use a conductor having a silicon concentration obtained by RBS. It is preferable that the SiO 2 has a region where the SiO 2 content is 5 atomic % or more and 70 atomic % or less.

[0056] Furthermore, when a tungsten film is formed by sputtering, a crystalline conductor is formed. This may result in poor surface flatness of the conductor. By using a conductor as clearly shown, it is possible to form a conductor having an amorphous structure. This makes it easier to form a conductor with good surface flatness.

[0057] The conductor has a region on the surface thereof that contains silicon and oxygen, and the region The thickness of the region is preferably 0.2 nm or more and 20 nm or less. In this case, the region can function as an insulator. Furthermore, this region functions as a barrier layer against oxygen, preventing the entire conductor from being oxidized. This can suppress the risk of

[0058] Conductor 102, conductor 114, conductor 108a and conductor 108b are connected as shown above. By using a suitable conductor, for example, during the process of fabricating the transistor 10, a heat treatment can be performed. Even if the conductor is exposed to heat or an oxidizing atmosphere, the entire conductor is prevented from being oxidized. This can suppress an increase in the resistance value of the conductor, resulting in a favorable Therefore, it is possible to manufacture a transistor with good electrical characteristics (such as on-state current).

[0059] <Semiconductors> The detailed configuration of the semiconductor 106b will be described below.

[0060] The detailed configurations of the insulators 106a and 106c as well as the semiconductor 106b are also explain.

[0061] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, if indium is included, the carrier mobility (electron mobility) increases. 106b preferably contains an element M. The element M is preferably Ti, Ga, Y, Zr, Let La, Ce, Nd, Sn or Hf be used as the element M. There are cases where multiple combinations are acceptable. For example, the element M has a bond energy with oxygen of For example, it is an element whose bond energy with oxygen is higher than that of indium. Alternatively, the element M may have a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 106b preferably contains zinc. If it contains, it may be prone to crystallization.

[0062] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide, such as zinc tin oxide or gallium tin oxide. oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay.

[0063] For example, the insulators 106a and 106c are formed of a material other than oxygen that constitutes the semiconductor 106b. The semiconductor 106b is an oxide semiconductor composed of one or more elements. The insulator 106a and the insulator 106 are made of one or more elements other than oxygen. c is formed, the interface between the insulator 106a and the semiconductor 106b, and the semiconductor 106b Defect levels are unlikely to be formed at the interface between the insulator 106c and the insulator 106b.

[0064] The insulator 106a, the semiconductor 106b, and the insulator 106c contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When the atomic percentage is 100, it is preferable that In is less than 50 atomic percent and M is less than 50. atomic %, more preferably In is less than 25 atomic % and M is 75 atomic % When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, preferably In is 25 atomic %. %, and M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn. In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. The insulating material 106a and / or the insulating material 106c may be gallium oxide. The number of atoms of each element contained in the body 106a, the semiconductor 106b, and the insulator 106c is simply The ratio does not have to be an integer. The composition can be measured by RBS, for example. stomach.

[0065] For example, when the insulator 106a or the insulator 106c is formed by a sputtering method, A typical example of the atomic ratio of the metal elements in the target used in the present invention is In:M:Zn=1:2: 4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn= 1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Z n=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M :Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, In :M:Zn=1:6:9 etc.

[0066] In addition, for example, when a film is formed by sputtering, the target used for the semiconductor 106b is Typical examples of atomic ratios of metal elements in the ZnO are In:M:Zn=1:1:1, In:M: Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2 .3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4 :2:4.1, In:M:Zn=5:1:7, etc. In particular, sputtering targets When the atomic ratio of In:Ga:Zn=4:2:4.1 is used, the semiconductor to be formed is The atomic ratio of 106b may be approximately In:Ga:Zn=4:2:3.

[0067] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably Preferably, it is 90% or more.

[0068] The semiconductor 106b is made of, for example, an oxide with a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. The energy gap of the insulator 106c is larger than that of the semiconductor 106b. It's bigger than a pu.

[0069] The semiconductor 106b is an oxide having a larger electron affinity than the insulator 106a or the insulator 106c. For example, the semiconductor 106b is made of a material selected from the insulators 106a and 106c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. It is more preferable to use an oxide having a larger value by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. The energy level of the conduction band minimum of the insulator 106a or the semiconductor 106b is It is closer to the vacuum level than the energy level at the lower band edge.

[0070] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b, and the insulator 10 A channel is formed in the semiconductor 106b having a large electron affinity among the semiconductors 106a and 106b. When a voltage is applied to the insulator 106a, the insulator 106a is electrically connected to the semiconductor 106b. Current may also flow near the interface between semiconductor 106c and semiconductor 106b.

[0071] As described above, when the insulators 106a and 106c are used alone, they are not conductive or semi-conductive. However, semiconductors 10 When a transistor is formed by stacking the semiconductor 106b and the semiconductor 106b, electrons The flow passes through the vicinity of the interface between the semiconductor 106b and the insulator 106c. , the insulators 106a and 106c do not function as the channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 106 The insulator 106a and the insulator c are not described as semiconductors but as insulators. The body 106c is described as an insulator only because it is a transistor compared to the semiconductor 106b. Since the function is similar to that of an insulator, the insulator 106a or the insulator 106c is used. Therefore, a material that can be used for the semiconductor 106b may be used.

[0072] Here, the insulator 106a and the semiconductor 106b are separated by a gap between them. In addition, between the semiconductor 106b and the insulator 106c, The mixed region may have a semiconductor 106b and an insulator 106c. Therefore, the potential density of the insulator 106a, the semiconductor 106b, and the insulator 106c is In the laminate, the energy changes continuously near each interface (also known as continuous junction). The band diagram is as follows. The interface between the semiconductor 106c and the semiconductor 106b may not be clearly distinguishable.

[0073] At this time, the electrons move not in the insulator 106a and the insulator 106c but in the semiconductor 106b. As described above, the electrons move mainly through the interface between the insulator 106a and the semiconductor 106b. and the defect state density at the interface between the semiconductor 106b and the insulator 106c. By lowering the concentration, the movement of electrons in the semiconductor 106b is less hindered, The on-state current of the transistor can be increased.

[0074] In addition, the on-current of the transistor is increased as the factors that hinder the movement of electrons are reduced. For example, if there are no factors that hinder the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is caused by, for example, large physical irregularities in the channel formation region. is also inhibited.

[0075] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 106b (the surface to be formed, here the upper surface of the insulator 106a) Root Mean Square (RMS) roughness less than 1 nm, preferably It is preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the area of ​​1 μm × 1 μm is 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0 The maximum height difference (PV and ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, Preferably, it is less than 7 nm. RMS roughness, Ra and PV are measured by SII. Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0076] In addition, in order to increase the on-state current of the transistor, the smaller the thickness of the insulator 106c, the greater the The thickness of the insulator 106c is preferably smaller than that of the insulator 106a, and the thickness of the semiconductor 106b is preferably For example, the thickness is less than 10 nm, preferably 5 nm or less, and Preferably, the insulator 106c has a region of 3 nm or less. 6c is a semiconductor 106b in which a channel is formed, and is formed by introducing oxygen atoms other than oxygen constituting an insulator adjacent thereto. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. The insulator 106c preferably has a certain thickness, for example, 0.3 nm or more. Insulator 106 preferably having a region with a thickness of 1 nm or more, more preferably 2 nm or more Just use c.

[0077] In order to improve reliability, it is preferable that the insulator 106a is thick. nm or more, preferably 20 nm or more, further preferably 40 nm or more, and more preferably 6 The thickness of the insulator 106a may be set to 0 nm or more. By increasing the thickness, a channel is formed from the interface between the adjacent insulator and the insulator 106a. The distance to the semiconductor 106b can be increased, but the productivity of the semiconductor device decreases. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably The insulating layer 106a may have a region with a thickness of 80 nm or less.

[0078] Silicon in an oxide semiconductor can act as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the more preferable. and the insulator 106a, for example, in secondary ion mass spectroscopy (SIMS), 10 16 atoms / cm3 More than 1×10 19 atoms / cm 3 Below, preferably 1x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 The following is more preferably is 1 x 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 The following silicon In addition, there is a region between the semiconductor 106b and the insulator 106c, which is Put, 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below is good Preferably 1 x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 Below, More preferably, 1×10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 Below It has a region with a lower silicon concentration.

[0079] In order to reduce the hydrogen concentration in the semiconductor 106b, the insulator 106a and the insulator 106 It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c. In 1×10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 below, Preferably 1 x 10 16 atoms / cm 3 5x10 or more 19 atoms / cm 3 below, More preferably 1 × 1016 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below or less, more preferably 1 × 10 16 atoms / cm 3 5x10 or more 18 atoms / c m 3 In addition, in order to reduce the nitrogen concentration in the semiconductor 106b, Therefore, it is preferable to reduce the nitrogen concentration in the insulators 106a and 106c. The insulator 106a and the insulator 106c are 1×10 15 atoms / cm 3 Below Top 5×10 19 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 Below Top 5×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 or less, more preferably 1 × 10 15 atoms / cm 3 5x10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0080] Insulator 106a, semiconductor 106b, and insulator 106c shown in this embodiment, particularly semiconductor 106b is an oxide semiconductor having a low impurity concentration and a low density of defect states (few oxygen vacancies). and can be called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, Therefore, a channel region can be formed in the oxide semiconductor. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also known as normally-on). In addition, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic are The defect level density is low in the silicon dioxide, so the trap level density may also be low. Intrinsic or substantially highly purified intrinsic oxide semiconductors have a significantly small off-state current and a high channel density. The width W is 1×10 6 Even if the device has a channel length L of 10 μm, the source electrode and drain When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current is below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 A characteristic of A or less It is possible.

[0081] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor is provided with a channel region. The transistor in which the above-mentioned structure is formed has small fluctuations in electrical characteristics and is highly reliable. Note that charges trapped in the trap states of the oxide semiconductor remain trapped until they are lost. It takes a long time for the charge to be released and it may behave as if it were a fixed charge. A transistor whose channel region is formed in an oxide semiconductor with a high density of gate states has excellent electrical characteristics. The impurities that form trap states in an oxide semiconductor include water. Examples of the metals include silicon, nitrogen, alkali metals, and alkaline earth metals.

[0082] The hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c bonds with metal atoms. The lattice from which oxygen is released (or the part from which oxygen is released) reacts with the oxygen to form water. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. In particular, hydrogen trapped in oxygen vacancies can cause the band structure of semiconductors to change. Therefore, the oxide semiconductor containing hydrogen may have shallow donor levels. A transistor using a conductor tends to have a normally-on characteristic. a) It is preferable that the semiconductor 106b and the insulator 106c have as little hydrogen as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, S The hydrogen concentration obtained by IMS is 2×10 20 atoms / cm 3 Below, preferably 5 x10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Below Bottom, 5×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following applies.

[0083] In the insulator 106a, the semiconductor 106b, and the insulator 106c, one of the group 14 elements When some silicon or carbon is included, the insulator 106a, the semiconductor 106b, and the insulator 106 As a result, oxygen vacancies increase in the insulator 106a and the semiconductor 106c, which becomes n-type. The concentrations of silicon and carbon in the insulator 106a, the semiconductor 106b, and the insulator 106c are The concentration of silicon and carbon near the interface between the insulating layer 106b and the insulating layer 106c (obtained by SIMS) The concentration that can be measured is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 ato ms / cm 3 The following applies.

[0084] In addition, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIMS was used to The resulting concentration of alkali metal or alkaline earth metal is 1 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 The following applies: Alkali metals and When alkaline earth metals combine with oxide semiconductors, they can generate carriers, which can lead to transistors. Therefore, the insulator 106a and the semiconductor 106 b and the insulator 106c. preferable.

[0085] Furthermore, when nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, Electrons, which act as carriers, are generated, increasing the carrier density and making it easier to become n-type. A transistor using an oxide semiconductor film containing such a metal oxide tends to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by SIMS is 5×10 18 atoms / cm 3 Below It is preferable that

[0086] FIG. 1D shows an enlarged cross-sectional view of the insulator 106a and the semiconductor 106b near their centers. As shown in FIG. 1B and FIG. 1D, the conductor 108a of the semiconductor 106b and A low resistance region is formed in the region in contact with the conductor 108b (shown by the dotted line in FIGS. 1B and 1D). The low resistance region 109a and the low resistance region 109b may be formed. The low resistance region 109b is formed by the conductor 108a or the conductor 108b that is in contact with the semiconductor 106b. or the conductive material contained in the conductor 108a or the conductor 108b. Such low resistance may be formed by bonding with elements in the semiconductor 106b. The formation of the high resistance region 109a and the low resistance region 109b allows the conductor 108a or This makes it possible to reduce the contact resistance between the conductor 108b and the semiconductor 106b. The on-current of the transistor 10 can be increased.

[0087] Although not shown, the insulator 106c and the conductor 108a or conductor 108b A low resistance region may also be formed in the contact region. Similar dotted lines indicate low resistance regions.

[0088] As shown in FIG. 1D, the semiconductor 106b is a semiconductor having a conductor 108a and a conductor 108b. There is a region between the conductive layers 108a and 108b that is thinner than the region where the conductive layers 108a and 108b overlap. This is because when the conductor 108a and the conductor 108b are formed, the semiconductor 106 The upper surface of the semiconductor 106b is formed by removing a part of the upper surface of the semiconductor 106b. When the conductors to be the low-resistance regions 109a and 109b are formed, In this way, a low resistance region similar to that of semiconductor 106b may be formed. The region located between the conductors 108a and 108b on the top surface is removed to form a semiconductor This can prevent the formation of a channel in the low resistance region on the top surface of the body 106b. In the following drawings, even if an area with a thin film thickness is not shown in an enlarged view, it is assumed that the area has a similar film thickness. In some cases, thin areas may be formed.

[0089] The above-described three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Alternatively, a single-layer structure without the insulator 106a or the insulator 106c may be used. Alternatively, the semiconductor 106 may be exemplified as an insulator 106a, a semiconductor 106b, or an insulator 106c. The structure is an n-layer structure (n is an integer of 4 or more) having either an insulating material, a semiconductor material, or a conductor material. It's okay.

[0090] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0091] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned oxide semiconductor (CAAC-OS) crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0092] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0093] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0094] That is, the stable oxide semiconductor is completely amorphous. ) and cannot be called an oxide semiconductor. On the other hand, a-li oxide semiconductors cannot be called completely amorphous oxide semiconductors. The ke OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0095] <caac-os> First, let me explain about CAAC-OS.

[0096] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0097] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 2(A), a peak appears at a diffraction angle (2θ) of approximately 31°. is attributed to the (009) plane of the InGaZnO4 crystal, so in CAAC-OS The crystal has a c-axis orientation, and the c-axis is a surface on which a CAAC-OS film is to be formed (also called a surface on which a CAAC-OS film is to be formed). ) or in a direction almost perpendicular to the top surface. In addition to the peaks around 2θ, a peak may also appear around 36°. The peak is due to the crystal structure classified into the space group Fd-3m. It is preferable that the OS does not exhibit such a peak.

[0098] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). Even if the peak is increased, no clear peak appears, as shown in Figure 2(B). When φ scanning is performed with 2θ fixed at around 56° for O4, as shown in Figure 2(C), Six peaks attributable to the crystal plane equivalent to the (110) plane are observed. Structural analysis using NMR showed that the orientation of the a-axis and b-axis of CAAC-OS was irregular. You can confirm it.

[0099] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (limiting) like that shown in Figure 2(D) is generated. This diffraction pattern may include InG The electron diffraction pattern includes spots due to the (009) plane of the ZnO4 crystal. This also allows the pellets contained in the CAAC-OS to have a c-axis orientation, and the c-axis extends to the surface on which the film is formed. On the other hand, for the same sample, the direction perpendicular to the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident directly onto the sample is shown in Figure 2(E). Figure 2(E) shows a ring-shaped diffraction pattern. Electron diffraction using a 300 nm electron beam also revealed that the pellets contained in CAAC-OS It can be seen that the a-axis and b-axis have no orientation. This is thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Figure 2(E) is thought to be due to the (110) plane. .

[0100] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0101] Figure 3(A) shows a high-resolution TE image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The image shown is an M image. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope, JEM-ARM200F, manufactured by JEOL Ltd. It can be observed.

[0102] From Figure 3(A), pellets, which are regions where metal atoms are arranged in layers, can be confirmed. It was found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are also called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC- It reflects the unevenness of the surface on which the OS is formed or the top surface of the CAAC-OS. is parallel to

[0103] In addition, Figures 3(B) and 3(C) show the CAAC-O observed from a direction approximately perpendicular to the sample surface. Figure 3(D) and Figure 3(E) show Cs-corrected high-resolution TEM images of the S plane. These are images obtained by processing Figures 3(B) and 3(C). The image processing method is explained below. First, let us consider the case where the image in Figure 3(B) is subjected to a Fast Fourier Transform (FFT). Then, the FFT image is obtained by performing the Transform process. 2.8nm based on the origin -1 to 5.0 nm -1 Masking to leave the range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). The image is processed by Fast Fourier Transform (FTT) and the processed image is taken. The image obtained in this way is called an FFT filtered image. is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image, and shows the lattice arrangement. do.

[0104] In Figure 3(D), the area where the lattice arrangement is disrupted is indicated by a dashed line. The area indicated by the broken line is the connection between the pellets. The broken line indicates the hexagonal shape, which indicates that the pellets are hexagonal. The shape of the hole is not necessarily a regular hexagon, but is often a non-regular hexagon.

[0105] In Figure 3(E), a dotted line separates a region with a uniform lattice arrangement from another region with a uniform lattice arrangement. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points around a lattice point, a distorted hexagon, pentagon, or / and heptagon can be formed. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction. The substitution of metal elements causes changes in the bond distance between atoms, resulting in distortion. This is thought to be because it can tolerate the

[0106] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0107] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects ( It can also be said to be an oxide semiconductor with few oxygen vacancies.

[0108] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0109] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0110] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8 × 10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0111] <nc-os> Next, we will explain nc-OS.

[0112] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0113] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region in parallel to the surface to be formed, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in A) is observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron beam diffraction pattern is shown in Figure 4(B). Therefore, the nc-OS was obtained by electron beam irradiation with a probe diameter of 50 nm. However, when an electron beam with a probe diameter of 1 nm is incident, the order is not confirmed. This confirms order.

[0114] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 4(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, it is possible that the nc-OS has an ordered structure in the range of thickness less than 10 nm. It can be seen that the crystals are oriented in various directions. However, there are also regions where no regular electron diffraction pattern is observed.

[0115] Figure 4(D) shows a Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The high-resolution TEM image shows the nc-OS, which is clearly visible in the areas indicated by the auxiliary lines in the high-resolution TEM image. There are two areas where crystals can be seen, and there are also areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm or more and 10 nm or less. In particular, the size is often between 1 nm and 3 nm. Microcrystalline oxide semiconductors are oxide semiconductors with a size of more than 100 nm or less. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries may not be clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of the nc-OS may be referred to as a pellet below.

[0116] In this way, the nc-OS can be used in a microscopic area (e.g., an area of ​​1 nm or more and 10 nm or less, especially The atomic arrangement is periodic in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0117] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0118] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0119] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0120] Figure 5 shows a high-resolution cross-sectional TEM image of the a-like OS. Figure 5(B) shows a high-resolution cross-sectional TEM image of the a-like OS at the start of irradiation. .3×10 8 e - / nm 2 electrons (e - ) High resolution of a-like OS after irradiation Figure 5(A) and Figure 5(B) show that the a-like OS is From the start, striped bright regions extending in the vertical direction are observed. It can be seen that the shape changes after electron irradiation. The bright areas are assumed to be voids or low-density areas. It is measured.

[0121] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0122] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0123] First, high-resolution cross-sectional TEM images of each sample are acquired. Each of these has a crystalline portion.

[0124] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that it has a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is estimated to be 0.29 nm from crystal structure analysis. Below, the area where the lattice spacing is between 0.28 nm and 0.30 nm is InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0125] Figure 6 shows an example of an investigation into the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. S is the crystal size that increases according to the cumulative electron irradiation dose involved in obtaining a TEM image. As can be seen from Figure 6, the size was about 1.2 nm at the beginning of the TEM observation. The crystal part (also called the initial nucleus) has electrons (e - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 1.9 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of Regardless of the cumulative irradiation dose, the sizes of the crystalline parts of nc-OS and CAAC-OS were It can be seen that the thicknesses are approximately 1.3 nm and 1.8 nm. The observation of M was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were: The voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 s), the diameter of the irradiated area The wavelength was set to 230 nm.

[0126] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. That is, compared with nc-OS and CAAC-OS, It is clear that this is an unstable structure.

[0127] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0128] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0129] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0130] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0131] <Substrate, insulator, conductor> Each of the non-semiconductor components of transistor 10 will be described in detail below.

[0132] The substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the solid substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates and resin substrates. Examples of suitable substrates include silicon, germanium, and other single semiconductor substrates, silicon carbide, Silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Furthermore, there are semiconductor substrates having an insulating region inside the semiconductor substrate. Substrates, such as SOI (Silicon On Insulator) substrates, are used. The electric substrate may be a graphite substrate, a metal substrate, an alloy substrate, or a conductive resin substrate. , a substrate having a metal nitride, a substrate having a metal oxide, etc. Furthermore, an insulator A substrate in which a conductor or a semiconductor is provided, a semiconductor substrate in which a conductor or an insulator is provided, and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. These include elements, resistor elements, switch elements, light-emitting elements, and memory elements.

[0133] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication is used as the substrate 100. As a method for providing a transistor on a flexible substrate, a method for providing a transistor on a non-flexible substrate may be used. After the transistors are fabricated on the substrate, the transistors are peeled off and the substrate 10, which is a flexible substrate, is removed. There is also a method to transpose it to 0. In that case, a release layer is placed between the non-flexible substrate and the transistor. The substrate 100 may be a sheet, film or foil having woven fibers. The substrate 100 may be flexible. It may have the property of returning to its original shape when bending or pulling is stopped. The thickness of the substrate 100 may be, for example, 5 μm to 700 μm. Preferably, the thickness is 10 μm or more and 500 μm or less, and more preferably, the thickness is 15 μm or more and 300 μm or less. The thickness of the substrate 100 is set to be equal to or less than 1 m. By making the substrate 100 thinner, the weight of the semiconductor device can be reduced. By making the substrate 100 thin, it is possible to make it stretchable or foldable even when glass or the like is used. It may have the property of returning to its original shape when bending or pulling is stopped. As a result, it is possible to reduce the impact that is applied to the semiconductor device on the substrate 100. Therefore, a robust semiconductor device can be provided.

[0134] The substrate 100, which is a flexible substrate, may be made of, for example, metal, alloy, resin, glass, or The substrate 100, which is a flexible substrate, has a linear expansion coefficient of 1.5. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester, poly Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, making it suitable for flexible substrates. 100 is preferable.

[0135] The insulator 101 is an insulator that has the function of blocking hydrogen or water. 6a, the semiconductor 106b, and the hydrogen and water in the insulator provided near the insulator 106c. 106a, semiconductor 106b, and insulator 106c. This may result in a decrease in the reliability of the transistor 10. When using a substrate with a silicon-based semiconductor element such as a switch element as 0, Hydrogen is used to terminate dangling bonds in the semiconductor element, and the hydrogen There is a risk of hydrogen or water diffusing up to 10. The insulator 101 prevents hydrogen or water from diffusing from the lower layer of the transistor 10. This can suppress the breakdown voltage and improve the reliability of the transistor 10. It is preferable that the insulating layer 104 is less permeable to hydrogen or water than the insulating layer 105 or the insulating layer 104 .

[0136] In addition, the insulator 101 preferably has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, e.g. Oxygen can be effectively supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c. do.

[0137] The insulator 101 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride or the like can be used. By using these as the insulator 101, It can function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. The insulator 101 may be made of, for example, silicon nitride or silicon nitride oxide. By using these as the insulator 101, the diffusion of hydrogen and water can be blocked. It can function as an insulating film that exhibits a blocking effect.

[0138] At least a portion of the conductor 102 is sandwiched between the conductors 108a and 108b. The conductor 102 preferably overlaps the semiconductor 106b. By providing such a conductor 102, the transistor 1 The threshold voltage of the insulator 103 can be controlled. By controlling the threshold voltage, the gate of the transistor 10 can be When the voltage applied to the conductor 114 is low, for example, when the applied voltage is 0 V or less, This prevents the transistor 10 from being turned on. This makes it easier to shift the electrical characteristics of the transistor in the direction of normally-off.

[0139] The conductor 102 may be tungsten, silicon, carbon, germanium, tin, or aluminum. and one or more elements selected from the group consisting of tungsten, tungsten, nickel, and the like. In particular, a conductor containing tungsten and silicon is preferable. The silicon concentration obtained by BS is between 5 atomic % and 70 atomic %. It is preferable that the silicon concentration is 10 atomic % or more and 60 atomic % or more. It is more preferable that the conductive material 102 has a region below the surface. The insulating film may be formed as a single layer or a multilayer.

[0140] The conductor 102 has a region containing silicon and oxygen on the surface of the conductor 102, The thickness of the region is preferably 0.2 nm or more and 20 nm or less. In this case, the region can function as an insulator. In addition, this region functions as a barrier layer, preventing the entire conductor from being oxidized. This can suppress the risk of

[0141] The conductor 102 may be formed by sputtering. MCVD (Metal Chemical Vapor Deposition) method The film can be formed in this manner.

[0142] The insulator 105 is provided so as to cover the conductor 102. The insulator 105 is an insulator An insulator similar to 104 or insulator 112 can be used.

[0143] The insulator 103 is provided to cover the insulator 105. The insulator 103 blocks oxygen. By providing such an insulator 103, the insulator 1 This prevents the conductor 102 from extracting oxygen from the insulator 104. Oxygen can be effectively supplied from the semiconductor 106b to the insulator 106a, the semiconductor 106b, and the insulator 106c. This can be done.

[0144] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sm, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium The oxide or nitride may contain nium or thallium. Hafnium oxide or aluminum oxide is used.

[0145] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 can behave like fixed negative charges. be.

[0146] The insulator 104 preferably contains a small amount of water or hydrogen. The insulator 104 is preferably an insulator having excess oxygen. For example, the insulator 104 may be , for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tungsten, neodymium, hafnium or tantalum are used in single or multilayer configurations. For example, the insulator 104 may be aluminum oxide, magnesium oxide, or Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide Hafnium or tantalum oxide may be used. Preferably, silicon oxide or oxynitride is used. Silicon dioxide is used.

[0147] The amount of water or hydrogen contained in the insulator 104 is preferably small. 104 is a thermal desorption spectrometer (TDS). 100℃ to 700℃ or 100℃ to 500℃ In the surface temperature range, the number of water molecules desorbed is 1.0 × 10 13 molecules / cm 2 Over 1.4 x 10 16 molecules / cm 2 Below, 1.0 x 10 13 molecules / cm 2 Over 4.0 x 10 15 molecule / cm 2 Below, 1.0 x 10 13 molecules / cm 2 Over 2.0 x 10 15 molecules / cm 2 It is preferable that the temperature is 100°C or higher and 700°C or lower by TDS. In the surface temperature range of ℃ to 500℃, the amount of hydrogen molecules desorbed is 1.0×10 13 molecule / c m 2 Over 1.2 x 10 15 molecules / cm 2 Below, 1.0 x 10 13 molecules / cm 2 End 9.0×10 14 molecules / cm 2 It is preferable that the following is true: The method for measuring the amount of release will be described in detail below.

[0148] Impurities such as water and hydrogen are introduced into the insulator 106a, the semiconductor 106b and the insulator 106c, particularly Defect levels are formed in the semiconductor 106b, which is a factor that changes the electrical characteristics of the transistor. Therefore, the insulating layer 106a is formed under the semiconductor 106b and the insulating layer 106c. By reducing the amount of water or hydrogen in the insulator 104, the water or hydrogen can be removed from the insulator 104. This can reduce the formation of defect levels due to the supply of atoms and the like to the semiconductor 106b. By using an oxide semiconductor with a reduced defect state density, stable electrical characteristics can be achieved. A transistor having the above structure can be provided.

[0149] The insulator 104 is formed by plasma enhanced CVD (PECVD), which allows high quality films to be formed at relatively low temperatures. It is preferable to form the film using the plasma enhanced CVD method. For example, when forming a silicon oxide film by the PECVD method, silicon is used as the raw material gas. Hydrides are often used, and hydrogen, water, etc. are introduced into the insulator 104 during film formation. Therefore, in the formation of the insulator 104 in this embodiment, a halo is used as a source gas. It is preferable to use silicon halide. For example, SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 ( silicon trichloride), SiH2Cl2 (dichlorosilane) or SiBr4 (silicon tetrabromide) It is particularly preferable to use SiF4 (silicon tetrafluoride). stomach.

[0150] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water contents in the insulator 104 are reduced compared to when only the halogen-containing gas is used as the raw material gas. The film formation rate can be improved compared to when only silicon fluoride is used as the source gas. The insulator 104 can be formed using SiF4 and SiH4 as raw material gases. The ratio of the flow rates of 4 and SiH4 is determined by taking into consideration the content of water and hydrogen in the insulator 104 and the film formation rate. It may be set appropriately.

[0151] The insulator 104 is preferably an insulator having excess oxygen. By providing 104, the insulator 104 is connected to the insulator 106a, the semiconductor 106b, and the insulator Oxygen can be supplied to the insulator 106c, which is an oxide semiconductor. Oxygen vacancies that cause defects in the insulating layer 106a, the semiconductor 106b, and the insulator 106c can be reduced. This allows the insulator 106a, the semiconductor 106b, and the insulator 106c to have a low defect level density. Therefore, an oxide semiconductor having stable characteristics can be obtained.

[0152] In this specification and the like, excess oxygen refers to, for example, oxygen contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to a film containing the excess oxygen, for example, by heating. Excess oxygen is oxygen released from the membrane or layer. The movement of excess oxygen can occur between atoms in the film or layer, or between oxygen atoms that make up the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0153] The insulator 104 having excess oxygen is heated to 100°C or more and 700°C or less in TDS. In the surface temperature range of ℃ to 500℃, the amount of oxygen molecules desorbed is 1.0×10 14 molecule / c m 2 Over 1.0 x 10 16 molecules / cm 2 or less, more preferably 1.0 × 10 15 molecule / cm 2 Over 5.0 x 10 15 molecules / cm 2 The following is the result.

[0154] The method for measuring the amount of released molecules using TDS is explained below using the amount of released oxygen as an example. do.

[0155] The total amount of released gas when the measurement sample is analyzed by TDS is calculated by the integral of the ion intensity of the released gas. The total amount of gas released can then be calculated by comparison with a standard sample. .

[0156] For example, the TDS results of a silicon substrate containing a specified density of hydrogen as a standard sample, and the measurement From the TDS results of the sample, the amount of oxygen molecules released from the measured sample (N O2 ) is calculated using the formula below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of these are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but the possible It is not considered here because it has low affinity. The abundance ratio of elementary atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is is not taken into consideration because it is an extremely small amount.

[0157] N O2 =N H2 / S H2 ×S O2 ×α

[0158] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is analyzed by TDS. , N H2 / S H2 Let's say S O2 is the ion intensity when the measurement sample is analyzed by TDS. α is the coefficient that affects the ionic strength in TDS. For details, please refer to Japanese Patent Application Laid-Open No. 6-275697. The standard sample was measured using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Corporation. Measurements are performed using a silicon substrate containing a certain amount of hydrogen atoms as the surface active material.

[0159] In addition, some of the oxygen is detected as oxygen atoms in TDS. The ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate, by evaluating the amount of released oxygen molecules, the amount of released oxygen atoms can be calculated. can also be estimated.

[0160] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0161] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES) R: Electron Spin Resonance (G) shows a g value near 2.01. It may also have symmetrical signals.

[0162] The insulator 104 may also have a function of preventing diffusion of impurities from the substrate 100 .

[0163] As mentioned above, it is preferable that the upper or lower surface of the semiconductor 106b is highly flat. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). To improve the flatness, a flattening process is performed using methods such as CAL Polishing. Good too.

[0164] Conductor 108a and conductor 108b are the source electrode or The drain electrode can function as either a

[0165] The conductor 108a and the conductor 108b may be formed in a manner similar to that of the conductor 102.

[0166] In addition, the conductors 108a and 108b are arranged such that they are not overlapped with the conductor 114. It is preferable that at least a portion of the insulating layer 106 overlaps with the insulating layer 112 via the insulating layer 106c. For example, as shown in FIG. 1B, most of the upper surfaces of the conductors 108a and 108b are insulated. By using such a configuration, the conductor 108 The upper surfaces of the insulator 112 and the conductor 108b can be prevented from extracting oxygen from the insulator 112. As a result, the insulator 112 is transferred to the insulator 106a, the semiconductor 106b, and the insulator 106c. It can effectively supply oxygen to 6c.

[0167] The insulator 112 can function as a gate insulating film for the transistor 10. The insulator 112 may be an insulator having excess oxygen, similar to the insulator 104. By providing the insulator 112, the insulator 106a, the semiconductor 106b, and Oxygen can be supplied to the insulator 106 .

[0168] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 112 may be made of aluminum oxide, aluminum oxide, or aluminum alloy. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0169] Conductor 114 can function as the gate electrode of transistor 10. The conductive material 4 may be formed in the same manner as the conductive material 102 .

[0170] Here, as shown in FIG. 1C, the electric field generated by the conductor 102 and the conductor 114 The semiconductor 106b can be electrically surrounded by the electric field generated by the conductor. The structure of a transistor that electrically surrounds a semiconductor is called a surrounded channel. This is called a nel (s-channel) structure. In the s-channel structure, the transistor has a channel formed on the top surface (bottom and side). A large current can flow between the source and drain of the transistor, and the current when it is conducting (on-state current) can be increased.

[0171] In addition, the s-channel structure is suitable for miniaturized transistors because it can achieve a high on-state current. Since the transistor can be miniaturized, The semiconductor device can be a highly integrated and highly dense semiconductor device. For example, the transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. The transistor has a channel width of 20 nm or less, preferably 20 nm or less. Preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less It has an area of.

[0172] The insulator 116 can function as a protective insulating film for the transistor 10. The thickness of the insulator 116 can be, for example, 1 nm or more, or 20 nm or more. In addition, at least a portion of the insulator 116 is in contact with the upper surface of the insulator 104 or the insulator 112. It is preferable that the film is formed by the above method.

[0173] The insulator 116 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium Insulators containing sulphur, lanthanum, neodymium, hafnium or tantalum, either in a single layer or The insulator 116 may be formed of oxygen, hydrogen, water, alkali metals, alkaline earth metals, or the like. It is preferable that the insulating material has an effect of blocking metals, etc. Examples of such insulating materials include: A nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride and nitride oxide. Silicon, aluminum nitride, aluminum oxide nitride, etc. In place of nitride insulating film, Instead, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of oxide insulating films include aluminum oxide, aluminum oxynitride, gallium oxide, and oxynitride. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride There are nium etc.

[0174] Here, the insulator 116 is preferably formed by sputtering. It is more preferable to carry out the sputtering method in an atmosphere containing By forming the insulating film 116, the insulating film 104 or the insulating film 112 is formed. the surface (after the insulator 116 is formed, the interface between the insulator 104 or the insulator 112 and the insulator 116) Oxygen is added to the vicinity.

[0175] The insulator 116 is an insulator that is less permeable to oxygen than the insulators 104 and 112. It is preferable that the insulating material 116 has an effect of blocking oxygen. As a result, the insulators 104 and 112 are replaced by the insulators 106a, the semiconductors 106b, and When oxygen is supplied to the insulator 106c, the oxygen is released to the outside above the insulator 116. This can prevent the problem from occurring.

[0176] Aluminum oxide is permeable to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 116 because it has a high blocking effect of preventing the passage of light.

[0177] In addition, the insulator 116 can be used as the insulator 106a or the insulator 106c described above. These oxides can be relatively easily deposited by sputtering. Since the insulators 104 and 112 can be easily formed, oxygen can be effectively added to the insulators 104 and 112. As such an insulator 116, it is preferable to use an oxide insulator containing In. For example, In-Al oxide, In-Ga oxide, and In-Ga-Zn oxide are used. Oxide insulators containing In are prone to generate particles when they are formed by sputtering. Because they are few in number, they are suitable for use as insulator 116 .

[0178] The insulator 118 functions as an interlayer insulating film. It may be formed in the same manner as above.

[0179] Conductor 120a and conductor 120b are the source electrode and drain electrode of transistor 10. The conductors 120a and 120b function as wiring electrically connected to the electrodes. For example, a conductor that can be used as the conductor 108a and the conductor 108b may be used. This allows the wiring to function as a wiring having heat resistance and oxidation resistance.

[0180] By adopting the above-mentioned configuration, a transistor using a conductor having heat resistance and oxidation resistance can be obtained. It is possible to provide a transistor having stable electrical characteristics. Alternatively, a transistor with a small leakage current when not conducting can be provided. Alternatively, a transistor having high frequency characteristics can be provided. It is possible to provide a transistor having normally-off electrical characteristics. It is possible to provide a transistor with a small threshold swing value. It is possible to provide a transistor with high performance.

[0181] <Transistor Modification> Modifications of the transistor 10 will be described below with reference to FIGS. 7 to 12. 1B to 12 show the structure of the transistor in the channel length direction, similar to FIG. 1B and FIG. 1C. The diagrams are a cross-sectional view and a cross-sectional view in the channel width direction of the transistor.

[0182] The transistor 12 shown in FIGS. 7A and 7B has a silicon layer on the surface of the conductor 108a. The conductive material 108b has a region 108c containing silicon and oxygen. The transistor 10 differs from the transistor 10 in that it has a region 108d containing oxygen. FIG. 7(C) shows an enlarged view of the area surrounded by the dashed line in FIG. 7(A).

[0183] The regions 108c and 108d are formed by oxygen deposition on the surfaces of the conductors 108a and 108b. The silicon in the conductors 108a and 108b is segregated to the surface and reacts with oxygen. The regions 108c and 108d are formed by bonding with an insulator. Therefore, as shown in FIG. 7(C), for example, A region 108c that functions as an insulator is provided between the body 114 and the conductor 108a. This reduces the parasitic capacitance between the conductor 114 and the conductor 108a. In addition, the region 108d is provided, so that the region between the conductor 114 and the conductor 108b The parasitic capacitance is also reduced. By reducing the parasitic capacitance, the electrical characteristics of the transistor 12 are improved. can be improved.

[0184] Furthermore, by providing the regions 108c and 108d that function as insulators, The leakage current between the conductor 114 and the conductor 108a or the conductor 108b is also reduced. It can be done.

[0185] Also, if the thickness of the region 108c and the region 108d is too thin, they will not function sufficiently as an insulator. If it is too thick, the area of ​​the conductors 108a and 108b will be small. As a result, the electrical resistance of the conductors 108a and 108b increases. Therefore, the thickness of the region 108c and the region 108d is preferably 0.2 nm or more and 20 nm or less. It's nice.

[0186] Regions 108c and 108d may be formed naturally by simply exposing them to the atmosphere. It can also be formed intentionally. For example, For example, heat treatment may be performed in an oxidizing atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. The plasma treatment may be performed using a high density plasma treatment using a power supply with a frequency of, for example, 2.45 GHz. It is preferable to use Zuma treatment. At this time, oxygen is also added to the semiconductor 106b. The oxygen deficiency in the semiconductor 106b may be compensated for by the above.

[0187] The transistor 16 shown in FIGS. 8A and 8B includes a conductor 102, an insulator 101, It differs from the transistor 10 in that the insulator 105 is not formed.

[0188] The transistor 18 shown in FIGS. 8C and 8D has a conductor 114 and an insulator 112. , openings formed in the insulator 106c, the insulator 104, the insulator 103, the insulator 105, etc. The transistor 10 differs from the transistor 10 in that the transistor 10 is connected to the conductor 102 via a

[0189] The transistor 20 shown in FIGS. 9A and 9B has an insulator 107 on an insulator 101. The conductor 102 is embedded in the opening provided in the insulator 107. The insulator 107 is different from the transistor 10 in that it is made of insulator 105. In addition, the insulator 107 and the conductor 10 The upper surface of the substrate 2 is preferably subjected to a planarization process such as a CMP method to improve flatness. As a result, even if the conductor 102 functioning as a back gate is provided, the semiconductor 106b The flatness of the surface on which the transistor is formed is not compromised, improving carrier mobility. The on-current of the conductor 102 can be increased. By eliminating the step on the surface of 104, the drain of the conductor 108a or conductor 108b can be The step portion of the insulator 104 is formed between the conductor 102 and the insulator 104. This reduces the leakage current of the transistor 20. It is possible.

[0190] The transistor 22 shown in FIGS. 10A and 10B includes a conductor 108a, a conductor 108b, and a An insulator 117 is provided on the semiconductor 106 and the insulator 104. An opening is provided that reaches b. The opening is filled with the insulator 106c, the insulator 112, and the conductive material. It differs from transistor 10 in that the body 114 is embedded. Moreover, the opening separates the conductor 108a from the conductor 108b. The transistor 22 has a conductor 114 that can function as a gate electrode. The openings in the edge 117 are filled in a self-aligned manner. Therefore, TGSA s-channel FET (Trench Gate S It can also be called a FET (elf Align s-channel FET).

[0191] Here, the insulator 117 may be formed using an insulator that can be used for the insulator 104. The upper surface of the insulator 117 may be flattened by a CMP method or the like.

[0192] In the transistor 22, an insulator 117 is provided between the conductor 108a and the conductor 114, and an insulator 10 6c and an insulator 112 are provided between the conductor 108b and the conductor 114. The conductor 117, the insulator 106c, and the insulator 112 are provided. The distance between the upper surface of the conductor 108b and the lower surface of the conductor 114, and the distance between the upper surface of the conductor 108b and the lower surface of the conductor 114 The distance between the surfaces can be increased by the thickness of the insulator 117. In order to reduce the parasitic capacitance generated in the area where the conductor 114 overlaps with the conductor 108a and the conductor 108b, By reducing the parasitic capacitance, the switching speed of the transistor can be improved. Therefore, a transistor having high frequency characteristics can be provided. do.

[0193] The transistor 24 shown in FIGS. 10C and 10D has an insulator 117, an insulator 10 6c, the upper surfaces of the insulator 112 and the conductor 114 are generally flush with each other and are provided flat. In this respect, the transistor 22 is different from the transistor 22. The top surfaces of the insulator 106c, the insulator 112, and the conductor 114 are planarized by a CMP method or the like. Just do that.

[0194] By adopting such a structure, the conductor 114, the conductor 108a, and the conductor 108b Since the overlapping region is almost eliminated, the gate-source and The parasitic capacitance generated between the gate and drain can be reduced. This allows the transistor switching speed to be increased, making it possible to It is possible to provide a transistor having several characteristics.

[0195] The transistor 29 shown in FIGS. 11A and 11B has an insulator 107 and an insulator 10 1, and the conductor 102 is embedded in the opening in the insulator 107. The transistor 24 is different from the transistor 24 in that the insulator 106c is The transistor 29 is also different from the transistor 24 in that the conductor 106b is covered. The insulator 106c is not provided on the side of the opening of the insulator 117. The length of the conductor 114 in the channel length direction at the mouth is set to be longer than that of the transistor 24, etc. It is possible.

[0196] In the transistor 29, the surface of the conductor 108a is formed with silicon and oxygen. The conductor 108b has a region 108c, and the conductor 108b has a region 108c having silicon and oxygen on its surface. The transistor 24 also differs from the transistor 24 in that it has the region 108c and the region 108d. It may be formed in the same manner as the transistor 12 shown in FIG.

[0197] However, the region 108c and the region 108d are the transistors 12 and 29. For example, the case where another transistor is connected to the region 108c and the region 108d is not limited to this. It doesn't matter if you have it.

[0198] The transistor 26 shown in FIGS. 12A and 12B includes a conductor 108a and a conductor The side ends of the conductor 114 and the insulator 112 are It differs from transistor 10 in that it is provided approximately in the same place.

[0199] In the transistor 26, the low resistance region 109a and the low resistance region 109b are formed by insulating material 1. 16. In addition, the low resistance region 109a and Various elements may be added to the low resistance region 109b to reduce the electrical resistance. stomach.

[0200] The elements added to the low resistance region 109a and the low resistance region 109b include, for example, boron. silicon, phosphorus, nitrogen, argon, helium, magnesium, aluminum, silicon, titanium , vanadium, chromium, nickel, cobalt, germanium, yttrium, zirconium Niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium For example, the low resistance region 109a and the low The above elements are present in the resistance region 109b at 1×10 14 / cm 2 Over 2×10 16 / cm 2 Included below It is also preferable that the low resistance region 109a and the low resistance region 109b in the insulator 106c are The low resistance region 109b is the low resistance region 109a of the insulator 106c and the low resistance region 109b of the insulator 106c. The concentration of the above elements is higher than that of the non-insulating region (for example, the region where the insulator 106c overlaps with the conductor 114). High degree.

[0201] In the transistor 26, the semiconductor 106b is connected to the insulator 106a and the insulator 106c. Therefore, the side end portion of the semiconductor 106b, in particular, the chip The vicinity of the side end in the channel width direction is provided in contact with the insulators 106a and 106c. As a result, the insulator 106a or the insulating material 106b is in contact with the semiconductor 106b in the vicinity of the side edge of the semiconductor 106b. A continuous junction is formed between the layer 106c and the substrate 106, and the defect level density is reduced. By providing the low-resistance region 109a and the low-resistance region 109b, the on-current can be easily passed. The side edge of the semiconductor 106b in the channel width direction does not become a parasitic channel, and stable electrical characteristics are obtained. In addition, in a configuration without the insulator 106a and / or the insulator 106c, It may also be possible to use the following.

[0202] The transistor 28 shown in FIGS. 12C and 12D is made up of an insulator 112 and a conductor The transistor 10 differs from the transistor 10 in that the transistor 114 is not provided. The transistor 28 is a so-called bottom gate type transistor.

[0203] In this embodiment, a gate electrode, a source electrode, a drain electrode, etc. of a transistor are tungsten and silicon, carbon, germanium, tin, aluminum or nickel and a conductor having a region having one or more elements selected from the group consisting of However, the present invention is not limited to this. For example, MIM (Metal-Insulator-Metal l) Tungsten and silicon, carbon, germanium, and one or more elements selected from tin, aluminum, or nickel. A conductor may be used. In this case, a region having silicon and oxygen on the surface of the conductor may be formed. and a structure in which the region capable of functioning as an insulator is used as a dielectric of a capacitive element. It may also be possible to use the following.

[0204] This embodiment provides a transistor using a conductor having heat resistance and oxidation resistance. It is possible.

[0205] The structures and methods described in this embodiment may be combined as appropriate with structures and methods described in other embodiments. It can be used in combination.

[0206] (Embodiment 2) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 19 will be used to explain.

[0207] <Transistor manufacturing method 1> A method for manufacturing the transistor 10 will be described below with reference to FIGS.

[0208] First, a substrate 100 is prepared. The substrate 100 may be any of the above-described substrates. good.

[0209] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0210] The insulator 101 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition method, Molecular Beam Epitaxy (MBE) Laser Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) Laser Deposition) method, Atomic Layer Deposition (ALD) method This can be done using a method such as the r deposition method.

[0211] Next, a film of a conductor that will become the conductor 102 is formed. The conductive film can be formed by sputtering, CVD, MBE, etc. The method can be carried out by using a PLD method, an ALD method, or the like.

[0212] Next, a resist or the like is formed on the conductor, and the conductor 102 is processed using the resist or the like. (See FIG. 13(A) and FIG. 13(B)). Note that the resist is simply formed. This also includes the case where an anti-reflection layer is formed under the resist.

[0213] The resist is removed after the object is processed by etching or other methods. In this case, plasma treatment and / or wet etching is used. Plasma ashing is suitable for this purpose. If the removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% to 1% by volume The remaining resist may be removed by using water or the like.

[0214] Next, the insulator 105 is formed. The insulators described above may be used as the insulator 105. The insulating layer 105 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced. For example, the substrate may be heated during film formation. When a semiconductor device layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) is used. It may be heated to a temperature range of about 100°C or less.

[0215] In addition, by forming a film by the PECVD method using the same method as the insulator 104 described later, The water or hydrogen contained in the insulator 105 may be reduced.

[0216] Next, the insulator 103 is formed. The insulators described above may be used as the insulator 103. The insulating film 103 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 103 can be reduced. For example, the substrate may be heated during film formation. When a semiconductor device layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) is used. It may be heated to a temperature range of about 100°C or less.

[0217] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0218] The PECVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charge from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of the TCVD method, which does not use plasma, such plasma damage does not occur. Therefore, the yield of semiconductor devices can be increased. Since no plasma damage occurs, films with few defects can be obtained.

[0219] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0220] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. This is suitable for coating the surface of a high opening. However, the ALD method has a relatively slow film formation rate, so It may be preferable to use it in combination with other film formation methods such as high-speed CVD. .

[0221] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0222] In conventional film-forming equipment using the CVD method, one or more source gases for the reaction are used for film formation. Several species are supplied to the chamber simultaneously. The reactant gas is a gas that acts as a reactant (also called a reactant). The gases are introduced alternately into the chamber, and film formation is carried out by repeating the introduction of these gases. To switch the input gas, for example, use the respective switching valves (also called high-speed valves). It can be switched around.

[0223] For example, the film is formed in the following procedure: First, a precursor is introduced into a chamber, and then the substrate is The precursor is adsorbed onto the surface (first step). Here, the precursor is adsorbed onto the substrate surface. By doing so, a self-limiting mechanism of the surface chemical reaction takes effect, and the precursor layer on the substrate is formed. Furthermore, the precursor does not adsorb. The self-limiting mechanism of the surface chemical reaction works. The optimum range of substrate temperature is also called the ALD window. It is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the laser. or nitrogen) into the chamber, and excess precursors and reaction products are removed from the chamber. In addition, instead of introducing an inert gas, the gas is evacuated. Therefore, excess precursors and reaction products may be discharged from the chamber. An actant (e.g., an oxidizing agent (H2O, O3, etc.)) is introduced into the chamber and absorbed onto the substrate surface. The film reacts with the precursor adsorbed on the substrate, and part of the precursor is removed while the constituent molecules of the film are adsorbed on the substrate. (3rd step) Next, the excess is removed by introducing an inert gas or by evacuating. The reactants and reaction products are discharged from the chamber (fourth step).

[0224] The introduction of reactant in the third step and the introduction of inert gas in the fourth step The introduction may be repeated multiple times. That is, after the first and second steps, the third step may be performed. Step, fourth step, third step, fourth step... and third and fourth steps The loop may be repeated.

[0225] For example, in the third step, O3 is introduced as an oxidant, and in the fourth step, N2 is purged. This process may be repeated multiple times.

[0226] In addition, when repeating the third and fourth steps, the same type of reactant is not necessarily used. There is no need to repeat the introduction. For example, if H2O is used as the oxidizing agent in the first third step, In the third step from the second time onwards, O3 may be used as the oxidizing agent.

[0227] In this way, the introduction of oxidizing agent and inert gas (or vacuum exhaust) into the chamber is By repeating this process multiple times in a short time, excess hydrogen atoms and other impurities can be removed from the precursor adsorbed on the substrate surface. The oxidizer can be removed more reliably and expelled from the chamber. By increasing the number of types to two, excess hydrogen atoms and other In this way, hydrogen atoms are not incorporated into the film during film formation. By doing so, it is possible to reduce the amount of water, hydrogen, etc. contained in the formed insulator 103. This can be done.

[0228] In this way, a first monolayer can be formed on the substrate surface, and the first to fourth steps By repeating the above steps, a second monolayer can be laminated on top of the first monolayer. The fourth step is repeated multiple times while controlling the gas introduction until the film reaches the desired thickness. This allows the formation of a thin film with excellent step coverage. This allows precise film thickness control, making it possible to fabricate minute transistors. It is suitable for manufacturing.

[0229] The ALD method is a film formation method in which precursors are reacted using thermal energy. In the reaction of the reactant, the reactant is converted into a radical state using plasma. The ALD method in which the process is performed using a plasma is sometimes called the plasma ALD method. The ALD method in which the reaction between the catalyst and the reactant is carried out using thermal energy is called the thermal ALD method. There is.

[0230] The ALD method can deposit extremely thin films with uniform thickness. The surface coverage is also high.

[0231] In addition, by forming the film using the plasma ALD method, the film can be formed at an even lower temperature than with the thermal ALD method. The plasma ALD method can be used at temperatures below 100 degrees without reducing the film formation rate. In addition, plasma ALD can be used with not only oxidizing agents but also nitrogen gas, etc. Many reactants can be used, including not only oxides but also nitrides, fluorides, Many types of films, including metal films, can be deposited.

[0232] In addition, when performing plasma ALD, ICP (Inductively Coupled Plasma) Plasma can also be generated away from the substrate, such as in the case of a laser-assisted plasma. By generating plasma in this way, plasma damage can be suppressed. Cut.

[0233] Here, as an example of an apparatus capable of forming a film using the ALD method, a film forming apparatus 1000 The configuration will be explained using Fig. 16(A) and Fig. 16(B). Fig. 16(A) shows the FIG. 16(B) is a schematic diagram of a multi-chamber type film forming apparatus 1000. FIG. 1 is a cross-sectional view of an ALD apparatus that can be used in the present invention.

[0234] <Configuration example of film formation equipment> The film forming apparatus 1000 includes a carry-in chamber 1002, a carry-out chamber 1004, a transfer chamber 1006, and a film forming chamber 1007. 1008, a film forming chamber 1009, a film forming chamber 1010, and a transfer arm 1014. Here, the loading chamber 1002, the unloading chamber 1004, and the film forming chambers 1008 to 1010 are a transfer chamber 10 06. This allows the film formation chambers 1008 to 1010 to be exposed to the atmosphere. This allows continuous film formation without the need for a separate process, and prevents impurities from being mixed into the film.

[0235] The loading chamber 1002, the unloading chamber 1004, the transfer chamber 1006, the film forming chambers 1008 to 1010 To prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep it, and it is desirable to maintain reduced pressure.

[0236] In addition, an ALD apparatus can be used in the film formation chambers 1008 to 1010. Further, a configuration in which a film formation apparatus other than the ALD apparatus is used in any of the film formation chambers 1008 to 1010 may also be adopted. Examples of the film formation apparatus used in the film formation chambers 1008 to 1010 include a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, a MOCVD apparatus, and the like. For example, by providing an ALD apparatus and a PECVD apparatus in the film formation chambers 1008 to 1010, an insulator 105 made of silicon oxide of the transistor 10 shown in FIGS. 1(B) and (C) can be formed by the PECVD method, and an insulator 103 made of hafnium oxide can be formed by the ALD method. Further, an insulator 104 made of silicon oxide containing halogen can be formed by the PECVD method. Since a series of film formation is continuously performed without exposing the film to the atmosphere, film formation can be performed without impurities being mixed into the film.

[0237] The film formation apparatus 1000 has a loading chamber 1002, an unloading chamber 1004, and film formation chambers 1008 to 1010, but the present invention is not limited thereto. The film formation chambers of the film formation apparatus 1000 may be configured to have four or more, or a processing chamber for performing heat treatment or plasma treatment may be added. Further, the film formation apparatus 1000 may be a single wafer type, or may be a batch type for forming films on a plurality of substrates at once.

[0238]

[0239]

[0240] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film formation apparatus 1000 will be described. The D device includes a film-forming chamber (chamber 1020), raw material supply units 1021a and 1021b, and a flow The high-speed valves 1022a and 1022b are volume controllers, and the raw material inlets 1023a and 1023b are b, a raw material outlet 1024, and an exhaust device 1025. The raw material inlets 1023a and 1023b are connected to the raw material supply unit 1021 via supply pipes and valves. The raw material outlet 1024 is connected to the discharge pipe, valve, and pressure It is connected to the exhaust device 1025 via a power regulator.

[0240] Also, as shown in FIG. 16(B), a plasma generator 1028 is connected to the chamber 1020. By doing so, it is possible to form a film by the plasma ALD method in addition to the thermal ALD method. The plasma ALD method allows deposition without reducing the deposition rate even at low temperatures, so it is suitable for deposition with low deposition efficiency. It is suitable for use in a single-wafer deposition system.

[0241] Inside the chamber, there is a substrate holder 1026 equipped with a heater. A substrate 1030 on which a film is to be formed is placed thereon.

[0242] In the raw material supply units 1021a and 1021b, solid raw materials and liquid raw materials are supplied by vaporizers and heating means. Alternatively, the raw material supply units 1021a and 1021b may supply a gas The raw material gas may be supplied.

[0243] Although an example in which two raw material supply units 1021a and 1021b are provided is shown, this is not particularly limited. In addition, the high-speed valves 1022a and 1022b can be precisely controlled by the time. It is possible to control the supply of either the raw material gas or the inert gas. The high-speed valves 1022a and 1022b are flow rate controllers for the source gases and also for the inert gas. It can also be called a flow rate controller.

[0244] In the film forming apparatus shown in FIG. 16(B), the substrate 1030 is carried onto the substrate holder 1026. After the member 1020 is sealed, the substrate 103 is heated by the heater of the substrate holder 1026. 0 is set to a desired temperature (for example, 80°C or higher, 100°C or higher, or 150°C or higher), and the raw material gas is The exhaust device 1025 supplies an inert gas, and the exhaust device 1025 exhausts the inert gas. By repeating this process and exhausting the gas, a thin film is formed on the surface of the substrate.

[0245] In the film forming apparatus shown in FIG. 16(B), the raw materials (volatile materials) used in the raw material supply units 1021a and 1021b are By appropriately selecting the appropriate activating agent (e.g., volatile organometallic compounds), hafnium, aluminum, tungsten Oxides (including composite oxides) containing one or more elements selected from the group consisting of aluminum, zirconium, etc. Specifically, an insulating layer containing hafnium oxide can be formed. an insulating layer comprising aluminum oxide; an insulating layer comprising hafnium silicate; an insulating layer containing aluminum silicate; In addition, the raw materials ( By appropriately selecting the appropriate material (e.g., volatile organic metal compounds), it is possible to form a tungsten layer, a titanium layer, etc. It is also possible to form thin films such as metal layers and nitride layers such as titanium nitride layers.

[0246] For example, when forming a hafnium oxide layer using an ALD system, a solvent and a hafnium precursor are used. Liquids containing hafnium compounds (such as hafnium alkoxides and tetrakisdimethylamidohafnium The raw material gas is vaporized hafnium amide (TDMAH) and ozone is used as an oxidizer. In this case, two types of gases, ie, the first gas (O) and the second gas (O3), are used. The raw material gas is TDMAH, and the second raw material gas supplied from the raw material supply unit 1021b is ozone. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2 ]4. Another material liquid is tetrakis(ethylmethylamido)hafnium etc.

[0247] When forming an aluminum oxide layer using an ALD system, a solvent and an aluminum precursor are used. The raw material gas is made by vaporizing a liquid containing a compound (such as TMA: trimethylaluminum) and an oxidizing agent. In this case, two kinds of gases are used, one of which is a gas containing HCl and the other is H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1021b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0248] When forming a tungsten layer using an ALD system, WF6 gas and B2H6 gas are used. is introduced repeatedly to form an initial tungsten layer, and then WF6 gas and H2 gas are introduced. The tungsten layer is formed using SiH4 gas instead of B2H6 gas. These gases may be controlled by a mass flow controller. .

[0249] Next, the insulator 104 is formed (see FIGS. 13(C) and 13(D)). The insulator 104 can be formed by a sputtering method, a CV method, or the like. This can be done using the D method, MBE method, PLD method, ALD method, or the like.

[0250] The insulator 104 is preferably formed by CVD, particularly PECVD. It is preferable to do this.

[0251] When the insulator 104 is formed by the PECVD method, the source gas is preferably a gas containing no hydrogen or It is preferable to use a substance with a low hydrogen content, for example, a halide. For example, silicon oxide or silicon oxynitride is preferably formed as the insulator 104. In this case, it is preferable to use silicon halide as the source gas, for example, SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride) ), SiH2Cl2 (dichlorosilane) or SiBr4 (silicon tetrabromide), etc. It is possible.

[0252] When the insulator 104 is formed by the PECVD method, an oxidizing gas (such as N2O) is introduced. The silicon halide is less reactive than SiH4, so it is oxidizing. The gas easily acts on the insulator 103. As a result, the water or water contained in the insulator 103 The hydrogen is desorbed by the oxidizing gas, and the amount of water and hydrogen contained in the insulator 103 is reduced. It is possible that this can be done.

[0253] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water contents in the insulator 104 are reduced compared to when only the halogen-containing gas is used as the raw material gas. The film formation rate can be improved compared to when only silicon fluoride is used as the source gas. The insulator 104 can be formed by using SiF4 and SiH4 as raw material gases. The flow rate of H4 is set to more than 1 sccm and less than 10 sccm, preferably 2 sccm or more. By setting the flow rate to 4 sccm or less, both the content of water and hydrogen in the insulator 104 and the film formation rate can be controlled. However, the ratio of the flow rates of SiF4 and SiH4 is The temperature can be appropriately set in consideration of the water and hydrogen content in the insulating body 104 and the film formation rate.

[0254] In addition, in order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated while being grown. It is preferable to carry out a membrane.

[0255] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later is highly flat. Therefore, the top surface of the insulator 104 is subjected to a planarization process such as CMP to improve the planarity. That's fine.

[0256] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator 1 The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed to increase the crystallinity of the insulator 126a and the semiconductor 126b. The heating process can be performed by lamp heating. It is also possible to use an RTA (Rapid Thermal Annealing) device Heat treatment using an RTA device takes less time than using a furnace, so it is suitable for increasing productivity. It is effective for this purpose.

[0257] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range is used. It can be heated within a temperature range of, for example, 350°C to 445°C. For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0258] Next, the insulator 126a is formed. The insulator 126a may be formed using an insulator, a semiconductor, or the like that can be used. Sputtering, CVD, MBE, PLD, ALD, etc. can be done.

[0259] Next, the semiconductor 126b is formed. The semiconductor 126b can be formed by sputtering. The deposition can be carried out by using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 126a and the semiconductor 126b are deposited in succession without being exposed to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0260] Next, heat treatment is preferably performed. By the heat treatment, the insulator 126a and the semiconductor In some cases, the hydrogen concentration in the insulators 126a and 176b can be reduced. The heat treatment may be performed at 250° C. or higher than 650°C, preferably higher than 450°C and lower than 600°C, and more preferably higher than 520°C. The heat treatment can be carried out at a temperature of 570°C or less. The heat treatment is carried out in an atmosphere containing more than ppm, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by absorbing the desorbed oxygen. To compensate for this, heat treatment is carried out in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed to improve the crystallinity of the insulator 126a and the semiconductor 126b. The heat treatment can be performed by using a lamp. An RTA device can also be used. Heat treatment using an RTA device is more efficient than a furnace. This is effective in increasing productivity since it takes a short time. When CAAC-OS is used as 6b, the peak intensity increases by heat treatment. That is, the crystallinity of the CAAC-OS is increased by the heat treatment.

[0261] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range is used. It can be heated within a temperature range of, for example, 350°C to 445°C. For example, the substrate heating temperature during the deposition of the insulators 105, 103, and 104, or the insulating film the temperature of the heat treatment after the formation of the insulating film 104, or By forming the insulator 104 by the above-described method, the water in the insulator 104, Since hydrogen and the like have been sufficiently removed, the insulator 126a and the semiconductor 126b are not wetted with water or water. Therefore, the amount of the supplied element can be sufficiently reduced.

[0262] The heat treatment causes oxygen to be transferred from the insulator 104 to the insulator 126a and the semiconductor 126b. By subjecting the insulator 104 to heat treatment, Oxygen can be supplied to the insulator 126a and the semiconductor 126b.

[0263] Here, the insulator 103 functions as a barrier film that blocks oxygen. By providing the insulating layer 104 under the insulating layer 104, oxygen diffused into the insulating layer 104 is absorbed by the insulating layer 104. Diffusion to layers below 104 can be prevented.

[0264] In this way, oxygen is supplied to the insulator 126a and the semiconductor 126b, and oxygen vacancies are reduced. As a result, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor having a low density of defect states can be obtained. It can be said that:

[0265] Further, high density plasma treatment may be performed. High density plasma is generated by using microwaves. In the high-density plasma treatment, an oxidizing gas such as oxygen or nitrous oxide is generated. Alternatively, a mixture of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe can be used. A composite gas may be used. In the high-density plasma treatment, a bias may be applied to the substrate. This allows oxygen ions in the plasma to be drawn to the substrate side. The plasma treatment may be performed while heating the substrate. When performing plasma treatment, the same effect can be obtained at a temperature lower than that of the heat treatment. The high-density plasma treatment may be performed before the formation of the insulator 126a, or after the formation of the insulator 126b described later. The deposition may be performed before the deposition of the insulator 26a, after the deposition of the insulator 112, or after the deposition of the insulator 11 This may be done after the film formation of 6.

[0266] Next, a conductor 128 is formed (see FIGS. 13(E) and 13(F)). 8 is a conductor that can be used as the above-mentioned conductor 108a and conductor 108b. The conductor 128 can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0267] Next, a resist or the like is formed on the conductor 128, and the conductor is processed using the resist or the like. 108a and the conductor 108b are formed.

[0268] Next, a resist or the like is formed on the semiconductor 126b, and the conductor 108a and the resist or the like are and conductor 108b to form insulator 106a and semiconductor 106b (see FIG. See Figure 13(G) and Figure 13(H).

[0269] In addition, in the region of the semiconductor 106b that contacts the conductor 108a and the conductor 108b, In this case, low resistance regions 109a and 109b may be formed. Conductor 106b is connected between conductor 108a and conductor 108b. The conductive material 108a may have a region with a thinner film thickness than the region overlapping with the conductive material 108a. When forming the conductor 108b, a part of the upper surface of the semiconductor 106b is removed. is formed.

[0270] After the conductor 128 is formed, the insulator 126a, the semiconductor 126b, and the conductor 128 are The insulator 106a, the semiconductor 106b, and the semiconductor 106b are overlapped with each other. The conductor having a shape overlapping the semiconductor 106b is further processed to form a conductor 108a and conductor 108b may be formed.

[0271] Next, the insulator 126c is formed. The insulator 126c can be formed using an insulator or semiconductor that can be used. Sputtering, CVD, MBE, PLD, ALD, etc. Before the insulator 126c is formed, the semiconductor 106b, the conductor 108a, and the conductor The surface of 108b may be etched. For example, the surface may be etched using plasma containing a rare gas. After that, the insulator 126c is formed continuously without being exposed to the atmosphere. By filming, the semiconductor 106b, the conductors 108a and 108b, and the insulator 1 06c and can reduce the inclusion of impurities at the interface between films. Impurities that are introduced into the film may be more easily diffused than impurities in the film. By reducing the amount of ZnO, stable electrical characteristics can be imparted to the transistor.

[0272] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CVD method, or the like. The method can be performed by using a method such as an MBE method, a PLD method, or an ALD method. By continuously forming the film 26c and the film 132 without exposing them to the atmosphere, It is possible to reduce the amount of impurities entering the film and at the interface.

[0273] Next, a conductor 134 is formed (see FIGS. 14(A) and 14(B)). The conductive material 4 may be any conductive material that can be used as the conductive material 114 described above. The film 134 can be formed by a method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 132 and the conductor 134 can be formed by using a film such as a silicon dioxide film. By performing this process continuously without exposing it to the atmosphere, the incorporation of impurities into the film and at the interface is reduced. It is possible.

[0274] Next, a resist or the like is formed on the conductor 134, and the conductor is processed using the resist or the like. Form 114.

[0275] Next, a resist or the like is formed on the conductor 114 and the insulator 132, and the resist or the like is used to The insulating layer 106c and the insulating layer 112 are formed (FIG. 14(C) and FIG. 14(D)). (See (D).) At this time, the conductors 120a and 120b to be formed later The insulator 106c and the conductor 108b are removed so as to expose the area in contact with the conductor 108a and the conductor 108b. Insulator 112 may also be formed.

[0276] Next, the insulator 116 is formed (see FIGS. 14(E) and 14(F)). The insulator 116 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0277] Here, the insulator 116 is a material that blocks oxygen, hydrogen, water, etc., such as aluminum oxide. It is preferable to provide an oxide insulating film having such an effect.

[0278] The insulator 116 is preferably formed by plasma deposition, for example, by sputtering. It is more preferable to carry out the process by sputtering in an oxygen-containing atmosphere. is more preferable.

[0279] The sputtering method uses a direct current (DC) power supply for the sputtering power supply. current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering, which uses a high frequency power supply for sputtering. A sputtering method may also be used. Alternatively, a magnetron having a magnet mechanism inside the chamber may be used. Sputtering method, bias sputtering method in which voltage is applied to the substrate during film formation, reactive gas Alternatively, a reactive sputtering method in a gas atmosphere may be used. The flow rate of the elemental gas and the film-forming power may be appropriately determined depending on the amount of oxygen added, etc.

[0280] By forming the insulator 116 by sputtering, the insulator 10 4 or the surface of the insulator 112 (after the insulator 116 is formed, it is in contact with the insulator 104 or the insulator 112) Oxygen is added to the vicinity of the interface of the insulator 116. Here, the oxygen is, for example, oxygen radicals. When oxygen is added to the insulator 104 or the insulator 112, the state of the However, oxygen may be in the form of an oxygen atom or an oxygen ion. The addition of oxygen may be added to the insulator 104 or the insulator 112. In some cases, the oxygen contained in the insulating layer 112 exceeds the stoichiometric composition. It can also be called excess oxygen.

[0281] Next, it is preferable to carry out a heat treatment (see FIGS. 15(A) and 15(B)). By performing this treatment, the oxygen added to the insulator 104 or the insulator 112 is diffused, and the insulating The heat treatment can be applied to the body 106a, the semiconductor 106b, and the insulator 106c. The heat treatment may be carried out at a temperature of 50°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. Inert gas atmosphere or oxidizing gas is 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be carried out under reduced pressure. The heat treatment is carried out by lamp heating. An RTA device can also be used.

[0282] The heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after the semiconductor 126b is formed. The temperature difference between the heat treatment after the formation of the conductor 126b and the heat treatment after the formation of the conductor 126b is 20°C or more and 150°C or less, preferably 40 ℃ or more and 100 ℃ or less. This allows excess oxygen (oxygen) to be released from the insulator 104 etc. The heat treatment after the formation of the insulator 118 can be performed in the same manner as the heat treatment after the formation of the insulator 118. When the heat treatment can be performed by heating each layer during film formation (for example, when the insulator 118 In some cases, this may not be necessary (if equivalent heating is performed during film formation).

[0283] By this heat treatment, the insulator 116 is formed, and the insulators 104 and 112 The oxygen added thereto (hereinafter referred to as oxygen 186) is introduced into the insulator 104 or the insulator 112. The insulator 116 is then diffused (see FIGS. 15(A) and 15(B)). or an insulator that is less permeable to oxygen than the insulator 112, and acts as a barrier film that blocks oxygen. Such an insulator 116 is formed on the insulator 104 or the insulator 112. Therefore, oxygen 186 diffusing through insulator 104 or insulator 112 Alternatively, the insulator 104 or the insulator 112 may not be diffused upward, but may be diffused mainly laterally or laterally. or diffuse downwards.

[0284] Oxygen 186 diffusing through the insulator 104 or the insulator 112 flows through the insulator as shown by the arrows. 106a, the insulator 106c, and the semiconductor 106b. The insulating member 103 having the function of blocking is provided under the insulating member 104. Therefore, the oxygen 186 diffused in the insulator 104 can be prevented from diffusing to a layer below the insulator 104. Cut.

[0285] In this way, the insulator 106a, the insulator 106c and the semiconductor 106b, especially the semiconductor 106c, Oxygen 186 can be effectively supplied to the region where the channel is formed by O6b. In this way, oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen vacancies are formed. By reducing the density of the defect states, high purity intrinsic or substantially high purity intrinsic An oxide semiconductor can be used.

[0286] Note that the heat treatment after the formation of the insulator 116 may be performed at any time after the formation of the insulator 116 . For example, this may be done after the formation of the insulator 118 or after the formation of the conductors 120a and 120b. You can go later.

[0287] Next, the insulator 118 is formed. The insulator 118 may be any of the above-described insulators. The insulating layer 118 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using, for example.

[0288] Next, a resist or the like is formed on the insulator 118, and the insulators 118, 116, and 117 are laminated. An opening is then formed in the conductor 120a and the insulator 106c. The conductors to be the conductors 120a and 120b are formed as films. The conductive material can be formed by a method such as sputtering or CVD. The method can be carried out by using a method such as MBE, PLD, or ALD.

[0289] Next, a resist or the like is formed on the conductor, and the conductor 120 is processed using the resist or the like. a and conductor 120b are formed (see FIGS. 15(C) and 15(D)).

[0290] Through the above steps, the transistor 10 according to one embodiment of the present invention can be manufactured.

[0291] <Transistor manufacturing method 2> A manufacturing method of the transistor 29 will be described below with reference to FIGS. Regarding the manufacturing method of the transistor 29, the manufacturing method of the transistor described above may be referred to as appropriate. It is possible.

[0292] First, a substrate 100 is prepared. The substrate 100 may be any of the above-described substrates. good.

[0293] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0294] Next, an insulator that will become the insulator 107 is formed. The insulator may be any of the above-described insulators. The insulator film is formed by the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done using, for example.

[0295] Next, a resist or the like is formed on the insulator, and the resist or the like is used to process the insulator, forming a film having an opening. The insulating layer 107 is formed.

[0296] Next, a film of a conductor that will become the conductor 102 is formed. The conductive film can be formed by sputtering, CVD, MBE, etc. The method can be carried out by using a PLD method, an ALD method, or the like.

[0297] Next, the conductor is polished until the insulator 107 is exposed, forming the conductor 102 (FIG. 17( See Figure 17(A) and Figure 17(B). The polishing can be performed by CMP processing or the like.

[0298] Next, the insulator 105 is formed. The insulators described above may be used as the insulator 105. The insulating layer 105 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced. For example, the substrate may be heated during film formation. When a semiconductor device layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) is used. It may be heated to a temperature range of about 100°C or less.

[0299] In addition, by forming a film by the PECVD method using the same method as the insulator 104 described above, The water or hydrogen contained in the insulator 103 may be reduced.

[0300] Next, the insulator 103 is formed. The insulators described above may be used as the insulator 103. The insulating film 103 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 103 can be reduced. For example, the substrate may be heated during film formation. When a semiconductor device layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) is used. It may be heated to a temperature range of about 100°C or less.

[0301] Next, the insulator 104 is formed (see FIGS. 17(C) and 17(D)). The insulator 104 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0302] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later is highly flat. Therefore, the top surface of the insulator 104 is subjected to a planarization process such as CMP to improve the planarity. That's fine.

[0303] Next, a heat treatment is preferably carried out.

[0304] Next, an insulator that will become the insulator 106a is formed. An insulator or a semiconductor that can be used as a film may be used. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0305] Next, a semiconductor film that will become the semiconductor 106b is formed. The semiconductor film can be formed by sputtering, C This can be done using a VD method, an MBE method, a PLD method, an ALD method, or the like. By continuously forming the body film and the semiconductor film without exposing them to the atmosphere, This can reduce the amount of impurities entering the interface.

[0306] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator 1 The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than a furnace, making it effective for increasing productivity.

[0307] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range is used. It can be heated within a temperature range of, for example, 350°C to 445°C. For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0308] Next, a resist or the like is formed on the semiconductor, and the resist or the like is used to process the semiconductor, and an insulator 106 a and semiconductor 106b are formed (see FIGS. 17(E) and 17(F)).

[0309] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator 1 The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than a furnace, making it effective for increasing productivity.

[0310] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range is used. It can be heated within a temperature range of, for example, 350°C to 445°C. For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0311] Next, the insulator 106c is formed (see FIGS. 17(G) and 17(H)). The insulator 106c may be an insulator or a semiconductor that can be used as the insulator 106c. The insulator 106c can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0312] Next, a conductor that will become the conductor 108a and the conductor 108b is formed. Any conductor that can be used as the conductor 108a and the conductor 108b described above may be used. Conductive films are formed by sputtering, CVD, MBE, PLD, or ALD methods. This can be done using, for example.

[0313] In addition, the semiconductor 106b and the insulator 106c are adjacent to the conductor that will become the conductor 108. In the adjacent region, a low resistance region 109 may be formed.

[0314] Next, a resist or the like is formed on the conductor, and the conductor 108 is processed using the resist or the like. Form.

[0315] Next, the insulator 113 that will become the insulator 110 is formed. The insulator 113 can be formed by sputtering. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0316] When the insulator 110 is formed, a region 110 having silicon and oxygen is formed on the surface of the conductor 108. In some cases, the insulating layer 11 is formed (see Figures 18(A) and 18(B)). In some cases, the region 111 is formed even if the insulator 110 is not formed. Depending on the film conditions, the region 111 may not be formed when the insulator 110 is formed.

[0317] Next, a resist or the like is formed on the insulator 113, and the resist or the like is used to process the insulator. 110, forming region 108c, region 108d, conductor 108a and conductor 108b. (See FIG. 18(C) and FIG. 18(D)). At this time, the low To remove the resistive region 109, a part of the insulator 106c and the semiconductor 106b is processed. Good too.

[0318] Next, a high-density plasma treatment may be performed. The high-density plasma treatment is performed in an atmosphere containing oxygen. The oxygen-containing atmosphere is a gas atmosphere containing oxygen atoms, and , ozone or nitrogen oxides (nitric oxide, nitrogen dioxide, nitrous oxide, dinitrogen trioxide, tetranitrogen Also, in an atmosphere containing oxygen, nitrogen Inert gases such as nitrogen or rare gases (helium, argon, etc.) may also be included. By performing high density plasma treatment in an atmosphere containing oxygen, for example, carbon, hydrogen, etc. Furthermore, high density plasma treatment in an oxygen-containing atmosphere can This also makes it easier to desorb organic compounds such as hydrocarbons from the material to be treated.

[0319] Moreover, an annealing treatment may be performed before or after the high density plasma treatment. In order to increase the efficiency, it may be preferable to flow a sufficient amount of gas. Otherwise, the deactivation rate may be higher than the radical generation rate. In some cases, it may be preferable to flow at 00sccm or more, 300sccm or more, or 800sccm or more. be.

[0320] The high-density plasma treatment may be performed at a frequency of, for example, 0.3 GHz or more and 3.0 GHz or less, or 2.2 Generated using a high frequency generator between GHz and 2.8 GHz (typically 2.45 GHz) The processing pressure is preferably 10 Pa or more and 5000 Pa or less. Preferably, the pressure is 200 Pa or more and 1500 Pa or less, and more preferably, 300 Pa or more and 1000 Pa or less. a or less, and the substrate temperature is 100°C to 600°C (typically 400°C). This can be done using a mixed gas of acetone and propyl alcohol.

[0321] The high-density plasma is generated by using microwaves of, for example, 2.45 GHz. High density plasma treatment has an electron density of 1×10 11 / cm 3 More than 1×10 13 / cm 3 below, It is preferable to carry out the treatment under conditions where the electron temperature is 2 eV or less or the ion energy is 5 eV or less. In such high-density plasma processing, the kinetic energy of radicals is small, and Compared to conventional plasma treatment, plasma damage is minimal, resulting in the formation of films with fewer defects. The distance from the microwave generating antenna to the object to be treated must be 5 mm or more. 0 mm or less, preferably 20 mm or more and 60 mm or less.

[0322] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side The frequency of the RF bias may be, for example, 13.56 MHz or 27.1 By using high density plasma, high density oxygen ions can be generated. By applying RF bias to the substrate, high density plasma is generated. The oxygen ions can be efficiently guided to the object to be treated. Oxygen ions can be efficiently guided to the inside of the opening. It is preferable to perform high density plasma treatment while applying the voltage.

[0323] In addition, after the high-density plasma treatment, annealing treatment was performed continuously without exposure to the atmosphere. Furthermore, the high density plasma treatment may be performed continuously after the annealing treatment without exposing the substrate to the atmosphere. The high density plasma treatment and the annealing treatment may be performed successively. This prevents impurities from being mixed in during the treatment. After the treatment, annealing is performed to remove the oxygen added to the workpiece. It is possible to desorb unnecessary oxygen that was not used to compensate for the oxygen vacancies. The annealing process may be performed by, for example, lamp annealing.

[0324] The treatment time for high-density plasma treatment is 30 seconds or more and 120 minutes or less, or 1 minute or more and 90 minutes or less. , and it is preferable that the time is 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0325] Annealing should be performed at temperatures between 250°C and 800°C, between 300°C and 700°C, or between 400°C and 800°C. Treatment times between 00°C and 600°C are between 30 seconds and 120 minutes, between 1 minute and 90 minutes, It is preferable to set the time to between 2 and 30 minutes, or between 3 and 15 minutes.

[0326] By performing high density plasma treatment and / or annealing treatment, the semiconductor 106b It is possible to reduce the defect level in the region that will become the channel formation region. At this time, a part of the low resistance region 109 also becomes highly resistive, The conductive layer 109 may be separated into a low resistance region 109a and a low resistance region 109b. Regions 108c and 108d are also formed on the side surfaces of the conductive material 108a and the conductive material 108b. (See FIG. 18(E) and FIG. 18(F)).

[0327] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CVD method, or the like. The method can be performed by using a method such as an MBE method, a PLD method, or an ALD method. By continuously forming the film 26c and the film 132 without exposing them to the atmosphere, It is possible to reduce the amount of impurities entering the film and at the interface.

[0328] Next, a conductor 134 is formed (see FIGS. 19(A) and 19(B)). The conductive material 4 may be any conductive material that can be used as the conductive material 114 described above. The film 134 can be formed by a method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 132 and the conductor 134 can be formed by using a film such as a silicon dioxide film. By performing this process continuously without exposing it to the atmosphere, the incorporation of impurities into the film and at the interface is reduced. It is possible.

[0329] Next, the conductor 134 is polished until the insulator 113 is exposed. , the insulator 112 and the insulator 110 are formed (see FIG. 19(C) and FIG. 19(D)). The conductor 114 and the insulator 112 are the gate electrode and the gate electrode of the transistor 29, respectively. The conductor 114 and the insulator 112 can be formed in a self-aligned manner.

[0330] Next, the insulator 116 is formed (see FIG. 19(E) and FIG. 19(F)). The insulator 116 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0331] Next, a heat treatment is preferably carried out.

[0332] Through the above steps, the transistor 29 of one embodiment of the present invention can be manufactured.

[0333] By manufacturing a transistor using the method described in this embodiment, heat resistance and acid resistance can be improved. A transistor using a conductive material having chemical properties can be provided.

[0334] Furthermore, a transistor having stable electrical characteristics can be provided. It is possible to provide a transistor with low leakage current when the transistor is normally off. Alternatively, a transistor having subthreshold characteristics can be provided. It is possible to provide a transistor with a small swing value. A register can be provided.

[0335] Furthermore, by manufacturing a transistor by the method described in this embodiment, The heat treatment in a low temperature range suppresses the supply of water, hydrogen, etc. to the semiconductor 106b, etc. Therefore, a semiconductor element layer or a wiring layer can be formed in the layer below the transistor. Even if the transistor is formed, it can be manufactured without being deteriorated at high temperatures. do.

[0336] The structures and methods described in this embodiment may be combined as appropriate with structures and methods described in other embodiments. It can be used in combination.

[0337] (Embodiment 3) <Manufacturing equipment> A manufacturing apparatus for performing high-density plasma processing according to one embodiment of the present invention will be described below.

[0338] First, let us consider the configuration of manufacturing equipment that minimizes the inclusion of impurities during the manufacture of semiconductor devices, etc. (Fig. 20). This will be explained using FIGS.

[0339] FIG. 20 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing equipment 2700 includes a cassette port 2761 for accommodating substrates and a and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing alignment. The substrate is transported from the supply chamber 2701 to the atmospheric substrate transport chamber 2702, and a load lock chamber 2 for switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced to atmospheric pressure or reduced from atmospheric pressure. and an unload lock chamber 2703b for switching to a vacuum state, and a transfer chamber 2703c for transferring substrates in a vacuum state. 04, chamber 2706a, chamber 2706b, chamber 2706c, and a chamber 2706d.

[0340] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. b is connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chamber 2706a, the chamber -2706b, connected to chamber 2706c and chamber 2706d.

[0341] A gate valve GV is provided at the connection between each chamber, and the atmosphere-side substrate supply chamber 2701 With the exception of the atmospheric side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. In addition, a transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702. The chamber 2704 is provided with a transfer robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763b. .

[0342] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Below Pa, Preferably 3 x 10 -5 Pa or less, more preferably 1×10 -5 Pa or less. The transfer chamber 2704 and each chamber are filled with gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18. The partial pressure of the electrons is, for example, 3 x 10 -5 Pa or less, preferably 1×10 -5 Pa or less, Preferably 3 x 10 -6 Pa or less. The partial pressure of a gas molecule (atom) with m / z 28 is, for example, 3 x 10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. The partial pressure of gas molecules (atoms) with m / z 44 in the chamber 2704 and each chamber is, for example, , 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0343] The total pressure and partial pressure in the transfer chamber 2704 and each chamber were measured using a mass spectrometer. For example, a quadrupole mass spectrometer (Q-mass) manufactured by ULVAC, Inc. Also known as Qulee CGM-051.

[0344] In addition, the transfer chamber 2704 and each chamber are configured to have little external or internal leakage. For example, the leak rates of the transfer chamber 2704 and each chamber are as follows: 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z 18 is 1×10 -7 Pa m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. Also, for example, m The leak rate of gas molecules (atoms) with a z of 28 is 1×10 -5 Pa·m 3 / s or less, Preferably 1 x 10 -6 Pa·m 3 / s or less. For example, if m / z is 44, The leak rate of gas molecules (atoms) is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 1 0 -6 Pa·m 3 / s or less.

[0345] The leak rate was calculated from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on the external leak and the internal leak. The reason is that gas flows in from outside the vacuum system due to a small hole or a defective seal. The gas leaks are caused by leaks from valves and other partitions in the vacuum system, or by gases released from internal components. To keep the leak rate below the above-mentioned value, measures must be taken to prevent both external and internal leaks. Therefore, measures need to be taken.

[0346] For example, the opening and closing parts of the transfer chamber 2704 and each chamber are sealed with metal gaskets. Metal gaskets are made of iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a coated metal. Metal gaskets have a higher adhesion than O-rings, It can reduce external leakage. Also, iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivated metal coating, impurities released from the metal gasket are eliminated. The released gas is suppressed, and internal leakage can be reduced.

[0347] In addition, the components constituting the manufacturing equipment 2700 are aluminum, which emits less gas containing impurities. Cr, Ti, Zr, Ni or V is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. Alloys containing copper and nickel are rigid, heat resistant, and easy to process. Therefore, if the surface roughness of the component is reduced by polishing or other methods to reduce the surface area, the release Gas can be reduced.

[0348] Alternatively, the components of the manufacturing apparatus 2700 may be made of iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0349] It is preferable that the components of the manufacturing apparatus 2700 are made of metal only, for example, quartz. When installing a viewing window, the surface must be coated with iron fluoride or acid to suppress gas emission. It is recommended to thinly coat the surface with aluminum oxide or chromium oxide.

[0350] The adsorbed substances present in the transfer chamber 2704 and each chamber are adsorbed to the inner walls, etc. It does not affect the pressure in the transfer chamber 2704 and each chamber, but This causes gas emission when exhausting the nozzle. Therefore, there is a correlation between the leak rate and the pumping speed. Although there is no exhaust gas, the transfer chamber 2704 and each chamber are filled with the gas using a pump with high exhaust capacity. It is important to desorb as much of the adsorbed matter as possible and evacuate the gas in advance. To promote the removal of adhesions, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed substances by about 10 times. The heating may be performed at a temperature of 100° C. or higher and 450° C. or lower. If the adsorbed substances are removed while being introduced into each chamber, it is difficult to remove them by simply evacuating. The desorption rate of water and the like can be further increased. By heating the catalyst to a temperature similar to that of the catalyst, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas.

[0351] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the transfer chamber 270 The pressure in the transfer chamber 2704 and each chamber is increased, and after a certain time has passed, the transfer chamber 2704 and each chamber are again It is preferable to evacuate the chamber. and the adsorbed substances in each chamber can be desorbed. This treatment can reduce impurities present in the product. It is effective to repeat the process 5 to 15 times. an inert gas having a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower; By introducing oxygen etc., the pressure in the transfer chamber 2704 and each chamber is kept at 0.1 Pa or more. 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, and more preferably 5 Pa or more and 10 0 Pa or less, and the pressure is maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the transfer chamber 2704 and each chamber are heated for 5 minutes to 300 minutes. The evacuation is preferably carried out for a period of 10 minutes or more and 120 minutes or less.

[0352] Next, the chamber 2706b and the chamber 2706c are shown in the cross-sectional schematic diagram of FIG. This will be explained using the diagram.

[0353] The chambers 2706b and 2706c are used for, for example, applying high density plasma to the object to be processed. The chamber 2706b is a chamber in which a thermal treatment can be performed. The only difference between the 2706c and the 2706c is the atmosphere during high density plasma treatment. Since the configurations of the above are the same, they will be explained together below.

[0354] Chamber 2706b and chamber 2706c contain a slot antenna plate 2808 and It has a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Outside the chambers 2706b and 2706c, a gas supply source 2801 and A valve 2802, a high frequency generator 2803, a waveguide 2804, and a mode converter 2805 , a gas pipe 2806, a waveguide 2807, a matching box 2815, and a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0355] The high frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with the dielectric plate 2809. The gas supply 2801 is connected to the mode converter 2805 via a valve 2802. Then, a gas pipe passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809 2806 delivers gas to chambers 2706b and 2706c The vacuum pump 2817 also pumps the chamber through a valve 2818 and an exhaust port 2819. It has a function of exhausting gases and the like from the bar 2706b and the chamber 2706c. The high frequency power supply 2816 is connected to the substrate stage 2812 via a matching box 2815. Connected.

[0356] The substrate stage 2812 has a function of holding the substrate 2811. For example, It has the function of electrostatically chucking or mechanically chucking the object. It also has a heating mechanism 2813 inside, It has the function of heating the substrate 2811 .

[0357] Examples of the vacuum pump 2817 include dry pumps, mechanical booster pumps, and On-pump, titanium sublimation pump, cryopump or turbomolecular pump In addition to the vacuum pump 2817, a cryotrap can be used. Using a cryopump and a cryotrap allows for efficient pumping of water. Particularly preferred.

[0358] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like. Alternatively, the heat can be transferred by heat conduction or heat radiation from a medium such as a heated gas. A heating mechanism may be used. For example, a GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) RTAs such as nealing can be used. GRTAs use high-temperature gas Heat treatment is performed using an inert gas.

[0359] The gas supply source 2801 is connected to the refiner via a mass flow controller. The gas used has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) are used. That's good enough.

[0360] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide, or oxide. The surface of the dielectric plate 2809 may be coated with yttrium oxide (yttria). Further, another protective layer may be formed. The protective layer may be formed of magnesium oxide, titanium oxide, or the like. Tantalum, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, Aluminum oxide or yttrium oxide may be used. Since the device is exposed to a particularly high density region of the high density plasma 2810 described below, a protective layer is provided. As a result, the damage can be reduced by reducing the amount of particles during processing. It can be suppressed.

[0361] The high frequency generator 2803 may be, for example, 0.3 GHz or more and 3.0 GHz or less, or 2.2 GHz. It has the function of generating microwaves from Hz to 2.8 GHz. The microwaves generated in 3 are transmitted to the mode converter 2805 via a waveguide 2804 . In the mode converter 2805, microwaves transmitted as TE mode are converted into TEM mode. The microwaves are then guided to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 has a plurality of slot holes, The wave passes through the slot hole and the dielectric plate 2809. Then, An electric field can be generated in the plasma to generate a high density plasma 2810. In 810, ions and radicals corresponding to the gas species supplied from the gas supply source 2801 are supplied. For example, oxygen radicals or nitrogen radicals exist.

[0362] At this time, the ions and radicals generated by the high density plasma 2810 cause the substrate 2 The film on the substrate 2 can be modified by using a high frequency power supply 2816. It may be preferable to apply a bias to the 811 side. RF (Radio Frequency) frequencies such as 13.56MHz, 27.12MHz, etc. By applying a bias to the substrate side, high density plasma 28 The ions in the nozzle 10 can be efficiently guided to the depths of the openings in the film on the substrate 2811. Cut.

[0363] For example, in the chamber 2706b, oxygen is introduced from the gas supply source 2801 to form a high density The oxygen radical treatment is performed using the plasma 2810. Nitrogen radicals using high density plasma 2810 by introducing nitrogen from a supply source 2801 Processing can be performed.

[0364] Next, the chamber 2706a and the chamber 2706d are shown in the cross-sectional schematic diagram of FIG. This will be explained using the diagram.

[0365] The chambers 2706a and 2706d are used for, for example, irradiating the object to be treated with electromagnetic waves. The chamber 2706a and the chamber 27 The only difference between the 06d and the 06d is the type of electromagnetic wave. Because there are many, we will explain them together below.

[0366] Chamber 2706a and chamber 2706d may be connected to one or more lamps 2820. , a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. , outside chamber 2706a and chamber 2706d, a gas supply source 2821 , a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0367] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The air pump 2828 is connected to an exhaust port 2830 via a valve 2829. 820 is disposed opposite the substrate stage 2825. The substrate stage 2825 has a function of holding the substrate 2824. It has a mechanism 2826 and has the function of heating the substrate 2824 .

[0368] The lamp 2820 has a function of emitting electromagnetic waves such as visible light or ultraviolet light. For example, a light source with a wavelength of 10 nm or more and 2500 nm or less, or 500 nm or more Emitting electromagnetic waves with a peak of 2000 nm or less, or between 40 nm and 340 nm A light source having this function may be used.

[0369] For example, the lamp 2820 can be a halogen lamp, a metal halide lamp, a xenon lamp, or a lamp, carbon arc lamp, high pressure sodium lamp or high pressure mercury lamp A light source may be used.

[0370] For example, the electromagnetic waves emitted from the lamp 2820 may be partially or completely transmitted to the substrate 2824. The absorption can modify the film on the substrate 2824. For example, the generation of defects It is possible to reduce or remove impurities. By using this method, defects can be efficiently generated or reduced, or impurities can be efficiently removed.

[0371] Alternatively, for example, the substrate stage 2825 may be moved by electromagnetic waves emitted from the lamp 2820. In this case, the inside of the substrate stage 2825 may be heated. The heating mechanism 2826 may not be included.

[0372] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. 2826 refers to the description of the heating mechanism 2813. Also, the gas supply source 2821 , see the description of gas source 2801.

[0373] By using the above manufacturing equipment, it is possible to suppress the inclusion of impurities in the processed object while improving the film quality. This becomes possible.

[0374] The structures and methods described in this embodiment may be combined as appropriate with structures and methods described in other embodiments. It can be used in combination.

[0375] (Fourth embodiment) In this embodiment, a semiconductor device including a transistor according to one embodiment of the present invention will be described. An example of the circuit will be described.

[0376] <Circuit> An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described below. We will explain about this.

[0377] <CMOSインバータ> The circuit diagram shown in FIG. 23A includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The configuration of the S inverter is shown.

[0378] <Semiconductor device structure 1> 24 is a cross-sectional view of the semiconductor device corresponding to FIG. 23(A). The transistor 2200 includes a transistor 2100. The transistor 2100 is disposed above the transistor 2200. The transistor 2100 is The description of the transistor 20 shown in FIGS. 9(A) and 9(B) may be referred to as appropriate. The semiconductor device according to one aspect of the present invention is not limited to the above embodiment. The transistor described above can be used as the transistor 2100. For the transistor 2100, please refer to the above description of the transistor as appropriate. do.

[0379] A transistor 2200 shown in FIG. 24 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a region 472 b in the semiconductor substrate 450. The conductive material 454 includes a region 472b, an insulator 462, and a conductive material 454. The conductive material 454 includes a tongue. Stainless steel and silicon, carbon, germanium, tin, aluminum or nickel It is preferable to use a conductor having a region having one or more elements selected from the group consisting of:

[0380] In transistor 2200, regions 472a and 472b are source and The insulator 462 functions as a drain region. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the potential applied to the conductor 454 causes a conduction line between the region 472a and the region 472b. The non-conduction can be controlled.

[0381] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium, or or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate such as gallium oxide may be used. A single crystal silicon substrate is used.

[0382] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart p-type conductivity. In this case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, It's okay.

[0383] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The ON characteristics of the transistor 2200 can be improved.

[0384] Regions 472a and 472b are regions containing impurities that impart p-type conductivity. In this way, transistor 2200 constitutes a p-channel transistor.

[0385] Note that transistor 2200 is separated from adjacent transistors by regions 460 and the like. The region 460 is an insulating region.

[0386] The semiconductor device shown in FIG. 24 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator Insulator 489, insulator 490, insulator 491, insulator 492, insulator 493, and The conductor 480a, the conductor 480b, and the conductor 480c are , tungsten and silicon, carbon, germanium, tin, aluminum or nickel It is preferable to use a conductor having a region containing one or more elements selected from the group consisting of:

[0387] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 464. 64. Insulator 468 is disposed on insulator 466. Insulator 468 is disposed on insulator 466. 89 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 489. The insulator 493 is disposed on the transistor 2100. 94 is disposed on the insulator 493 .

[0388] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings have openings that reach the conductor 454. The openings also have conductors 480a, 480b, and 480c, respectively. The conductive material 480b or the conductive material 480c is embedded therein.

[0389] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a portion that is in contact with the conductor 480c, and an opening that reaches the conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0390] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0391] The insulator 489 has an opening overlapping with a channel formation region of the transistor 2100 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. are.

[0392] The conductor 474a may function as the gate electrode of the transistor 2100. Alternatively, for example, applying a constant potential to the conductor 474a can turn on the transistor 210. The electrical properties, such as the threshold voltage of 0, may be controlled. a and the conductor 504 that functions as the gate electrode of the transistor 2100 are electrically connected to each other. This can increase the on-state current of the transistor 2100. In addition, since the punch-through phenomenon can be suppressed, the transistor 210 The electrical characteristics in the saturated region of 0 can be stabilized. Since this corresponds to the conductor 102 in the embodiment, please refer to the description of the conductor 102 for details. It is possible.

[0393] Insulator 490 also has an opening that reaches conductor 474b and an opening that reaches conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment, and therefore For details, the description of the insulator 103 can be referred to. Insulator 490 is provided to cover conductors 474a to 474c except for openings. By doing so, the conductors 474a to 474c can extract oxygen from the insulator 491. This can prevent the insulator 491 from forming an oxide semiconductor layer of the transistor 2100. can effectively supply oxygen to the

[0394] The insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 491 corresponds to the insulator 104 in the above embodiment, and therefore For details, the description of the insulator 104 can be referred to.

[0395] As shown in the above embodiment, by reducing the content of water and hydrogen in the insulator 491, Therefore, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This allows the electrical characteristics of the transistor 2100 to be stabilized.

[0396] In addition, such an insulator with reduced water and hydrogen is not only insulator 491 but also other insulators. For example, the insulator 466, the insulator 468, the insulator 489, the insulator 493, etc. It can be used anywhere.

[0397] In addition, in FIG. 24, the insulators 105 and 101 in the transistor 20 are Although the insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the body 489 and the insulator 490. Between the insulator 468 and the insulator 489, there is an insulator 101 that blocks water, hydrogen, etc. By providing an insulator having the function, the water and hydrogen content of the insulator 491 can be reduced as described above. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 2100. It is possible.

[0398] The insulator 492 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c are provided. The insulator 492 corresponds to the insulator 116 in the above embodiment. Therefore, for details, the description of the insulator 116 can be referred to.

[0399] The insulator 493 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c are provided. The openings are provided with a conductor 496a and a conductor 496b. , the conductor 496c or the conductor 496d is embedded in each opening. , and through an opening in any of the components such as the transistor 2100. There is.

[0400] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b and the conductor The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive material 498a, the conductive material 498b, and the conductive material 498c are embedded in the respective conductive materials. do.

[0401] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 and Insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. Alternatively, they may be used in layers.

[0402] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of the components of 494 has an insulator that blocks impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 2100. By disposing an insulator having a locking function, the electrical characteristics of the transistor 2100 are improved. It can stabilize gender.

[0403] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in single or multilayer configurations.

[0404] Conductor 454, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor Conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor The conductor 496d, the conductor 498a, the conductor 498b, and the conductor 498c are Stainless steel and silicon, carbon, germanium, tin, aluminum or nickel In particular, a conductor having a region containing one or more elements selected from tungsten may be used. A conductor containing boron, nitrogen, oxygen, fluorine, silicon, or the like is preferable. Copper, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc , Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Conductors containing one or more of tin, tantalum, and tungsten are used in a single layer or multilayer. For example, the material may be an alloy or a compound, and may be a conductor containing aluminum, copper, and Conductors containing titanium, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0405] The semiconductor device shown in FIG. 25 is the same as the transistor 2200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. This increases the effective channel width, improving the on-state characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0406] 26 is a circuit diagram of the semiconductor device shown in FIG. 24. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 26 shows a case where the semiconductor device 200 is provided on a semiconductor substrate 450 which is an SOI substrate. 1 shows a structure in which region 456 is separated from semiconductor substrate 450 by insulator 452. By using an SOI substrate as the conductor substrate 450, punch-through phenomena and the like can be suppressed. Therefore, the off-state characteristics of the transistor 2200 can be improved. The insulator 452 can be formed by insulating the semiconductor substrate 450. For example, the insulator 452 can be silicon oxide.

[0407] The semiconductor device shown in FIGS. 24 to 26 is a semiconductor substrate in which a p-channel transistor is formed. The area occupied by the element is reduced by fabricating an n-channel transistor above it. That is, the degree of integration of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Compared to the conventional method, the process can be simplified, thereby increasing the productivity of semiconductor devices. In addition, the yield of the semiconductor device can be increased. The transistor is placed in the LDD (Lightly Doped Drain) region, shallow trench In some cases, complex processes such as choke structure and distortion design can be omitted. Compared to manufacturing transistors using semiconductor substrates, productivity and yield can be improved. It may be possible to reduce the

[0408] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 23B is that of the transistor 2100 and the transistor 2200. The figure shows a configuration in which the source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0409] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0410] The semiconductor device shown in FIG. 27A includes a transistor 3200 using a first semiconductor and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. It is possible.

[0411] The transistor 3300 preferably has a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. It is possible to retain the memory contents, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in low power consumption semiconductors. It becomes a body device.

[0412] In FIG. 27A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0413] The semiconductor device shown in FIG. 27A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. do.

[0414] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the capacitor The voltage is applied to a node FG electrically connected to one of the electrodes of the capacitor 3400. A predetermined charge is applied to the gate of the register 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. The transistor 3300 is set to a potential at which it is in a non-conductive state, thereby making the transistor 3300 in a non-conductive state. As a result, charge is held at the node FG (retention).

[0415] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long time. It will be held.

[0416] Next, the reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the second wiring 3002 takes a potential according to the amount of charge held in the node FG. If 3200 is an n-channel type, a high level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 Apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it "conductive." The potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, the charge applied to node FG can be determined. When a high level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." Meanwhile, the node FG When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. You can put it out.

[0417] When memory cells are arranged in an array, the information of the desired memory cell is read. In a memory cell where information is not read, The potential at which the transistor 3200 is in a "non-conducting state" regardless of the applied charge, i.e. Ri, V th_H By applying a lower potential to the fifth wiring 3005, the information of the desired memory cell is Alternatively, in a memory cell from which information is not read, This means that transistor 3200 is in a "conducting state" regardless of the charge applied to node FG. Such a potential, that is, V th_L By applying a higher potential to the fifth wiring 3005, a desired It is only necessary to have a configuration in which only the information in the memory cells can be read.

[0418] In the above, an example in which two types of charges are held in the node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, It may be configured to be able to hold three or more types of charges. The semiconductor device can be made multi-valued to increase the storage capacity.

[0419] <Memory device structure 1> 28 is a cross-sectional view of the semiconductor device corresponding to FIG. 27(A). has a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are arranged above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. The transistor 3200 may be the transistor shown in FIG. Please refer to the description of transistor 2200. Note that in FIG. The case where the transistor 3200 is an n-channel transistor has been described. It may also be a transistor of the NAND type.

[0420] A transistor 3200 shown in FIG. 28 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472 a in the semiconductor substrate 450 and a region 472 b in the semiconductor substrate 450. It has a region 472b, an insulator 462, and a conductor 454.

[0421] The semiconductor device shown in FIG. 28 includes an insulator 464, an insulator 466, an insulator 468, and a conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator Insulator 489, insulator 490, insulator 491, insulator 492, insulator 493, and and an edge 494.

[0422] The insulator 464 is disposed on the transistor 3200. The insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 468 is disposed on insulator 466. 89 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 489. Also, an insulator 493 is disposed on the transistor 3300. Also, an insulator 4 94 is disposed on the insulator 493 .

[0423] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings have openings that reach the conductor 454. The openings also have conductors 480a, 480b, and 480c, respectively. The conductive material 480b or the conductive material 480c is embedded therein.

[0424] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a portion that is in contact with the conductor 480c, and an opening that reaches the conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0425] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0426] The insulator 489 has an opening overlapping the channel formation region of the transistor 3300 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. are.

[0427] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a can turn on the transistor It is also possible to control electrical properties such as the threshold voltage of 3300. 474a and the conductor 504 which is the top gate electrode of the transistor 3300 are electrically connected. This can increase the on-state current of the transistor 3300. In addition, punch-through phenomenon can be suppressed, so the transistor 3300 This makes it possible to stabilize the electrical characteristics in the saturated region.

[0428] Insulator 490 also has an opening that reaches conductor 474b and an opening that reaches conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment, and therefore For details, the description of the insulator 103 can be referred to. Insulator 490 is provided to cover conductors 474a to 474c except for openings. By doing so, the conductors 474a to 474c can extract oxygen from the insulator 491. This prevents the insulator 491 from forming an oxide semiconductor layer of the transistor 3300. can effectively supply oxygen to the

[0429] The insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 491 corresponds to the insulator 104 in the above embodiment, and therefore For details, the description of the insulator 104 can be referred to.

[0430] As shown in the above embodiment, by reducing the content of water and hydrogen in the insulator 491, Therefore, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This allows the electrical characteristics of the transistor 2100 to be stabilized.

[0431] In addition, such an insulator with reduced water and hydrogen is not only insulator 491 but also other insulators. For example, the insulator 466, the insulator 468, the insulator 489, the insulator 493, etc. It can be used anywhere.

[0432] In addition, in FIG. 24, the insulators 105 and 101 in the transistor 20 are Although the insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the body 489 and the insulator 490. Between the insulator 468 and the insulator 489, there is an insulator 101 that blocks water, hydrogen, etc. By providing an insulator having the function, the water and hydrogen content of the insulator 491 can be reduced as described above. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 3300. It is possible.

[0433] The insulator 492 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and transistor 3300 The other of the source electrode and the drain electrode is overlapped with the conductor 516a via the insulator 511. conductor 514, which is the gate electrode of transistor 3300; 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening is provided through a certain conductor 516a to reach the conductor 474c. The insulator 492 corresponds to the insulator 116 in the above embodiment, and therefore, the details thereof will be explained with reference to the insulator 116. The following description can be taken into consideration.

[0434] The insulator 493 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and transistor 3300 The other of the source electrode and the drain electrode is overlapped with the conductor 516a via the insulator 511. conductor 514, which is the gate electrode of transistor 3300; 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening extending through one conductor 516a to the conductor 474c. The portions are respectively provided with a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496 However, each opening is filled with transistors 3300 and the like. This may be through an opening in one of the components.

[0435] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. 496c, an opening that reaches conductor 496d, and an opening that reaches conductor 496e. The openings are provided with a conductor 498a, a conductor 498b, a conductor 498c, and a conductor 498d. Electrical body 498d is embedded.

[0436] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of the components of 494 has an insulator that blocks impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 3300. By disposing an insulator having a locking function, the electrical characteristics of the transistor 3300 are It can stabilize gender.

[0437] The source or drain of transistor 3200 is connected to conductor 480b, conductor 478b, and , the conductor 476a, the conductor 474b, and the conductor 496c. The conductor 516b is electrically connected to one of the source and drain electrodes of the MOSFET 00. The conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c. Conductor 478c, conductor 476b, conductor 474c, and conductor 496d. The conductor 516a, which is the other of the source electrode or drain electrode of the transistor 3300, is electrically connected to the Connect to the target.

[0438] The capacitor 3400 is the other of the source electrode and the drain electrode of the transistor 3300. The insulating film 511 includes a conductor 516a, a conductor 514, and an insulator 511. The insulator can be formed in the same process as the insulator that functions as the gate insulator of the transistor 3300. This can be preferable in some cases because it can increase productivity. , formed through the same process as the conductor 504 that functions as the gate electrode of the transistor 3300. The use of such a layer may be preferable in some cases because it can increase productivity.

[0439] For other structures, please refer to the descriptions in Figure 24 etc. as appropriate.

[0440] The semiconductor device shown in FIG. 29 is the same as the transistor 3200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The figure shows the case where the transistor 200 is a fin type. For details, refer to the description of the transistor 2200 shown in FIG. The case where the transistor 2200 is a p-channel transistor has been described. The transistor 3200 may be an n-channel transistor.

[0441] 30 is a semiconductor device having a transistor 3200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450, which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. In FIG. 26, the transistor 2200 is p The case where the transistor 3200 is an n-channel transistor has been described. It may also be a transistor of the NAND type.

[0442] <Storage device 2> The semiconductor device shown in FIG. 27B differs from the semiconductor device shown in FIG. 27A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information.

[0443] The reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0444] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the 3400 electrodes takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+CV1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+CV0) / (CB+C)).

[0445] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0446] In this case, the transistor to which the first semiconductor is applied is used in a drive circuit for driving the memory cell. A transistor to which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the drive circuit.

[0447] The semiconductor device described above uses a transistor including an oxide semiconductor and having low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the data for a long period of time. It is possible to maintain the volume.

[0448] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as a conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which has led to a dramatic improvement in reliability. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0449] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 27(A), a circuit diagram shown in FIG. 31 is used. and explain.

[0450] The semiconductor device illustrated in FIG. 31 includes transistors 4100 to 4400 and a capacitor. The transistor 4100 has a capacitor 4500 and a capacitor 4600. A transistor similar to the transistor 3200 can be used, and the transistor 420 0 to 4400 can be transistors similar to the transistor 3300 described above. Although not shown in FIG. 31, the semiconductor device shown in FIG. 31 can be implemented in a matrix. The semiconductor device shown in FIG. 31 includes a wiring 4001, a wiring 4003, and a wiring 400 5 to 4009, the writing and reading of the data voltage is controlled according to the signal or potential applied to It can be controlled.

[0451] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and the drain of the transistor 4100 is connected to a wiring 4001. In FIG. 31, the conductivity type of the transistor 4100 is shown as a p-channel type. That's fine too.

[0452] The semiconductor device shown in FIG. 31 has two data holding units. For example, the first data holding unit is , one of the source and drain of the transistor 4400 connected to the node FG1, One electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores a charge between the transistor connected to node FG1 and the transistor connected to node FG2. the gate of the transistor 4100, the other of the source or drain of the transistor 4200, One of the source or drain of the transistor 4300 and one of the electrodes of the capacitor element 4500 The charge is held between

[0453] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4006. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of 00 is connected to a wiring 4009 .

[0454] The transistors 4200 to 4400 are transistors that control writing of data voltages and retention of charges. Note that the transistors 4200 to 4400 are in a non-conducting state. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, a transistor having an oxidized layer in a channel formation region is preferably used. Preferably, the transistor is an OS transistor. The transistor has advantages such as low off-state current and the ability to be stacked with a silicon-containing transistor. In FIG. 31, the conductivity types of the transistors 4200 to 4400 are n-channel. However, it may be a p-channel type.

[0455] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor uses a compound semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 1 includes a first layer 4 having a transistor 4100 as shown in FIG. 021 and a second layer 4022 having transistors 4200 and 4300. and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced, and This allows for the body device to be made smaller.

[0456] Next, the operation of writing information into the semiconductor device shown in FIG. 31 will be described.

[0457] First, a data voltage write operation (hereinafter, ) will be described below. The data voltage written to the data storage unit is V D1 and the threshold voltage of the transistor 4100 is The voltage is Vth.

[0458] In write operation 1, the wiring 4003 is connected to V D1 Then, after setting the wiring 4001 to the ground potential, The wirings 4005 and 4006 are set to a high level. 007 to 4009 are set to low level. Then, the node FG2 in an electrically floating state The potential of the wiring 40 increases, and a current flows through the transistor 4100. The potential of the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 also increase. The potential of the node FG2 rises, and a potential difference between the gate and source of the transistor 4100 is When the voltage (Vgs) reaches the threshold voltage Vth of the transistor 4100, the transistor 410 Therefore, the potential of the wiring 4001 and the nodes FG1 and FG2 is The rise stopped, and V D1 Vth has dropped from D1 -Vth" and becomes constant.

[0459] In other words, the V given to wire 4003 D1 When a current flows through the transistor 4100, The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. , the potential of node FG2 is "V D1 -Vth", the Vgs of transistor 4100 is Vth is reached, and the current stops.

[0460] Next, the data voltage is written to the data storage unit connected to the node FG2 (hereinafter, referred to as the write The data holding operation connected to node FG2 is called write operation 2. The data voltage written to the part is V D2 It will be explained as follows.

[0461] In write operation 2, wire 4001 is connected to V D2 Then, after setting the wiring 4003 to the ground potential, The wiring 4007 is set to a high level. 4006, 4008, and 4009 are set to low level. Transistor 4300 is set to the conductive state. Therefore, the potential of the node FG2 is also set to low level. The voltage of the wiring 4003 decreases as the voltage of the wiring 4003 decreases. The potential of the wiring 4003 increases. As the potential at node FG2 rises, the potential at node FG2 also rises. When Vgs of transistor 4100 becomes Vth of transistor 4100, transistor 4 The current flowing through 100 becomes smaller. Therefore, the potential of wiring 4003 and FG2 does not stop rising. Ri, V D2 Vth has dropped from D2 -Vth" and becomes constant.

[0462] In other words, the V given to wire 4001 D2 When a current flows through the transistor 4100, The potential of the node FG2 is increased by the increase in the potential. The potential of FG2 is "V D2 -Vth", Vgs of transistor 4100 is Vth. At this time, the potential of the node FG1 is 400 are in a non-conductive state, and the "V D1 -Vth" is maintained can be.

[0463] In the semiconductor device shown in FIG. 31, after writing data voltages to a plurality of data holding units, 4009 is set to high level, and the potentials of the nodes FG1 and FG2 are raised. The transistor is made non-conductive, preventing the movement of charge and maintaining the written data voltage. .

[0464] By the above-described operation of writing data voltages to the nodes FG1 and FG2, multiple data The data voltage can be held in the data holding section. D 1-Vth" and "V D2 -Vth" was used as an example, but these are multi-value data. Therefore, each data storage unit stores 4 bits of data. When holding 16 values ​​of "V D1 -Vth" and "V D2 -Vth" can be used.

[0465] Next, the operation of reading information from the semiconductor device shown in FIG. 31 will be described.

[0466] First, the data voltage is read from the data storage unit connected to the node FG2 (hereinafter, This will be referred to as read operation 1.

[0467] In the read operation 1, the wiring 4003 is precharged and then brought into an electrically floating state. The wirings 4005 to 4008 are set to a low level. The potential of the electrically floating node FG2 is set to "V D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the electrically floating wiring 4003. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D2 -Vth" Vth is larger than Vth. D2 The potential of the wiring 4003 is The data voltage of the data storage section connected to G2 corresponds to the data of the analog value that is read out. The voltage of the capacitor undergoes A / D conversion and acquires data from the data storage section connected to node FG2. .

[0468] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D2 ". Tran In register 4100, the "V D2 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D2 " is read out.

[0469] After acquiring the data of the data storage section connected to node FG2, transistor 4300 is turned on. In the conductive state, the "V D2 -Vth" is discharged.

[0470] Next, the charge held at node FG1 is distributed to node FG2, and the The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. The wiring 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. , the wiring 4005 and the wirings 4007 to 4009 are set to low level. is turned on, the charge of the node FG1 is shared with the node FG2.

[0471] Here, the potential after the charge distribution is the written potential "V D1 -Vth" and Therefore, the capacitance value of the capacitor 4600 is set to be larger than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -Vth" is the same data The potential "V D2 It is preferable to set the capacitance value to be larger than "-Vth". By changing the ratio of the potential and increasing the potential to be written in advance, the potential after the charge distribution can be reduced. The fluctuation of the potential due to the distribution of the charge will be described later.

[0472] Next, a data voltage is read from the data storage unit connected to the node FG1 (hereinafter referred to as a read This is called "read-out operation 2.") will be explained below.

[0473] In the read operation 2, the wiring 4003 is precharged and then placed in an electrically floating state. The wirings 4005 to 4008 are set to a low level. It is set to high level during precharge and then to low level. By using this as a pin, the electrically floating node FG2 is set to the potential "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. As a result, the potential of the wiring 4003 in an electrically floating state is reduced. As the voltage drops, the Vgs of transistor 4100 decreases. When gs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes lower than the potential of the node FG2 “V D1 -Vth" or Vth is larger than Vth. D1 The potential of the wiring 4003 is The analog value data read out corresponds to the data voltage of the data storage section connected to 1. The voltage undergoes A / D conversion, and data is acquired from the data storage unit connected to node FG1. The above is the operation of reading out the data voltage to the data holding unit connected to node FG1.

[0474] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D1 ". Tran In register 4100, the "V D1 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D1 " is read out.

[0475] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, a plurality of data For example, the data voltage can be read from the data storage unit. FG2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values) In FIG. 31, the first layer 4021 to the third layer 4022 can store data. However, by forming further layers, the surface of the semiconductor device can be It is possible to increase the storage capacity without increasing the product.

[0476] The potential that is read out is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" and "V D2 - As a result, the Vth of the memory cell can be offset and read. This improves the storage capacity per memory and also brings the read data closer to the correct data. This allows for excellent data reliability.

[0477] 32 is a cross-sectional view of the semiconductor device corresponding to FIG. 31. The semiconductor device shown in FIG. , transistor 4100, transistor 4200, transistor 4300, transistor 4400, a capacitor 4500, and a capacitor 4600. 100 is formed in the first layer 4021, and transistors 4200, 4300, The transistor 4400 and the capacitor 4500 are formed in the second layer 4022. The capacitor 4600 is formed in the third layer 4023 .

[0478] Here, the description of the transistor 3300 is used as the transistors 4200 to 4400. The description of the transistor 3200 can be taken into consideration for the transistor 4100. The description in Figure 28 can also be taken into consideration as appropriate for other wiring, insulators, etc.

[0479] In the capacitor element 3400 of the semiconductor device shown in FIG. 28, the conductive layer is provided parallel to the substrate. In the capacitor elements 4500 and 4600, a conductive layer is formed in a trench shape. By providing this structure, the occupied area can be reduced. Even if the capacitance is large, a large capacitance value can be ensured.

[0480] <Storage device 4> The semiconductor device shown in FIG. 27C includes a transistor 3500 and a sixth wiring 3006. This is different from the semiconductor device shown in FIG. It is possible to write and store information by the same operation as the device. The transistor 3500 may be the same as the transistor 3200 described above.

[0481] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500. One of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200. The other of the source and drain of the transistor 3500 is electrically connected to a third wiring 3003. Connected.

[0482] 33 shows an example of a cross-sectional view of the semiconductor device shown in FIG. 27(C). 33 and 34 show an example of a cross section that is approximately perpendicular to the A1-A2 direction. The semiconductor device shown in C) has five layers, ie, layers 1627 to 1631. The layer 1627 is The layers 1628 and 1629 include transistors 3200 to 3600. It has a transistor 3300.

[0483] Layer 1627 is a layer that connects substrate 1400 and transistors 3200 to 3204 on substrate 1400. 3600, insulator 1464 on transistor 3200, etc., and plugs such as plug 1541. The plugs 1541 and the like are used to form gate electrodes and source electrodes of the transistors 3200 and the like. The plug 1541 is connected to the insulator 1464. It is preferable that the ion exchange film is formed as follows.

[0484] The transistors 3200 to 3600 are the same as those of the transistor 2200. Please refer to the attached.

[0485] The insulator 1464 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride Aluminum or the like may be used.

[0486] Insulator 1464 is made by sputtering, CVD (thermal CVD, MOCVD, PECVD) The layer can be formed by a method such as a PLD method, an MBE method, an ALD method, or a PLD method. In particular, when the insulator is formed into a film by a CVD method, preferably a plasma CVD method, the coating property is improved. In addition, to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0487] Also, silicon carbonitride (silicon carbonitride) is used as the insulator 1464. Silicon oxycarbide, silicon oxycarbide, etc. In addition, USG (Undoped Silicate Glass), BPS G(Boron Phosphorus Silicate Glass), BSG(B orosilicate glass) can be used. USG, BPSG, etc. The film may be formed by atmospheric pressure CVD. The film may be formed by coating.

[0488] The insulator 1464 may be a single layer or may be a laminate of multiple materials.

[0489] Here, in FIG. 33, the insulator 1464 is an insulator 1464a and an insulator on the insulator 1464a. An example of two layers with 1464b is shown below.

[0490] Insulator 1464a is formed between region 1476 of transistor 3200, transistor 3200, etc. It is preferable that the contact and coverage with the conductor 1454 functioning as a gate be good.

[0491] An example of the insulator 1464a is silicon nitride formed by a CVD method. Here, it may be preferable that the insulator 1464a contains hydrogen. By having the element, defects and the like of the substrate 1400 are reduced, and the transistor 3200 and the like For example, if a material containing silicon is used as the substrate 1400, the characteristics of the substrate may be improved. In this case, defects such as dangling bonds of silicon can be terminated by hydrogen. .

[0492] Here, the conductor under the insulator 1464a, such as the conductor 1454, and the insulator, such as the conductor 1511, It is preferable that the parasitic capacitance formed between 1464b and the conductor formed on it is small. Therefore, it is preferable that the insulator 1464b has a low dielectric constant. It has a lower dielectric constant than the insulator 1462 that serves as the gate insulator, such as Dielectric 3200. It is also preferable that the insulator 1464b has a lower dielectric constant than the insulator 1464a. For example, the relative dielectric constant of the insulator 1464b is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of insulator 1464b is 0.5 times that of insulator 1464a. It is preferably 7 times or less, and more preferably 0.6 times or less.

[0493] Here, as an example, silicon nitride is used for the insulator 1464a and USG is used for the insulator 1464b. You can be there.

[0494] Here, the insulators 1464a and 1581a are made of silicon nitride or silicon carbonitride. By using materials with low copper permeability such as copper, In addition, when the diffusion of copper into the upper and lower layers of the insulator 1464a and the insulator 1581a can be suppressed, There is a match.

[0495] In addition, for example, impurities such as copper may be introduced from the upper surface of the conductor 1511 through the insulator 1584 or the like. Therefore, the insulator 1584 on the conductor 1511 is made of copper or other impurities. It is preferable to use a material with low pure permeability. For example, the insulator 1584 is A layered structure such as the layered structure of the insulating material 581a and the insulating material 1581b may be used.

[0496] Layer 1628 includes insulator 1581, insulator 1584 on insulator 1581, and insulator 158 4 and an insulator 1585 on the insulator 1571. Conductors 1511 etc. on the body 1464, plugs 1543 etc. connecting to the conductors 1511 etc., The conductor 1511 is formed by the opening of the insulator 1581. It is preferable that the plug 1543 is formed so as to fill the opening. It is preferable that the conductor 1513 is formed so as to fill the opening of the insulator 1571. , and is preferably formed so as to fill the opening of the insulator 1585.

[0497] The layer 1628 may also include a conductor 1413. The conductor 1413 may be formed by insulating the insulator 158. It is preferable that the opening of the insulating film 5 is filled.

[0498] The insulators 1584 and 1585 may be, for example, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, nitride oxide Aluminum, aluminum nitride, or the like may be used.

[0499] The insulators 1584 and 1585 are formed by sputtering, CVD (thermal CVD, M OCVD, PECVD, etc.), MBE, ALD, or PLD In particular, the insulator can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form a film by plasma deposition because it can improve the coating property. To reduce the image, thermal CVD, MOCVD, or ALD is preferred.

[0500] Further, as the insulators 1584 and 1585, silicon carbide, silicon carbonitride ( silicon carbonitride, silicon carbide oxide xycarbide, etc. can also be used. licate Glass), BPSG (Boron Phosphorus Sili Uses borosilicate glass (BSG), borosilicate glass (BSG), etc. USG, BPSG, etc. can be formed by atmospheric pressure CVD. For example, HSQ (hydrogen silsesquioxane) or the like may be formed using a coating method.

[0501] The insulators 1584 and 1585 may be single layers or may be laminated with multiple materials. stomach.

[0502] The insulator 1581 may be formed by stacking multiple layers. For example, as shown in FIG. The body 1581 is made up of two layers: an insulator 1581a and an insulator 1581b on the insulator 1581a. Good too.

[0503] The plug 1543 also has a protrusion on the insulator 1571 .

[0504] Metal materials such as the conductor 1511, the conductor 1513, the conductor 1413, the plug 1543, etc. Conductive materials such as metal alloys or metal oxide materials can be used. Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, molybdenum Metals such as iridium, silver, tantalum, or tungsten, or alloys containing these as the main components Gold can be used as a single layer or a multilayer structure. Tungsten nitride, nitride Metal nitrides such as molybdenum and titanium nitride can be used.

[0505] Here, the conductors such as the conductor 1511 and the conductor 1513 are the same as those of the semiconductor device shown in FIG. It is preferable that these conductors function as wiring. These conductors are connected by plugs such as plug 1543. It is preferable.

[0506] The insulator 1581 can be described by referring to the description of the insulator 1464. Insulator 1581 may be a single layer, or multiple materials may be laminated. An example of two layers, an insulator 1581a and an insulator 1581b on the insulator 1581a, is shown. Regarding materials that can be used for the insulators 1581a and 1581b and methods of forming them, The materials and shapes that can be used for the insulators 1464a and 1464b are as follows: The description of the synthesis method can be found in the literature.

[0507] An example of the insulator 1581a is silicon nitride formed by CVD. Here, a semiconductor element included in the semiconductor device shown in FIG. 00, etc., hydrogen diffuses into the semiconductor element, causing a deterioration in the characteristics of the semiconductor element. Therefore, it is preferable to use a film that releases less hydrogen as the insulator 1581a. The amount of desorbed hydrogen can be analyzed using, for example, TDS. The amount of hydrogen desorption from 81a was measured by TDS in the range of 50 to 500°C. The amount of desorption converted to electrons is, for example, 5 × 10 20 atoms / cm 3 Less than or equal to 2 x 10 20 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 Below is Alternatively, the amount of desorption of the insulator 1581a converted into hydrogen atoms is For example, 5 x 10 15 atoms / cm 2 Less than or equal to 2 x 10 15 atoms / cm 2 Less than 1×10, more preferably 15 atoms / cm 2 The following is fine.

[0508] In addition, silicon nitride, which has a small amount of hydrogen desorption, can be used not only for the insulator 1581a but also for the It may be used for the insulator layer above the insulator 1581a shown in FIG. Instead of the capacitor, an insulator similar to the insulator 104 in which hydrogen and water are reduced as shown in the above embodiment is used. You can also use your body.

[0509] Furthermore, it is preferable that the insulator 1581b has a lower dielectric constant than the insulator 1581a. The relative dielectric constant of the insulator 1581b is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 1581b is preferably 0.7 times or less the relative dielectric constant of the insulator 1581a. It is more preferable that the ratio is 0.6 times or less.

[0510] The insulator 1571 is preferably formed using an insulating material with low impurity permeability. For example, it is preferable that the insulator 1571 has low oxygen permeability. It is preferable that the insulator 1571 has low hydrogen permeability. It is preferable that

[0511] Examples of the insulator 1571 include aluminum oxide, hafnium oxide, tantalum oxide, and oxide. Zirconium, lead zirconate titanate (PZT), strontium titanate (SrTiO 3) or (Ba,Sr)TiO3 (BST), silicon nitride, etc. are used in a single layer or multilayer. Alternatively, these insulators may be made of, for example, aluminum oxide, bismuth oxide, or Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, tungsten oxide Sodium oxide, zirconium oxide, or gallium oxide may be added. The above insulators may be silicon oxide, silicon oxynitride, or the like. In particular, aluminum oxide has high resistance to water and hydrogen. This is preferred because it has excellent barrier properties.

[0512] The insulator 1571 may be, for example, silicon carbide, silicon carbonitride, or silicon oxycarbide. A .g., a .

[0513] The insulator 1571 is made by laminating a layer of material with low water and hydrogen permeability with a layer containing other insulating material. For example, a layer containing silicon oxide or silicon oxynitride, or a layer containing metal oxide may be used. The above may be used in a laminated form.

[0514] For example, the semiconductor device shown in FIG. 27C has an insulator 1571. The elements contained in the conductor 1513, the conductor 1413, etc. are contained in the insulator 1571 and the layer below it (insulator This can suppress diffusion into the layer 1584, the insulator 1581, the layer 1627, etc.

[0515] If the dielectric constant of the insulator 1571 is higher than that of the insulator 1584, The thickness of the film is preferably smaller than that of the insulator 1584. The dielectric constant is preferably 0.7 times or less, more preferably 0. For example, the thickness of the insulator 1571 is preferably 5 nm or more and 200 nm or less. The thickness of the insulator 1584 is preferably 5 nm or more and 60 nm or less. The thickness is preferably 30 nm or more and 800 nm or less, and more preferably 50 nm or more and 500 nm or less. For example, the thickness of the insulator 1571 is one-third or less of the thickness of the insulator 1584. preferable.

[0516] FIG. 33 is a cross-sectional view showing some of the components of the semiconductor device shown in FIG. 27(C). The insulator 1464b and the plug 15 formed to be embedded in the insulator 1464b are 41, insulator 1581 on insulator 1464b, plug 1541 and insulator 1464 Conductor 1511 on b, insulator 1584 on insulator 1481, and insulator 1584 on insulator 1584. The insulating member 1584 is formed so as to be embedded in the insulating member 1571. a plug 1543 located on the conductor 1511, an insulator 1585 located on the insulator 1571; The plug 1543 and the conductor 1513 on the insulator 1571 are shown. In the cross section, the height of the highest region of the upper surface of the plug 1543 is It is preferable that the height of the upper surface of the insulating film is higher than the height of the highest region of the insulating film.

[0517] In addition, the opening for forming the conductor 1513 is formed by removing a part of the insulator 1571. There is.

[0518] Here, as an example, silicon nitride is used as the insulator 1464a and carbon dioxide is used as the insulator 1581a. Silicon nitride is used. Here, at least one of the insulator 1571a and the insulator 1571 is For example, titanium nitride is used as the conductor 1513b. By using silicon nitride or silicon carbonitride, hydrogen contained in the silicon nitride or silicon carbonitride is converted into transistor 3. This can prevent the spread to 300.

[0519] Layer 1629 includes transistor 3300 and plugs such as plug 1544 and plug 1544b. Plugs such as plug 1544 and plug 1544b are formed by layer 1628. the conductor 1513, the gate electrode, the source electrode, or the like of the transistor 3300. The transistor 3300 is configured in the same manner as the transistor 20. The descriptions in Jista 2100 and other publications can be taken into consideration.

[0520] The transistor 3300 includes a conductor 1413, an insulator 1571a, an insulator 1402, and a conductor 1416a, conductor 1416b, conductor 1404, insulator 1408, and insulator 591. The configuration of the transistor 3300 can be understood by taking into consideration the configuration of the transistor 20. The conductor 1413 is the conductor 102, the insulator 1571a is the insulator 103, and the insulator 14 102 is the insulator 104, the conductor 1416a is the conductor 108a, and the conductor 1416b is the conductor 1 08b, conductor 1404 is conductor 114, insulator 1408 is insulator 116, insulator 591 In addition, in FIG. 33, the transistor 20 Although an insulator corresponding to the insulator 105 in the figure is not shown, it is of course possible to provide such an insulator. For example, a layer corresponding to the insulator 105 may be provided between the insulator 1585 and the insulator 1571a. An insulator may be provided.

[0521] As in the above embodiment, the insulator 1571 and the insulator 106a of the transistor 20 are A laminate of insulators (in this embodiment, insulator 1585, The amount of water or hydrogen contained in the laminate of the insulator 1571a and the insulator 1402 is small. As described above, the insulator 1571 is preferably an insulator having a function of blocking water and hydrogen. As an insulator, the oxides that become the insulator 106a and the semiconductor 106b of the transistor 20 are When forming the film, water and hydrogen are supplied to the oxide, and the insulators 1585 and 1571 are a, which is included in the insulator 1402. Therefore, when forming the oxide film, A laminate of the insulator 1585, the insulator 1571a and the insulator 1402, particularly the insulator If the amount of water or hydrogen contained in 1402 is small enough, the oxide will not contain water or hydrogen. The amount of water supplied can be reduced.

[0522] The conductors 1416a and 1416b are plugs formed in contact with their upper surfaces. It is preferable that 1544b be made of a material that has low permeability to the elements contained therein.

[0523] The conductor 1416a and the conductor 1416b may be a stacked film. Thus, the conductor 1416a and the conductor 1416b form a stack of the first and second layers. Here, a first layer is formed on the oxide layer 406b, and a second layer is formed on the first layer. The first layer is made of, for example, tungsten, and the second layer is made of, for example, tantalum nitride. Therefore, copper is used for the plug 1544b etc. Copper has low resistance and is suitable for plugs, wiring etc. On the other hand, copper is easily diffused and is used as a conductor in the semiconductor layer of a transistor. The diffusion of these elements into the gate insulating film or other parts may degrade the transistor characteristics. The conductors 1416a and 1416b contain tantalum nitride, so that the plug This may prevent copper contained in 1544b and the like from diffusing into oxide layer 406b.

[0524] In the semiconductor device illustrated in FIG. 27C of one embodiment of the present invention, plugs, wirings, and the like are used to improve the characteristics of semiconductor elements. When the semiconductor device contains elements and compounds that cause degradation, the elements and compounds may diffuse into the semiconductor device. It is preferable that the structure suppresses the above.

[0525] Layer 1630 includes insulator 1592, conductors such as conductor 1514, and plugs such as plug 1545. The plugs, such as plug 1545, connect to electrical conductors, such as electrical conductor 1514.

[0526] The layer 1631 includes a capacitor 3400. The capacitor 3400 includes the conductor 1516 and , a conductor 1517, and an insulator 1571. The insulator 1571 is The layer 1631 has a region sandwiched between the insulator 1594 and the conductor 1517. It is preferable to have a plug 1547 on the insulator 1517. The plug 1547 is connected to the insulator 15 It is preferable that the layer 1631 is formed so as to fill the opening of the layer 163. conductor 1516b connected to a plug having 0, and plug 1547 on conductor 1516b It is preferred that b.

[0527] The layer 1631 may also have a wiring layer that connects to the plug 1547 and the plug 1547b. In the example shown in FIG. 33, the wiring layer is a conductor connected to the plug 1547 and the plug 1547b. 1518, etc., plug 1548 on conductor 1518, insulator 1595, and plug 154 8 and an insulator 1599 on the conductor 1519. 8 is preferably formed so as to fill the opening of the insulator 1595. 599 has an opening over the conductor 1519 .

[0528] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0529] (Embodiment 5) In this embodiment, an imaging device including a transistor according to one embodiment of the present invention will be described. An example will be described.

[0530] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0531] FIG. 35A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) are arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 are each The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0532] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0533] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. , the peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290 One or more of these may be omitted.

[0534] As shown in FIG. 35B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0535] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel By combining a filter (color filter) that transmits light in a specific wavelength range with the pixel 212, This allows the acquisition of information for realizing color image display.

[0536] FIG. 36(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 36(A) is provided with a color filter that transmits light in the red (R) wavelength range. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits light in the green (G) wavelength range. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. and a sub-pixel 212 (hereinafter referred to as a sub-pixel 213) provided with a color filter that transmits light in the blue (B) wavelength range. The subpixel 212 functions as a photosensor. It can be done.

[0537] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, the pixel 211 in the nth row is connected to The wiring 248 and the wiring 249 are respectively denoted as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 36A, the sub-pixel 212R of the pixel 211 in the m-th column is written as follows: The wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0538] In addition, the imaging device 200 has color filters that transmit light in the same wavelength range of adjacent pixels 211. The sub-pixels 212 provided with the filters are electrically connected to each other via the switches. In Figure 36(B), the matrix is ​​arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The sub-pixel 212 of the pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is 36B shows an example of connection of sub-pixels 212 included in a pixel 211 placed in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. The sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are switched. 203.

[0539] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels 212 for detecting light in three different wavelength ranges. By providing the sensor 12, a full color image can be obtained.

[0540] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have four sub-pixels 21 for detecting light in different wavelength ranges. By providing 2, the color reproducibility of the acquired image can be further improved.

[0541] Also, for example, in FIG. 36(A), the sub-pixel 212 for detecting light in the red wavelength region and the sub-pixel 213 for detecting light in the green wavelength region are The sub-pixels 212 for detecting light in the long wavelength range and the sub-pixels 212 for detecting light in the blue wavelength range The ratio of the number of pixels (or the ratio of the light receiving area) does not have to be 1:1:1. The area ratio may be a Bayer array with red:green:blue = 1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0542] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that there are two or more. By providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy is increased, and imaging The reliability of the device 200 can be improved.

[0543] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0544] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0545] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 37(A), a lens 255 and a filter 25 formed in the pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0546] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is reflected by the wiring 257. Therefore, as shown in Figure 37(B), A lens 255 and a filter 254 are arranged on the conversion element 220 side, and the photoelectric conversion element 220 It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. can be done.

[0547] As the photoelectric conversion element 220 shown in FIG. 37, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0548] The photoelectric conversion element 220 is made of a material that has the function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be a ceramic. Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0549] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 22 that has a light absorption coefficient over a wide wavelength range, such as X-rays and gamma rays 0 can be achieved.

[0550] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2. The pixel 212 may have a first filter.

[0551] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of configuring a pixel using the above will be described.

[0552] 38(A) and 38(B) are cross-sectional views of elements that constitute the imaging device. The imaging device shown in A) is a silicon-based transistor provided on a silicon substrate 300. 351, a transistor using an oxide semiconductor stacked on the transistor 351 352 and transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 3 70 and the wiring 371. The lead 361 has an electrical connection with the plug 370 via the low resistance region 363 .

[0553] The imaging device also includes a transistor 351 and a photodiode 352 provided on the silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and a layer 320, which are provided in contact with the layer 320 and have a transistor 352 and a transistor 353. and a layer 330 provided in contact with the layer 330 and having wiring 372 and wiring 373. It has 40.

[0554] In the example of the cross-sectional view of FIG. 38(A), the transistor 35 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the surface opposite to the surface on which the photodiode 1 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light receiving surface of 360 may be the same as the surface on which the transistor 351 is formed.

[0555] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0556] If a pixel is constructed using only silicon transistors, layer 330 can be omitted. An example of a cross-sectional view in which the layer 330 is omitted is shown in FIG.

[0557] The silicon substrate 300 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide The substrate has aluminum gallium, indium phosphide, gallium nitride, or an organic semiconductor. You can also be there.

[0558] Here, a layer 310 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 330 having the resistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.

[0559] The hydrogen in the insulator provided near the channel forming region of the transistor 351 is converted into silicon dioxide. This has the effect of terminating the ring bonds and improving the reliability of the transistor 351. , hydrogen in an insulator provided near the transistor 352 and the transistor 353, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 380 having a function of blocking hydrogen is provided between them. By confining hydrogen below the insulator 380, the transistor The reliability of the insulator 351 can be improved. Since hydrogen diffusion to the layer above 380 can be suppressed, the transistor 352 and the transistor The reliability of the transistor 353 can be improved.

[0560] As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used. There are.

[0561] In the cross-sectional view of FIG. 38(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0562] Also, as shown in FIGS. 39(A1) and 39(B1), part or all of the imaging device may be curved. FIG. 39(A1) shows the state in which the imaging device is curved in the direction of the dashed line X1-X2 in the figure. FIG. 39(A2) is a cross-sectional view of the part indicated by the dashed line X1-X 2 in FIG. 39(A1). FIG. 39(A3) is a cross-sectional view of the part indicated by the dashed line Y1- Y2 in FIG. 39(A1).

[0563] FIG. 39(B1) shows the state in which the imaging device is curved in the direction of the dashed line X3-X4 in the figure and also curved in the direction of the dashed line Y3-Y4 in the figure. FIG. 39(B2) is a cross-sectional view of the part indicated by the dashed line X3-X4 in FIG. 39(B1). FIG. 39(B3) is a cross-sectional view of the part indicated by the dashed line Y3-Y4 in FIG. 39(B1). 39(B1). a cross-sectional view of the part indicated by the dashed line Y3-Y4 in FIG.

[0564] By curving the imaging device, curvature of the image plane and aberration can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lens elements for aberration correction can be reduced, miniaturization and weight reduction of an electronic device or the like using the imaging device can be achieved. Also, the quality of the captured image can be improved. .

[0565] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0566] (Embodiment 6) In this embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described memory device will be described.

[0567] <Configuration of CPU> FIG. 40 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0568] The CPU shown in FIG. 40 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 40 is merely an example of a simplified configuration. There are a wide variety of configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 40 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0569] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0570] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0571] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0572] In the CPU shown in FIG. 40, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0573] In the CPU shown in FIG. 40, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in the register 1196. That is, the register 1196 In the memory cell of the Select whether to hold data by flip-flop. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention in the capacitor is selected, the data is rewritten to the capacitor. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0574] FIG. 41 is an example circuit diagram of a storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 that prevents stored data from volatilizing when turned off, a switch 1203, and a switch 1204. , a logic element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0575] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, the gate of the transistor 1209 is configured to be grounded via a load such as a resistor. .

[0576] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conducting or non-conducting state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The conducting or non-conducting state of transistor 1214 is selected.

[0577] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0578] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0579] A control signal WE is input to the gate of the transistor 1209. The switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. This becomes:

[0580] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 41, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0581] In FIG. 41, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0582] In addition, in FIG. 41, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or The transistor may have a channel formed in a silicon substrate. All transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements in addition to the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0583] The circuit 1201 in FIG. 41 can be, for example, a flip-flop circuit. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0584] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0585] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of transistors whose channels are formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitor 1208 is maintained for a long period of time even when power supply voltage is not supplied to the capacitor 1208. In this way, the storage element 1200 maintains its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0586] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0587] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the state of the transistor 1210 changes in response to the signal held by the capacitor element 1208. The state (conducting or non-conducting) can be determined and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original The signal can be read out accurately.

[0588] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0589] Although the storage element 1200 has been described as being used in a CPU, the storage element 1200 can also be used in a DSP ( Digital Signal Processor), custom LSI, PLD (Pr LSIs such as programmable logic devices, RF (Radio Frequency It can also be applied to high-speed (high-speed) devices.

[0590] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0591] (Embodiment 7) In this embodiment, a display device including a transistor according to one embodiment of the present invention will be described. This will be explained with reference to FIGS. 42 and 43.

[0592] <Display device configuration> Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) These include organic EL displays, etc. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0593] The display device described below is a panel in which a display element is sealed, and a connector for the panel. This includes modules in which ICs including controllers are mounted.

[0594] The display device shown below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and printers at the end of TCP The IC (integrated circuit) is mounted directly on the module or display element with a printed wiring board using the COG method. All modules mounted on the display device are also included in the display device.

[0595] 42A and 42B are diagrams illustrating an example of an EL display device according to one embodiment of the present invention. FIG. 42(B) is a top view showing the entire EL display device. FIG. 42(C) is a cross section of MN corresponding to a part of the dashed line MN in FIG. 42(B). .

[0596] FIG. 42(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0597] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple When multiple locations are expected, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations of only some of the terminals possessed by devices such as It may be possible to configure a different embodiment.

[0598] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0599] The EL display device shown in FIG. 42(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitor 742 and a light emitting element 719 .

[0600] Note that FIG. 42(A) is an example of a circuit configuration, and therefore, if a transistor is added, Conversely, at each node in FIG. 42(A), it is possible to It is also possible to avoid adding passive elements.

[0601] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitor element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0602] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switching element 743 is a transistor manufactured through the same process as the transistor 741. The use of transistor 74 can improve productivity of the EL display device. 1 and / or the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0603] 42(B) is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealing material 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 covers the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively, the driving circuit 736 may be disposed outside the sealing material 734 .

[0604] FIG. 42(C) is a cross-sectional view of the EL display device corresponding to a part of the dashed line MN in FIG. 42(B). is.

[0605] In FIG. 42C, a conductor 704a and a conductor Insulator 712a on body 704a, insulator 712b on insulator 712a, and insulator 712 semiconductor 706a and semiconductor 706b that are on top of conductor 704b and overlap with conductor 704a; Conductors 716a and 716b in contact with semiconductor 706a and semiconductor 706b, respectively. 6b, an insulator 718a on the conductor 716a and the conductor 716b, and an insulator 718a an insulator 718b on the insulator 718b; an insulator 718c on the insulator 718c; The transistor 706b has a structure including a conductor 714a overlapping with the semiconductor 706b. The structure of 41 is an example, and it may be different from the structure shown in FIG. 42(C).

[0606] Therefore, in the transistor 741 shown in FIG. 42C, the conductor 704a is The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as gate electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. The electrical characteristics of the semiconductors 706a and 706b may change when exposed to light. Therefore, any of the conductors 704a, 716a, 716b, and 714a It is preferable that one or more of them have a light-blocking property.

[0607] The interface between the insulator 718a and the insulator 718b is shown by a broken line. For example, the insulators 718a and 718b may be Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method.

[0608] In FIG. 42C, a conductor 704b on a substrate and a conductor 704b Insulator 712a on top, insulator 712b on insulator 712a, and insulator 712b on A conductor 716a overlapping the conductor 704b, an insulator 718a on the conductor 716a, and an insulating Insulator 718b on insulator 718a, insulator 718c on insulator 718b, and insulator 718 and a conductor 714b that is on top of the conductor 716c and overlaps the conductor 716a. In the overlapping region of the insulator 714b, a part of the insulator 718a and the insulator 718b is removed. The structure shown is:

[0609] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a functions as the other electrode.

[0610] Therefore, the capacitor 742 can be formed using the same film as that of the transistor 741. It is also preferable that the conductors 704a and 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0611] A capacitor 742 shown in FIG. 42C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 42(C) has high display quality. The capacitor element 742 shown in FIG. 1 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulators 718a and 718b have a structure in which parts thereof are removed. The capacitive element according to one embodiment is not limited to this. A structure in which a part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b is used. It's okay to have it.

[0612] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to the conductor 716a, which serves as the source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. 1 may be electrically connected to the transistor 741 through an opening in the insulator 720.

[0613] A partition 784 having an opening that reaches the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 and is in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0614] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0615] 43(A) is a circuit diagram...

Claims

1. a first transistor having a first channel formation region; a second transistor having a second channel formation region; a third transistor having a third channel formation region; a capacitive element; a first insulating layer above the first channel formation region; a first conductive layer provided above the first insulating layer and having a region overlapping the first channel formation region; a second insulating layer above the first conductive layer; a second conductive layer and a third conductive layer above the second insulating layer; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer provided above the second channel formation region and having a region overlapping with the second conductive layer via the second channel formation region; a fifth conductive layer provided above the third channel formation region and having a region overlapping with the third conductive layer via the third channel formation region; a fourth insulating layer above the fourth conductive layer and above the fifth conductive layer; a sixth conductive layer above the fourth insulating layer; a fifth insulating layer above the sixth conductive layer; a seventh conductive layer provided above the fifth insulating layer and having a region overlapping with the sixth conductive layer; the second channel formation region and the third channel formation region are located above the third insulating layer; the second channel formation region has a region overlapping with the second conductive layer, the third channel formation region has a region overlapping with the third conductive layer, the sixth conductive layer functions as one electrode of the capacitor, the seventh conductive layer functions as the other electrode of the capacitor element, the sixth conductive layer is electrically connected to the second channel formation region and the third channel formation region; the sixth conductive layer is electrically connected to the first conductive layer; the first channel formation region includes silicon; the second channel formation region includes an oxide semiconductor; the third channel formation region includes an oxide semiconductor; the seventh conductive layer has regions overlapping with the second conductive layer and the fourth conductive layer in a cross-sectional view of the second transistor in a channel length direction; the seventh conductive layer has regions overlapping with the third conductive layer and the fifth conductive layer in a cross-sectional view in a channel length direction of the third transistor.

2. a first transistor having a first channel formation region; a second transistor having a second channel formation region; a third transistor having a third channel formation region; a capacitive element; a first insulating layer above the first channel formation region; a first conductive layer provided above the first insulating layer and having a region overlapping the first channel formation region; a second insulating layer above the first conductive layer; a second conductive layer and a third conductive layer above the second insulating layer; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer provided above the second channel formation region and having a region overlapping with the second conductive layer via the second channel formation region; a fifth conductive layer provided above the third channel formation region and having a region overlapping with the third conductive layer via the third channel formation region; a fourth insulating layer above the fourth conductive layer and above the fifth conductive layer; a sixth conductive layer above the fourth insulating layer; a fifth insulating layer above the sixth conductive layer; a seventh conductive layer provided above the fifth insulating layer and having a region overlapping with the sixth conductive layer; the second channel formation region and the third channel formation region are located above the third insulating layer; the second channel formation region has a region overlapping with the second conductive layer, the third channel formation region has a region overlapping with the third conductive layer, the sixth conductive layer functions as one electrode of the capacitor, the seventh conductive layer functions as the other electrode of the capacitor element, the sixth conductive layer is electrically connected to one of the source and the drain of the second transistor and one of the source and the drain of the third transistor; the sixth conductive layer is electrically connected to the first conductive layer; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; the first channel formation region includes silicon; the second channel formation region includes an oxide semiconductor; the third channel formation region includes an oxide semiconductor; the seventh conductive layer has regions overlapping with the second conductive layer and the fourth conductive layer in a cross-sectional view of the second transistor in a channel length direction; the seventh conductive layer has regions overlapping with the third conductive layer and the fifth conductive layer in a cross-sectional view in a channel length direction of the third transistor.

3. a first transistor having a first channel formation region; a second transistor having a second channel formation region; a third transistor having a third channel formation region; a capacitive element; Wiring and a first insulating layer above the first channel formation region; a first conductive layer provided above the first insulating layer and having a region overlapping the first channel formation region; a second insulating layer above the first conductive layer; a second conductive layer and a third conductive layer above the second insulating layer; a third insulating layer above the second conductive layer and above the third conductive layer; a fourth conductive layer provided above the second channel formation region and having a region overlapping with the second conductive layer via the second channel formation region; a fifth conductive layer provided above the third channel formation region and having a region overlapping with the third conductive layer via the third channel formation region; a fourth insulating layer above the fourth conductive layer and above the fifth conductive layer; a sixth conductive layer above the fourth insulating layer; a fifth insulating layer above the sixth conductive layer; a seventh conductive layer provided above the fifth insulating layer and having a region overlapping with the sixth conductive layer; the second channel formation region and the third channel formation region are located above the third insulating layer; the second channel formation region has a region overlapping with the second conductive layer, the third channel formation region has a region overlapping with the third conductive layer, the sixth conductive layer functions as one electrode of the capacitor, the seventh conductive layer functions as the other electrode of the capacitor element, the sixth conductive layer is electrically connected to one of the source and the drain of the second transistor and one of the source and the drain of the third transistor; the sixth conductive layer is electrically connected to the first conductive layer; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; the seventh conductive layer is electrically connected to the wiring; the first channel formation region includes silicon; the second channel formation region includes an oxide semiconductor; the third channel formation region includes an oxide semiconductor; the seventh conductive layer has regions overlapping with the second conductive layer and the fourth conductive layer in a cross-sectional view of the second transistor in a channel length direction; the seventh conductive layer has regions overlapping with the third conductive layer and the fifth conductive layer in a cross-sectional view in a channel length direction of the third transistor.

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