Photonic Integrated Circuits

Abstract

The device includes a substrate, a dielectric layer on the substrate, a waveguide in the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and monolithically integrated with the substrate. The photodetector is configured to operate at a low temperature, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes a thermal isolation structure and an optical isolation structure. Techniques for fabricating a monolithic photonic device including a thermal isolation structure and an optical isolation structure are also described.

Description

[Technical Field]

[0001] Cross-referencing with other applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 039,840, filed June 16, 2020, for "Photonic Integrated Circuits," which is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002]

[0001] Photonic integrated circuits, such as those in photonic quantum computing systems, may include a variety of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. Integrating different types of integrated optical components onto a single chip can be challenging due to the different processes and materials used to fabricate these integrated optical components.

[0003]

[0002] Integrating different types of integrated optical components onto a single chip can also adversely affect the performance of photonic integrated circuits due to, for example, noise caused by stray light or heat dissipation from heat-generating components to other components. For example, highly sensitive photodetectors, such as single-photon detectors, can be used in many photonic quantum technologies, such as quantum cryptography and quantum computing. Due to their high sensitivity, these photodetectors can be highly susceptible to noise, such as unwanted ambient or stray light, which can reach the photodetector via direct or indirect paths. Certain thermo-optical components, such as thermal tuners for tuning filters, may use heaters. Heat generated by the heaters can be dissipated to other areas of the photonic integrated circuit, reducing the efficiency of the thermo-optical components and / or increasing the temperature of other components that must operate at low temperatures, such as cryogenic temperatures. Summary of the Invention

[0004]

[0003] The present disclosure relates generally to photonic integrated circuits. More specifically, the present disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and / or thermal isolation structures. For example, the monolithic photonic integrated circuit may include optical isolation structures to prevent background light from reaching high-sensitivity photodetectors (e.g., superconducting nanowire single-photon detectors) within the photonic integrated circuit (PIC) to achieve high sensitivity and a high signal-to-noise ratio (SNR). The monolithic photonic integrated circuit may also include thermal isolation structures to reduce or prevent heat dissipation from some thermo-optical devices to other regions of the photonic integrated circuit. Monolithic photonic integrated circuits with optical and / or thermal isolation structures may be fabricated using a combination of semiconductor processing techniques. Various invention embodiments, including methods, processes, systems, apparatus, and the like, are described herein.

[0005] According to certain embodiments, a photonic integrated circuit may include a photonic integrated circuit for optical quantum computing. A photonic integrated circuit may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, and delay lines. For example, a photonic integrated circuit may include a single-photon generator for generating individual photons, filters and switches that may be tuned or controlled by a thermo-optical device or other tuner, and a single-photon detector for detecting individual photons. Different types of integrated optical components may operate at different temperatures. For example, a single-photon detector may include a superconducting nanowire single-photon detector that may operate at low temperatures, while a thermo-optical device may operate at much higher temperatures.

[0006] According to certain embodiments, a photonic integrated circuit may include isolation structures fabricated using a CMOS back end of line (BEOL) process to prevent ambient or stray light from reaching the photodetector directly or indirectly. The isolation structures may include, for example, metal layers, arrays of vias, air gaps, trenches filled with reflective or absorbing materials, etc. The isolation structures may provide local and / or global isolation to the photodetector and / or waveguide at different locations, including the input and output ports of the photonic integrated circuit and the photodetector, such that scattered, reflected, diffused, or otherwise leaked light from either the light source or the photonic integrated circuit is partially or completely blocked, thereby preventing it from reaching the photodetector.

[0007] The systems, devices, and methods disclosed herein can improve the signal-to-noise ratio of a photodetector by preventing unwanted light from reaching a highly sensitive photodetector. In this way, the photodetector may achieve high sensitivity and have minimal dead time. The isolation structure may be fabricated using standard CMOS back-end-of-line (BEOL) processes or CMOS-compatible BEOL processes. Some isolation may be local, requiring no additional global layers or materials in the stackup and therefore may not add additional thermal load to the circuit or device.

[0008] According to certain embodiments, a photonic integrated circuit may include thermal isolation structures, such as trenches and large undercut regions, adjacent to a heat-generating device. The thermal isolation structures may be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet / dry etching. The thermal isolation structures may conserve heat in localized areas to improve the efficiency of the thermo-optical device and reduce the burden on cooling areas that may require lower temperature operation.

[0009]

[0008] Aspects of the present disclosure are illustrated by way of example. Non-limiting and non-exhaustive aspects are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various views unless otherwise specified: [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a simplified block diagram illustrating an example of an optical device including a photonic integrated circuit (PIC) and a highly sensitive photodetector according to an embodiment. [Figure 2] FIG. 2 illustrates an example of stray light isolation at input and / or output ports of a photonic integrated circuit according to an embodiment. [Figure 3] FIG. 3 illustrates an example of locally isolating photodetectors using various isolation structures according to an embodiment. [Figure 4A] 4A-4D show another example of locally isolating photodetectors using various isolation structures in an optical device according to an embodiment: Figure 4A is a cross-sectional view of an optical device including a photodetector and a light isolation structure. [Figure 4B] FIG. 4B is a perspective view of the optical device of FIG. 4A. [Figure 4C] FIG. 4C is a top view of the optical device of FIG. 4A. [Figure 4D] FIG. 4D is a cross-sectional top view of the optical device of FIG. 4A. [Figure 5] FIG. 5 is a flowchart illustrating an example method for fabricating various optical isolation structures in a photonic integrated circuit according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view of an example photonic integrated circuit including a photodetector fabricated using a front end of a line process according to one embodiment. [Figure 7] FIG. 7 is a cross-sectional view of an example photonic integrated circuit having vias or trenches etched into an oxide layer using the back end of a line process according to an embodiment. [Figure 8]FIG. 8 is a cross-sectional view of an example photonic integrated circuit having vias or trenches etched into an oxide layer filled with a reflective or absorptive material (eg, metal) according to an embodiment. [Figure 9] FIG. 9 is a cross-sectional view of an example photonic integrated circuit with a metal cover fabricated on a metal layer for localized isolation of photodetectors according to one embodiment. [Figure 10] FIG. 10 is a cross-sectional view of an example photonic integrated circuit after additional BEOL processing according to an embodiment. [Figure 11] FIG. 11 is a cross-sectional view of an example photonic integrated circuit including deep trenches etched into a substrate of the photonic integrated circuit according to one embodiment. [Figure 12] FIG. 12 is a cross-sectional view of an example photonic integrated circuit including deep trenches filled with a reflective or absorptive material within the substrate of the photonic integrated circuit according to an embodiment. [Figure 13] FIG. 13 is a cross-sectional view of an example photonic integrated circuit illustrating optical isolation due to various isolation structures in the photonic integrated circuit according to some embodiments. [Figure 14] FIG. 14 is a flowchart illustrating an example method for fabricating a photonic integrated circuit according to an embodiment. [Figure 15] FIG. 15 illustrates an example of a type of base PIC according to one embodiment. [Figure 16] FIG. 16 shows an example of additional layers that can be deposited for use in a tri-layer lithography process according to an embodiment. [Figure 17] FIG. 17 shows an example of an etched PIC structure according to one embodiment. [Figure 18] FIG. 18 shows an example of an oxide layer on an etched PIC according to one embodiment. [Figure 19] FIG. 19 illustrates an example of an etching process for forming trench structures in thermal isolation regions according to an embodiment. [Figure 20]FIG. 20 illustrates an example of an etching process for forming an undercut structure according to an embodiment. [Figure 21] FIG. 21 illustrates an example of an undercut structure according to an embodiment. [Figure 22] FIG. 22 illustrates an example process for forming an oxide layer that seals trench and undercut structures according to an embodiment. [Figure 23] FIG. 23 shows examples of additional layers that can be deposited for use in a tri-layer lithography process according to certain embodiments. [Figure 24] FIG. 24 shows an example of a contact hole for forming an electrical contact according to an embodiment. [Figure 25] FIG. 25 shows an example of an additional layer that can be deposited for use in a tri-layer lithography process according to an embodiment. [Figure 26] FIG. 26 shows an example of a contact hole for forming electrical contacts for a photodetector according to an embodiment. [Figure 27] FIG. 27 illustrates an example of an electrical contact for a photonic integrated circuit according to an embodiment. [Figure 28] FIG. 28 illustrates an example of a scattering mitigation structure according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0037] The technology disclosed herein relates generally to photonic integrated circuits. More specifically, the present disclosure relates to techniques for integrating different types of components onto a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and / or thermal isolation structures. Various invention embodiments are described herein, including methods, processes, systems, devices, and the like.

[0012]

[0038] According to certain embodiments, photonic integrated circuits may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. For example, a photonic integrated circuit may include a photonic integrated circuit for optical quantum computing, which may include single-photon generators for generating individual photons, filters and switches that may be tuned or controlled by thermo-optical devices or other tuners, and single-photon detectors for detecting individual photons. Different types of integrated optical components may operate at different temperatures. For example, a single-photon detector may include a superconducting nanowire single-photon detector that may operate at low temperatures, while a thermo-optical device may operate at much higher temperatures.

[0013]

[0039] Monolithic photonic integrated circuits may include optical isolation structures to prevent background light within the photonic integrated circuit (PIC) from reaching highly sensitive photodetectors (e.g., single-photon detectors) to achieve high sensitivity and a high signal-to-noise ratio (SNR). Monolithic photonic integrated circuits may also include thermal isolation structures to reduce or prevent heat dissipation from one thermo-optical device to another region of the photonic integrated circuit. Monolithic photonic integrated circuits with optical and / or thermal isolation structures may be fabricated using a combination of semiconductor processing techniques.

[0014]

[0040] Highly photosensitive photodetectors, such as single-photon detectors (e.g., superconducting nanowire SPDs (SNSPDs)), used in many photonic quantum technologies, can be extremely sensitive to many types of optical radiation. Often, highly sensitive photodetectors cannot achieve their potential sensitivity or SNR due to various noise sources, such as noise caused by background light, including stray light within the system and ambient light entering the system. The techniques disclosed herein can reduce or prevent unwanted background light (such as stray light or ambient light) from reaching highly sensitive photodetectors (e.g., superconducting nanowire single-photon detectors) in photonic integrated circuits in order to achieve high sensitivity and a high signal-to-noise ratio.

[0015]

[0041] According to certain embodiments, to improve the sensitivity and SNR of the photodetector, the photodetector (e.g., an SNSPD) may be optically isolated from background radiation (e.g., ambient or stray light) using reflective or absorbing structures surrounding the photodetector. In some embodiments, additional isolation structures may be added at any other location within the PIC where background light may propagate before reaching the photodetector to reduce the number of stray photons that may reach the area of ​​the photodetector. For example, because one of the main sources of background or stray light in a photonic integrated circuit is light that is reflected, scattered, or diffused at the optical input and / or optical output ports (e.g., input or output waveguide couplers) to the PIC due to imperfect coupling of light into or out of the PIC (e.g., waveguides), isolation structures may be used at the optical input and / or optical output ports to prevent stray light from entering the PIC. Thus, the probability of stray or ambient light entering the waveguide or reaching the area of ​​the photodetector may be significantly reduced. Furthermore, even if background light reaches the area where the photodetector is located, the local isolation structure surrounding the photodetector can block the background light from being detected by the photodetector. In various embodiments, the optical isolation structure can be fabricated using standard CMOS back-end-of-line (BEOL) processes or other CMOS-compatible manufacturing processes.

[0016]

[0042] According to certain embodiments, a photonic integrated circuit may include heaters for tuning several integrated optical components, such as optical filters, optical switches, and optical interferometers. The photonic integrated circuit may also include thermal isolation structures, such as trenches and large undercut regions adjacent to the heaters. The thermal isolation structures may conserve heat in localized areas to improve the efficiency of thermo-optical devices and reduce the burden on cooling areas, including devices that must operate at low temperatures, such as SNSPDs. The thermal isolation structures may also be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet / dry etching.

[0017]

[0043] Several exemplary embodiments are described with reference to the accompanying drawings, which form a part of this specification. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of the embodiments will provide those skilled in the art with an effective description for practicing one or more embodiments. It will be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the present disclosure. In the following description, for purposes of explanation, specific details are set forth to provide a thorough understanding of particular inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and descriptions are not intended to be limiting. As used herein, the words "example" or "exemplary" are used to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0018]

[0044] FIG. 1 is a simplified block diagram illustrating an example of an optical device 100 including a photonic integrated circuit (PIC) 120 and a highly sensitive photodetector 130, according to one embodiment. The PIC 120 may include a photonic circuit formed by waveguides and other active or passive optical components, such as filters, resonators, splitters, optical amplifiers, etc. The optical device may include a light source, such as a laser 110, which may be an ultrafast (e.g., picosecond or femtosecond) pulsed laser. In some embodiments, the light source may be an external light source and may be connected to the PIC 120, for example, via one or more optical fibers. Light from the light source may be coupled to the waveguides within the PIC 120 via a coupler, such as a grating coupler or an edge coupler. However, achieving very high coupling efficiencies may be difficult. For example, in many cases, coupling efficiencies may be less than 90%, 75%, 60%, or even 50%. Therefore, a significant amount of light from the light source may not enter the waveguides within the PIC 120 and may instead be reflected, scattered, or diffused, becoming stray light 140. Stray light 140 may be reflected, refracted, diffracted, or otherwise deflected by structures or components within optical device 100, such as metal layers, interfaces between dissimilar materials, etc. Thus, some of the stray light 140 may ultimately reach photodetector 130. Additionally, portions of PIC 120 may leak light from the desired path. For example, instead of being guided into the photonic circuit to reach photodetector 130, light may be coupled out of the waveguide, for example, when the waveguide has a sharp turn or if there is a defect in the waveguide or other photonic circuit. Light that leaks from the photonic circuit may become stray light 150, which may also be at least partially deflected to photodetector 130. In some embodiments, ambient light may also enter PIC 120, for example, through an oxide layer and / or be reflected by a metal layer.

[0019]

[0045] The photodetector 130 may be a highly sensitive photodetector, such as a single photon detector. For example, in some embodiments, the photodetector 130 may include a superconducting nanowire single-photon detector capable of detecting individual photons. In one embodiment, the photodetector 130 may include a waveguide coupled to a superconducting nanowire, such as a niobium-germanium nanowire, which may have an ultralow resistance in the superconducting state. The superconducting nanowire may be photosensitive or photoactive, such as absorbing a photon. For example, a photon passing through the waveguide may be absorbed by the superconducting nanowire, causing the superconducting nanowire to become non-superconducting (i.e., change its resistance or impedance). The resistance or impedance change in the nanowire may be converted into an electrical detection signal (e.g., a current or voltage signal) indicating that one or more photons have been detected.

[0020]

[0046] If at least some of the stray light 140, 150 reaches the photodetector 130, it may change the state of the superconducting nanowire, and the photodetector 130 may generate a detection signal indicating that one or more photons are detected, even though no photons reach the superconducting nanowire from the waveguide, or the magnitude of the detection signal may not correctly indicate the number of photons reaching the photodetector from the waveguide. Thus, a false or incorrect (e.g., noisy) detection signal may be generated by the photodetector 130, which may reduce the effective sensitivity or SNR of the photodetector 130.

[0021]

[0047] According to certain embodiments, optical isolation structures may be added at different locations in optical device 100 to block stray or ambient light from reaching photodetector 130. For example, isolation structure 160 may be added to the input port of PIC 120, isolation structure 170 may be fabricated to surround photodetector 130, and isolation structure 180 may be added anywhere within optical device 100 where background light may otherwise propagate. Details of several embodiments of optical isolation structures and their fabrication processes are described in the Examples below.

[0022]

[0048] 2 illustrates an example of stray light isolation at input and / or output ports of a photonic integrated circuit 200 according to an embodiment. Figure 2 illustrates a cross-sectional view of a PIC 200, which may include a waveguide 210 fabricated on a substrate 205 (e.g., a silicon handle wafer). PIC 200 may also include an input port 220 for waveguide 210 and an output port 230 for waveguide 210. Waveguide 210 may carry light from input port 220 to the interior of PIC 200, where several photosensitive components may be located, or may guide light out of PIC 200 via output port 230.

[0023]

[0049] As mentioned above, at the input port 220 or the output port 230, light may not be completely coupled into or out of the waveguide 210. A significant portion of the input or output light may enter the PIC 200 through a path other than the waveguide 210. In some cases, approximately 10 photons may enter the PIC 200 as stray light in each laser pulse. To prevent these photons from reaching the interior of the PIC 200, one or more optical isolation structures may be fabricated at the input and / or output ports. For example, as illustrated in FIG. 2, the PIC 200 may include one or more metal trenches 240 and one or more deep trenches 260, which may act as the isolation structures 160 shown in FIG. 1. The metal trenches 240 may include a metal layer that is thick enough to block (e.g., reflect or absorb) incident photons. Metal trench 240 may act as a mirror-like barrier, for example, extending from metal 1 (M1, which may be about 1 μm above waveguide 210) to substrate 205 (which may be about 2-3 μm below waveguide 210) to block light that may propagate within the cladding of waveguide 210 from reaching the interior of PIC 200. Deep trench 260 may extend through substrate 205 of PIC 200 and may be empty (i.e., an air gap) or filled with a reflective or absorptive material to at least partially reflect or absorb incident photons that may propagate within or be scattered from substrate 205 so that the photons do not enter the cladding of the waveguide.

[0024]

[0050] A gap 250 may exist between adjacent metal trenches 240 such that waveguide 210 may pass through the gap between metal trenches 240. A gap 270 may exist between adjacent deep trenches 260 such that waveguide 210 may be supported by the substrate at gap 270. As shown in FIG. 2 , gap 250 and gap 270 may be misaligned and offset from each other by a certain distance such that gap 250 may not be within the line of sight of stray photons from input port 220 and therefore stray photons from input port 220 may not pass through gap 250 but instead be blocked by metal trench 240.

[0025]

[0051] FIG. 3 illustrates an example of using various isolation structures to locally isolate a photodetector 350 in a photonic integrated circuit 300 according to an embodiment. The PIC 300 may include a substrate 305 (e.g., a silicon handle wafer). A waveguide 310 may be formed on the substrate 305, where the waveguide 310 may include multiple turns for changing direction. Optical isolation structures, such as a top metal cover 320, a metal trench 330, and a deep trench 340, may be fabricated within the PIC 300 to surround and isolate the waveguide 310 and the photodetector 350. The optical isolation structure illustrated in FIG. 3 may be a specific embodiment of the isolation structure 170 in FIG. 1 and may form an isolation structure comparable to a castellated structure.

[0026]

[0052] As illustrated in FIG. 3 , the waveguide 310 may carry signal light from the photonic circuitry within the PIC 300 to the photodetector 350 (e.g., an SNSPD), where the signal light can be detected. Similar to the deep trench 260, the deep trench 340 may include an air gap that passes completely through the substrate 305, or may be filled with a reflective or absorbing material. In some embodiments, the deep trench 340 may pass partially through the substrate 305. The deep trench may isolate the photodetector 350 from light that may propagate within or be scattered from the substrate 305. The metal trench 330 may be similar to the metal trench 240 and may create a mirror-like barrier that may extend from M1 to the substrate 305, as described above with respect to FIG. 2 . In some embodiments, the metal trench 330 may include multiple nested rings centered around the photodetector 350, where an inner ring may be surrounded by one or more outer rings. Each ring may include an opening through which the waveguide 310 may pass. The openings in each ring may be on a different side (e.g., opposite or adjacent side) relative to the openings in adjacent rings. The metal trench 330 may block light that may propagate within the cladding of the waveguide 310 from reaching the photodetector 350. The top metal cover 320 may function as a roof for the light blocking structure, which may be compared to a castle-like structure, and may prevent light from reaching the photodetector 350 from above the photodetector 350 and the PIC 300.

[0027]

[0053] 4A to 4D show another example of locally isolating a photodetector 470 using various isolation structures in an optical device 400 according to an embodiment. FIG. 4A is a cross-sectional view of the optical device 400 including the photodetector 470 and an optical isolation structure surrounding the photodetector 470. FIG. 4B is a perspective view of the optical device 400 shown in FIG. 4A. The optical device 400 may include a substrate 410 (e.g., a silicon handle wafer), a barrier oxide (BOX) layer 420 (e.g., silicon dioxide), a waveguide 440 formed on the BOX layer 420, and a low-temperature oxide (LTO) layer 430 covering the waveguide 440. The optical device 400 may also include an array of vias 450 and a top metal cover 460, which may be formed on a metal 1 layer.

[0028]

[0054] Figure 4C is a top view of the optical device 400 of Figure 4A. Figure 4C shows a top metal cover 460 that covers the photodetector 470 from above so that background light cannot reach the photodetector 470 from above, where the top metal cover 460 may be part of the Metal 1 layer.

[0029]

[0055] 4D is a cross-sectional top view of the optical device 400 of FIG. 4A. FIG. 4D shows the arrangement of an array of vias 450 and a photodetector 470. As shown, the array of vias 450 may be arranged in a two-dimensional array, where the vias in one row (or column) may be offset from the vias in an adjacent row (or column) so that the array of vias may effectively form a wall. The photodetector 470 may include a photoactive nanowire 480 (e.g., a niobium-germanium nanowire) on the waveguide 440.

[0030]

[0056] FIG. 5 is a flowchart 500 illustrating an example of a method for fabricating various optical isolation structures in a photonic integrated circuit according to an embodiment. While FIG. 5 describes operations in a sequential flow, some operations may be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may include additional steps not included in the figure. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with other operations.

[0031]

[0057] Optionally, in block 510, a waveguide layer may be formed on a barrier oxide layer of a PIC, such as the BOX layer 420 shown in FIGS. 4A and 4B. The waveguide layer may be patterned and etched, for example, using photolithography techniques, to form waveguide cores and / or input / output couplers. In block 520, an optically active layer, such as a niobium-germanium layer, may be deposited on the waveguide layer. The optically active layer may be patterned and etched to form nanowires in the region of the waveguide core. The processing in blocks 510 and 520 may be part of a front-end of line process in a CMOS process.

[0032]

[0058] 6 is a cross-sectional view of an example of a photonic integrated circuit 600 including a photodetector fabricated using the front-end of line process in blocks 510 and 520 according to an embodiment. PIC 600 may include a substrate 610 (e.g., a silicon handle wafer), a BOX layer 620 formed on the substrate 610, various devices on the device layer (e.g., an optical input / output coupler 640, a waveguide 650, and a photodetector including a waveguide 660 and a nanowire 670 including an optically active material), and an oxide layer 630 covering the device layer. Optical input / output coupler 640 may include a grating coupler. Oxide layer 630 and BOX layer 620 may act as cladding for waveguide 650. In one example, oxide layer 630 may have a thickness of about 1 μm.

[0033]

[0059] In block 530, vias or trenches may be etched in the oxide layer down to the substrate. For example, a patterned mask layer may be formed on the oxide layer (e.g., the LTO layer and the BOX layer), and wet or dry etching techniques may be used to etch vias (holes) or trenches in the oxide layer, which may have a total thickness of, for example, 3-4 μm.

[0034]

[0060] 7 is a cross-sectional view of an example of a photonic integrated circuit 700 having a via or trench 710 etched into an oxide layer using back-end-of-line (BEOL) processing in block 530 according to an embodiment. PIC 700 may be fabricated from PIC 600. Via or trench 710 may be etched through oxide layer 630 and BOX layer 620 down to substrate 610.

[0035]

[0061] The via or trench may be filled with a reflective or absorbing material, such as a metallic material, at block 540. For example, a metal layer may be deposited on the oxide layer and selectively etched over one or more cycles to form a metal plug in the via or trench.

[0036]

[0062] 8 is a cross-sectional view of an example of a photonic integrated circuit 800 having vias or trenches etched in an oxide layer filled with a reflective or absorptive material (e.g., a metal such as copper, aluminum, cobalt, tungsten, etc.) using the BEOL process in block 540 according to an embodiment. PIC 800 may be fabricated from PIC 700, where vias or trenches 710 may be filled with metal plugs 810.

[0037]

[0063] In block 550, standard CMOS BEOL processing techniques may be used to deposit a metal 1 layer on the oxide layer and etch the metal 1 layer to leave a top metal cover in the area above the photodetector. The top metal cover may be aligned with vias or trenches filled with a reflective or absorptive material, such as metal. Thus, the top metal cover and vias or trenches may block background light from at least three (e.g., top, left, and right) directions or five (e.g., top, left, right, front, and back) directions.

[0038]

[0064] 9 is a cross-sectional view of an example photonic integrated circuit 900 with a top metal cover 910 fabricated as part of a metal layer for localized isolation of photodetectors using the BEOL process in block 550 according to an embodiment. PIC 900 may be fabricated from PIC 800 and may include an additional top metal cover 910 formed as part of the metal 1 layer. Top metal cover 910 may be located above (e.g., on) the photodetectors including waveguides 660 and nanowires 670. Top metal cover 910 may contact metal plugs 810 in vias or trenches 710 to block light from the top, left, and right directions in a two-dimensional cross-section.

[0039]

[0065] Optionally, other BEOL processes may be performed in block 560, for example, to form additional dielectric (e.g., oxide) layers and top metal layers (e.g., metal 2, metal 3, etc.). The BEOL processes may include standard CMOS BEOL processes.

[0040]

[0066] 10 is a cross-sectional view of an example photonic integrated circuit 1000 after additional BEOL processing at block 560 according to an embodiment. PIC 1000 may be fabricated from PIC 900 and may include upper level metal layers, such as additional metal layer 1010 and metal layer 1020.

[0041]

[0067] In block 570, the substrate may be etched from the backside to form a deep trench in the substrate from the backside. The deep trench may reflect photons propagating within the substrate at the interface between the substrate material and the air gap. For example, total internal reflection may occur when a photon is incident at an angle on the interface from the substrate material to the air gap.

[0042]

[0068] 11 is a cross-sectional view of an example photonic integrated circuit 1100 including a deep trench 1110 etched into the substrate of the photonic integrated circuit using the BEOL process in block 570 according to an embodiment. PIC 1100 may be fabricated from PIC 1000 and may include a deep trench 1110 in the substrate 610. The deep trench 1110 may be offset from the metal plug 810. For example, the deep trench 1110 may be slightly farther from the photodetector than the metal plug 810 to prevent light from the bottom side of the substrate 610 and BOX layer 620 from bypassing the metal plug 810 and reaching the photodetector.

[0043]

[0069] Optionally, at block 580, the deep trench may be filled with a reflective or absorptive material that may block light, such as a metallic material.

[0044]

[0070] 12 is a cross-sectional view of an example of a photonic integrated circuit 1200 including deep trenches in a substrate filled with a reflective or absorptive material using the process at block 580 according to an embodiment. PIC 1200 may be fabricated from PIC 1100 and may include a reflective or absorptive material 1210, such as a metallic material, filled in the deep trenches 1110.

[0045]

[0071] 13 is a cross-sectional view of a photonic integrated circuit 1200 illustrating optical isolation due to various isolation structures in the photonic integrated circuit according to an embodiment. Light from a laser may be sent to the PIC 1200 via an input fiber 1310, which may include a collimator such as a GRIN lens or a microlens. Input light 1320 from the input fiber 1310 may propagate through an oxide layer and may be partially coupled into a waveguide within the PIC 1200 by an optical input / output coupler 640, which in some embodiments may include a tilted grating.

[0046]

[0072] Light that is not coupled into the waveguide by the optical input / output coupler 640 may be scattered in various directions. For example, a portion of the input light 1320 may be reflected at the interface between the substrate 610 and the BOX layer 620 as light 1330 and may be further reflected by the metal layer 1020 as light 1370, which may be blocked by one of the metal plugs 810. A portion of the input light 1320 may be scattered as light 1335, propagate toward the metal plugs 810, and be blocked by the metal plugs. A portion of the input light 1320 may be scattered at the bottom surface of the substrate 610, a portion of the scattered light 1350 may be blocked by the reflective or absorbing material 1210 in the deep trench 1110, and another portion of the scattered light 1340 may be blocked by the metal plugs 810.

[0047]

[0073] Light 1360 scattered or otherwise leaking from the waveguide 650 may also be blocked from reaching the photodetector by the metal plug 810. Ambient light 1380 that may enter the oxide layer from the top, or stray light reflected by various metal layers, may be blocked by the top metal cover 910 on top of the photodetector and therefore may not even reach the photodetector. In this way, only photons guided into the waveguide 660 may reach the photodetector, thus greatly reducing or virtually eliminating ambient noise. In this way, high sensitivity and a high SNR may be achieved by the photodetector.

[0048]

[0074] In various embodiments, other dielectric layers used in CMOS processing may be used to replace one or more of the oxide layers (e.g., silicon dioxide layers) described above. For example, the dielectric layer may include silicon nitride, alkali halides, barium titanate, lead titanate, tantalum oxide, tungsten oxide, zirconium oxide, etc.

[0049]

[0075] The above-mentioned highly sensitive photodetectors can be used to detect individual photons in quantum computing or quantum cryptography. For example, single-photon sources can be used in many photonic quantum technologies. An ideal single-photon source deterministically generates single photons. One way to realize a deterministic single-photon source is to use cascaded (or multiplexed) heralded photon sources, for example, based on spontaneous four-wave mixing (SFWM) or spontaneous parametric downconversion (SPDC), in a passive nonlinear optical medium. In each heralded photon source (HPS), photons can be nondeterministically generated in pairs (including a signal photon and an idler photon), where one photon (e.g., the signal photon) signals the presence of the other photon (e.g., the idler photon) in the pair. Thus, when a signal photon is detected in one heralded photon source by a highly sensitive photodetector (e.g., a single-photon detector as described above), the corresponding idler photon can be used as the output of the single-photon source, while other heralded photon sources in the cascade (or multiplexed) heralded photon source of single-photon sources can be bypassed or switched off.

[0050]

[0076] FIG. 14 is a flowchart 1400 illustrating an example method for fabricating a photonic integrated circuit according to an embodiment. More specifically, FIG. 14 illustrates an example integration flow for forming a thermal isolation structure, a scattered light mitigation structure, a photodetector, and metal contacts on and within a base photonic integrated circuit (PIC). Other combinations of elements are possible without departing from the scope of the present disclosure. For example, the method may not include steps for forming other structures, such as thermal isolation structures or additional photonic structures formed in one or more additional photonic layers.

[0051]

[0077] In step 1401, a base PIC is provided. This base PIC can be any integrated circuit structure, and thus the examples shown here are not intended to limit the scope of the present disclosure. In some embodiments, the base PIC can be provided as the output of any previous sequence of processing steps, for example, silicon photonics processing steps for processing silicon-on-insulator (SOI) wafers, etc.

[0052]

[0078] 15 illustrates an example of one type of base PIC that may be provided in step 1401. The base PIC may include a PIC stack 1501. The PIC stack 1501 includes a multi-layer photonic integrated circuit stack including a substrate 1524 (e.g., a silicon handle wafer), a first oxide layer 1520, a waveguide layer 1521, and a spacer / protective capping layer 1522. In some embodiments, a second oxide layer 1518 may be disposed between the waveguide layer 1521 and the spacer / protective capping layer 1522. The waveguide layer 1521 may be patterned to include various photonic components, including one or more input coupler regions 1503, waveguide regions 1505, heater regions 1507, thermal isolation trench regions 1509, photonic switch regions 1511, photon detector regions 1513, photon detector contact regions 1515, and / or scattering mitigation structure regions 1517. Those skilled in the art will appreciate that the number, order, and location of the various regions and components shown herein are merely exemplary, and that any arrangement is possible without departing from the scope of the present disclosure.

[0053]

[0079] In some embodiments, the input coupler region 1503 can include any type of photonic input / output structure, such as a grating coupler 1519. The photonic input / output structures can be pre-formed in a waveguide layer 1521, such as a Si layer, a SiN layer, or any other material suitable for integrated photonics. The waveguide region 1505 can include one or more waveguides 1523, which can be part of one or more photonic structures and / or photonic components. For example, within the waveguide layer 1521, waveguide structures can be used to form input / output structures (such as grating couplers), optical routing structures (such as straight linear waveguides and waveguide bends), light generation structures (such as coupled microring photon sources), switch structures (such as Mach-Zehnder interferometers (MZIs)), coupling structures (such as directional couplers), optical filters (e.g., wavelength division multiplexing (WDM) wavelength filters), photonic delay line structures, etc.

[0054]

[0080] In the example illustrated in Figure 15, the structures within the waveguide layer are arranged pictorially to facilitate explanation of the fabrication process. Those skilled in the art will understand that the exact arrangement of components (and the interconnections between components) can vary greatly depending on the application for which the PIC is designed. As such, the illustrated waveguide layer 1521 is intended to represent any possible combination of photonic components that can be designed using one or more waveguides as building blocks.

[0055]

[0081] The heater region 1507 can also be part of one or more optical components, such as filters, microrings, and MZIs (not shown), and can be used to thermally tune these structures. In some embodiments, a heater 1525 (e.g., a strip heater) can be disposed in the heater region 1507. In some embodiments, the heater 1525 can be formed in the waveguide layer 1521 and can include a doped silicon (n- or p-doped silicon) layer 1525a and a capping layer 1525b formed of a silicide, such as cobalt silicide, nickel silicide, or any other silicide. While the heater region 1507 is shown adjacent to the waveguide 1523 in FIG. 15, other embodiments can employ a silicide and / or metal heater fabricated on top of the waveguide 1523, such as doped Si with a silicide top layer, a metal material such as TiN, TaN, or any other suitable heater material.

[0056]

[0082] In some embodiments, thermal isolation trench region 1509 is adjacent to heater region 1507, which allows subsequent processing, as described in more detail below with reference to Figures 19-20, to form trenches and undercuts (not shown) in the silicon oxide and silicon regions to provide thermal isolation around heater region 1525. Such trenches and undercuts can not only result in more power-efficient operation of heater 1525 (by reducing heating of the adjacent oxide layer and substrate), but can also provide thermal isolation between the region of the PIC containing heater 1525 (which may have a local temperature of 150 K to 200 K) and the region of the PIC containing photon detector (which may be cryogenic, e.g., having a local temperature of 3 K to 20 K, e.g., 4 K, 10 K, etc.). In some embodiments, many heaters may be used to tune many photonic components (e.g., single photon sources, filters, MZIs, etc.) that are located close to one another, and the thermal isolation regions may prevent crosstalk between heating of the components such that one heater for heating each component only needs to minimally heat adjacent components due to the thermal isolation properties of the thermal isolation structures formed in the thermal isolation regions. In some embodiments, thermal tuning may not be required, and therefore heaters and heater regions may not be present.

[0057]

[0083] In some embodiments, the photonic switch region 1511 includes any suitable photonic switch 1527, such as, for example, a pn switch, a pin switch, a DC Kerr switch, a Pockels effect switch, or any other type of optical switch.

[0058]

[0084] In some embodiments, photon detector region 1513 and photon detector contact region 1515 can employ any waveguide-integrated photon detection technology. For example, shown here in cross section is a superconducting nanowire single-photon detector 1529. Photon detector region 1513 and photon detector contact region 1515 can include, for example, an AlN layer 1530, an NbN layer 1532, an amorphous silicon layer 1534, and a silicon oxide layer 1536. Details of photon detector region 1513 and photon detector contact region 1515 are described below.

[0059]

[0085] Surrounding the photon detector region 1513 may be a scattering mitigation structure region 1517 which may include one or more scattering mitigation structures (not shown) fabricated therein, such as the scattering mitigation structures described above with reference to Figures 1-13.

[0060]

[0086] According to some embodiments, the base PIC can be covered with a spacer / protective cap layer 1522 shown in FIG. 15, such as a SiN layer. The spacer / protective cap layer 1522 can be conformally deposited beforehand on the base PIC wafer. In other embodiments, the base PIC can include a planarized capping layer or any other layer without departing from the scope of the present disclosure.

[0061]

[0087] Referring back to FIG. 14 , in step 1403, the base PIC is prepared for a first lithography process. The lithography process referred to herein employs tri-layer lithography, although any lithography technique can be used without departing from the scope of this disclosure. FIG. 16 shows examples of additional layers that can be deposited for use in a tri-layer lithography process. For example, a planarization layer 1603 can be deposited on a pre-formed spacer layer (e.g., spacer / protective cap layer 1522). Examples of planarization layer 1603 include organic planarization layers, such as a spin-on hard mask (SOH), an organic planarization layer (OPL), or any other layer or material that can be used to planarize the topography of the base PIC's top layer. An anti-reflective coating 1605 can be deposited on the planarization layer. Examples of anti-reflective coating 1605 include a silicon-based anti-reflective coating (SiARC), a bottom anti-reflective coating (BARC), etc. A photoresist layer 1607 may be deposited over the antireflective coating 1605 and lithographically patterned according to known methods. In the example shown in Figure 16, the photoresist layer 1607 is patterned to protect certain portions of the spacer layer (e.g., nitride layer) located over the heater contact areas, switch contact areas, and photon detector contact areas, as shown in Figure 16.

[0062]

[0088] In step 1405, a first etching process is performed to pattern the spacer / protective cap layer 1522 (e.g., a nitride layer). For example, the anti-reflective coating 1605 and planarization layer 1603 are etched in areas that do not contain photoresist (acting as an etch mask), resulting in the etched PIC structure 1701 shown in FIG. 17, with the spacer / cap 1705 (e.g., silicon nitride) remaining on top of the heater contact areas, switch contact areas, and photon detector contact areas. More generally, the photoresist can be lithographically patterned in any manner that preserves islands of SiN layer. These islands can be used, for example, as an etch stop in a subsequent contact formation etch process.

[0063]

[0089] In step 1407, an oxide deposition process (e.g., using middle of the line (MOL) SiO2 deposition) is performed to form an oxide layer 1803 on the etched PICs, as shown in FIG. 18.

[0064]

[0090] In step 1409, the patterned base PIC is prepared for a second lithography process, which involves another layer deposition and lithographic patterning of photoresist, similar to step 1403.

[0065]

[0091] In step 1411, a second etching process is performed to create deep trenches 1903 in the thermal isolation regions (e.g., thermal isolation trench regions 1509), as shown in FIG. 19. Deep trenches 1903, referred to herein as "deep trenches," are trenches in the PIC stack that may extend down to the substrate 1524. Any suitable etching process may be used to etch the deep trenches. Etching processes such as, for example, oxide etching processes, may be employed without departing from the scope of the present disclosure. In some embodiments, the etching may be a selective etch that etches the oxide but not the Si substrate. The etching process may be an anisotropic etching process that etches the deep trenches 1903.

[0066]

[0092] In step 1413, as shown in FIG. 20, an undercut 2003 is etched into the substrate 1524 at the base of the deep trench 1903. Such an undercut is formed using a combination dry / wet etching process. The dry etch can be a sulfur hexafluoride etch, a chlorine etch, or any other dry etching process that is selective to etching silicon but not oxide, so that only the silicon at the base of the deep trench 1903 is etched, preserving the overlying oxide layer. A wet etch can then be performed using, for example, tetramethylammonium hydroxide (TMAH), KOH, or any other suitable etchant. In some embodiments, the etching of the silicon occurs along the 111 crystal plane (e.g., at about 54 degrees). Such etching results in an undercut 2003 with angled walls resulting from the etching of the silicon.

[0067]

[0093] FIG. 21 illustrates an example of a heater 2103 and a full undercut structure 2105 according to some embodiments. The full undercut structure 2105 may be an example of the undercut 2003 shown in FIG. 20 and may be formed using the etching process described above with respect to FIG. 20. In some embodiments, the undercut structure 2105 may be disposed below any photonic device 2109 employing a heater. Thermal isolation from the deep trench and undercut structure 2105 may reduce or prevent heat loss to the surrounding substrate 2107. Examples of photonic devices 2109 include single-photon sources, optical filters, Mach-Zehnder interferometers, microring resonators, or any other structures that may employ thermal tuning and / or switching. FIG. 21 illustrates an example in which two deep trenches 2105a and 2105b are formed on each side of the waveguide and heater, respectively, to thermally isolate the heater element from the surrounding region, including the substrate (referred to herein as the silicon handle) and oxide layer. In some embodiments, the cooling member can be in thermal contact with the substrate to provide a head sink for the PIC during operation. For circuits operating at cryogenic temperatures, the cooling member can be part of a larger cryostat that is cooled to cryogenic temperatures. In such a scenario, without a thermal undercut structure disposed between the heater and the cooling structure, much of the heat generated by the heater could be shunted directly to the cooling structure, thereby adversely affecting the heating efficiency of the heater and / or unnecessarily increasing the heat load on the cryogenic cooling system.

[0068]

[0094] In step 1415, as illustrated in FIG. 22, an oxide layer 2210 is deposited over the PIC stack, including the deep trenches and undercuts formed therein for thermal isolation. The oxide layer 2210 can be planarized, for example, via chemical mechanical polishing (CMP). In some embodiments, the oxide layer 2210 is deposited without breaking vacuum, thus sealing the deep trench undercut regions so that these regions remain sealed under vacuum. Keeping the deep trench and undercut regions under vacuum can improve the thermal isolation capabilities of the deep trench undercut structure by eliminating the most effective heat transfer mechanism within voids. For example, heat transfer through the deep trench occurs primarily via radiative transfer, while more efficient processes such as diffusion and convection are minimized.

[0069]

[0095] In step 1417, a patterned photoresist layer 2301 may be formed on the PIC stack for a third lithography process as shown in Figure 23. This process involves deposition of another layer of photoresist and lithographic patterning, similar to step 1403. For example, patterned photoresist layer 2301 may be formed on planarization layer 2305 and anti-reflective coating layer 2303. In this case, patterning is performed to form an etch mask for etching silicide contact holes.

[0070]

[0096] In step 1419, an oxide etch process can be performed to etch oxide layer 2210, followed by a SiN punch process to etch spacer / cap 1705, thereby forming silicide contact holes 2401 for contacting a silicide layer (e.g., capping layer 1525b), as shown in FIG.

[0071]

[0097] In step 1421, lithography preparation, lithography, and etching processes are performed in a manner similar to that described above. For example, as shown in FIG. 25, a patterned photoresist layer 2501 may be formed over planarization layer 2505 and anti-reflective coating layer 2503. In this case, photoresist layer 2501 is patterned to stop on an appropriate layer of the photon detector, e.g., an amorphous silicon layer, and to enable etching of photon detector contact holes. As shown in FIG. 26, planarization layer 2505 (e.g., an SOH or OPL layer) may be removed to open silicide contact hole 2401 and photon detector contact hole 2601.

[0072]

[0098] In step 1423, metal silicide contacts 2701 are formed as shown in FIG. 27. For example, a liner layer 2703 can first be deposited in the contact holes (e.g., silicide contact hole 2401 and photon detector contact hole 2601). In some embodiments, liner layer 2703 can be formed from tungsten, tungsten carbide, tungsten nitride, or any other suitable liner. After liner layer deposition, an annealing step can be performed to form silicide regions 2705 at the bottom of metal silicide contact 2701 for detector contact, such as amorphous silicon layer 1534. Following silicide formation, a metallization process is performed to fill the contact holes with a suitable contact metal 2707, such as tungsten, copper, aluminum, cobalt, or the like. In some embodiments, a cleaning process can be performed to clean the amorphous silicon prior to silicide formation. Any suitable cleaning process can be used, such as, for example, a chemical cleaning step, argon sputtering, or the like.

[0073]

[0099] In step 1425, scattering mitigation structures 2801 are formed using lithography and etching processes, as illustrated in FIG. 28. In some embodiments, scattering mitigation structures 2801 can be formed in deep trenches disposed on substrate 1524. In other embodiments, scattering mitigation structures 2801 can be formed in through-silicon vias (TSVs), such as the trench shown in FIG. 28. After the trench is etched, an oxide liner 2803 is formed to prevent the fill material (which subsequently fills scattering mitigation structures 2801) from reacting with silicon. A metal liner layer 2805, such as a Ti-Cu barrier and seed layer, may then be formed on oxide liner 2803 before filling the scattering mitigation structures with fill material 2807 (e.g., a metal such as copper). The fill material 2807 may have a coefficient of thermal expansion (CTE) similar to that of substrate 1524 and / or the oxide. In some embodiments, scattering mitigation structures such as TSVs can be on the order of 10 microns deep, e.g., 40-60 microns deep, and therefore much deeper than thermal isolation trenches (which can be 10 times deeper or more).

[0074]

[0100] Those skilled in the art will appreciate that substantial variations may be made depending on the particular implementation. For example, customized hardware may also be used, and / or particular elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connection to other computing devices, such as network input / output devices, may be employed.

[0075]

[0101] With reference to the accompanying figures, components that may include memory may also include non-transitory machine-readable media. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any storage medium that participates in providing data that causes a machine to operate in a specific manner. In the embodiments provided herein, various machine-readable media may participate in providing instructions / code to a processor and / or other devices for execution. Additionally or alternatively, machine-readable media may be used to store and / or transport such instructions / code. In many implementations, computer-readable media are physical and / or tangible storage media. Such media may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punch cards, paper tape, any other physical medium with a pattern of holes, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash-EPROM, any other memory chip or cartridge, a carrier wave as described below, or any other medium from which a computer can read instructions and / or code.

[0076]

[0102] The methods, systems, and devices discussed herein are examples. Various embodiments may omit, substitute, or add various procedures or components, as appropriate. For example, features described with respect to one embodiment may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Various components of the diagrams provided herein may be embodied in hardware and / or software. Also, technology evolves, and therefore, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

[0077]

[0103] It has proven convenient at times, primarily for reasons of common usage, to refer to bits, information, values, elements, symbols, characters, variables, terms, numbers, or similar signals. It should be understood, however, that all of these or similar terms must be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise indicated, and as is clear from the above discussion, throughout this specification, discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” “ascertaining,” “identifying,” “associating,” “measuring,” “performing,” and the like, are understood to refer to the actions or processes of a specific apparatus, such as a special purpose computer or similar special purpose electronic computing device. Thus, in the context of this specification, a special purpose computer or similar special purpose electronic computing device can manipulate or transform signals that are typically represented as physical electronic, electrical, or magnetic quantities in memories, registers, or other information storage, transmission, or display devices of the special purpose computer or similar special purpose electronic computing device.

[0078]

[0104] Those skilled in the art will understand that the information and signals used to convey the messages described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0079]

[0105] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings that are expected to depend, at least in part, on the context in which such terms are used. Typically, when used to associate a list, such as A, B, or C, “or” is intended to refer to A, B, and C, which are used herein in an inclusive sense, as well as A, B, or C, which are used herein in an exclusive sense. Additionally, as used herein, the term “one or more” may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe any combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and claimed subject matter is not limited to this example. Furthermore, when used to associate a list, such as A, B, or C, the term “at least one” can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABCCC, etc.

[0080]

[0106] References throughout this specification to "one example," "example," "an example," or "exemplary implementation" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Thus, the appearances of "in one example," "in an example," "in an example," "in an implementation," or other similar phrases in various places throughout this specification do not necessarily all refer to the same features, examples, and / or limitations. Furthermore, particular features, structures, or characteristics may be combined in one or more examples and / or characteristics.

[0081]

[0107] In some implementations, operations or processing may involve physical manipulation of physical quantities. Typically, though not necessarily, such quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms must be associated with the appropriate physical quantities and are merely convenient labels. Unless otherwise noted, as will be apparent from the discussion herein, discussions throughout this specification utilizing terms such as “processing,” “computing,” “calculating,” “determining,” and the like will be understood to refer to operations or processes of a particular apparatus, e.g., a special purpose computer, special purpose computing device, or similar special purpose electronic computing device. Thus, in the context of this specification, a special purpose computer or similar special purpose electronic computing device can manipulate or transform signals that are typically represented as physical electronic or magnetic quantities in memory, registers, or other information storage, transmission, or other devices within the special purpose computer or similar special purpose electronic computing device.

[0082]

[0108] In the preceding detailed description, numerous specific details are set forth to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by those skilled in the art have not been described in detail so as not to obscure the claimed subject matter. Therefore, it is not intended that the claimed subject matter be limited to the particular examples disclosed, but rather that such claimed subject matter may include all aspects falling within the scope of the appended claims, and equivalents thereof.

Claims

1. A substrate; a dielectric layer on the substrate; a waveguide within the dielectric layer; a heater disposed within the dielectric layer; a thermal isolation structure including a trench in the dielectric layer and an undercut in the substrate; a photodetector disposed above the waveguide and monolithically integrated with the substrate, the photodetector optically coupled to the waveguide and configured to operate at a temperature below 50 K; An apparatus comprising:

2. The apparatus of claim 1 , wherein the heater is disposed proximate to the waveguide and configured to thermally condition a portion of the waveguide.

3. The apparatus of claim 2 , wherein the waveguide and the heater are components of a single photon generator, a ring oscillator, an optical filter, an optical switch, or an optical interferometer.

4. The apparatus of claim 2 , wherein the thermal isolation structure surrounds the heater.

5. The device of claim 4 , wherein the undercut extends horizontally within the substrate and underlies the portion of the waveguide.

6. The apparatus of claim 4 , wherein the trench and the undercut form a vacuum region.

7. The apparatus of claim 4 , further comprising a cooling structure disposed in thermal contact with the substrate, the undercut being disposed between the heater and the cooling structure.

8. 10. The device of claim 1, further comprising a plurality of optical isolation structures in at least one of the substrate or the dielectric layer, the plurality of optical isolation structures configured to prevent photons from reaching the photodetector other than through the waveguide.

9. the plurality of light separating structures an array of metal vias in the dielectric layer; or a metal cover within the dielectric layer and over the photodetector; 9. The apparatus of claim 8, comprising at least one of:

10. The device of claim 9 , wherein the metal cover is in a metal layer and is aligned or bonded to the array of metal vias to form a continuous structure surrounding the photodetector.

11. the waveguide includes an input port; The apparatus of claim 9 , wherein the array of metal vias is disposed in an area that includes the input port.

12. The apparatus of claim 1 , wherein the photodetector comprises a superconducting nanowire single-photon detector.

13. The device of claim 1 , wherein the dielectric layer comprises an oxide layer.

14. Receiving a wafer, the wafer comprising: A substrate; a dielectric layer on the substrate; a waveguide formed in the dielectric layer; a heating structure disposed within the dielectric layer; a photodetector in the dielectric layer and coupled to the waveguide; Etching a first set of vias or a first trench in the dielectric layer to expose a first portion of the substrate, the first set of vias or the first trench surrounding the photodetector; etching the substrate through the first set of vias or the first trenches to form a second set of vias or a second trench in the substrate; filling the first set of vias or the first trenches and the second set of vias or the second trenches with a light reflective or light absorbing material; A method comprising:

15. The method of claim 14 , wherein the heating structure is configured to thermally condition a portion of the waveguide.

16. etching a third set of vias or a third trench in the dielectric layer to expose a second portion of the substrate, the third set of vias or the third trench surrounding the heating structure; etching the substrate through the third set of vias or the third trench to form undercuts in the substrate, the undercuts underlying the second portion of the substrate; depositing an oxide layer over the dielectric layer to seal the third set of vias or the third trenches and the undercuts; 16. The method of claim 15, further comprising:

17. etching the dielectric layer to form contact holes for the heating structures; filling the contact holes with a conductive material to form electrical contacts for the heating structure; 16. The method of claim 15, further comprising:

18. 15. The method of claim 14, further comprising forming an oxide liner layer in the second set of vias or the second trenches prior to the filling step.

19. 20. The method of claim 18, further comprising depositing a barrier and seed layer on the oxide liner layer.

20. The method of claim 14 , further comprising forming a top metal cover over the dielectric layer and on top of the photodetector.

21. 21. The method of claim 20, wherein the top metal cover is in a metal 1 layer.

22. etching the dielectric layer to form contact holes for the photodetectors; filling the contact holes with a conductive material to form electrical contacts for the photodetectors; 15. The method of claim 14, further comprising:

23. 23. The method of claim 22, wherein filling the contact holes comprises depositing a liner layer on sidewalls of the contact holes.

24. 24. The method of claim 23, wherein the liner layer comprises tungsten, tungsten carbide, or tungsten nitride.

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