Pipelined successive approximation analog-to-digital converter, integrated circuit and electronic device

Abstract

A pipelined successive approximation analog-to-digital converter, an integrated circuit, and an electronic device include a first-stage successive approximation analog-to-digital converter (10), an interstage gain amplifier (30), a second-stage successive approximation analog-to-digital converter (20), and a digital encoding unit (40).

Description

[Technical Field]

[0001] This application is filed based on a Chinese patent application bearing application number Pipeline Successive Approximation Analog-Digital Converter, Integrated Circuit and Electronic Device No. and filed on November 24, 2021, and claims priority to that Chinese patent application, the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of integrated circuit technology, and more particularly to pipelined successive approximation analog-to-digital converters, integrated circuits, and electronic devices. [Background technology]

[0003] Pipelined Successive Approximation Register (PSAR) analog-to-digital converters (ADCs) are widely used in various analog-to-digital converter applications due to their high speed and high accuracy. A pipelined SAR ADC typically includes at least two SAR ADC stages, each of which includes a digital-to-analog converter (DAC), a comparator, and a SAR control logic unit. An interstage gain amplifier is located between the DACs of two adjacent SAR ADC stages to amplify the sampling residual signal of the preceding SAR ADC and transmit it to the succeeding SAR ADC. In deep submicron CMOS technology, the inherent gain of transistors gradually decreases, making it difficult for the interstage gain amplifier to achieve high-gain linear amplification. To address this technical issue, prior art has proposed a two-stage interstage gain halving technique, which reduces the reference voltage of the succeeding ADC by half that of the preceding ADC, thereby reducing the gain of the interstage gain amplifier. However, halving the reference voltage significantly reduces the ADC's conversion speed and power consumption. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present application provide a pipelined successive approximation analog-to-digital converter, an integrated circuit, and an electronic device. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application is a first-stage successive approximation type analog-to-digital converter including a first digital-to-analog converter, a first comparator, and a first digital control logic unit connected in series, wherein the first digital-to-analog converter includes a first capacitor array, and the first capacitor array includes one first phase compensation capacitor and an M-bit first capacitor, and a first end of each of the first phase compensation capacitors is respectively connected to an analog input voltage, and a second end of each of the first capacitors is respectively connected to a forward reference voltage and a negative reference voltage via a multi-selection switch, and the first phase compensation a second end of the capacitance is connected to a negative reference voltage, the capacitance value of the first phase compensation capacitance is equal to the capacitance value of a first-bit capacitance of the M-bit first capacitance, and the capacitance values ​​of the M-bit first capacitances increase by a power of 2 in order from the smallest bit number to the largest bit number, where M is an integer greater than 1; a first-stage successive approximation analog-to-digital converter; an inter-stage gain amplifier whose input end is connected to a residual voltage output from the first digital-to-analog converter; a second digital-to-analog converter connected in series; a second comparator; and a second digital control logic unit. a first end of the half-gain capacitance, a second phase compensation capacitance, and an N-1 bit second capacitance; a first end of the half-gain capacitance, a second phase compensation capacitance, and each second capacitance is connected to an output terminal of the interstage gain amplifier; a second end of each second capacitance is connected to a forward reference voltage and a negative reference voltage via a multi-selection switch; a second end of the half-gain capacitance and the second phase compensation capacitance is connected to the negative reference voltage; and a capacitance value of the second phase compensation capacitance is the capacitance value of the gain halving capacitance is the sum of the capacitance values ​​of the N-1 bit second capacitance and the second phase compensation capacitance, where N is an integer greater than 1; and a digital encoding unit connected to the output terminals of the first digital control logic unit and the second digital control logic unit.

[0006] In a second aspect, an embodiment of the present application provides an integrated circuit including the pipelined successive approximation analog-to-digital converter according to the first aspect.

[0007] In a third aspect, an embodiment of the present application provides an electronic device comprising the integrated circuit according to the second aspect. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a frame schematic diagram of a pipelined successive approximation analog-to-digital converter provided by an embodiment of the present application; [Figure 2] 1 is a schematic circuit diagram of a first-stage successive approximation type analog-to-digital converter provided by an embodiment of the present application; [Figure 3] 1 is a schematic circuit diagram of a second-stage successive approximation type analog-to-digital converter provided by an embodiment of the present application; [Figure 4] FIG. 2 is a schematic diagram of an encoding process of a digital encoding unit provided by an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0009] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application, but it is clear that the described embodiments are only some of the embodiments of the present application and do not represent all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without exerting their creative efforts are all within the scope of the claims of the present application.

[0010] When expressions such as "first" and "second" are used in the description of the embodiments of the present application, it should be understood that they are used merely to distinguish technical features and cannot be understood to indicate or imply relative importance, the number of technical features indicated, or the context of the technical features indicated. The phrase "at least one" means one or more, and the phrase "plurality" means two or more. The phrase "and / or" describes a relationship between related objects and indicates that three types of relationships may exist. For example, A and / or B can indicate that A exists alone, A and B exist simultaneously, or B exists alone. Here, A and B may be singular or plural. The symbol " / " generally indicates that the related objects before and after it are in an "or" relationship. The phrase "at least one of the following" and similar expressions refer to any group of items, including any combination of single or multiple items. For example, at least one of a, b, and c can represent a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c may be singular or plural.

[0011] In order to facilitate understanding of the technical solutions of the embodiments of the present application, the following first briefly introduces the prior art of pipelined successive approximation analog-to-digital converters.

[0012] A pipelined successive approximation analog-to-digital converter generally includes a multi-stage SAR ADC, encodes the digital signal output from the multi-stage SAR ADC, and is used to finally output a digital signal obtained by converting an analog input signal.

[0013] Each stage of the SAR ADC mainly consists of three parts: a digital-to-analog converter (DAC), a comparator, and a SAR control logic unit (SAR logic). The basic operating principle of each stage of the SAR ADC is that during the first sampling period, the DAC's most significant bit (MSB) is set to 1 and the remaining bits are set to 0. The comparator compares the analog input voltage with the initial value of the DAC output voltage (typically half the full-range voltage). If the analog input voltage is greater than the DAC output voltage, the code of the current bit is 1 and the DAC's switching state remains unchanged. If the analog input voltage is less than the DAC output voltage, the code of the current bit is 0 and the DAC's switching state returns to its pre-operation state. The SAR logic then moves on to the next bit, changes the DAC's switching state again, and compares it with the analog input voltage. This process is repeated until the last bit is compared, obtaining all the A / D conversion codes. The core idea behind the working principle of SAR ADC is dichotomy, where the DAC output voltage changes by 1 / 2 each time, gradually approaching the analog input voltage to achieve analog-to-digital conversion.

[0014] In a pipelined successive approximation analog-to-digital converter, an interstage gain amplifier is provided between the DACs of two adjacent stages of SAR ADCs. The interstage gain amplifier amplifies the residual amount (residual voltage) of the analog input voltage of the previous stage SAR ADC, and then supplies this as the analog input to the subsequent stage SAR ADC.

[0015] In deep submicron CMOS technology, the inherent gain of transistors gradually decreases, making it difficult for the interstage gain amplifier to achieve high-gain linear amplification. To address this technical issue, the prior art proposes reducing the reference voltage in the subsequent ADC to half of the reference voltage in the previous ADC, realizing a two-stage interstage gain halving technique and reducing the gain of the interstage gain amplifier. For example, if the number of bits in the previous SAR ADC is M bits, the amplification factor of the interstage gain amplifier is generally 2. M-1However, if the interstage gain halving technique is adopted, the amplification factor of the interstage gain amplifier can be set to 2. M-2 However, halving the interstage gain by halving the reference voltage significantly reduces the ADC's conversion speed and power consumption.

[0016] As described above, a drawback of the conventional two-stage or more-stage pipelined successive approximation analog-to-digital converter structure is that the gain of the inter-stage gain amplifier is high, making it unsuitable for deep submicron CMOS technology. In the conventional technology, the reference voltage is lowered, which can realize the inter-stage gain halving technique, but this limits the speed and accuracy of the entire pipelined successive approximation analog-to-digital converter and increases power consumption. In light of this, embodiments of the present application provide a pipelined successive approximation analog-to-digital converter, an integrated circuit, and an electronic device that halves the inter-stage gain without requiring halving the reference voltage in order to improve the conversion speed and power consumption of the ADC.

[0017] Please refer to Figure 1. Figure 1 is a structural block diagram of a pipelined successive approximation type analog-to-digital converter provided by an embodiment of the present application. As shown in Figure 1, the pipelined successive approximation type analog-to-digital converter of the embodiment of the present application includes a first-stage successive approximation type analog-to-digital converter 10, an inter-stage gain amplifier 30, a second-stage successive approximation type analog-to-digital converter 20, and a digital encoding unit 40. Here, the first-stage successive approximation type analog-to-digital converter 10 is connected to the second-stage successive approximation type analog-to-digital converter 20 via the inter-stage gain amplifier 30, and the first-stage successive approximation type analog-to-digital converter 10 and the second-stage successive approximation type analog-to-digital converter 20 are respectively connected to the digital encoding unit 40.

[0018] The first-stage successive approximation type analog-to-digital converter 10 (hereinafter referred to as first-stage SAR ADC) in this embodiment is implemented as an M-bit SAR ADC, i.e., the first-stage SAR ADC is for outputting an M-bit digital signal to the digital encoding unit 40, where M is an integer greater than 1. The second-stage successive approximation type analog-to-digital converter 20 (hereinafter referred to as second-stage SAR ADC) in this embodiment is implemented as an N-bit SAR ADC, i.e., the second-stage SAR ADC is for outputting an N-bit digital signal to the digital encoding unit 40, where N is an integer greater than 1. The digital encoding unit 40 encodes the M-bit digital signal (B11:B1M) output from the first-stage SAR ADC and the N-bit digital signal (B21:B2N) output from the second-stage SAR ADC using an inter-stage transposition accumulation method to obtain a final (M+N-1)-bit binary digital signal (D1:D(M+N-1)).

[0019] Please refer to Figure 2. Figure 2 is a schematic diagram of the circuit structure of a first-stage SAR ADC provided by an embodiment of the present application. The first-stage SAR ADC includes a first digital-to-analog converter, a first comparator, and a first digital control logic unit, which are connected in series. Here, the first digital-to-analog converter includes a first capacitor array, which includes the first phase compensation capacitor C0 and M-bit first capacitors C1 to C2. M Includes.

[0020] The M-bit first capacitors C1 to C M The capacitance value of the first capacitance C increases in powers of 2 in the order from smallest to largest number of bits. i The capacitance value of is given by the formula C i =2 i-1 *CU, where i=any integer from 1 to M, and CU is the unit capacity.

[0021] The capacitance value of the first phase compensation capacitance C0 is equal to the capacitance value of the first bit capacitance C1 of the M-bit first capacitance, that is, C0=CU.

[0022] As shown in FIG. 2, the first phase compensation capacitance C0, the first capacitances C1 to C M The first terminals of the first capacitors C1 to C2 are connected to the analog input voltages, respectively. M The second terminal of each is connected to the forward reference voltage V ref and the second terminal of the first phase compensation capacitor C0 is connected to a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage), and the second terminal of the first phase compensation capacitor C0 is permanently connected to the negative reference voltage.

[0023] It can be understood that the analog input voltage can be connected to the input terminal of the first digital-to-analog converter via a sample-and-hold circuit (S / H). When converting an analog signal to digital, a certain conversion time is required, and during this conversion time, the analog signal must be held essentially unchanged, which is how conversion accuracy can be guaranteed. A sample-and-hold circuit is a circuit that realizes this function.

[0024] As shown in Figure 2, the first-stage SAR ADC samples the analog input voltage using the upper plate. In the first-stage SAR ADC, the upper plate of each capacitor is connected to the analog input voltage, and the M-bit first capacitors C1 to C M The bottom plates of the transistors are connected to multiple reference signal sources via multiple selection switches. Illustratively, the reference signal sources are forward reference voltages V ref and a negative-going reference voltage (in this example, the reference ground GND is the negative-going reference voltage). In some examples, the reference signal source may include a common-mode voltage V CM The bottom plate of the first phase compensation capacitor C0 is permanently connected to a negative reference voltage.

[0025] In the example shown in Figure 2, the sampling method of the first-stage SAR ADC is differential top-plate sampling, and the analog input voltage input to the first-stage SAR ADC is the differential voltage V ip1 and V in1 and V ip1 is the forward analog input voltage, and V in1is the negative analog input voltage. In the top plate differential sampling method, the first-stage SAR ADC has two first capacitor arrays, and the two first capacitor arrays have the same structure. The two first capacitor arrays are connected corresponding to the forward analog input voltage and the negative analog input voltage. For an M-bit differential output first-stage SAR ADC, each first capacitor array includes M+1 capacitors, and the first-stage SAR ADC shares 2M+2 capacitors.

[0026] Among the M-bit first capacitors of the first capacitor array, C1 to C M-1 belongs to the weight capacitance, and in the successively approaching conversion process, the first capacitance array output voltage can be increased or decreased by switching the corresponding weight capacitance. C M can be understood to be for generating a residual voltage signal to the second stage SAR ADC.

[0027] It should be understood that the circuit structure of the first-stage SAR ADC shown in Figure 2 is merely an example. In concrete implementation, the circuit structure of the first-stage SAR ADC can be appropriately modified according to different analog sampling methods. For example, when a single-ended sampling method is adopted, the first-stage SAR ADC only needs to have one first capacitor array.

[0028] In this embodiment, the inter-stage gain amplifier 30 is disposed between the first and second stage SAR ADCs, and the input terminal of the inter-stage gain amplifier 30 is connected to the residual voltage output from the first digital-to-analog converter.

[0029] As shown in Figure 2, when the sampling method of the first-stage SAR ADC is differential top-plate sampling, the interstage gain amplifier 30 uses a differential amplifier. When a differential amplifier is used, the interstage gain amplifier 30 has two input terminals corresponding to the residual voltages (forward residual voltage and negative residual voltage) connected to the outputs of the two first capacitor arrays. The interstage gain amplifier 30 is V ip1 and V in1 The residual voltage of is amplified and the differential analog input voltage V ip2 and Vin2 Correspondingly, the interstage gain amplifier 30 has two outputs, V ip2 and V in2 is output to the second-stage SAR ADC.

[0030] It can be understood that the two inputs of the interstage gain amplifier 30 can be provided with switches (S1, S2) respectively to control the input of the residual voltage through the switches.

[0031] Please refer to Figure 3. Figure 3 is a circuit structure schematic diagram of a second-stage SAR ADC provided by an embodiment of the present application. As shown in Figure 3, the second-stage SAR ADC includes a second digital-to-analog converter, a second comparator, and a second digital control logic unit, which are connected in series. Here, the second digital-to-analog converter includes a second capacitor array, and the second capacitor array includes one gain halving capacitor C a and one second phase compensation capacitance C0 and N-1-bit second capacitances C1 to C N-1 Includes.

[0032] The N-1 bit second capacitances C1 to C N-1 The capacitance value of the second capacitor Ci increases in powers of 2 in the order from the smallest to the largest number of bits. i =2 i-1 *CU, where i=any integer from 1 to N-1, and CU is the unit capacity.

[0033] The capacitance value of the second phase compensation capacitance C0 is the capacitance value of the N-1 bit second capacitances C1 to C N-1 The capacitance value of the first capacitor C1 is equal to that of the first capacitor C0, that is, C0=CU.

[0034] The capacitance value of the gain half capacitance Ca is the capacitance value of the N-1 bit second capacitances C1 to C N-1 and the capacitance value of the second phase compensation capacitance C0, and the capacitance value of Ca is expressed by the formula Ca=2 N-1 *Can be expressed in CU.

[0035] As shown in FIG. 3, the gain halving capacitance C a, the second phase compensation capacitance C0, the N-1-bit second capacitances C1 to C N-1 The first terminals of the second capacitors C1 to C2 are connected to the output terminal of the interstage gain amplifier 30. N-1 The second terminal of each is connected to the forward reference voltage V ref , connected to a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage), and the gain halving capacitance C a , the second terminal of the second phase compensation capacitor C0 is permanently connected to the negative reference voltage.

[0036] As shown in Figure 3, the second-stage SAR ADC uses its upper plate to sample the analog input voltage. In the second-stage SAR ADC, the upper plate of each capacitor is connected to the output of the interstage gain amplifier 30, and the analog input voltage is accessed from the interstage gain amplifier 30 (obtained by amplifying the residual voltage of the first-stage SAR ADC by the interstage gain amplifier 30). The N-1-bit second capacitors C1 to C N-1 The bottom plates of the are connected to multiple reference signal sources via multiple selection switches. Illustratively, the reference signal sources are forward reference voltages V ref and a negative-going reference voltage (in this example, the reference ground GND is the negative-going reference voltage). In some examples, the reference signal source may include a common-mode voltage V CM The gain halving capacitance C a The bottom plate of the second phase compensation capacitor C0 is permanently connected to the negative reference voltage.

[0037] In the example shown in FIG. 3, the sampling method of the second stage SAR ADC is differential top plate sampling, and the two outputs of the interstage gain amplifier 30 output a differential voltage V ip2 and V in2 (V of the first stage SAR ADC is output by the interstage gain amplifier 30) ip1 and V in1 (The residual voltage of V is amplified.) ip2 is the forward analog input voltage, V in2 is the negative-going analog input voltage.

[0038] In the top plate differential sampling method, the second stage SAR ADC has two second capacitor arrays, and the two second capacitor arrays have the same structure. The two second capacitor arrays are connected to the forward analog input voltage V ip2 and the negative-going analog input voltage V in2 For a second-stage SAR ADC with an N-bit differential output, each first capacitor array includes N+1 capacitors (one gain halving capacitor, one second phase compensation capacitor, and an N-1-bit second capacitor), and the second-stage SAR ADC shares 2N+2 capacitors.

[0039] Among the N-1-bit second capacitors of the second capacitor array, C1 to C N-1 are all weighted capacitances, and it can be understood that in the successively approaching conversion process, the output voltage of the second capacitance array can be increased or decreased by switching the switches of the corresponding weighted capacitances.

[0040] It should be understood that the circuit structure of the second-stage SAR ADC shown in Figure 3 is merely an example. In concrete implementation, the circuit structure of the second-stage SAR ADC can be appropriately modified according to different analog sampling methods. For example, when a single-ended sampling method is adopted, the second-stage SAR ADC only needs to have one second capacitor array.

[0041] In this embodiment, the digital encoding unit 40 is connected to the output terminals of the first digital control logic unit and the second digital control logic unit. The analog input voltage is amplified and quantized by the two-stage successive approximation type analog-to-digital converter and the inter-stage gain amplifier 30 to generate an (M+N)-bit code, and finally the digital encoding unit 40 outputs the final (M+N-1)-bit digital code.

[0042] Figure 4 is a schematic diagram of the encoding process of the digital encoding unit 40. The first-stage SAR ADC (M-bit SAR ADC) and the second-stage SAR ADC (N-bit SAR ADC) jointly generate an (M+N)-bit code, and the final (M+N-1)-bit binary digital output code (D1:D(M+N-1)) is obtained according to the inter-stage transposition and addition scheme shown in Figure 3. The subtraction process of the input digital encoding is necessary to maintain full amplitude quantization. The decoding circuit can implement the encoding process shown in Figure 4 using a full adder (FA) and a half adder (HA).

[0043] In the solution of this embodiment, a gain halving capacitor is provided in the second digital-to-analog converter in the second-stage successive approximation type analog-to-digital converter 20, and the capacitance value of this gain halving capacitor is the sum of the capacitance values ​​of the remaining capacitances in the second digital-to-analog converter. This doubles the capacitance DAC of the second-stage successive approximation type analog-to-digital converter 20, thereby realizing a two-stage inter-stage gain halving structure. This reduces the gain of the inter-stage gain amplifier 30 (reducing the amplification factor of the inter-stage gain amplifier 30 from 2M-1 times to 2M-2 times), but the forward reference voltage of the second-stage successive approximation type analog-to-digital converter 20 is not halved and remains consistent with the forward reference voltage of the first-stage successive approximation type analog-to-digital converter 10. This is effective in reducing power consumption and improving conversion speed, and is also adaptable to deep submicron CMOS technology. The analog input signal is amplified and quantized by a two-stage successive approximation type analog-to-digital converter and an interstage amplifier to generate an (M+N)-bit digital signal, and finally passes through a digital encoding unit 40 to output an (M+N-1)-bit digital signal.

[0044] The solutions of the embodiments of the present invention can be applied not only to two-stage successive approximation type analog-to-digital converters but also to three-stage or more successive approximation type analog-to-digital converters.

[0045] An embodiment of the present invention further provides an integrated circuit including the pipelined successive approximation analog-to-digital converter described in any of the above embodiments.

[0046] Furthermore, the present embodiment further provides an electronic device including a main body and the integrated circuit described above, wherein the integrated circuit is provided within the main body. For example, the electronic device may be a network device (such as a base station device).

[0047] In the present embodiment, a gain-halving capacitor is provided in the second digital-to-analog converter of the second-stage successive approximation type analog-to-digital converter, and the capacitance value of the gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitances in the second digital-to-analog converter. This realizes a two-stage inter-stage gain-halving technology, which reduces the gain of the inter-stage gain amplifier, but the forward reference voltage of the second-stage successive approximation type analog-to-digital converter is not halved and remains the same as the forward reference voltage of the first-stage successive approximation type analog-to-digital converter. This is effective in reducing power consumption and improving conversion speed, and is also compatible with deep submicron CMOS technology. An analog input signal is amplified and quantized by the two-stage successive approximation type analog-to-digital converter and the inter-stage amplifier to generate an (M+N)-bit digital signal, which is finally output as an (M+N-1)-bit digital signal via a digital encoding unit.

[0048] Although several embodiments of the present application have been specifically described above, the present application is not limited to the above-described embodiments, and a person skilled in the art may make various equivalent modifications or substitutions without violating the spirit and conditions of the present application, and all of these equivalent modifications or substitutions are included in the scope limited by the claims of the present application.

Claims

1. a first-stage successive approximation type analog-to-digital converter including a first digital-to-analog converter, a first comparator, and a first digital control logic unit connected in series, the first digital-to-analog converter including a first capacitor array, the first capacitor array including one first phase compensation capacitor and an M-bit first capacitor, a first end of each of the first phase compensation capacitors is connected to an analog input voltage, a second end of each of the first capacitors is connected to a reference voltage and a reference ground via a multi-selection switch, and the second end of the first phase compensation capacitor is connected to the reference ground, a capacitance value of the first phase compensation capacitor is equal to a unit capacitance value, and a capacitance value of the M-bit first capacitor increases by a power of two in order from the smallest bit number to the largest bit number, M is an integer greater than 1, and the first comparator has an input terminal connected to an output of a residue voltage from the first digital-to-analog converter and an output terminal connected to an input terminal of the first digital control logic unit; an interstage gain amplifier having an input connected to an output of the first digital-to-analog converter for obtaining the residual voltage output from the first digital-to-analog converter; a second stage successive approximation type analog-to-digital converter including a second digital-to-analog converter, a second comparator, and a second digital control logic unit connected in series, wherein the second digital-to-analog converter includes a second capacitance array, the second capacitance array including one half-gain capacitance, one second phase compensation capacitance, and an N-1 bit second capacitance, a first end of the half-gain capacitance, the second phase compensation capacitance, and each second capacitance is respectively connected to an output end of the interstage gain amplifier, and a second end of each second capacitance is respectively connected to a reference voltage or a reference ground via a multi-selection switch, and a second stage successive approximation type analog-to-digital converter, wherein second ends of the capacitors are respectively connected to the reference ground, the capacitance value of the second phase compensation capacitor is equal to a unit capacitance value, and the capacitance value of the N-1 bit second capacitor increases by a power of 2 in order from the smallest bit to the largest bit, the capacitance value of the gain halving capacitor is the sum of the capacitance values ​​of the N-1 bit second capacitor and the second phase compensation capacitor, N is an integer greater than 1, and the second comparator has an input terminal connected to an output of a residual voltage from the second digital-to-analog converter and an output terminal connected to an input terminal of the second digital control logic unit; a digital encoding unit having a first input connected to the output of the first digital control logic unit and a second input connected to the output of the second digital control logic unit; Pipelined successive approximation analog-to-digital converter.

2. the analog input voltage is a differential voltage, two first capacitor arrays are provided, and first ends of the two first capacitor arrays receive a forward input voltage and a negative input voltage of the differential voltage; 2. The pipelined successive approximation type analog-to-digital converter according to claim 1.

3. the interstage gain amplifier is a differential amplifier, and two input terminals of the differential amplifier receive residual voltages output from the two first capacitor arrays; 3. The pipelined successive approximation type analog-to-digital converter according to claim 2.

4. two output terminals are provided to the differential amplifier, two second capacitance arrays are provided, and each second capacitance array corresponds to two output terminals of the differential amplifier to which it is connected; 4. The pipelined successive approximation type analog-to-digital converter according to claim 3.

5. The amplification factor of the interstage gain amplifier is 2(M-2), 2. The pipelined successive approximation type analog-to-digital converter according to claim 1.

6. the second end of each of the first capacitors is further connected to a common-mode voltage via the multi-selection switch; 2. The pipelined successive approximation type analog-to-digital converter according to claim 1.

7. the second end of each of the second capacitors is further connected to a common-mode voltage via the multi-selection switch; 2. The pipelined successive approximation type analog-to-digital converter according to claim 1.

8. a sample and hold circuit coupled to the analog input voltage and the first digital-to-analog converter; 2. The pipelined successive approximation type analog-to-digital converter according to claim 1.

9. A pipelined successive approximation type analog-to-digital converter according to any one of claims 1 to 8, Integrated circuit.

10. A device comprising: a device body; and the integrated circuit according to claim 9, wherein the integrated circuit is provided within the device body. electronic equipment.

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