Image display device manufacturing method and image display device

Abstract

A method for manufacturing an image display device according to an embodiment comprises: a step for forming a first section of a single crystal metal on a substrate; a step for forming, on the first section, a semiconductor layer that includes a light-emitting layer; a step for processing the semiconductor layer to form a light-emitting element that includes a light-emitting surface on the first section; a step for forming a first insulating film that covers the substrate and the light-emitting element; a step for forming a circuit element on the first insulating film; a step for forming a light-blocking member between the circuit element and the light-emitting element; a step for forming a second insulating film that covers the first insulating film and the circuit element; a step for forming a first via penetrating the first and second insulating films; a step for forming a wiring layer on the second insulating film; a step for removing the substrate; and a step for removing at least a portion of the first section.

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device. [Background technology]

[0002] There is a demand for thin image display devices that have high brightness, a wide viewing angle, high contrast, and low power consumption. To meet this market demand, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is anticipated as a self-emitting element. A method of manufacturing display devices using micro LEDs has been introduced in which individually formed micro LEDs are sequentially transferred to a driving circuit. However, as the number of micro LED elements increases with the trend toward higher image quality, such as full HD, 4K, and 8K, the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and then sequentially transferred to a substrate on which a driving circuit, etc., is formed. Furthermore, there is a risk of poor connections between the micro LEDs and the driving circuit, etc., resulting in reduced yields.

[0004] A technique is known in which a semiconductor layer including a light-emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-141492 [Non-patent literature]

[0006] [Non-Patent Document 1] H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils", SCIENTIFIC REPORTS, 7:2112, 18 May 2017 [Non-patent document 2] JW Shon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes on amorphous substrates by pulsed sputtering", SCIENTIFIC REPORTS, 4:5325, 23 June 2014 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0008] A method for manufacturing an image display device according to one embodiment of the present invention includes the steps of: forming a layer including a first portion of a single-crystal metal on a substrate; forming a semiconductor layer including a light-emitting layer on the first portion; processing the semiconductor layer to form a light-emitting element including a light-emitting surface on the first portion and an upper surface opposite the light-emitting surface; forming a first insulating film covering the substrate, the layer including the first portion, and the light-emitting element; forming a circuit element on the first insulating film; forming a light-shielding member between the circuit element and the light-emitting element; forming a second insulating film covering the first insulating film and the circuit element; forming a first via that penetrates the first insulating film and the second insulating film; forming a wiring layer on the second insulating film; removing the substrate; and removing at least a portion of the first portion on the light-emitting surface. The first via is provided between the wiring layer and the upper surface and electrically connects the wiring layer to the upper surface.

[0009] An image display device according to one embodiment of the present invention includes a light-emitting element including a light-emitting surface and an upper surface opposite the light-emitting surface, a first insulating film covering the light-emitting element so as to expose the light-emitting surface, a circuit element provided on the first insulating film, a light-shielding member provided between the circuit element and the upper surface, a second insulating film covering the first insulating film and the circuit element, a first via provided through the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The first via is provided between the wiring layer and the upper surface and electrically connects the wiring layer to the upper surface. The first insulating film includes a first surface on the light-emitting surface side. The light-emitting surface is provided in a recessed position relative to the first surface.

[0010] An image display device according to one embodiment of the present invention includes a first semiconductor layer including a light-emitting surface capable of forming a plurality of light-emitting regions; a plurality of light-emitting layers spaced apart from one another on the first semiconductor layer; a plurality of second semiconductor layers each provided on the plurality of light-emitting layers, each having a conductivity type different from that of the first semiconductor layer, and each including a plurality of upper surfaces opposite to the surface on which the plurality of light-emitting layers are provided; a first insulating film covering the first semiconductor layer, the plurality of light-emitting layers, and the plurality of second semiconductor layers so as to expose the light-emitting surface; a plurality of transistors spaced apart from one another on the first insulating film; a light-shielding member provided between the plurality of transistors and the plurality of upper surfaces; a second insulating film covering the first insulating film and the plurality of transistors; a plurality of first vias extending through the first insulating film and the second insulating film; and a wiring layer provided on the second insulating film. The plurality of second semiconductor layers are separated from one another by the first insulating film. The plurality of light-emitting layers are separated from one another by the first insulating film. The plurality of first vias are respectively provided between the wiring layer and the plurality of upper surfaces, electrically connecting the wiring layer to the plurality of upper surfaces. The first insulating film includes a first surface on the light emitting surface side, and the light emitting surface is provided in a recessed portion relative to the first surface.

[0011] An image display device according to one embodiment of the present invention includes a plurality of light-emitting elements, each of which includes a light-emitting surface and an upper surface opposite the light-emitting surface; a first insulating film covering the plurality of light-emitting elements so as to expose the light-emitting surface; a circuit element provided on the first insulating film; a light-shielding member provided between the circuit element and the upper surface; a second insulating film covering the first insulating film and the circuit element; a plurality of first vias provided through the first insulating film and the second insulating film; and a wiring layer provided on the second insulating film. The plurality of first vias are provided between the wiring layer and the plurality of upper surfaces and electrically connect the wiring layer to the plurality of upper surfaces, respectively. The first insulating film includes a first surface on the side of the plurality of light-emitting surfaces. The plurality of light-emitting surfaces are provided in a recessed position relative to the first surface. [Effects of the Invention]

[0012] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer step of light emitting elements and improves yield.

[0013] According to one embodiment of the present invention, it is possible to reduce the size of the light emitting element, and a high-definition image display device is realized. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic cross-sectional view illustrating a part of an image display device according to a first embodiment. [Figure 2] FIG. 2 is a schematic enlarged view of part A in FIG. [Figure 3] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 4] FIG. 1 is a schematic plan view illustrating a part of an image display device according to a first embodiment. [Figure 5A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 5B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6C] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 8A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 8B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 9B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 10A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 10B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 10C] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 10D] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views illustrating a part of a modified example of the manufacturing method of the image display device of the first embodiment. [Figure 12] FIG. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 13] FIG. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a second embodiment. [Figure 15] FIG. 15 is a schematic enlarged view of part C in FIG. [Figure 16] FIG. 10 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 17A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 17B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 18A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 18B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 19A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 19B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 20] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment. [Figure 21A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 21B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 22A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 22B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 23] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 24] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment. [Figure 25A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 25B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 26A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 26B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 27] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fifth embodiment. [Figure 28] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fifth embodiment. [Figure 29] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 30] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 31] FIG. 13 is a block diagram illustrating an image display device according to a seventh embodiment. [Figure 32] FIG. 13 is a block diagram illustrating an image display device according to a modified example of the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0016] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. FIG. 1 shows a schematic configuration of a sub-pixel 20 of the image display device of this embodiment. In the following, the description may be made using the XYZ three-dimensional coordinate system. The light-emitting elements 150 are arranged in a two-dimensional plane as shown in FIGS. 12 and 13 (described later). A light-emitting element 150 is provided for each subpixel 20. The two-dimensional plane on which the subpixels 20 are arranged is defined as the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line BB' in FIG. 4 (described later), and is a cross section obtained by connecting multiple cross sections perpendicular to the XY plane on a single plane. In other figures, as in FIG. 1, the cross sections of multiple planes perpendicular to the XY plane do not show the X-axis and Y-axis, but show only the Z-axis perpendicular to the XY plane. In other words, in these figures, the plane perpendicular to the Z-axis is defined as the XY plane.

[0017] In the following, the positive direction of the Z axis may be referred to as "up" or "above," and the negative direction of the Z axis may be referred to as "down" or "below," but the direction along the Z axis is not necessarily limited to the direction in which gravity acts. The length along the Z axis may be referred to as height.

[0018] The subpixel 20 has a light-emitting surface 151S that is substantially parallel to the XY plane. The light-emitting surface 151S is a surface that emits light mainly in the negative direction of the Z axis, which is perpendicular to the XY plane. In this embodiment, its modifications, and all embodiments and modifications thereof described below, the light-emitting surface emits light mainly in the negative direction of the Z axis.

[0019] 1, a subpixel 20 of the image display device includes a light-emitting element 150, a light-shielding electrode (light-shielding member) 160a, a first interlayer insulating film 156, a transistor (circuit element) 103, a second interlayer insulating film 108, a via (first via) 161a, and a wiring layer 110. The subpixel 20 further includes a color filter (wavelength conversion member) 180.

[0020] In this embodiment, the light-emitting element 150 is provided on a color filter 180. The first interlayer insulating film 156 is also provided on the color filter 180. The surface of the light-emitting element 150 on the color filter 180 is a light-emitting surface 151S. The surface of the first interlayer insulating film 156 on the color filter 180 is a first surface 156S1. The light-emitting surface 151S and the first surface 156S1 are connected to the color filter 180 via a transparent resin layer 188. The transparent resin layer 188 is provided to planarize the light-emitting surface 151S and the first surface 156S1 and connect the color filter 180. The light-emitting element 150 emits light via the light-emitting surface 151S, the transparent resin layer 188, and the color filter 180.

[0021] The light emitting element 150 is driven by a transistor 103 provided on the first interlayer insulating film 156. The transistor 103 is a thin film transistor (TFT).

[0022] The configuration of the sub-pixel 20 will be described in detail below. The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly below the light-emitting surface 151S of the light-emitting element 150 in accordance with the shape of the light-emitting surface 151S. In the color filter 180, the portion other than the color conversion portion 182 is made into a light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a clear image.

[0023] The color conversion section 182 may have one layer or two or more layers. FIG. 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., wavelength, of the light emitted by the subpixel 20. When the emission color of the subpixel 20 is red, the color conversion section 182 preferably has two layers, made up of a color conversion layer 183 and a filter layer 184 that transmits red light. When the emission color of the subpixel 20 is green, the color conversion section 182 preferably has two layers, made up of a color conversion layer 183 and a filter layer 184 that transmits green light. When the emission color of the subpixel 20 is blue, the color conversion section 182 preferably has one layer.

[0024] When color conversion section 182 has two layers, one layer is color conversion layer 183 and the other layer is filter layer 184. Color conversion layer 183 is stacked on filter layer 184, and is provided at a position closer to light emitting element 150 than filter layer 184.

[0025] Color conversion layer 183 converts the wavelength of light emitted by light emitting element 150 to a desired wavelength. In the case of a subpixel 20 that emits red light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 630 nm±20 nm. In the case of a subpixel 20 that emits green light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 532 nm±20 nm.

[0026] Filter layer 184 blocks the wavelength component of blue light emission that remains without being color converted by color conversion layer 183 .

[0027] When the color of light emitted by subpixel 20 is blue, the light may be output via color conversion layer 183, or may be output directly without going through color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is approximately 467 nm±30 nm, the light may be output without going through color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is 410 nm±30 nm, it is preferable to provide color conversion layer 183 in order to convert the wavelength of the output light to approximately 467 nm±30 nm.

[0028] Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with a filter layer 184 that transmits blue light, minute reflections of external light other than blue light that occur on the surface of the light-emitting element 150 are suppressed.

[0029] The color filter 180 has a connection surface 180S. A transparent resin layer 188 is provided on the connection surface 180S. The light emitting element 150 and the first interlayer insulating film 156 are provided on the connection surface 180S with the transparent resin layer 188 interposed therebetween.

[0030] The light emitting element 150 includes a light emitting surface 151S provided on the connection surface 180S. The light emitting element 150 includes an upper surface 153U provided on the opposite side of the light emitting surface 151S. In this example, the outer peripheral shapes of the light emitting surface 151S and the upper surface 153U in the XY plane are square or rectangular, and the light emitting element 150 is a prismatic element having the light emitting surface 151S on the connection surface 180S. The cross section of the prismatic element may be a polygon with five or more sides. The light emitting element 150 is not limited to a prismatic element, and may also be a cylindrical element.

[0031] The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from the light-emitting surface 151S toward the upper surface 153U. The light-emitting surface 151S, which is the n-type semiconductor layer 151, is provided on the connection surface 180S. Therefore, the light-emitting element 150 emits light in the negative direction of the Z axis through the transparent resin layer 188 and the color conversion unit 182 of the color filter 180.

[0032] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided on the connection surface 180S so as to protrude in one direction from the n-type semiconductor layer 151. The height of the connection portion 151a from the light emitting surface 151S is the same as the height from the light emitting surface 151S to the n-type semiconductor layer 151 or is shorter than the height from the light emitting surface 151S to the n-type semiconductor layer 151. The n-type semiconductor layer 151 includes the connection portion 151a, and the connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0033] When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane is, for example, approximately square or rectangular. When the shape of the light emitting element 150 in the XY plane is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane is cylindrical, the shape of the light emitting element 150 in the XY plane is not limited to a circle and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element in the planar view, the degree of freedom in the wiring layout, etc. is improved.

[0034] The light emitting element 150 may include, for example, In X Al Y Ga 1-X-YA gallium nitride compound semiconductor including a light emitting layer such as N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, approximately 467 nm±30 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of approximately 410 nm±30 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned values ​​and can be any appropriate wavelength.

[0035] The light-shielding electrode 160a is provided over the upper surface 153U. The light-shielding electrode 160a is provided between the upper surface 153U and the via 161a, and electrically connects the upper surface 153U to one end of the via 161a. The light-shielding electrode 160a is made of a conductive material with light-shielding properties and is formed to a sufficient thickness to exhibit light-shielding properties. The light-shielding electrode 160a establishes an ohmic connection with the p-type semiconductor layer 153 and blocks emitted light and scattered light from the light-emitting element 150 upward. The light-shielding electrode 160a prevents light from reaching circuit elements, including the transistor 103, which are provided above the light-emitting element 150, to prevent malfunction of the circuit elements.

[0036] The first interlayer insulating film (first insulating film) 156 has a first surface 156S1 provided on the transparent resin layer 188. The first interlayer insulating film 156 is provided on a connection surface 180S of the color filter 180 via the transparent resin layer 188. The first surface 156S1 of the first interlayer insulating film 156 is the surface that connects to the transparent resin layer 188.

[0037] The first interlayer insulating film (first insulating film) 156 covers the side surfaces of the light-emitting element 150 and the light-shielding electrodes 160a. The first interlayer insulating film 156 electrically isolates adjacently arranged light-emitting elements 150. The first interlayer insulating film 156 also electrically isolates the light-shielding electrodes 160a provided on the electrically isolated light-emitting elements 150. The first interlayer insulating film 156 electrically isolates the light-emitting element 150 and the light-shielding electrodes 160a from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming the circuit 101 including circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from thermal stress and the like that occurs when the transistor 103 and the like are formed.

[0038] The first interlayer insulating film 156 is made of an organic insulating material. The organic insulating material used for the first interlayer insulating film 156 is preferably a white resin that has light reflectivity. By using a white resin for the first interlayer insulating film 156, it is possible to reflect light emitted laterally from the light emitting element 150 and return light resulting from the interface between the light emitting surface 151S and the substrate 102, etc. Therefore, the light emitting efficiency of the light emitting element 150 is substantially improved.

[0039] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin, such as SOG (Spin On Glass), or a novolac-type phenolic resin. The scattering particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light emitting element 150. The scattering particles preferably have a diameter of about 1 / 2 the wavelength of the light. Examples of such scattering particles include TiO2, Al2O3, and ZnO.

[0040] In addition to the above, the white resin can also be formed by utilizing a large number of minute pores dispersed in the transparent resin. When the first interlayer insulating film 156 is whitened, a SiO2 film formed by ALD (Atomic-Layer-Deposition) or CVD may be used on top of the SOG film or the like.

[0041] The first interlayer insulating film 156 may be a black resin. By using a black resin for the first interlayer insulating film 156, scattering of light within the subpixels 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display sharper images.

[0042] A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided to ensure flatness when forming the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is an insulating film made of, for example, SiO2 or the like.

[0043] The transistor 103 is formed on a TFT lower layer film 106. In addition to the transistor 103, other circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and a circuit 101 is formed with wiring and the like. For example, in FIG. 3 described below, the transistor 103 corresponds to the drive transistor 26. Other circuit elements in FIG. 3 include the selection transistor 24 and the capacitor 28. The circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a first wiring layer 110.

[0044] In this example, the transistor 103 is a p-channel TFT. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous silicon region formed on the TFT underlayer film 106. For example, laser annealing using a laser is used to polycrystallize and activate the amorphous silicon region. A TFT formed by the LTPS process has sufficiently high mobility.

[0045] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the regions 104s and 104d. The regions 104s and 104d contain impurities such as boron (B) and boron fluoride (BF), forming p-type semiconductor regions. The region 104s is in ohmic contact with the via 111s, and the region 104d is in ohmic contact with the via 111d.

[0046] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate it from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i. The channel formed in the region 104i can be controlled by the potential of the gate 107, thereby controlling the current flowing between the regions 104s and 104d.

[0047] The insulating layer 105 is made of, for example, SiO2. The insulating layer 105 may be a multi-layer insulating layer containing SiO2, Si3N4, or the like.

[0048] The gate 107 may be formed of, for example, polycrystalline Si, or may be formed of a high-melting point metal such as W or Mo. When the gate 107 is formed of a polycrystalline Si film, it is formed by, for example, CVD or the like.

[0049] The second interlayer insulating film 108 is provided on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of a white resin or an inorganic film such as SiO2. The second interlayer insulating film 108 also functions as a planarizing film for forming the wiring layer 110.

[0050] The vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108 and the insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes a plurality of wirings that may have different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110k. These wirings 110s, 110d, and 110k are formed separately.

[0051] A portion of the wiring 110s is provided above the region 104s. Another portion of the wiring 110s is connected to a power supply line 3 shown in FIG. 3, which will be described later, for example. A portion of the wiring (first wiring) 110d is provided above the region 104d. Another portion of the wiring 110d is provided above the upper surface 153U. A portion of the wiring (second wiring) 110k is provided above the connection portion 151a. The wiring 110k is connected to a ground line 4 shown in the circuit shown in FIG. 3, which will be described later, for example.

[0052] In the cross-sectional views from Figure 1 onwards, unless otherwise specified, the symbol representing a wiring layer is shown next to one of the wires that make up that wiring layer. In the example of Figure 1, the symbol for wiring layer 110 is shown next to wire 110s.

[0053] The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0054] The wiring 110s is connected to the region 104s through a via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the power line 3 through the via 111s and the wiring 110s.

[0055] The wiring 110d is connected to the region 104d through a via 111d. The region 104d is the drain region of the transistor 103.

[0056] The via (first via) 161a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the light-shielding electrode 160a. The via 161a is provided between the wiring (first wiring) 110d and the light-shielding electrode 160a, and electrically connects the wiring 110d and the light-shielding electrode 160a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the light-shielding electrode 160a, the via 161a, the wiring 110d, and the via 111d.

[0057] The via (second via) 161k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the connection portion (first connection portion) 151a. The via 161k is provided between the wiring (second wiring) 110k and the connection portion 151a, and electrically connects the wiring 110k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 3 via the connection portion 151a, the via 161k, and the wiring 110k.

[0058] The wiring layer 110 and the vias 111s, 111d, 161a, and 161k are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the Al and Ti laminated film, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0059] A protective layer may be provided over the second interlayer insulating film 108 and the wiring layer 110 to protect them from the external environment.

[0060] FIG. 2 is a schematic enlarged view of part A in FIG. 2 shows in detail the positional relationship in the Z-axis direction between first surface 156S1 of first interlayer insulating film 156 and light-emitting surface 151S. First surface 156S1 is one surface of first interlayer insulating film 156, and is the surface on the light-emitting surface 151S side. 2, the recess 156C is formed by the first interlayer insulating film 156 and the light-emitting surface 151S, and is recessed from the first surface 156S1 in the positive direction of the Z axis. The light-emitting surface 151S is a surface that is approximately parallel to the first surface 156S1, and is provided at a position offset in the positive direction of the Z axis from the first surface 156S1. The offset in the Z axis direction between the light-emitting surface 151S and the first surface 156S1 is approximately equal to the thickness of the single-crystal metal layer used to form the light-emitting element 150 in the description of the manufacturing method using FIGS. 5A to 9B, which will be described later.

[0061] The recess 156C is filled with the transparent resin layer 188 shown in FIG. 1, and the transparent resin layer 188 flattens the first surface 156S1 and the light-emitting surface 151S to some extent, facilitating the formation of a color filter.

[0062] FIG. 3 is a schematic block diagram illustrating an image display device according to this embodiment. As shown in Fig. 3, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged, for example, in a lattice pattern. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.

[0063] A pixel 10 includes multiple subpixels 20 that emit light of different colors. Subpixel 20R emits red light. Subpixel 20G emits green light. Subpixel 20B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 20R, 20G, and 20B emitting light at desired brightness.

[0064] One pixel 10 includes three subpixels 20R, 20G, and 20B, which are arranged linearly on the X axis, as shown in Fig. 3. In each pixel 10, subpixels of the same color may be arranged in the same column, or, as in this example, subpixels of different colors may be arranged in different columns.

[0065] The image display device 1 further includes power lines 3 and ground lines 4. The power lines 3 and ground lines 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power lines 3 and ground lines 4 are electrically connected to each subpixel 20, and supply power to each subpixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and the GND terminal 4a are provided at the ends of the power lines 3 and the ground lines 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power terminal 3a with respect to the GND terminal 4a.

[0066] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction of the sub-pixels 20.

[0067] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 in each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0068] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0069] The subpixel 20 includes a light-emitting element 22, a select transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3 and Figure 4 described below, the select transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0070] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness that corresponds to the current flowing through the light-emitting element 22.

[0071] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a power line 3.

[0072] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current that has passed through it.

[0073] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. In other words, the row selection circuit 5 scans the rows in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned subpixels 20, causing them to emit light. The brightness of the subpixels 20 is determined by the current flowing through the light-emitting elements 22. The subpixels 20 emit light at a gradation based on the determined brightness, and an image is displayed in the display area 2.

[0074] FIG. 4 is a schematic plan view illustrating a part of the image display device of this embodiment. In Fig. 4, line BB' represents a cutting line in the cross-sectional view of Fig. 1 etc. In this embodiment, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction with a first interlayer insulating film 156 interposed therebetween. The light-emitting element 150 corresponds to the light-emitting element 22 in Fig. 3. The driving transistor 103 corresponds to the driving transistor 26 in Fig. 3 and is also denoted as T2.

[0075] 4, the cathode electrode of the light-emitting element 150 is provided by a connection portion 151a. The connection portion 151a is provided in a layer lower than the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k through a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k through a contact hole 161k1.

[0076] The anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in FIG. 1. The light-shielding electrode 160a is provided on the upper surface 153U of the p-type semiconductor layer 153. The light-shielding electrode 160a is connected to one end of the wiring 110d through a via 161a. More specifically, one end of the via 161a is connected to the light-shielding electrode 160a, and the other end of the via 161a is connected to the wiring 110d through a contact hole 161a1.

[0077] The other end of the wiring 110d is connected to the drain electrode of the transistor 103 through a via 111d. The drain electrode of the transistor 103 is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through a via 111s. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the wiring layer 110 includes a power line 3, and the wiring 110s is connected to the power line 3.

[0078] In this example, the ground line 4 is provided in a layer higher than the wiring layer including the wiring 110s. Although not shown in FIG. 1, an interlayer insulating film is further provided on the wiring layer 110, and the ground line 4 is provided on the interlayer insulating film.

[0079] In this way, the light emitting element 150 can be electrically connected to the wiring layer 110 provided above the light emitting element 150 by using the vias 161a and 161k.

[0080] A method for manufacturing the image display device 1 of this embodiment will be described. 5A to 9B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. 5A, in the manufacturing method of the image display device of this embodiment, a substrate 102 is prepared. The substrate 102 is a light-transmitting substrate, for example, a substantially rectangular glass substrate measuring approximately 1500 mm × 1800 mm. A metal layer 1130 is formed on the substrate surface 102a. The metal layer 1130 is formed, for example, by forming a layer of a metal material over the entire surface of the substrate surface 102a by sputtering or the like, and then patterning the layer so as to leave areas where a light-emitting layer will be formed.

[0081] Alternatively, the metal layer 1130 may be formed by providing a mask having a pattern with openings corresponding to the locations where the light-emitting layer is to be formed on the substrate surface 102a, and then forming the patterned metal layer 1130.

[0082] The metal layer 1130 is formed using a metal material such as Cu, Hf, etc. The metal layer 1130 is preferably formed by sputtering or the like, since it can be formed at a low temperature.

[0083] The patterned metal layer 1130 is single-crystallized by annealing. Preferably, the annealing is performed so that the entire patterned metal layer 1130 is single-crystallized. For example, annealing by laser irradiation is suitably used to single-crystallize the metal layer 1130. Pulsed laser annealing can single-crystallize the metal layer 1130 while suppressing the temperature influence on layers below the metal layer 1130 to a low temperature of approximately 400°C to 500°C, so that a substrate made of glass, organic resin, or the like can be used for the substrate 102.

[0084] 5B, the metal layer 1130 shown in FIG. 5A is subjected to an annealing process to form a metal seed layer (a layer including a first portion) 1130a that is single-crystallized. The semiconductor layer 1150 is formed over the metal seed layer 1130a. In the semiconductor layer 1150, an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153 are formed in this order from the metal seed layer 1130a toward the positive direction of the Z axis.

[0085] The semiconductor layer 1150 can be formed by physical vapor deposition methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering, with low-temperature sputtering being preferred. Low-temperature sputtering is preferably performed using light or plasma assistance during film formation, since this allows for lower temperatures. Epitaxial growth by MOCVD can sometimes exceed 1000°C. In contrast, it is known that low-temperature sputtering can epitaxially grow GaN crystals, including light-emitting layers, on single-crystal metal layers at low temperatures of approximately 400°C to 700°C (see Non-Patent Documents 1 and 2, etc.). Such low-temperature sputtering is suitable for forming the semiconductor layer 1150 on a circuit substrate having TFTs and the like formed by the LTPS process.

[0086] The semiconductor layer 1150 may include, for example, GaN, and more particularly, In X Al Y Ga 1-X-Y Includes N (0≦X, 0≦Y, X+Y<1), etc.

[0087] In the early stages of crystal growth, crystal defects may occur due to mismatching of crystal lattice constants, and crystals with crystal defects exhibit n-type. Therefore, when semiconductor layer 1150 is formed from n-type semiconductor layer 1151 on substrate 102, as in this example, a large margin can be taken in the production process, which has the advantage of making it easier to improve yield.

[0088] By using an appropriate deposition technique to grow a GaN semiconductor layer 1150 on the entire surface of the single-crystallized metal seed layer 1130a, the single-crystallized semiconductor layer 1150 including the light-emitting layer 1152 is formed on the metal seed layer 1130a. The semiconductor layer 1150 is formed within the region indicated by the two-dot chain line in FIG. 5B.

[0089] During the growth process of the semiconductor layer 1150, amorphous deposits 1162 containing Ga, a growth seed material, etc., may be deposited on the substrate surface 102a where the metal seed layer 1130a is not present. In this example, the deposits 1162 are stacked in the order of deposits 1162a, 1162b, and 1162c from the substrate surface 102a toward the positive direction of the Z axis. The deposit 1162a is deposited when the n-type semiconductor layer 1151 is formed, the deposit 1162b is deposited when the light-emitting layer 1152 is formed, and the deposit 1162c is deposited when the p-type semiconductor layer 1153 is formed, but this is not limitative.

[0090] A metal layer 1160 is formed on the semiconductor layer 1150. In this example, the metal layer 1160 is also formed on the deposit 1162. More specifically, the metal layer 1160 is formed on the p-type semiconductor layer 1153 and on the deposit 1162c.

[0091] The relationship between the single-crystallized region of the metal seed layer and the region where the semiconductor layer 1150 grows will be described. 6A to 6C show cross-sectional views of three types of patterned portions 1131a. The patterned portions 1131a are portions formed by patterning the metal seed layer 1130a shown in FIG. 5B. FIG. 6A shows a state in which the entire patterned portion 1131a has been single-crystallized. As shown in Fig. 6A, the entire patterned portion (first portion) 1131a is single-crystallized. More specifically, the patterned portion 1131a is single-crystallized across the XY plane, and is single-crystallized from the surface of the patterned portion 1131a to the substrate surface 102a in the Z-axis direction. The semiconductor layer 1150 is formed over the patterned portion 1131a, as indicated by the two-dot chain line in Fig. 6A.

[0092] 6B and 6C show that part of the patterned portion 1131a has been single-crystallized. As shown in FIG. 6B, the patterned portion 1131a includes a single-crystallized portion (first portion) 1131a1 and a non-single-crystallized portion 1131a2. The single-crystallized portion 1131a1 is formed from the surface of the patterned portion 1131a in the Z-axis direction to the substrate surface 102a. In this example, the non-single-crystallized portion 1131a2 is formed to surround the single-crystallized portion 1131a1, but the non-single-crystallized portion 1131a2 is formed to contact at least a portion of the outer periphery of the single-crystallized portion 1131a1. As shown by the two-dot chain line in FIG. 6B, the semiconductor layer 1150 is formed over the single-crystallized portion 1131a1 of the patterned portion 1131a. Amorphous deposits containing, for example, Ga, a growth seed material, are deposited on the non-single-crystallized portion 1131a2 and the substrate surface 102a.

[0093] As shown in FIG. 6C, the patterned portion 1131a includes a single-crystallized portion (first portion) 1131a1 and a non-single-crystallized portion 1131a2. The single-crystallized portion 1131a1 is formed near the surface of the patterned portion 1131a in the Z-axis direction and does not reach the substrate surface 102a. The non-single-crystallized portion 1131a2 is formed around the single-crystallized portion 1131a1, as in the case of FIG. 6B. The semiconductor layer 1150 is formed over the single-crystallized portion 1131a1 of the patterned portion 1131a, as indicated by the two-dot chain line in FIG. 6C. Amorphous deposits containing, for example, Ga, a growth seed material, are deposited on the non-single-crystallized portion 1131a2 and the substrate surface 102a.

[0094] In this way, the semiconductor layer 1150 is formed on the single-crystallized portion of the patterned portion 1131a. Therefore, the area of ​​the single-crystallized portion (first portion) of the patterned portion 1131a in the XY plane is sufficiently larger than the area of ​​the bottom surface of the light-emitting element, and the periphery of the single-crystallized portion in the XY plane is set to include the periphery of the light-emitting element 150. In other words, in the XY plane, the periphery of the light-emitting element 150 is located within the periphery of the single-crystallized portion.

[0095] 5A is made of, for example, Cu or Hf. The metal material used for metal layer 1130 is not limited to Cu or Hf, as long as it can be made into a single crystal by annealing. From the viewpoint of reducing thermal stress on circuit board 100, a metal material that can be made into a single crystal by annealing at a lower temperature is preferable.

[0096] In this embodiment, the crystal formation of GaN is promoted using a metal seed layer 1130a made of a single crystal metal as a seed. When the semiconductor layer 1150 is formed on the metal seed layer 1130a, a conductive buffer layer may be provided on the metal seed layer 1130a, and the semiconductor layer may be grown on this buffer layer by the above-mentioned low-temperature sputtering method or the like. The buffer layer may be made of any material that promotes the crystal formation of GaN. A graphene sheet may also be used as the buffer layer.

[0097] As shown in FIG. 7A, the metal layer 1160 and the semiconductor layer 1150 shown in FIG. 5B are processed into a desired shape by etching, and a light-shielding electrode (light-shielding member) 160a and a light-emitting element 150 are formed.

[0098] In the process of forming the light-emitting element 150, the connection portion 151a is formed, and then, by further etching, a light-shielding electrode (light-shielding member) 160a is formed in other portions and on the upper surface 153U. This makes it possible to form the light-emitting element 150 having the connection portion 151a that protrudes from the n-type semiconductor layer 151 onto the substrate surface 102a in the positive direction of the X axis. The light-emitting element 150 is formed, for example, by a dry etching process, and preferably by anisotropic plasma etching (reactive ion etching, RIE).

[0099] The metal seed layer 1130a shown in FIG. 5B is etched and formed into a seed plate (first portion) 130a. In this example, the outer periphery of the seed plate 130a in the XY plane view is formed so as to substantially coincide with the outer periphery of the light emitting surface 151S of the light emitting element 150. The outer periphery of the seed plate 130a in the XY plane view may be formed so as to include the outer periphery of the bottom surface 151B. In other words, the outer periphery of the bottom surface 151B may be positioned within the outer periphery of the seed plate 130a in the XY plane view.

[0100] A first interlayer insulating film (first insulating film) 156 is formed so as to cover the substrate surface 102a, the light emitting element 150, and the light-shielding electrode 160a.

[0101] 7B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156 by, for example, CVD. A Si layer 1104 is formed on the formed TFT lower layer film 106. The Si layer 1104 is an amorphous Si layer when formed, and after formation, the Si layer 1104 is polycrystallized by, for example, scanning with an excimer laser pulse multiple times to form the Si layer 1104.

[0102] As shown in FIG. 8A, the polycrystallized Si layer 1104 shown in FIG. 7B is processed into an island shape to form the TFT channel 104. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104 with the insulating layer 105 interposed therebetween. The transistor (circuit element) 103 is formed by selectively doping the gate 107 with impurities such as B and thermally activating it. Regions 104s and 104d are p-type active regions and function as the source region and drain region of the transistor 103, respectively. Region 104i is an n-type active region and functions as the channel.

[0103] When the LTPS process is used, the transistor 103 is formed in the desired position on the TFT underlayer film 106 in this manner.

[0104] 8B, a second interlayer insulating film (second insulating film) 108 is provided so as to cover the insulating layer 105 and the gate 107. An appropriate manufacturing method is applied to form the second interlayer insulating film 108 depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is made of SiO2, a technique such as ALD or CVD is used.

[0105] The flatness of the second interlayer insulating film 108 only needs to be such that the wiring layer 110 can be formed thereon, and a planarization step does not necessarily have to be performed. If the planarization step is not performed on the second interlayer insulating film 108, the number of steps can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 is thin, the depth of the via holes for the vias 161a and 161k can be made shallower, ensuring a sufficient opening diameter. This makes it easier to ensure electrical connection through the vias, and reduces yield losses due to poor electrical characteristics.

[0106] Vias 161a and 161k are formed penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via (first via) 161a is formed by filling a conductive material into a via hole formed to reach the light-shielding electrode 160a, and is electrically connected to the light-shielding electrode 160a. The via (second via) 161k is formed by filling a conductive material into a via hole formed to reach the connection portion (first connection portion) 151a, and is electrically connected to the connection portion 151a.

[0107] Vias 111s and 111d are formed to penetrate the second interlayer insulating film 108 and the insulating layer 105. The via 111s is formed to reach the region 104s. The via 111d is formed to reach the region 104d. RIE, for example, is used to form via holes to form the vias 161a, 161k, 111s, and 111d.

[0108] The wiring layer 110 is formed on the second interlayer insulating film 108. Wirings 110k, 110d, and 110s are formed. The wiring 110k is connected to one end of the via 161k. The wiring 110d is connected to one end of the via 161a and one end of the via 111d. The wiring 110s is connected to one end of the via 111s. In forming the wiring layer 110, the wirings 110k, 110d, and 110s may be formed simultaneously with the formation of the vias 161k, 111d, and 111s.

[0109] 9A, an adhesive layer 1170 is formed on the second interlayer insulating film 108 and the wiring layer 110, and a reinforcing substrate 1180 is bonded to the adhesive layer 1170. The reinforcing substrate 1180 is provided to maintain sufficient strength for the structure after the substrate 102 shown in FIG. 8B has been removed, during subsequent processing, movement, and the like.

[0110] After the reinforcing substrate 1180 is provided, the substrate 102 is removed. Simultaneously with the removal of the substrate 102, the seed plate 130a shown in FIG. 8B is also removed. The seed plate 130a may be removed after the removal of the substrate 102. The removal of the substrate 102 and the seed plate 130a is performed by wet etching, laser lift-off, or the like. After the substrate 102 and the seed plate 130a are removed, the first surface 156S1 of the first interlayer insulating film 156 and the light-emitting surface 151S are exposed.

[0111] 9B, a transparent resin layer 188 is formed on the first surface 156S1 and the light-emitting surface 151S. The transparent resin layer 188 is formed so as to fill the recess 156C of the first interlayer insulating film 156 shown in FIG. 2, and forms a CF formation surface 188S for forming a color filter.

[0112] 10A to 10D are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. 10A to 10D show a method for forming a color filter by an inkjet method.

[0113] 10A, a structure 1192 is prepared in which the CF formation surface 188S of the transparent resin layer 188 is exposed. The structure 1192 includes the transparent resin layer 188, the light-emitting element 150 on the transparent resin layer 188, the adhesive layer 1170, and the reinforcing substrate 1180, as well as the first interlayer insulating film 156, the light-shielding electrode 160a, the TFT lower layer film 106, the TFT channel, the insulating layer 105, the gate 107, the vias 111s, 111d, 161a, and 161k, the wiring layer 110, and the like shown in FIG.

[0114] 10B, the light-shielding portion 181 is formed in an area on the CF forming surface 188S that does not include the light-emitting surface 151S. The light-shielding portion 181 is formed using, for example, screen printing or photolithography technology.

[0115] As shown in FIG. 10C, phosphors corresponding to the emitted light color are ejected from inkjet nozzles to form color conversion layers 183. The phosphors color the areas on the CF formation surface 188S where the light-shielding portions 181 are not formed. For example, fluorescent paints using general phosphor materials, perovskite phosphor materials, or quantum dot phosphor materials are used as the phosphors. Perovskite phosphor materials and quantum dot phosphor materials are preferred because they can realize each emitted color, have high monochromaticity, and enhance color reproducibility. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and for an appropriate time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portions 181.

[0116] As already explained, if no color conversion unit is formed for a blue-emitting subpixel, then color conversion layer 183 is not formed. Furthermore, if a single layer of color conversion unit is sufficient when forming a blue color conversion layer for a blue-emitting subpixel, then the thickness of the blue phosphor coating is preferably the thickness of filter layer 184 laminated on color conversion layer 183, and is approximately the same as the thickness of light-shielding unit 181.

[0117] 10D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied on top of the phosphor coating. The total thickness of the phosphor and paint coating is approximately the same as the thickness of the light-shielding portion 181.

[0118] A process for forming a film-type color filter 180a will be described below instead of the inkjet-type color filter formation process. FIG. 11 is a schematic cross-sectional view illustrating a part of a modified example of the manufacturing method of the image display device of this embodiment. In Fig. 11, the diagram above the arrow is structural body 1192. Structural body 1192 includes transparent resin layer 188, light-emitting element 150, adhesive layer 1170, and reinforcing substrate 1180, etc., as shown in Fig. 9B. The diagram below the arrow shows glass substrate 186, color filter 180a bonded to glass substrate 186, and transparent thin-film adhesive layer 189 that bonds color filter 180a to structural body 1192. The arrow represents the state in which color filter 180a, together with glass substrate 186 and transparent thin-film adhesive layer 189, is attached to structural body 1192. 11, to avoid complexity, the reference numerals and the components themselves including the reference numerals are omitted for some of the components of the structure 1192. The components in the structure 1192 that are not shown are the first interlayer insulating film 156, the circuit 101, and the vias 161a and 161k shown in FIG.

[0119] As shown in Figure 11, color filter (wavelength conversion member) 180a includes light-shielding portion 181a, color conversion layers 183R, 183G, and 183B, and filter layer 184a. Light-shielding portion 181a has the same function as in the inkjet system. Color conversion layers 183R, 183G, and 183B have the same function and are made of the same material as in the inkjet system. Filter layer 184a also has the same function as in the inkjet system.

[0120] One surface of color filter 180a is bonded to structural body 1192. The other surface of color filter 180a is bonded to glass substrate 186. A transparent thin film adhesive layer 189 is provided on one surface of color filter 180a, and color filter 180a is bonded to the exposed surface of transparent resin layer 188 of structural body 1192 via transparent thin film adhesive layer 189.

[0121] In this example, the color filter 180a has color conversion sections arranged in the positive direction of the X axis in the order of red, green, and blue. For the red color conversion section, a red color conversion layer 183R is provided on the layer closer to the transparent thin film adhesive layer 189. For the green color conversion section, a green color conversion layer 183G is provided on the layer closer to the transparent thin film adhesive layer 189. For the red and green color conversion sections, a filter layer 184a is provided on the layer closer to the glass substrate 186. For the blue color conversion section, in this example, a single-layer color conversion layer 183B is provided from the glass substrate 186 side to the transparent thin film adhesive layer 189 side. However, this is not limiting; similarly to the case of other colors, a filter layer 184a may be provided on the glass substrate 186 side. The frequency characteristics of the filter layer 184 may be the same for all colors of the color conversion section, or may differ for each color of the color conversion section. A light-shielding section 181a is provided between each color conversion section.

[0122] As shown by the arrows in FIG. 11, the positions of the color conversion layers 183R, 183G, and 183B of each color are aligned with the positions of the light emitting elements 150, and the color filter 180a is attached to the structure 1192 via a transparent thin film adhesive layer 189.

[0123] Thereafter, the reinforcing substrate 1180 is removed together with the adhesive layer 1170, but an image display device may be formed without removing the reinforcing substrate 1180 and the adhesive layer 1170.

[0124] In this way, color filters 180, 180a are formed on structure 1192 including light-emitting element 150 and circuit 101, thereby forming subpixels. An appropriate method for forming color filters is selected from inkjet methods, film methods, and other methods that can equally form color filters. Forming color filter 180 using the inkjet method can omit the film attachment process, making it possible to manufacture the image display device 1 shown in FIG. 3 at lower cost.

[0125] Whether the color filter 180 is formed by an inkjet method or the film-type color filter 180a, it is desirable that the color conversion layer 183 be as thick as possible to improve color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light will approximate Lambertian, while the emission angle of the unconverted blue light will be limited by the light-shielding portion 181. This will cause the problem of viewing-angle dependency in the display color of the displayed image. In order to match the light distribution of the unconverted blue light with the light distribution of the subpixels provided with the color conversion layer 183, it is desirable that the thickness of the color conversion layer 183 be approximately half the opening size of the light-shielding portion 181.

[0126] For example, in the case of a high-resolution image display device with a resolution of about 250 ppi (pitch per inch), the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, if the color conversion material is made of spherical phosphor particles, it is preferable that they be stacked in a close-packed structure to suppress light leakage from the light emitting element 150. To achieve this, at least three particle layers are required. Therefore, the particle size of the phosphor material that makes up the color conversion layer 183 is preferably about 5 μm or less, and more preferably about 3 μm or less.

[0127] After the color filters 180 and 180a are formed, the structure 1192 shown in Fig. 10D and the like is diced together with the color filters 180 and 180a to form an image display device. Note that the step of forming the color filters 180 and 180a may be performed after the structure 1192 is diced. FIG. 12 is a schematic perspective view illustrating the image display device according to this embodiment. 12, the image display device of this embodiment has a light-emitting circuit section 172 having a large number of light-emitting elements 150 on a color filter 180. The light-emitting circuit section 172 includes, in addition to the light-emitting elements 150, a light-shielding electrode 160a and a first interlayer insulating film 156. A circuit 101 including circuit elements such as a transistor 103 is provided on the light-emitting circuit section 172 via the TFT lower layer film 106 shown in FIG. 1. The circuit 101 and the light-emitting circuit section 172 are electrically connected via vias 161a and 161k shown in FIG. 1.

[0128] (Variation) FIG. 13 is a schematic perspective view illustrating an image display device according to a modified example of this embodiment. In the image display device of the first embodiment described above, the color filter 180 is provided, but as shown in FIG. 13, the image display device may be configured to emit monochromatic light without providing a color filter.

[0129] The effects of the image display device 1 of this embodiment will be described. In the manufacturing method of the image display device 1 of this embodiment, the light emitting element 150 is formed by etching the semiconductor layer 1150 that has been crystal-grown on the substrate 102. Thereafter, the light emitting element 150 is covered with a first interlayer insulating film 156, and a circuit 101 including circuit elements such as a transistor 103 that drives the light emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, the manufacturing process is significantly shortened compared to the case where individual light emitting elements are transferred to the substrate 102.

[0130] In the manufacturing method of the image display device 1 of this embodiment, the metal layer 1130 formed on the substrate 102 is single-crystallized to form a metal seed layer 1130a, which can be used as a seed for crystal growth of the semiconductor layer 1150. For example, the metal layer 1130 can be single-crystallized by laser annealing, thereby achieving sufficiently high productivity.

[0131] For example, an image display device with 4K resolution has more than 24 million subpixels, and an image display device with 8K resolution has more than 99 million subpixels. Individually forming such a large number of light-emitting elements and mounting them on a circuit board requires an enormous amount of time. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, mounting a large number of light-emitting elements individually reduces yield due to poor connections during mounting, and further increases in costs are unavoidable. However, the manufacturing method for the image display device of this embodiment provides the following advantages.

[0132] In the manufacturing method of the image display device 1 of this embodiment, the light emitting element 150 is formed after the entire semiconductor layer 1150 is formed on the metal seed layer 1130a formed on the substrate 102, which makes it possible to eliminate the transfer step of the light emitting element 150. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time required for the transfer step can be shortened and the number of steps can be reduced compared to conventional manufacturing methods.

[0133] Since the semiconductor layer 1150 having a uniform crystal structure is grown on the metal seed layer 1130a made of a single crystal metal, the light emitting element 150 can be arranged in a self-aligned manner by appropriately patterning the metal seed layer 1130a. This eliminates the need to align the light emitting element on the substrate 102, makes it easy to miniaturize the light emitting element 150, and is suitable for high-definition displays.

[0134] After forming the light-emitting element directly on the substrate 102 by etching or the like, the light-emitting element 150 and the circuit element formed on the upper layer of the light-emitting element 150 are electrically connected by forming a via, thereby realizing a uniform connection structure and suppressing a decrease in yield.

[0135] In this embodiment, for example, the light emitting elements 150 on the glass substrate formed as described above are covered with a first interlayer insulating film 156, and a driving circuit including a TFT and a scanning circuit can be formed on the planarized surface using an LTPS process or the like. The LTPS process has the advantage that it can utilize existing flat panel display manufacturing processes and plants, and can also reduce thermal stress on the underlying light emitting elements 150 and the like, thereby improving yield.

[0136] In this embodiment, the light-emitting element 150 formed below the transistor 103 and the like can be electrically connected to the power supply line, ground line, driving transistor, and the like formed above by forming vias that penetrate the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technically established multilayer wiring technology, a uniform connection structure can be easily realized, thereby improving yield. Therefore, a decrease in yield due to poor connection of the light-emitting element and the like is suppressed.

[0137] In the image display device 1 of this embodiment, the transistor 103 is formed above the light-emitting element 150, but the light-shielding electrode 160a is formed across the upper surface 153U of the light-emitting element 150. Therefore, the light-shielding electrode 160a prevents upward scattered light and the like emitted from the light-emitting element 150 from reaching the transistor 103. This prevents the transistor 103 from malfunctioning.

[0138] The light-shielding electrode 160a can be made highly light-reflective by appropriately selecting a conductive material. The light-reflective property of the light-shielding electrode 160a allows it to reflect scattered light upward toward the light-emitting surface 151S, thereby improving the substantial light-emitting efficiency.

[0139] (Second embodiment) FIG. 14 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. 14, in the subpixel 220 of the image display device of this embodiment, the configurations of the light-emitting element 250 and the transistor 203 differ from those of the other embodiments described above. Specifically, the light-emitting surface 253S of the light-emitting element 250 is provided by a p-type semiconductor layer 253, and the transistor 203 is an n-channel transistor, which are different from those of the other embodiments described above. Another difference from the other embodiments described above is that the p-type semiconductor layer 253 and the via 261a are connected by a connection plate 230a. The same components as those of the other embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0140] The image display device of this embodiment includes a subpixel 220. The subpixel 220 includes a light-emitting element 250, a light-shielding electrode 160a, a first interlayer insulating film 156, a transistor (circuit element) 203, a second interlayer insulating film 108, a via (first via) 261k, and a wiring layer 110.

[0141] The light emitting element 250 is provided on the color filter 180. A first interlayer insulating film 156 covering the side surfaces of the light emitting element 250 is also provided on the color filter 180. The surface of the light emitting element 250 on the color filter 180 is a light emitting surface 253S. The surface of the first interlayer insulating film 156 on the color filter 180 is a first surface 156S1. The light emitting surface 253S and the first surface 156S1 are connected to the color filter 180 via a transparent resin layer 188. The transparent resin layer 188 is provided to flatten the light emitting surface 253S and the first surface 156S1 and connect the color filter 180.

[0142] The connection plate (second connection portion) 230a is a plate-like member having both sides. One surface of the connection plate 230a is connected to the surface including the light-emitting surface 253S of the p-type semiconductor layer 253. The connection plate 230a is provided so as to protrude in one direction above the color filter 180 from the surface including the light-emitting surface 253S. One end of the via 261a is connected to the surface of the connection plate 230a that is connected to the surface including the light-emitting surface 253S. The surface of the connection plate 230a opposite to the surface connected to the one end of the via 261a is covered with a transparent resin layer 188.

[0143] The light-emitting element 250 emits light through the light-emitting surface 253S, the transparent resin layer 188, and the color filter 180. The light-emitting element 250 includes an upper surface 251U provided on the opposite side of the light-emitting surface 253S. The light-emitting element 250 is a prismatic or cylindrical element, as in the other embodiments described above.

[0144] The light-emitting element 250 includes a p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked in this order from the light-emitting surface 253S toward the upper surface 251U. In this embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253. The upper surface 251U is the surface opposite to the light-emitting surface 253S.

[0145] The light emitting element 250 has the same shape in the XY plane as the light emitting element 150 of the other embodiments described above. An appropriate shape is selected depending on the layout of the circuit elements and the like.

[0146] The light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiments described above. That is, the wavelength of light emitted by the light emitting element 250 is, for example, blue light of about 467 nm±30 nm or blue-violet light of about 410 nm±30 nm. The wavelength of light emitted by the light emitting element 250 is not limited to the above values ​​and can be any appropriate value.

[0147] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the second interlayer insulating film 108, the vias 111s and 111d, and the wiring layer 110.

[0148] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with impurities such as phosphorus (P) and activated to form n-type semiconductor regions. The region 204s is in ohmic contact with the via 111s. The region 204d is in ohmic contact with the via 111d.

[0149] The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0150] In transistor 203, when a voltage higher than that of region 204s is applied to gate 107, a channel is formed in region 204i. The current flowing between regions 204s and 204d is controlled by the voltage applied to region 204s by gate 107. The TFT channel 204 and gate 107 are formed using the same materials and methods as the TFT channel 104 and gate 107 in the other embodiments described above.

[0151] The wiring layer 110 includes wirings 110s, 110d, and 210a. A part of the wiring 210a (second wiring) is provided above the connection plate 230a. Another part of the wiring 210a is connected to a power supply line 3 shown in FIG. 16, which will be described later, for example.

[0152] The vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108. The via 111s is provided between the wiring 110s and the region 204s. The via 111s electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d. The via 111d electrically connects the wiring 110d and the region 204d. The vias 111s and 111d are formed using the same materials and manufacturing methods as in the other embodiments described above.

[0153] The via (first via) 261k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the light-shielding electrode 160a. The via 261k is provided between the wiring (first wiring) 110d and the light-shielding electrode 160a, and electrically connects the wiring 110d and the light-shielding electrode 160a. Therefore, the n-type semiconductor layer 251 is electrically connected to the region 204d where the drain electrode of the transistor 203 is formed, via the light-shielding electrode 160a, the via 261k, the wiring 110d, and the via 111d.

[0154] The via (second via) 261a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connection plate (second connection portion) 230a. The via 261a is provided between the wiring (second wiring) 210a and the connection plate 230a, and electrically connects the wiring 210a and the connection plate 230a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power supply line 3 of the circuit in FIG. 16 via the connection plate 230a, the via 261a, and the wiring 210a.

[0155] FIG. 15 is a schematic enlarged view of part C in FIG. 15 shows in detail the positional relationship in the Z-axis direction between first surface 156S1 of first interlayer insulating film 156 and light-emitting surface 253S, as well as the connection relationship between connecting plate 230a and the surface including light-emitting surface 253S. As in the case of the other embodiment described above with reference to FIG. 2, first surface 156S1 is the surface of first interlayer insulating film 156 on the light-emitting surface 253S side. 15, first interlayer insulating film 156 has a first surface 156S1. Recess 256C is formed by first interlayer insulating film 156, connecting plate 230a, and light-emitting surface 253S. Recess 256C is surrounded by connecting plate 230a and light-emitting surface 253S of first interlayer insulating film 156, and is recessed from first surface 156S1 in the positive direction of the Z axis.

[0156] The connecting plate 230a is connected to the light emitting surface 253S at a surface connected to one end of the via 261a. The surface 230S opposite to the surface connected to one end of the via 261a is substantially flush with the first surface 156S1.

[0157] Light-emitting surface 253S is located in the positive direction of the Z axis relative to first surface 156S1 and surface 230S of connecting plate 230a, and is a plane that is approximately parallel to first surface 156S1 and surface 230S. The deviation of the position of light-emitting surface 253S from the positions of first surface 156S1 and surface 230S is approximately equal to the length of connecting plate 230a in the Z axis direction, i.e., the thickness of connecting plate 230a.

[0158] The recess 256C is filled with the transparent resin layer 188 shown in FIG. 14, and the light emitting surface 253S is connected to the color filter via the transparent resin layer 188 filled in the recess 256C.

[0159] FIG. 16 is a schematic block diagram illustrating an image display device according to this embodiment. 16, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, subpixels 220 are arranged in a lattice pattern on the XY plane.

[0160] As in the other embodiments described above, pixel 10 includes multiple subpixels 220 that emit light of different colors. Subpixel 220R emits red light. Subpixel 220G emits green light. Subpixel 220B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 220R, 220G, and 220B emitting light at desired brightnesses.

[0161] One pixel 10 includes three subpixels 220R, 220G, and 220B, which are arranged linearly on the X axis, as in this example. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, may have subpixels of different colors arranged in different columns.

[0162] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 16, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0163] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the ground line 4 side. In other words, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0164] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power line 3.

[0165] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

[0166] In this embodiment, the polarity of the drive transistor 226 is n-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of subpixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each subpixel 220 in the selected row. The drive transistor 226 of the subpixel 220 in the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the current that has passed through it.

[0167] The manufacturing method of this embodiment will be described. 17A to 19B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. In this example, the substrate 102 described in relation to Fig. 5A in the other embodiment above is used. The substrate 102 has a metal layer 1130 formed on a substrate surface 102a. In the following description, it is assumed that the steps in Fig. 17A and subsequent steps are applied after the step in Fig. 5A.

[0168] As shown in FIG. 17A , a semiconductor layer 1150 is formed over a single-crystallized metal seed layer 1130a. The semiconductor layer 1150 is formed in the following order: a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151, from the metal seed layer 1130a toward the positive direction of the Z axis. The semiconductor layer 1150 is formed over the metal seed layer 1130a as shown within the two-dot chain line in FIG. 17A . As in the other embodiments described above, amorphous deposits 1162 containing Ga, a growth seed material, may be deposited on the substrate surface 102a where the metal seed layer 1130a is not present. In this example, the deposits 1162 are stacked in the following order: deposits 1162d, 1162e, and 1162f, from the substrate surface 102a toward the positive direction of the Z axis. Deposit 1162d is shown as being deposited during the formation of p-type semiconductor layer 1153, deposit 1162e is shown as being deposited during the formation of light-emitting layer 1152, and deposit 1162f is shown as being deposited during the formation of n-type semiconductor layer 1151, but this is not limited to this.

[0169] A metal layer 1160 is formed on the semiconductor layer 1150. In this example, the metal layer 1160 is also formed on the deposit 1162. More specifically, the metal layer 1160 is formed on the n-type semiconductor layer 1151 and the deposit 1162f.

[0170] As shown in Figure 17B, a light-shielding electrode 160a, a light-emitting element 250, and a connecting plate 230a1 are formed. The light-shielding electrode 160a is formed in the same manner as in the other embodiments described above. The connecting plate 230a1 is formed by etching the metal seed layer 1130a shown in Figure 17A. After forming the connecting plate 230a1, the light-emitting element 250 is formed.

[0171] In the process of forming the connecting plate 230a1, the connecting plate 230a1 is formed so as to protrude from the light emitting element 250 in one direction on the substrate surface 102a. The outer periphery of the connecting plate 230a1 is set so as to include the outer periphery of the light emitting element 250 when the light emitting element 250 is projected onto the connecting plate 230a1 in an XY plane view. In other words, the outer periphery of the light emitting element 250 is disposed within the outer periphery of the connecting plate 230a1. Furthermore, the protruding portion of the connecting plate 230a1 is formed so as to ensure an area for connecting one end of a via 261a shown in FIG. 19A, which will be described later.

[0172] The connecting plate 230a1 is processed into the connecting plate 230a shown in Fig. 14 in a later step. The p-type semiconductor layer 253 of the light-emitting element 250 is connected to the via 261a through the connecting plate 230a shown in Fig. 14, so the light-emitting element 250 is formed into a single rectangular pillar or cylindrical shape without forming a connecting portion as in the other embodiments described above.

[0173] After the light-shielding electrode 160a, the light-emitting element 250, and the connecting plate 230a1 are formed, the first interlayer insulating film 156 is formed to cover the substrate surface 102a, the connecting plate 230a1, the light-emitting element 250, and the light-shielding electrode 160a.

[0174] As shown in FIG. 18A, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the Si layer 1104 is formed on the TFT lower layer film 106 and polycrystallized.

[0175] As shown in FIG. 18B, the polycrystallized Si layer 1104 shown in FIG. 18A is processed into an island shape to form a TFT channel 204. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 204. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. A transistor (circuit element) 203 is formed by selectively doping the gate 107 with impurities such as P and thermally activating it. Regions 204s and 204d are n-type active regions and function as the source region and drain region of the transistor 203, respectively. Region 204i is a p-type active region and functions as a channel.

[0176] As shown in FIG. 19A , the second interlayer insulating film 108 is formed to cover the insulating layer 105 and the transistor 203. Vias 111s and 111d are formed to penetrate the second interlayer insulating film 108 and the insulating layer 105. A via hole is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the light-shielding electrode 160a, and the via 261k is filled with a conductive material to form the via. The via 261k is electrically connected to the light-shielding electrode 160a. A via hole is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connecting plate 230a1, and the via 261a is filled with a conductive material to form the via. The via 261a is electrically connected to the connecting plate 230a1. The wirings 110s, 110d, and 210a of the wiring layer 110 are connected to the vias 111s, 111d, 261k, and 261a, respectively.

[0177] As shown in FIG. 19B, an adhesive layer 1170 is formed on the second interlayer insulating film 108 and the wiring layer 110, and a reinforcing substrate 1180 is adhered to the adhesive layer 1170.

[0178] Thereafter, the substrate 102 is removed by wet etching, laser lift-off, or the like. The connection plate (first portion) 230a1 shown in FIG. 19A is processed to expose the light-emitting surface 253S, and the connection plate (second connection portion) 230a is formed. In the process of forming the connection plate 230a, the connection plate 230a is etched to leave a portion that is connected to the surface including the light-emitting surface 253S. The formation of the connection plate 230a forms a recess 256C.

[0179] Thereafter, a transparent resin layer is formed to cover the first surface 156S1, the light-emitting surface 253S, and the surface 230S of the connecting plate 230a, and a color filter is formed therebetween. In this manner, the sub-pixels 220 are formed.

[0180] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 250 and reducing the number of processes. In addition, by setting the polarity of the TFT to p-channel, it becomes possible to use the light-emitting surface 253S as the p-type semiconductor layer 253. This has the advantage of improving the degree of freedom in arranging circuit elements and designing the circuit.

[0181] In this embodiment, the connection plate 230a is made of a metal material and can have high conductivity, so that the p-type semiconductor layer 253 on the light emitting surface 253S side can be connected to the via 261a with low resistance.

[0182] (Third embodiment) FIG. 20 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that the light-emitting element 150, whose light-emitting surface 151S is provided by an n-type semiconductor layer 151, is driven by an n-channel transistor 203. This embodiment differs from the other embodiments described above in that a light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 203. The light-emitting element 150 of this embodiment also differs from the other embodiments described above in that the light-emitting surface 151S is roughened. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0183] 20 , the image display device of this embodiment includes a subpixel 320. The subpixel 320 includes a light-emitting element 150, a light-shielding electrode 160a, a first interlayer insulating film 156, a light-shielding layer 330, a transistor 203, a second interlayer insulating film 108, a via (first via) 361a, and a wiring layer 110. The subpixel 320 further includes a color filter 180.

[0184] In this embodiment, the light-emitting element 250 is provided on the color filter 180 and has a roughened light-emitting surface 151S. A transparent resin layer 188 is provided between the roughened light-emitting surface 151S and the color filter 180. The transparent resin layer 188 is also provided on the first surface 156S1 of the first interlayer insulating film 156, and the light-emitting element 150 and the first interlayer insulating film 156 are provided on the color filter 180 with the transparent resin layer 188 interposed therebetween.

[0185] As in the other embodiments described above, the position of the light-emitting surface 151S is shifted in the positive direction of the Z axis from the position of the first surface 156S1, and the transparent resin layer 188 forms a plane that is flattened to a certain extent in order to form the color filter 180.

[0186] The light-emitting element 150 has an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153 stacked in this order from the light-emitting surface 151S toward the upper surface 153U. The light-emitting surface 151S, which is the n-type semiconductor layer 151, is provided on the connection surface 180S. Therefore, the light-emitting element 150 emits light in the negative direction of the Z axis via the transparent resin layer 188 and the color conversion unit 182 of the color filter 180, as in the first embodiment.

[0187] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided so as to protrude in one direction from the n-type semiconductor layer 151 on the connection surface 180S. In this example, the connection portion 151a is provided so as to protrude in a direction different from that in the first embodiment. The shape and configuration of the connection portion 151a are the same as in the first embodiment, and the shape and configuration of the light-emitting element 150 are also the same as in the first embodiment. One end of a via 361k is connected to the connection portion 151a.

[0188] The light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. Since the TFT lower film 106 and the insulating layer 105 are provided between the first interlayer insulating film 156 and the second interlayer insulating film 108, more specifically, the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the TFT lower film 106. In other words, the light-shielding layer 330 is provided over the second surface 156S2 opposite to the first surface 156S1. The light-shielding layer 330 is provided over the entire surface between the first interlayer insulating film 156 and the TFT lower film 106 except for a portion.

[0189] The light-shielding layer 330 is formed of a material having light-shielding properties. The material of the light-shielding layer 330 may be conductive or non-conductive as long as it has light-shielding properties, and may be formed of, for example, a metal material having light reflectivity as in this example. The light-shielding layer 330 includes through-holes 331a and 331k. The through-hole 331a is provided at a position through which the via 361a of the light-shielding layer 330 passes in the XY plane view. The diameter of the through-hole 331a is set larger than the diameter of the via 361a so that the light-shielding layer 330 does not come into contact with the via 361a when the via 361a passes through the through-hole 331a. The through-hole 331k is provided at a position through which the via 361k of the light-shielding layer 330 passes in the XY plane view. The diameter of the through hole 331k is set larger than the diameter of the via 361k so that the light blocking layer 330 does not come into contact with the via 361k when the via 361k is passed through the through hole 331k.

[0190] The via 361a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the light-shielding electrode 160a. The via 361k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the connection portion 151a.

[0191] In the above description, the light-shielding layer 330 is made of a metal material, but the light-shielding layer 330 may be made of a non-conductive black resin. When the light-shielding layer 330 is made of a black resin, the vias can be formed by forming via holes together with the first interlayer insulating film 156 and the like and filling them with a conductive material, without previously forming through holes 331k, 331a having diameters larger than those of the vias 361k, 361a.

[0192] The light-shielding layer 330 is provided to cover the TFT channel 204. The light-shielding layer 330 is formed so as to include the outer periphery of the TFT channel 204 when the TFT channel 204 is projected onto the light-shielding layer 330 in the XY plane view. In other words, the outer periphery of the TFT channel 204 is disposed inside the light-shielding layer 330 in the XY plane view. Even when scattered light or the like is emitted upward from the light-emitting element 150 provided below the TFT channel 204, the light-shielding layer 330 blocks the scattered light or the like, and the scattered light or the like is hardly able to reach the TFT channel, thereby suppressing malfunction of the transistor 203.

[0193] From the viewpoint of light-blocking properties, it is desirable that the light-blocking layer 330 be provided over the entire surface between the first interlayer insulating film 156 and the second interlayer insulating film 108, as in this example; however, the light-blocking layer 330 is not limited to being a single physical component. For example, the light-blocking layer 330 may be provided separately in a portion directly below the TFT channel 204 and a portion directly above the light-emitting element 150. In this example, the light-blocking layer 330 is not connected to any potential, but may be connected to a specific potential such as ground potential or power supply potential. When the light-blocking layer 330 has multiple separated portions, all of the portions may be connected to a common potential, or each portion may be connected to a different potential.

[0194] In this embodiment, both the light-shielding electrode 160a and the light-shielding layer 330 function as light-shielding members for the circuit elements including the TFT channel 204. That is, in this embodiment, the double light-shielding members prevent light from reaching the circuit elements, thereby sufficiently preventing malfunction of the circuit elements.

[0195] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 110s, 110d, and 310a.

[0196] The via 111s is provided between the wiring 110s and the region 204s, and electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d, and electrically connects the wiring 110d and the region 204d.

[0197] The wiring 110s is connected to the region 204s through the via 111s. The region 204s is the source region of the transistor 203. Therefore, the source region of the transistor 203 is electrically connected to, for example, the ground line 4 shown in FIG. 16 through the via 111s and the wiring 110s.

[0198] The wiring 110d is connected to the region 204d through a via 111d. The region 204d is the drain region of the transistor 203. One end of the wiring 110d is provided above the connection portion 151a. One end of the wiring 310a is provided above the light emitting element 150 and the light-shielding electrode 160a. The wiring 310a is electrically connected to the power supply line 3 in FIG.

[0199] The via 361k is provided between the wiring 110d and the connection portion 151a and electrically connects the wiring 110d and the connection portion 151a. Therefore, the drain region of the transistor 203 is electrically connected to the n-type semiconductor layer 151 via the via 111d, the wiring 110d, the via 361k, and the connection portion 151a.

[0200] The via 361a is provided between the wiring 310a and the light-shielding electrode 160a, and electrically connects the wiring 310a and the light-shielding electrode 160a. Therefore, the p-type semiconductor layer 153 is electrically connected to the power line 3 through the light-shielding electrode 160a, the via 361a, and the wiring 310a.

[0201] A method for manufacturing the image display device of this embodiment will be described. 21A to 23 are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. In this example, the steps up to the step described in relation to Figure 7A of the first embodiment are applied in the same manner as in the first embodiment. In the following, the steps from Figure 21A onwards will be described as being applied after the step of Figure 7A. However, as described above, in this embodiment, the protruding direction of the connecting portion 151a is different from that in Figure 7A. 21A, a light-shielding layer (light-shielding member) 330 is formed over the second surface 156S2 of the first interlayer insulating film 156. Through-holes 331a and 331k are formed through the light-shielding layer 330 to expose the second surface 156S2.

[0202] As shown in FIG. 21B, the TFT lower layer film 106 is formed on the light-shielding layer 330 and the second surface 156S2, and a Si layer 1104 is formed on the TFT lower layer film 106.

[0203] 22A, the Si layer 1104 is processed to form a TFT channel 204, an insulating layer 105 and a gate 107, and a transistor 203. These steps can be performed using the LTPS process in the same manner as in the second embodiment.

[0204] 22B, second interlayer insulating film 108 is formed to cover insulating layer 105 and gate 107, and vias 111s, 111d, 361k, and 361a are formed therein. Wiring layer 110 is formed on second interlayer insulating film 108, and via 111s is connected to wiring 110s, vias 111d and 361k are connected to wiring 110d, and via 361a is connected to wiring 310a. These steps are the same as those in the other embodiments described above.

[0205] As shown in FIG. 23, an adhesive layer 1170 is applied onto the second interlayer insulating film 108 and the wiring layer 110, and a reinforcing substrate 1180 is attached by the adhesive layer 1170.

[0206] Thereafter, the substrate 102 and seed plate 130a shown in FIG. 22B are removed sequentially or simultaneously by wet etching or laser lift-off.

[0207] After removing the substrate 102 and the seed plate 130a, the exposed light-emitting surface 151S is roughened by, for example, wet etching.

[0208] Thereafter, a transparent resin layer is formed to cover the first surface 156S1 and the light-emitting surface 151S, a color filter is formed, and sub-pixels are formed.

[0209] The effects of the image display device of this embodiment will be described. In the manufacturing method of the image display device of this embodiment, similar to the other embodiments described above, there are effects of shortening the time of the transfer step for forming the light emitting element 150 and reducing the number of steps, and in addition, since the light emitting surface 151S is made of the n-type semiconductor layer 151, which has a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thick and the light emitting surface 151S can be sufficiently roughened. In the image display device of this embodiment, the roughening of the light emitting surface 151S diffuses the emitted light, so that even a small light emitting element 150 can be used as a light source with a sufficient light emitting area.

[0210] In the image display device 201 of this embodiment, the light emitting element 150, whose light emitting surface 151S is the n-type semiconductor layer 151, can be driven by the n-channel transistor 203. This increases the degree of freedom in circuit configuration, and improves design efficiency.

[0211] In the image display device 201 of this embodiment, the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. That is, the light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 203. Therefore, even if scattered light or the like is emitted upward from the light-emitting element 150, the emitted light is unlikely to reach the TFT channel 204, and malfunction of the transistor 203 can be prevented.

[0212] The light-shielding layer 330 can be formed of a conductive material such as metal, and can be connected to any potential. For example, by arranging a part of the light-shielding layer 330 directly under a switching element such as the transistor 203 and connecting it to a ground potential or a power supply potential, it can be used to suppress noise.

[0213] The light-shielding layer 330 is not limited to application in this embodiment, but can be commonly applied to the subpixels of the other embodiments described above and other embodiments to be described later. Even when applied to other embodiments, the same effects as those described above can be obtained.

[0214] In the above example, the configuration and manufacturing method of a light-emitting element having a roughened light-emitting surface have been described. A light-emitting element having a connection portion can have a roughened light-emitting surface, as in the present embodiment. Specifically, this can be applied to the light-emitting element 150 in the first embodiment, and the light-emitting element 150 in the fourth embodiment described below is an example in which a roughened surface is applied. This can also be applied to the semiconductor layer 650 in the sixth embodiment described below. By roughening the light-emitting surfaces of the components of these light-emitting elements, the above-mentioned effects can be achieved.

[0215] (Fourth embodiment) FIG. 24 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. This embodiment differs from the third embodiment in that the light-shielding electrode 160a shown in Fig. 20 is not provided, but is otherwise the same as the third embodiment. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0216] 24, the image display device of this embodiment includes a subpixel 420. The subpixel 420 includes a light-emitting element 150, a first interlayer insulating film 156, a light-shielding layer 330, a transistor 203, a second interlayer insulating film 108, a via 361a, and a wiring layer 110. The subpixel 420 further includes a color filter 180.

[0217] In this embodiment, no light-shielding electrode is provided on the upper surface 153U of the light emitting element 150. Therefore, the via 361a is provided between the wiring 310a and the upper surface 153U to electrically connect the wiring 310a and the upper surface 153U.

[0218] The light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108, and is formed in the same manner as in the third embodiment. That is, the light-shielding layer 330 is provided so as to cover the TFT channel 204. More specifically, the light-shielding layer 330 is set so as to include the entire periphery of the TFT channel 204 when the TFT channel 204 is projected onto the light-shielding layer 330 in the XY plane view. That is, the periphery of the TFT channel 204 is disposed within the periphery of the light-shielding layer 330 in the XY plane view. Therefore, scattered light emitted upward from the light-emitting element 150 is blocked by the light-shielding layer 330, and the transistor 203 including the TFT channel 204 is prevented from malfunctioning due to light.

[0219] A method for manufacturing the image display device of this embodiment will be described. 25A to 26B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. In this example, the steps up to the step described in relation to Fig. 5A of the first embodiment are applied in the same manner as in the first embodiment. In the following, the description will be given assuming that the steps from Fig. 25A onwards are applied after the step of Fig. 5A. 25A, a semiconductor layer 1150 is formed over the single-crystallized metal seed layer 1130a. In the semiconductor layer 1150, an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153 are formed in this order from the metal seed layer 1130a toward the positive direction of the Z axis.

[0220] The semiconductor layer 1150 is formed by the same technique as in the other embodiments described above, preferably by low-temperature sputtering. The semiconductor layer 1150 is formed in the region indicated by the two-dot chain line on the metal seed layer 1130a, and in other regions, amorphous deposits 1162 containing Ga, which is a growth seed material, may be deposited, as in the other embodiments described above.

[0221] 25B, a light-shielding layer 330 is formed over the second surface 156S2 of the first interlayer insulating film 156. Through holes 331a and 331k are formed in the light-shielding layer 330, and the second surface 156S2 is exposed through the through holes 331a and 331k.

[0222] 26A, the TFT lower layer film 106 is formed on the light-shielding layer 330 and the second surface 156S2, and the transistor 203 is formed on the TFT lower layer film 106. The procedure for forming the transistor 203 is the same as in the second and third embodiments.

[0223] 26B, the second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107, the vias 111s, 111d, 361k, and 361a are formed, and the wiring layer 110 is formed. In the step of forming the via 361a, the via 361a is formed by filling a via hole formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156 and reach the upper surface 153U with a conductive material.

[0224] Thereafter, in the same manner as in the third embodiment, a reinforcing substrate 1180 is bonded via the adhesive layer 1170 shown in Fig. 23, and the substrate 102 and seed plate 130a shown in Fig. 26B are removed. The exposed light-emitting surface 151S is roughened, and a color filter is formed via the transparent resin layer 188 shown in Fig. 24.

[0225] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the advantage of being able to shorten the time and reduce the number of steps required for the transfer process to form the light-emitting element 150. In addition, in this embodiment, no light-shielding electrode is formed on the upper surface 153U of the light-emitting element 150, so the step of forming the light-shielding electrode can be omitted.

[0226] (Fifth embodiment) FIG. 27 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the configurations of the light-emitting element 550 and the light-shielding electrode 560a are different from those of the other embodiments. The other components are the same as those of the other embodiments described above. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. As shown in FIG. 27 , the light emitting element 550 is provided on a color filter 180. A first interlayer insulating film 156 covering the side surfaces of the light emitting element 550 is also provided on the color filter 180. The surface of the light emitting element 550 on the color filter 180 is a light emitting surface 551S. The position of the light emitting surface 551S is shifted in the positive direction of the Z axis from the position of the first surface 156S1. A transparent resin layer 188 is formed over the light emitting surface 551S and the first surface 156S1, and the light emitting element 550 and the first interlayer insulating film 156 are provided on the color filter 180 with the transparent resin layer 188 interposed therebetween.

[0227] The connecting plate 530a is a plate-like member having two surfaces. One surface of the connecting plate 530a is connected to the surface including the light-emitting surface 551S. The connecting plate 530a is provided on the connecting surface 180S of the color filter 180 so as to protrude in one direction from the light-emitting surface 551S. One end of a via 561k is connected to the surface of the connecting plate 530a connected to the surface including the light-emitting surface 551S. A transparent resin layer 188 is provided across the surface of the connecting plate 530a opposite to the surface to which the via 561k is connected.

[0228] The connection plate 530a has the same function as the connection plate 230a in the second embodiment shown in Fig. 14. That is, the connection plate 530a is made of a conductive material, and electrically connects the light emitting surface 551S and the via 561k.

[0229] The light-emitting element 550 includes a light-emitting surface 551S and an upper surface 553U opposite the light-emitting surface. In the light-emitting element 550, an n-type semiconductor layer 551, a light-emitting layer 552, and a p-type semiconductor layer 553 are stacked in this order from the light-emitting surface 551S toward the upper surface 553U. As will be described later with reference to FIG. 28 , the light-emitting element 550 has a truncated pyramid or truncated cone shape formed so that the area in the XY plane view gradually decreases from the light-emitting surface 551S toward the upper surface 553U. The light-shielding electrode 560a is provided on the upper surface 553U of the light-emitting element 550 and has a truncated pyramid or truncated cone shape continuing from the apex of the light-emitting element 550.

[0230] In this embodiment, a light-shielding layer 330 is provided between the TFT lower film 106 and the first interlayer insulating film 156. The light-shielding layer 330 is the same as that described in the third embodiment with reference to FIG. 20. Therefore, the light-shielding layer 330 is provided so as to cover the TFT channel 104, and can block light emitted from the light-emitting element 550, thereby preventing malfunction of the transistor 103 including the TFT channel 104.

[0231] The via 561k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the connecting plate 530a. The via 561k is provided between the wiring 110k and the connecting plate 530a, and to electrically connect the wiring 110k and the connecting plate 530a. The via 561a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the light-shielding electrode 560a. The via 561a is provided between the wiring 110d and the light-shielding electrode 560a, and to electrically connect the wiring 110d and the light-shielding electrode 560a. The other components are the same as those in the second embodiment, and detailed description thereof will be omitted.

[0232] FIG. 28 is an enlarged view of the light emitting element 550 in FIG. 27, showing in detail the relationship between the light emitting surface 551S and the side surface 555a. 28, the light-emitting surface 551S is a plane substantially parallel to the XY plane. The first surface 156S1 of the first interlayer insulating film 156 is also a plane substantially parallel to the XY plane. The light-emitting element 550 and the first interlayer insulating film 156 are provided on the connection surface 180S of the color filter via the transparent resin layer 188, and the light-emitting surface 551S and the first surface 156S1 are planes substantially parallel to the connection surface 180S. As in the other embodiments described above, the position of the light-emitting surface 551S is shifted in the positive direction of the Z axis from the position of the first surface 156S1.

[0233] For simplicity, the following description will be given assuming that first interlayer insulating film 156 is a transparent resin, but even if first interlayer insulating film 156 is a white resin, the effect of the scattering particles in the white resin on the refractive index is small and can be ignored.

[0234] Side surface 555a of light-emitting element 550 is a surface between upper surface 553U and light-emitting surface 551S, and is a surface adjacent to light-emitting surface 551S and upper surface 553U. An interior angle θ between side surface 555a and light-emitting surface 551S is smaller than 90°. Preferably, interior angle θ is approximately 70°. More preferably, interior angle θ is smaller than a critical angle of side surface 555a, which is determined based on the refractive index of light-emitting element 550 and the refractive index of first interlayer insulating film 156. Light-emitting element 550 is covered with first interlayer insulating film 156, and side surface 555a is in contact with first interlayer insulating film 156.

[0235] The critical angle θc of the interior angle θ formed between the side surface 555a of the light emitting element 550 and the light emitting surface 551S is determined, for example, as follows. When the refractive index of light emitting element 550 is n0 and the refractive index of first interlayer insulating film 156 is n1, the critical angle θc of light emitted from light emitting element 550 to first interlayer insulating film 156 is found using the following equation (1).

[0236] θc=90°-sin -1 (n1 / n0) (1)

[0237] For example, it is known that the refractive index of a typical transparent organic insulating material such as acrylic resin is approximately 1.4 to 1.5. Therefore, if light-emitting element 550 is made of GaN and first interlayer insulating film 156 is made of a typical transparent organic insulating material, the refractive index n0 of light-emitting element 550 can be set to 2.5, and the refractive index n of first interlayer insulating film 156 can be set to 1.4. By substituting these values ​​into equation (1), the critical angle θc = 56° is obtained.

[0238] This indicates that, when the interior angle θ between light-emitting surface 551S and side surface 555a is θc=56°, light parallel to light-emitting surface 551S among the light emitted from light-emitting layer 552 is totally reflected by side surface 555a. It also indicates that light having a component in the positive direction of the Z axis among the light emitted from light-emitting layer 552 is totally reflected by side surface 555a.

[0239] On the other hand, of the light emitted from light-emitting layer 552, light having a component in the negative direction of the Z axis is emitted from side surface 555a at an emission angle according to the refractive index at side surface 555a. Light incident on first interlayer insulating film 156 is emitted from first interlayer insulating film 156 at an angle determined by the refractive index of first interlayer insulating film 156.

[0240] The light totally reflected by side surface 555a is reflected again by light-shielding electrode 560a, and the light having a component in the negative direction of the Z axis among the reflected light is emitted from light-emitting surface 551S and side surface 555a. Light parallel to light-emitting surface 551S and light having a component in the positive direction of the Z axis are totally reflected by side surface 555a.

[0241] In this way, of the light emitted from light-emitting layer 552, light parallel to light-emitting surface 551S and light having a component in the positive direction of the Z axis are converted by side surface 555a and light-shielding electrode 160a into light having a component directed in the negative direction of the Z axis. Therefore, the proportion of light emitted from light-emitting element 550 that is directed toward light-emitting surface 551S increases, and the substantial light-emitting efficiency of light-emitting element 550 improves.

[0242] By setting θ<θc, most of the light having a component parallel to the light-emitting surface 551S can be totally reflected inside the light-emitting element 550. If the refractive index of the first interlayer insulating film 156 is n=1.4, the critical angle θc is approximately 56°, so it is more preferable to set the interior angle θ to 45°, 30°, or the like. Furthermore, the critical angle θc becomes smaller for materials with a larger refractive index n. However, even if the interior angle θ is set to approximately 70°, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis. Therefore, taking into account manufacturing variations and the like, the interior angle θ may be set to, for example, 80° or less.

[0243] A method for manufacturing the image display device of this embodiment will be described. In this embodiment, the manufacturing process of the light-emitting element 550 and the light-shielding electrode 560a is different from that of the other embodiments, and the other manufacturing processes can be applied to the other embodiments described above. The different parts of the manufacturing process will be described below. In this embodiment, the following steps are carried out to form the light emitting device 550 in the shape shown in FIG. After forming the metal layer 1160, the semiconductor layer 1150 shown in FIG. 17A is etched into the shape of the light-emitting element 550 shown in FIG. 27. Etching is performed continuously from the metal layer 1160 to the semiconductor layer 1150. To form the light-shielding electrode 560a and the light-emitting element 550, an etching rate is selected so that the side surface 555a shown in FIG. 28 forms an interior angle θ with the light-emitting surface 551S. For example, a higher etching rate is selected closer to the top surface 553U. Preferably, the etching rate is set to increase linearly from the light-emitting surface 551S side toward the top surface 553U and the light-shielding electrode 560a side.

[0244] Specifically, for example, the resist mask pattern used in dry etching is designed to become gradually thinner toward its edge during exposure. This allows the resist to gradually recede from the thinner portion during dry etching, increasing the amount of etching from the light-emitting surface 551S toward the top surface 553U. As a result, the side surface 555a of the light-emitting element 550 is formed to form a certain angle with respect to the light-emitting surface 551S. Therefore, in the light-emitting element 550, the areas of the layers in the XY plane view from the top surface 553U increase in the order of p-type semiconductor layer 553, light-emitting layer 552, and n-type semiconductor layer 551.

[0245] Subpixels 520 are then formed in the same manner as in the other embodiments.

[0246] The effects of the image display device of this embodiment will be described. The image display device of this embodiment, like the image display devices of the other embodiments described above, has the effect of shortening the time required for the transfer process for forming the light-emitting element 550 and reducing the number of processes, as well as the following effects. In the image display device of this embodiment, light emitting element 550 is formed to have side surface 555a that forms an interior angle θ with respect to light emitting surface 551S on which light emitting element 550 is provided. Interior angle θ is set to be smaller than 90° based on critical angle θc, which is determined by the refractive index of the materials of light emitting element 550 and first interlayer insulating film 156. Interior angle θ enables light emitted from light emitting layer 552 that is directed to the side or above light emitting element 550 to be converted into light directed toward light emitting surface 551S and then emitted. By making interior angle θ sufficiently small, the substantial light emitting efficiency of light emitting element 550 is improved.

[0247] In this embodiment, the light emitting element 550 is a vertical element and is connected to the via 561k using the connection plate 530a. However, as in the first embodiment, the light emitting element may be provided with a connection portion formed on the connection surface 180S and connected to the via 561k through the connection portion.

[0248] (Sixth embodiment) FIG. 29 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the image display device differs from the other embodiments in that it includes a subpixel group 620 including a plurality of light-emitting regions on one light-emitting surface. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. 29, the image display device of this embodiment includes a sub-pixel group 620. The sub-pixel group 620 includes a semiconductor layer 650, a plurality of light-shielding electrodes 660a1 and 660a2, a first interlayer insulating film 156, a plurality of transistors 103-1 and 103-2, a second interlayer insulating film 108, a plurality of vias (first vias) 661a1 and 661a2, and a wiring layer 110. The sub-pixel group 620 further includes a color filter 180. The semiconductor layer 650 is provided on a connection surface 180S of the color filter 180.

[0249] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one side of the semiconductor layer 650 via the wiring layer 110 and vias 661a1 and 661a2. By turning on the p-channel transistors 103-1 and 103-2, electrons are injected from the other side of the semiconductor layer 650 via the wiring layer 110 and vias 661k. Holes and electrons are injected into the semiconductor layer 650, and the separated light-emitting layers 652a1 and 652a2 emit light due to the recombination of the holes and electrons. A drive circuit for driving the light-emitting layers 652a1 and 652a2 may have the circuit configuration shown in FIG. 3, for example. Using the example of the second embodiment, the n-type and p-type semiconductor layers of the semiconductor layers may be interchanged, and the semiconductor layers may be driven by n-channel transistors. In this case, the drive circuit may have the circuit configuration shown in FIG. 16.

[0250] The configuration of the sub-pixel group 620 will now be described in detail. The semiconductor layer 650 has a light-emitting surface 651S. The light-emitting surface 651S is provided on the connection surface 180S of the color filter 180 via a transparent resin layer 188. The light-emitting surface 651S is a surface of the n-type semiconductor layer 651. The light-emitting surface 651S includes a plurality of light-emitting regions 651R1 and 651R2.

[0251] The semiconductor layer 650 includes an n-type semiconductor layer 651, light-emitting layers 652a1 and 652a2, and p-type semiconductor layers 653a1 and 653a2. The light-emitting layer 652a1 is provided on the n-type semiconductor layer 651. The light-emitting layer 652a1 is provided on the n-type semiconductor layer 651, separated from the light-emitting layer 652a2. The p-type semiconductor layer 653a1 is provided on the light-emitting layer 652a1. The p-type semiconductor layer 653a2 is provided on the light-emitting layer 652a2, separated from the p-type semiconductor layer 653a1.

[0252] The p-type semiconductor layer 653a1 has an upper surface 653U1 provided on the side opposite to the surface on which the light emitting layer 652a1 is provided, and the p-type semiconductor layer 653a2 has an upper surface 653U2 provided on the side opposite to the surface on which the light emitting layer 652a2 is provided.

[0253] Light emitting region 651R1 substantially coincides with the region of light emitting surface 651S that faces upper surface 653U1. Light emitting region 651R2 substantially coincides with the region of light emitting surface 651S that faces upper surface 653U2.

[0254] The light-shielding electrode 660a1 is provided on the upper surface 653U1. The light-shielding electrode 660a2 is provided on the upper surface 653U2. As in the other embodiments described above, the light-shielding electrodes 660a1 and 660a2 reflect light scattered upward from the semiconductor layer 650 to prevent malfunction of the transistors 103-1 and 103-2 due to the scattered light. The light-shielding electrodes 660a1 and 660a2 reflect the scattered light upward toward the light-emitting surface 651S, thereby improving the substantial light-emitting efficiency of the semiconductor layer 650.

[0255] The relationship between the semiconductor layer 650 and the light emitting regions 651R1 and 651R2 will be described. FIG. 30 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. FIG. 30 is a schematic diagram for explaining the light emitting regions 651R1 and 651R2 of the semiconductor layer 650. As shown in FIG. As shown in Fig. 30, light emitting regions 651R1 and 651R2 are surfaces on light emitting surface 651S. In Fig. 30, the portions of semiconductor layer 650 that include light emitting regions 651R1 and 651R2 are referred to as light emitting portions R1 and R2, respectively. Light emitting portion R1 includes a portion of n-type semiconductor layer 651, light emitting layer 652a1, and p-type semiconductor layer 653a1. Light emitting portion R2 includes a portion of n-type semiconductor layer 651, light emitting layer 652a2, and p-type semiconductor layer 653a2.

[0256] The semiconductor layer 650 includes a connection portion R0. The connection portion R0 is provided between the light emitting portion R1 and the light emitting portion R2, and is a part of the n-type semiconductor layer 651. One end of the via 661k shown in FIG. 29 is connected to the connection portion R0, and provides paths for current to the light emitting portions R1 and R2.

[0257] In the light-emitting portion R1, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 652a1. In the light-emitting portion R1, holes supplied via the light-shielding electrode 660a1 are supplied to the light-emitting layer 652a1. The electrons and holes supplied to the light-emitting layer 652a1 are combined to emit light. The light emitted from the light-emitting layer 652a1 reaches the light-emitting surface 651S through the n-type semiconductor layer 651 of the light-emitting portion R1. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R1, the light-emitting region 651R1 is the portion of the light-emitting surface 651S that emits light. Therefore, in this example, the light-emitting region 651R1 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 652a1 projected onto the light-emitting surface 651S in the XY plane view.

[0258] The light-emitting portion R2 is similar to the light-emitting portion R1. That is, in the light-emitting portion R2, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 652a2. In the light-emitting portion R2, holes supplied via the light-shielding electrode 660a2 are supplied to the light-emitting layer 652a2. The electrons and holes supplied to the light-emitting layer 652a2 are combined to emit light. The light emitted from the light-emitting layer 652a2 reaches the light-emitting surface 651S through the n-type semiconductor layer 651 of the light-emitting portion R2. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R2, the light-emitting portion 651R2 is the portion of the light-emitting surface 651S that emits light. Therefore, in this example, the light-emitting region 651R2 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 652a2 projected onto the light-emitting surface 651S in the XY plane view.

[0259] In this way, in the semiconductor layer 650, the n-type semiconductor layer 651 can be shared to form a plurality of light emitting regions 651R1, 651R2 on the light emitting surface 651S.

[0260] In this embodiment, the semiconductor layer 650 can be formed by using a part of the n-type semiconductor layer 651 as the connection portion R0 in the plurality of light-emitting layers 652a1, 652a2 and the plurality of p-type semiconductor layers 653a1, 653a2 of the semiconductor layer 650. Therefore, the semiconductor layer 650 can be formed in the same manner as the method for forming the light-emitting elements 150, 250 in the first embodiment, the second embodiment, etc. described above.

[0261] Returning to FIG. 29, the explanation continues. The first interlayer insulating film 156 (first insulating film) is provided on the color filter 180 via a transparent resin layer 188. The first interlayer insulating film 156 is provided to cover the side surfaces of the semiconductor layer 650, the n-type semiconductor layer 651, and the light-shielding electrodes 660a1 and 660a2.

[0262] The TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is planarized, and the TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

[0263] An insulating layer 105 covers the TFT lower film 106 and the TFT channels 104-1 and 104-2. A gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0264] A second interlayer insulating film (second insulating film) 108 is provided to cover the insulating layer 105 and the gates 107-1 and 107-2.

[0265] The TFT channel 104-1 includes p-type doped regions 104s1 and 104d1, which are the source and drain regions of the transistor 103-1. The region 104i1 is n-type doped and forms the channel of the transistor 103-1. The TFT channel 104-2 similarly includes p-type doped regions 104s2 and 104d2, which are the source and drain regions of the transistor 103-2. The region 104i2 is n-type doped and forms the channel of the transistor 103-2. In this embodiment, the circuit 101 includes the TFT channels 104-1 and 104-2, the insulating layer 105, the second interlayer insulating film 108, the vias 111s1, 111d1, 111s2, and 111d2, and the wiring layer 110.

[0266] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 610s1, 610d1, 610k, 610d2, and 610s2.

[0267] The wiring 610k is provided above the n-type semiconductor layer 651. The via 661k is provided between the wiring 610k and the n-type semiconductor layer 651, and electrically connects the wiring 610k to the n-type semiconductor layer 651. The wiring 610k is connected to, for example, the ground line 4 of the circuit in FIG.

[0268] The vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106. The via 111d1 is provided between the region 104d1 and the wiring 610d1, and electrically connects the region 104d1 and the wiring 610d1. The via 111s1 is provided between the region 104s1 and the wiring 610s1, and electrically connects the region 104s1 and the wiring 610s1. The via 111d2 is provided between the region 104d2 and the wiring 610d2, and electrically connects the region 104d2 and the wiring 610d2. The via 111s2 is provided between the region 104s2 and the wiring 610s2, and electrically connects the region 104s2 and the wiring 610s2. The wirings 610s1 and 610s2 are connected to the power supply line 3 of the circuit in FIG. 3, for example.

[0269] The wiring 610d1 is provided above the light-shielding electrode 660a1. The via 661a1 is provided between the wiring 610d1 and the light-shielding electrode 660a1 and electrically connects the wiring 610d1 and the light-shielding electrode 660a1. Therefore, the p-type semiconductor layer 653a1 is electrically connected to the drain region of the transistor 103-1 via the light-shielding electrode 660a1, the via 661a1, the wiring 610d1, and the via 111d1.

[0270] The wiring 610d2 is provided above the light-shielding electrode 660a2. The via 661a2 is provided between the wiring 610d2 and the light-shielding electrode 660a2 and electrically connects the wiring 610d2 and the light-shielding electrode 660a2. Therefore, the p-type semiconductor layer 653a2 is electrically connected to the drain region of the transistor 103-2 via the light-shielding electrode 660a2, the via 661a2, the wiring 610d2, and the via 111d2.

[0271] For example, transistors 103-1 and 103-2 are drive transistors for adjacent subpixels and are driven sequentially. When holes supplied from transistor 103-1 are injected into light-emitting layer 652a1 and electrons supplied from wiring 610k are injected into light-emitting layer 652a1, light-emitting layer 652a1 emits light and light is emitted from light-emitting region 651R1. When holes supplied from transistor 103-2 are injected into light-emitting layer 652a2 and electrons supplied from wiring 610k are injected into light-emitting layer 652a2, light-emitting layer 652a2 emits light and light is emitted from light-emitting region 651R2.

[0272] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the advantage of shortening the time required for the transfer process for forming the semiconductor layer 650 and reducing the number of processes. Furthermore, since the connection portion R0 can be shared by multiple light-emitting portions R1 and R2, the number of vias 661k provided in the connection portion R0 can be reduced. Reducing the number of vias allows the pitch of the light-emitting portions R1 and R2 constituting the subpixel group 620 to be reduced, resulting in a compact, high-resolution image display device. While this example describes the case of two light-emitting regions, the number of light-emitting regions formed on the light-emitting surface is not limited to two and can be any number of three or more.

[0273] (Seventh embodiment) The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0274] FIG. 31 is a block diagram illustrating an image display device according to this embodiment. FIG. 31 shows the main components of a computer display. 31 , an image display device 701 includes an image display module 702. The image display module 702 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 702 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0275] The image display device 701 further includes a controller 770. The controller 770 receives control signals separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each subpixel and to control the driving order.

[0276] (Variation) The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0277] FIG. 32 is a block diagram illustrating an image display device according to a modified example of this embodiment. FIG. 32 shows the configuration of a high-definition flat-screen television. As shown in Fig. 32, an image display device 801 includes an image display module 802. The image display module 802 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied via a bus 840. The frame memory 880 stores one frame's worth of display data and is used for processing such as smooth video playback.

[0278] The image display device 801 has an I / O circuit 810. The I / O circuit 810 is simply represented as "I / O" in Fig. 32. The I / O circuit 810 provides an interface circuit or the like for connecting to an external terminal or device. The I / O circuit 810 includes, for example, a USB interface for connecting an external hard disk drive or the like, an audio interface, and the like.

[0279] Image display device 801 has a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to receiving unit 820, and separates and generates necessary signals from radio waves received by antenna 822. Signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by receiving unit 820 are separated by signal processing unit 830 into image data, audio data, etc., and generated.

[0280] By configuring the receiving unit 820 and the signal processing unit 830 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for Wi-Fi, a GPS receiver, etc., the image display device can also be configured as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be configured as a mobile information terminal such as a smartphone or a car navigation system.

[0281] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified example thereof or an example of another embodiment. The image display module in this embodiment and the modified example includes a large number of sub-pixels, as shown in Figures 3, 12, and 16.

[0282] According to the embodiment described above, it is possible to realize a method for manufacturing an image display device and an image display device that shortens the transfer step of light emitting elements and improves yield.

[0283] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0284] 1,201,701,801 image display device, 2 display area, 3 power supply line, 4 ground line, 5,205 row selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8,208 signal line, 10 pixel, 20,220,320,420,520 subpixel, 22,222 light emitting element, 24,224 selection transistor, 26,226 drive transistor, 28,228 capacitor, 101 circuit, 102 substrate, 103,103-1,103-2,203 transistor, 104,104-1,104-2,204 TFT channel, 105 insulating layer, 107,107-1,107-2 gate, 108 second interlayer insulating film, 110 wiring layer, 130a Seed plate, 150, 250, 550 Light emitting element, 151S, 253S, 651S Light emitting surface, 156 First interlayer insulating film, 156S1 First surface, 156S2 Second surface, 160a, 560a, 660a1, 660a2 Light shielding electrode, 161a, 161k, 261a, 261k, 361a, 361k, 661a1, 661a2, 661k Via, 180, 180a Color filter, 230a Connection plate, 620 Subpixel group, 1130 Metal layer, 1130a Metal seed layer, 1150 Semiconductor layer, 1160 Metal layer, 1180 Reinforcing substrate, 1192 Structure

Claims

1. forming a metal layer on a substrate and annealing the metal layer at a temperature of 400° C. to 500° C. to form a layer including a first portion of a single-crystal metal; forming a semiconductor layer including a light emitting layer on the first portion; processing the semiconductor layer to form a light emitting device including a light emitting surface on the first portion and a top surface opposite the light emitting surface; forming a first insulating film covering the substrate, the layer including the first portion, and the light emitting element; forming a circuit element on the first insulating film; forming a light-shielding member between the circuit element and the light-emitting element; forming a second insulating film covering the first insulating film and the circuit element; forming a first via that penetrates the first insulating film and the second insulating film; forming a wiring layer on the second insulating film; removing the substrate; removing at least a portion of the first portion on the light emitting surface; Equipped with The first via is provided between the wiring layer and the upper surface, and electrically connects the wiring layer and the upper surface.

2. A method for manufacturing an image display device as described in Claim 1, wherein the outer periphery of the light-emitting element is arranged within the outer periphery of the first part in a planar view.

3. 3. The method for manufacturing an image display device according to claim 1, wherein the step of forming the layer including the first portion includes the step of patterning the metal layer before subjecting the metal layer to an annealing treatment.

4. the step of forming the light-shielding member includes the step of forming a light-shielding electrode on the upper surface; 4. The method for manufacturing an image display device according to claim 1, wherein the first via is electrically connected to the upper surface via the light-shielding electrode.

5. 5. The method for manufacturing an image display device according to claim 1, wherein the step of forming the light-shielding member includes a step of forming a light-shielding layer on the first insulating film before the step of forming the circuit element.

6. forming a second via that penetrates the first insulating film and the second insulating film; Furthermore, the light-emitting element includes a first connection portion provided along the light-emitting surface, A method for manufacturing an image display device according to any one of claims 1 to 5, wherein the second via is provided between the wiring layer and the first connection portion, electrically connecting the wiring layer and the first connection portion.

7. 7. The method for manufacturing an image display device according to claim 1, further comprising the step of roughening the exposed light-emitting surface after the step of removing at least a part of the first portion on the light-emitting surface.

8. further comprising a step of forming a second via penetrating the first insulating film and the second insulating film; the step of removing at least a part of the first portion on the light-emitting surface includes the step of forming a second connection portion connected to a surface including the light-emitting surface by removing a part of the first portion; A method for manufacturing an image display device according to any one of claims 1 to 5, wherein the second via is provided between the wiring layer and the second connection portion, electrically connecting the wiring layer and the second connection portion.

9. A method for manufacturing a semiconductor device comprising the steps of: forming a layer including a first portion of a single crystal metal on a substrate; forming a semiconductor layer including a light emitting layer on the first portion; processing the semiconductor layer to form a light emitting device including a light emitting surface on the first portion and a top surface opposite the light emitting surface; forming a first insulating film covering the substrate, the layer including the first portion, and the light emitting element; forming a circuit element on the first insulating film; forming a light-shielding member between the circuit element and the light-emitting element; forming a second insulating film covering the first insulating film and the circuit element; forming a first via and a second via penetrating the first insulating film and the second insulating film; forming a wiring layer on the second insulating film; removing the substrate; removing at least a portion of the first portion on the light emitting surface; Equipped with the step of removing at least a part of the first portion on the light-emitting surface includes the step of forming a second connection portion connected to a surface including the light-emitting surface by removing a part of the first portion; the first via is provided between the wiring layer and the upper surface and electrically connects the wiring layer and the upper surface; The second via is provided between the wiring layer and the second connection portion, electrically connecting the wiring layer and the second connection portion.

10. 10. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer contains a gallium nitride compound semiconductor.

11. 11. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a wavelength conversion member on the light emitting surface in place of the substrate after removing the substrate.

12. a light emitting element including a light emitting surface and a top surface opposite the light emitting surface; a first insulating film covering the light emitting element so as to expose the light emitting surface; a circuit element including a transistor, the circuit element being provided on the first insulating film; a light-shielding member provided between the circuit element and the upper surface; a second insulating film covering the first insulating film and the circuit element; a first via provided through the first insulating film and the second insulating film; a wiring layer provided on the second insulating film; Equipped with the first via is provided between the wiring layer and the upper surface and electrically connects the wiring layer and the upper surface; the first insulating film includes a first surface on the light-emitting surface side, The image display device, wherein the light emitting surface is provided in a recessed position relative to the first surface.

13. The image display device according to claim 12 , wherein the first insulating film has light reflectivity.

14. the light-shielding member includes a light-shielding electrode provided on the upper surface, 14. The image display device according to claim 12, wherein the first via is electrically connected to the upper surface through the light-shielding electrode.

15. 15. The image display device according to claim 12, wherein the light-shielding member includes a light-shielding layer provided on a second surface of the first insulating film opposite to the first surface.

16. a second via provided through the first insulating film and the second insulating film; the light-emitting element includes a first connection portion provided along the light-emitting surface, the wiring layer includes a first wiring and a second wiring separated from the first wiring, the first via is provided between the first wiring and the upper surface and electrically connects the first wiring and the upper surface; An image display device according to any one of claims 12 to 15, wherein the second via is provided between the second wiring and the first connection portion, and electrically connects the second wiring and the first connection portion.

17. 17. The image display device according to claim 12, wherein the light-emitting surface is roughened.

18. a second via provided through the first insulating film and the second insulating film; a second connection portion electrically connected to a surface of the light-emitting element that includes the light-emitting surface; Furthermore, the wiring layer includes a first wiring and a second wiring separated from the first wiring, the first via is provided between the first wiring and the upper surface and electrically connects the first wiring and the upper surface; An image display device according to any one of claims 12 to 15, wherein the second via is provided between the second wiring and the second connection portion, and electrically connects the second wiring and the second connection portion.

19. 16. The image display device according to claim 12, wherein an interior angle formed between the light emitting surface and a side surface of the light emitting element is smaller than 90°.

20. A light emitting device comprising: a light emitting surface and an upper surface opposite the light emitting surface; a first insulating film covering the light emitting element so as to expose the light emitting surface; a circuit element provided on the first insulating film; a light-shielding member provided between the circuit element and the upper surface; a second insulating film covering the first insulating film and the circuit element; a first via provided through the first insulating film and the second insulating film; a wiring layer including a first wiring and a second wiring separated from the first wiring and provided on the second insulating film; a second via provided through the first insulating film and the second insulating film; a second connection portion electrically connected to a surface of the light-emitting element that includes the light-emitting surface; Equipped with the first via is provided between the first wiring and the upper surface and electrically connects the first wiring and the upper surface; the first insulating film includes a first surface on the light-emitting surface side, the light-emitting surface is provided in a recessed position relative to the first surface, The second via is provided between the second wiring and the second connection portion, and electrically connects the second wiring and the second connection portion.

21. 21. The image display device according to claim 12, wherein the light emitting element includes a gallium nitride compound semiconductor.

22. 22. The image display device according to claim 12, further comprising a wavelength conversion member provided on the light emitting surface.

23. a first semiconductor layer including a light emitting surface on which a plurality of light emitting regions can be formed; a plurality of light emitting layers spaced apart from one another on the first semiconductor layer; a plurality of second semiconductor layers respectively provided on the plurality of light emitting layers, each having a conductivity type different from that of the first semiconductor layer, and each including a plurality of upper surfaces opposite to the surface on which the plurality of light emitting layers are provided; a first insulating film covering the first semiconductor layer, the plurality of light emitting layers, and the plurality of second semiconductor layers so as to expose the light emitting surface; a plurality of transistors spaced apart from one another on the first insulating film; a light-shielding member provided between the plurality of transistors and the plurality of upper surfaces; a second insulating film covering the first insulating film and the plurality of transistors; a plurality of first vias provided through the first insulating film and the second insulating film; a wiring layer provided on the second insulating film; Equipped with the plurality of second semiconductor layers are separated from one another by the first insulating film; the plurality of light-emitting layers are separated from one another by the first insulating film, the plurality of first vias are provided between the wiring layer and the plurality of upper surfaces, and electrically connect the wiring layer to the plurality of upper surfaces, respectively; the first insulating film includes a first surface on the light-emitting surface side, The image display device, wherein the light emitting surface is provided in a recessed position relative to the first surface.

24. a plurality of light emitting elements each including a light emitting surface and an upper surface opposite to the light emitting surface; a first insulating film covering the plurality of light-emitting elements so as to expose the light-emitting surfaces; a circuit element including a transistor, the circuit element being provided on the first insulating film; a light-shielding member provided between the circuit element and the upper surface; a second insulating film covering the first insulating film and the circuit element; a plurality of first vias provided through the first insulating film and the second insulating film; a wiring layer provided on the second insulating film; Equipped with the plurality of first vias are provided between the wiring layer and the plurality of upper surfaces, and electrically connect the wiring layer to the plurality of upper surfaces, respectively; the first insulating film includes a first surface on the side of the plurality of light emitting surfaces, The image display device, wherein the plurality of light-emitting surfaces are provided in a recessed position relative to the first surface.

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