Exposure apparatus and method for creating wiring patterns

Abstract

To perform patterning of a wiring capable of suppressing a decrease of throughput, in a semiconductor package manufacturing process and the like.SOLUTION: In a FO-WLP exposure process, an amount of positional deviation between semiconductor chips SC placed on a temporary substrate B with respect to a reference position is measured. In accordance with the correction of a formation position of an in-area wiring pattern AD, correction of the formation position and scaling correction for the out-of-area wiring pattern BD are performed, and an arc-shaped supplementary wiring pattern CD is generated. Then, the corrected in-area wiring pattern AD, out-of-area wiring pattern BD, and generated arc-shaped supplementary wiring pattern CD are combined as raster data.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to wiring patterning in a semiconductor package manufacturing process, and more particularly to wiring patterning in wafer-level packaging (hereinafter referred to as WLP) technology for packaging semiconductors at the wafer level. [Background technology]

[0002] In WLP, electronic components such as semiconductor chips (hereafter referred to as ICs or dies) and passive components are placed on a temporary support substrate, which is then sealed with resin, followed by RDL (Redistribution Layer) wiring, and then dicing to obtain a semiconductor package (this process is called mold-first (chip-first) WLP).

[0003] For example, FI (Fan-In)-WLP, which routes the I / O terminals of a die to the placement location of a BGA (Ball Grid Array) that can be mounted on a motherboard, within the chip size, and FO (Fan-Out)-WLP, which virtually expands the area around the die with resin for RDL routing, are known. FO-WLP packages multiple semiconductor chips (Multi-Chip FO-WLP), enabling the realization of a SiP (System in Package) that integrates and modularizes various electronic devices such as semiconductor chips and passive components.

[0004] In mold-first WLP, random misalignment occurs in individual semiconductor chips relative to the reference design position, so the wiring pattern data created in CAD / CAM format must be corrected accordingly.

[0005] For example, a wiring pattern to be connected to an external electrode in accordance with a misaligned semiconductor chip is determined based on a netlist included in design information, and wiring pattern data is generated (see Patent Document 1). Also, a wiring pattern determined for a region (zone) determined according to the semiconductor chip size, etc., is reconverted (resampled) (see Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5779145 [Patent Document 2] Patent No. 5767255 Summary of the Invention [Problem to be solved by the invention]

[0007] The misalignment of individual semiconductor chips must be measured by taking photos with a camera before exposure. Therefore, the task of redesigning the wiring pattern after measurement takes time. In particular, with the increasing demand for multi-layered substrates and SiP using FO-WLP, the data correction process for wiring patterns takes a lot of time, affecting throughput.

[0008] Therefore, in semiconductor package manufacturing processes and the like, there is a demand for wiring patterning that can suppress a decrease in throughput. [Means for solving the problem]

[0009] The exposure apparatus of the present invention can realize patterning of wiring such as RDL wiring in semiconductor package manufacturing processes such as WLP. For example, it can be applied to exposure processes in SiP using FI-WLP, FO-WLP, multi-chip FO-WLP, etc. RDL wiring patterning can also be performed on single-layer or multi-layer RDL.

[0010] The exposure apparatus of the present invention can perform wiring patterning based on an intra-area wiring pattern formed in a wiring area the size of a die (semiconductor chip) placed on a support substrate or a size larger than the die, and an out-of-area wiring pattern that is connected to the intra-area wiring pattern by design and connects to a die or electronic component adjacent to the die. The wiring pattern is created in advance as vector data in, for example, a CAD / CAM format and input to the exposure apparatus.

[0011] The support substrate may be any substrate capable of being configured as a temporary substrate, and its shape may be any suitable one, including a wafer (including rectangular panels), as long as the die can be arranged on it. For example, a pseudo-wafer in which the die is sealed with a mold may be configured as the temporary support substrate. Furthermore, a wiring area larger than the die size may be defined as a rectangular area scaled (enlarged) to match the rectangular shape of the die, or may have a different shape, as long as it is configured as an area that encompasses the die. Electronic components include external electrodes, passive components, etc., and can be defined as elements that can be electrically connected to the die.

[0012] Intra-area wiring patterns include, for example, RDL wiring in areas expanded by resin or the like in FO-WLP and RDL wiring in FI-WLP. Out-area wiring patterns include, for example, in the case of FO-WLP, wiring patterns that connect intra-area wiring patterns formed in the expanded areas of adjacent dies. They also include wiring patterns that connect intra-area wiring patterns formed in the expanded areas to electronic components such as external electrodes. Meanwhile, wiring patterns can be configured as either a single wire or a pattern consisting of multiple wires. For example, in the case of FO-WLP, the intra-area wiring patterns and extra-area wiring patterns that connect adjacent dies can be configured as wiring groups consisting of multiple wires.

[0013] The exposure apparatus of the present invention includes an exposure data generation unit that converts the intra-area wiring pattern and the extra-area wiring pattern into raster data and generates exposure data. The exposure data may be configured as data capable of driving a light modulation element of the exposure apparatus. For example, in the case of an exposure apparatus equipped with a light modulation element array such as a DMD, exposure data for controlling the ON / OFF of a light modulation element such as a micromirror can be generated. The exposure data generation unit can convert overall pattern data, including the intra-area wiring pattern and the extra-area wiring pattern along with other patterns (other wiring patterns, patterns other than wiring, etc.), into raster data and generate the exposure data. Alternatively, the exposure data generation unit can distinguish the intra-area wiring pattern and the extra-area wiring pattern from other patterns and perform raster conversion to generate exposure data. Alternatively, the exposure data generation unit can include the intra-area wiring pattern in other patterns while converting the extra-area wiring pattern into raster data as separate data.

[0014] The exposure apparatus of the present invention also includes a positional deviation measurement unit that measures the positional deviation of the die relative to a reference position. The reference position can be set, for example, to a representative position of the die (e.g., the center position) determined by design. The measurement unit can measure, for example, the degree of positional deviation (positional deviation amount). The positional deviation amount can be measured as the deviation between the coordinates measured when the support substrate is placed on a stage or the like and the designed coordinates. It is also possible to measure a rotational deviation relative to the center position of the die as a positional deviation.

[0015] In the present invention, the exposure data generation unit generates a supplementary wiring pattern that connects the intra-region wiring pattern and the outside-region wiring pattern, whose ends are separated from each other due to the correction of the formation position of the intra-region wiring pattern in accordance with the die misalignment. The formation position, wiring shape, etc. of the outside-region wiring pattern may be corrected in accordance with the die misalignment, or the formation position may not be corrected. The shape, length, line width, etc. of the supplementary wiring pattern can be determined in accordance with the corrected formation position of the intra-region wiring pattern.

[0016] The exposure data generation unit can be configured as a circuit including, for example, a raster conversion circuit, and may also include a circuit for performing misalignment correction processing, a circuit for performing data synthesis processing, etc. Furthermore, the exposure data generation unit is not limited to its specifications or form, such as hardware, software, or firmware. There are various ways to generate the intra-area wiring pattern, the out-of-area wiring pattern, and the supplementary wiring pattern. For example, the exposure data generation unit can separately convert the intra-area wiring pattern and the out-of-area wiring pattern, the formation positions of which have been corrected, from CAD / CAM format data (vector data) to raster data, while generating the supplementary wiring pattern as raster data. Alternatively, the supplementary wiring pattern may be generated as vector data and then converted to raster data.

[0017] Correction of the formation position of the intra-region wiring pattern, conversion of the corrected intra-region wiring pattern and the out-of-region wiring pattern into raster data, and generation of the supplementary wiring pattern may be performed according to measurement of die positional deviation. Furthermore, the raster data conversion process for the intra-region wiring pattern can be performed by creating standard exposure raster data before the start of exposure, and then performing raster conversion along with the correction process. For example, the exposure data generation unit can determine a block that includes the intra-region wiring pattern and create standard exposure raster data based on the position coordinate data of the input block.

[0018] The raster conversion process can be performed similarly for the outside-area wiring pattern. For example, the exposure data generation unit can perform pattern formation position correction and scaling correction for the outside-area wiring pattern in accordance with the inside-area wiring pattern whose formation position has been corrected. The scaling correction here includes scaling (reduction or enlargement) along the wiring length direction. Then, the exposure apparatus performs an exposure operation based on exposure data that combines the inside-area wiring pattern, the outside-area wiring pattern, and the supplementary wiring pattern in accordance with the generation of the supplementary wiring pattern.

[0019] The wiring width, shape, etc. of the supplementary wiring pattern vary. For example, the exposure data generation unit can form an arc-shaped pattern as the supplementary wiring pattern. The arc-shaped pattern here includes not only arcs with a strictly constant radius of curvature, but also patterns that are approximately arc-shaped. For example, when the intra-area wiring pattern and the extra-area wiring pattern are configured as a wiring group in which a plurality of wirings are arranged, the exposure data generation unit can generate an arc-shaped pattern, taking into consideration that the wiring width, wiring spacing, overall wiring width, etc. are maintained unchanged overall.

[0020] The exposure data generation unit can generate an arc-shaped filler wiring pattern by extracting a portion of the circular pattern. For example, data of the circular pattern can be saved in memory at timing such as when a lot changes, and the exposure data generation unit can generate an arc-shaped filler wiring pattern from the circular pattern by masking. For example, when the intra-area wiring pattern and the extra-area wiring pattern are configured as a wiring group in which multiple wires are arranged as wiring patterns connecting adjacent dies, concentric wiring patterns having the same wiring width and wire-to-wire spacing as the intra-area wiring pattern and the extra-area wiring pattern can be created in advance and saved in memory before the start of exposure.

[0021] Another aspect of the present invention is a wiring pattern creation method that converts into raster data an intra-area wiring pattern formed in a wiring area the size of a die placed on a support substrate or larger than the die, and an out-area wiring pattern that is connected to the intra-area wiring pattern by design and connects to a die or electronic component adjacent to the die, generates exposure data, measures a positional deviation of the die from a reference position, and generates a supplemental wiring pattern that connects the intra-area wiring pattern and the out-area wiring pattern, whose ends are separated due to the correction of the formation position of the intra-area wiring pattern in accordance with the die positional deviation. The positional deviation of the die from a reference position can be measured by an exposure apparatus. The supplemental wiring pattern can be generated as vector data or raster data. For example, in an exposure process for fan-out (FO)-wafer-level packaging (WLP), an exposure operation can be performed by an exposure apparatus based on the wiring pattern created by the wiring pattern creation method of the present invention. As described above, various data processing techniques can be applied to the conversion to raster data and the generation of exposure data. [Effects of the Invention]

[0022] According to the present invention, in a semiconductor package manufacturing process or the like, it is possible to perform wiring patterning that can suppress a decrease in throughput. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a block diagram of an exposure apparatus according to an embodiment of the present invention. [Figure 2] FIG. 1 is a diagram showing a part of a semiconductor chip mounted on a support substrate (temporary substrate) in a mold-first type FO-WLP. [Figure 3] 10A and 10B are diagrams illustrating the formation of wiring patterns based on misalignment of semiconductor chips; [Figure 4] FIG. 10 is a diagram showing a flow of data processing of a wiring pattern accompanied by alignment adjustment in a wafer-level exposure process. [Figure 5] 1A and 1B are diagrams showing an in-area wiring pattern, an out-of-area wiring pattern, a supplementary wiring pattern, and a template pattern. [Figure 6] FIG. 1 is a diagram showing pattern formation positions of intra-region wiring patterns on a substrate; [Figure 7] 10A and 10B are diagrams showing a part of a method for generating a supplementary wiring pattern CD. [Figure 8] 10A and 10B are diagrams showing a part of a method for generating a supplementary wiring pattern CD. [Figure 9] 10A and 10B are diagrams showing correction of a pattern formation position and scaling correction for an outside-area wiring pattern BD. [Figure 10] FIG. 10 is a diagram showing a wiring pattern obtained by combining an in-area wiring pattern, an out-of-area wiring pattern, and a supplementary wiring pattern. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0025] FIG. 1 is a block diagram of the exposure apparatus according to this embodiment.

[0026] The exposure apparatus 10 is capable of forming a circuit pattern by irradiating light onto a substrate B, and is configured here as a maskless exposure apparatus equipped with multiple exposure heads 15 (only one exposure head is shown in FIG. 1). The substrate B is mounted on a drawing table 12, and can be moved in the main scanning direction (X direction) and the sub-scanning direction (Y direction) by a table drive mechanism 13. An XY coordinate system is defined on the drawing table 12.

[0027] The exposure head 15 includes an illumination optical system and an imaging optical system (not shown) together with a DMD (Digital Micro-mirror Device) 16. Light emitted from a light source 20 (laser, discharge lamp, etc.) included in the exposure apparatus 10 is guided to the DMD 16 via the illumination optical system.

[0028] DMD16 is an optical modulation element array in which tiny rectangular micromirrors (here, several μm to several tens of μm) are arranged two-dimensionally in a matrix, and each micromirror is selectively positioned in either a first position (ON state) that reflects the beam from light source 20 toward substrate B, or a second position (OFF state) that reflects the beam toward outside the exposure surface, depending on the exposure data.

[0029] The rectangular projection area (hereinafter referred to as the exposure area) defined when all the micromirrors are in the ON state moves relative to the substrate B as the drawing table 12 moves along the main scanning direction (X direction). However, here, the exposure head 15 is installed so that the exposure area is tilted at a predetermined small angle with respect to the main scanning direction (X direction).

[0030] The light reflected by the micromirrors in the ON state is imaged on the exposure surface of the substrate B as a pattern light according to the relative position of the exposure area on the substrate B. The pattern light is projected while the drawing table 12 moves at a constant speed, thereby drawing on the entire substrate B. Here, multiple exposure (overlapping exposure) is performed at a predetermined pitch.

[0031] Controller 30, which is connected to an external workstation or server (not shown), controls the operation of exposure apparatus 10 and outputs control signals to each circuit such as light source driver 21. A program for controlling the operation of exposure apparatus 10 is stored in advance in a ROM (not shown) within controller 30. Drawing data (pattern data) input to exposure apparatus 10 from a workstation or the like is vector data (coordinate data) configured in CAD / CAM format, and is input to vector data processing circuit 31.

[0032] In the exposure apparatus 10, raster data (hereinafter referred to as standard raster data for exposure) is created for some standard patterns of the drawing data input to the vector data processing circuit 31, and is stored in the memory 39 before the start of exposure. The other drawing data (vector data) is converted into raster data by the raster conversion circuit 26, and then sent to the composition circuit 40.

[0033] The correction circuit 33 is a raster data conversion processing circuit that processes standard pattern data that requires conversion into raster data after alignment adjustment, and outputs raster data based on standard raster data for exposure stored in memory 39 to a composition circuit 40. As will be described later, the mask processing circuit 34 performs mask processing on template data stored in memory 41, and then outputs the raster data (hereinafter referred to as supplementary raster data) to the composition circuit 40.

[0034] The combining circuit 40 combines the raster data output from the correction circuit 33 with the raster data output from the raster conversion circuit 26, and also combines the fill raster data output from the mask processing circuit 34. The standard raster data and fill raster data are combined according to the position of the exposure area during the exposure operation. The DMD driving circuit 35 drives and controls the DMD 16 based on the exposure data obtained by the combination, thereby performing the multiple exposure operation.

[0035] The camera 38 is installed so as to be able to capture an image of the substrate B placed on the drawing table 12, and is used during alignment adjustment. Exposure control of the camera 38, such as image magnification, AF processing, and aperture adjustment, is performed by the camera control unit 36. The measurement circuit 37 detects the positions of characteristic points such as alignment marks based on the image data captured by the camera 38. The controller 30 performs alignment adjustment for the drawing data based on the amount of positional deviation, which is the difference between the position of the detected characteristic point and its reference position in the design.

[0036] 2 is a diagram showing a portion of a semiconductor chip mounted on a support substrate (temporary substrate) B in a mold-first type FO-WLP. Fig. 2 compares the designed arrangement of the semiconductor chips SC (four in this case) with the semiconductor chips SC placed on the support substrate B while embedded in resin.

[0037] In FO-WLP, a wiring area D larger than the chip size of the semiconductor chip SC is defined, and wiring patterns that connect to the chip terminals can be formed in the chip area (hereinafter referred to as the extended area) MD that is pseudo-extended by resin around the semiconductor chip SC. This makes it possible to achieve a pitch similar to the I / O terminal pitch of a BGA even for miniaturized semiconductor chips SC. In addition, high-density wiring patterns that are not limited by wiring design rules can be formed between semiconductor chips SC, making it possible to realize a more compact SiP by mounting multiple chips.

[0038] Due to the malleability of the resin, each semiconductor chip SC has a random amount of positional deviation from the reference position in the design. Therefore, if the design wiring pattern data is not corrected for the resin portion M, a disconnection or short circuit will occur between adjacent semiconductor chips SC. For this reason, alignment adjustment is performed before the exposure operation to correct the drawing data.

[0039] 3 is a diagram showing the formation of wiring patterns based on the misalignment of semiconductor chips. In this embodiment, in the RDL wiring at the wafer level in the FO-WLP process, the wiring patterns connecting adjacent semiconductor chips are divided into two groups: wiring patterns AD formed within the semiconductor chip SC and the extension region MD (also called fan-out wiring patterns, hereinafter referred to as intra-region wiring patterns), and wiring patterns BD formed outside the wiring region D (hereinafter referred to as extra-region wiring patterns).

[0040] With regard to the intra-area wiring patterns AD in the extension area MD, the pattern formation positions are corrected in accordance with the positional deviation of the semiconductor chip SC (see symbol P'). Then, with regard to the extra-area wiring patterns BD, the formation positions etc. are corrected based on the formation positions of the intra-area wiring patterns AD after the correction (see symbol P").

[0041] Furthermore, a wiring pattern (hereinafter referred to as a supplementary wiring pattern) CD is generated to connect the ends of the intra-area wiring patterns AD and the extra-area wiring patterns BD, whose ends are spaced apart due to the formation position correction, to compensate for this. Such synthesis of wiring patterns is also performed for connections between semiconductor chips and electronic components such as external electrodes and passive components. This will be described in detail below with reference to Figures 4 to 10.

[0042] Fig. 4 is a diagram showing the flow of data processing of wiring patterns accompanied by alignment adjustment in a wafer-level exposure process. Fig. 5 is a diagram showing an intra-area wiring pattern AD, an extra-area wiring pattern BD, a supplementary wiring pattern CD, and a template pattern CO. For ease of explanation, the following mainly describes data processing of wiring patterns that connect specific semiconductor chips.

[0043] When drawing data in CAD / CAM format data is input from a workstation or the like to exposure apparatus 10, data for the intra-area wiring pattern AD and data for the extra-area wiring pattern BD are identified and extracted (S101). The intra-area wiring pattern AD is configured as design data as a group of wires extending from a terminal and arranged in parallel at equal intervals, with each wire having the same line width W and the same distance (pitch) M between adjacent wires. Here, it is configured as a five-wire pattern.

[0044] The outside-area wiring pattern BD is configured as a wiring group with the same line width W as the inside-area wiring pattern AD, the wiring distance M between them, the overall wiring width L, and the same number of wires (5) as the inside-area wiring pattern AD in design data. The inside-area wiring pattern AD and the outside-area wiring pattern BD are configured as a wiring group that extends in a straight line across the wiring area D specified in FO-WLP (see Figure 3).

[0045] Here, blocks BL1 and BL2 are defined that respectively surround the intra-area wiring pattern AD and the extra-area wiring pattern BD. The drawing data for the entire substrate input to the exposure apparatus 10 in the exposure process includes pattern data for block BL1 that surrounds the intra-area wiring pattern AD. Meanwhile, pattern data for block BL2 that surrounds the extra-area wiring pattern BD is input separately from the drawing data. Furthermore, coordinate data for blocks BL1 and BL2 (here, position coordinate data for the block endpoints) is input separately.

[0046] Meanwhile, in memory 41 of exposure apparatus 10, a template pattern C0, which serves as a prototype for forming the above-mentioned supplementary wiring pattern (see FIG. 3), is saved and registered as raster data in memory 39. Template pattern C0 is configured as five concentric wiring patterns, matching the number of wires (five) of the intra-area wiring pattern AD and the extra-area wiring pattern BD.

[0047] The overall wiring width l, individual wiring width w, and wiring distance interval m of the template pattern C0 are equal to the overall wiring width L, individual wiring width W, and wiring distance interval M determined for the intra-area wiring pattern AD and the extra-area wiring pattern BD. Data on the template pattern C0 is input and stored in the exposure tool 10, for example, for each lot.

[0048] 5 shows a mask pattern MD for extracting a portion of the template pattern C0 to generate a fill wiring pattern CD. The mask pattern MD has a size that covers the entire template pattern C0 when the center D is aligned with the center C of the template pattern C0, and is configured as raster data that masks an area MA other than the area surrounded by a predetermined angle α from the center D, i.e., invalidates the data.

[0049] In the exposure apparatus 10, alignment measurement by camera scanning is performed in parallel with the data processing of the input drawing data described above, thereby measuring the amount of positional deviation of each semiconductor chip on the substrate B from a reference position (based on the design) (S102).

[0050] The amount of misalignment can be calculated by, for example, extracting the terminals (connection pads) of the semiconductor chip as feature points through image processing and performing template matching. Alternatively, alignment marks on the semiconductor chip can be measured. The amount of misalignment of the semiconductor chip can be calculated as the amount of misalignment from a reference position in the main scanning direction (X direction) and the sub-scanning direction (Y direction), as well as the amount of rotational misalignment (angle (θ)) from the chip center position.

[0051] 6 is a diagram showing the pattern formation position of the intra-area wiring pattern AD on the substrate B. As shown in Fig. 6, the pattern formation position of the intra-area wiring pattern AD is corrected based on the detected positional deviation amount of each semiconductor chip SC. Since the semiconductor chip SC itself does not deform, when a boundary line D'L of the wiring area D is defined on the substrate B, a process is executed to correct the X and Y positions and the rotation angle so that the wiring group of the intra-area wiring pattern AD remains perpendicular to the boundary line D'L (S104).

[0052] Here, the pattern data of the block BL1 surrounding the intra-area wiring pattern AD is treated as a standard pattern to be used for repeated exposure, and corrected standard raster data for exposure is output to the synthesis circuit 40 based on the positional deviation amount of each semiconductor chip SC described above.

[0053] The outside-area wiring pattern BD included in block BL2 and the inside-area wiring pattern AD included in block BL1 have the same line width W, overall wiring width L, and wiring distance interval M. The template pattern C0 also has the same overall wiring width l, individual wiring width w, and wiring distance interval m.

[0054] Therefore, by extracting a part of the template pattern C0 shown in Fig. 5, a circular arc-shaped supplementary wiring pattern CD (see Fig. 3) is generated, and the formation position of the outside wiring pattern BD of the block BL2 is corrected and scaled along the length direction. In this way, a wiring pattern that connects semiconductor chips that are misaligned is formed.

[0055] First, a method for generating a supplementary wiring pattern CD will be described with reference to Figures 7 and 8. If the end points of the connection block B1 of one semiconductor chip SC are A1 and B1, and the end points of the connection block B1 of the adjacent semiconductor chip are A2 and B2, the two points that form the shortest distance between the block end points are found. In Figure 7, end points A1 and A2 are identified as the end points that create the shortest distance K. These end points A1 and A2 are used as placement reference points.

[0056] Then, a circle (arc) CA centered at the midpoint A0 of the placement reference points A1 and A2, and circles (arcs) CB1 and CB2 centered at the placement reference points A1 and A2 and passing through the block end points B1 and B2, respectively, are defined, and intersections C1 and C2 are obtained. A rectangular area G defined by connecting the block end point A1, intersection C1, block end point A2, and intersection C2 is given as the area for forming the outside-area wiring pattern BD. Rectangular area G is an area that contacts the wiring areas of adjacent semiconductor chips at a single point.

[0057] 8 shows the template pattern C0 and mask data MD superimposed on placement reference points (A1, A2). When the center D of the mask data MD is superimposed on the block end point A1, the area MA outside the area MG of the included angle α, which is surrounded by the line G1 connecting the block end point A1 and the block end point B1 and the line G2 connecting the block end point A1 and the intersection point C1, is defined as the masking area MA.

[0058] Then, by performing a masking process, a supplementary wiring pattern CD that fits within the area MG of the included angle α is generated (S104). Specifically, the data of the area MA of the template pattern C0, which is raster data, is invalidated, and the raster data of the supplementary wiring pattern CD is output to the synthesis circuit 40.

[0059] The supplementary wiring pattern CD is formed at a position that is continuously connected to the corrected formation position of the intra-area wiring pattern AD. The radial distance t (see FIG. 5) to the innermost wiring of the template pattern C0 is determined so that the connection from the intra-area wiring pattern AD to the supplementary wiring pattern CD becomes a continuous connection from a straight line to a circle.

[0060] For the other semiconductor chip SC, the block end point A2 is set as the placement reference point, and similar masking is performed to extract a supplementary wiring pattern CD. The shape of the supplementary wiring pattern CD follows the range of the non-masking area MG, i.e., the positions of the placement reference positions A1 and A2.

[0061] 9 is a diagram showing the correction of the pattern formation position and the scaling correction for the outside-area wiring pattern BD. The formation position of the pattern data of block BL2 (see FIG. 5) is corrected and scaling correction is performed in accordance with the rectangular area G defined by connecting the block end point A1, the intersection point C1, the block end point A2, and the intersection point C2 (S105).

[0062] Specifically, the pattern formation position is rotated and scaling correction is performed to change the block length E to E' so that the two end points b1 and b3 of block BL2 shown in Figure 5 coincide with the end points A1 and A2 of blocks BL1 and BL1'. These correction processes are performed using vector data. The above corrections to the intra-area wiring pattern AD and the extra-area wiring pattern BD, and the generation of the supplementary wiring pattern CD are performed for each of the wiring patterns that connect semiconductor chips together.

[0063] The intra-area wiring pattern AD and the extra-area wiring pattern BD are converted into raster data through respective correction processes, and then combined with the drawing data for the entire board that has been converted into raster data. Then, the raster data of the supplementary wiring pattern generated by the masking process is combined with the drawing data (S106). An exposure operation is performed using the exposure data obtained by the data combination (S107).

[0064] 10 is a diagram showing a wiring pattern obtained by combining an intra-area wiring pattern AD, an extra-area wiring pattern BD, and a supplementary wiring pattern CD. As shown in FIG. 10, a wiring pattern DD is formed across adjacent semiconductor chips SC, with the line width W, overall wiring width L, and wiring distance M remaining constant.

[0065] As described above, according to this embodiment, in the FO-WLP exposure process, the amount of misalignment between the semiconductor chips SC placed on the temporary substrate B and the reference position is measured. Based on the input drawing data, the wiring area D larger than the chip size is classified into an in-area wiring pattern AD of the fan-out wiring formed in the extended area MD around the chip, and an out-area wiring pattern BD formed in the resin between the wiring area D.

[0066] In accordance with the correction of the formation position of the inside-area wiring pattern AD, the outside-area wiring pattern BD is corrected in its formation position and scaled, and an arc-shaped supplementary wiring pattern CD is generated. Then, the corrected inside-area wiring pattern AD, the outside-area wiring pattern BD, and the generated arc-shaped supplementary wiring pattern CD are synthesized as raster data.

[0067] In this embodiment, the RDL wiring pattern is corrected along a series of exposure processes, from input of drawing data (vector data) to conversion processing to raster data, and then exposure operation. Since the wiring pattern is not redesigned in the vector data, the impact on throughput can be suppressed.

[0068] In particular, by generating the arc-shaped supplementary wiring pattern CD, it is possible to continuously connect the in-area wiring pattern AD and the out-of-area wiring pattern BD, which would otherwise become separated due to correction of the pattern formation position. In particular, since the two chips are connected without changing the line width W, overall wiring width L, and wiring distance M, it is possible to suppress changes in electrical characteristics such as changes in impedance.

[0069] Since the fill wiring pattern CD is created based on the concentric template pattern C0, it is possible to generate an appropriate fill wiring pattern CD for each semiconductor chip SC, even if the amount of misalignment varies. Furthermore, in the FO-WLP exposure process, the wiring pattern connecting semiconductor chips is usually a group of multiple wiring patterns, but the masking process alone can smoothly connect and compensate for both ends of the wiring. Furthermore, because the masking process itself is fast, it does not significantly reduce throughput.

[0070] A configuration may be adopted in which a supplementary wiring pattern other than an arc shape is generated, or supplementary wiring patterns of various shapes may be prepared and saved in advance, and a supplementary wiring pattern of an appropriate shape may be applied to connect wiring ends that would otherwise be separated. Furthermore, for the out-of-area wiring pattern BD, the formation position may not be rotated, and only scaling correction may be performed. This method may be applied not only to the FO-WLP exposure process, but also to the FI-WLP exposure process. Furthermore, the above-described exposure process may be applied to a laser scanning exposure apparatus. [Explanation of symbols]

[0071] 10 Exposure equipment 26 Raster conversion circuit 33 Correction circuit 37 Measurement circuit 38 Camera 40 Synthesis circuit AD area wiring pattern BD area outside wiring pattern CD supplementary wiring pattern

Claims

1. an exposure data generation unit that converts a linear intra-area wiring pattern formed in a wiring area that is the size of a die placed on a support substrate or is larger than the die, and a linear out-of-area wiring pattern that is connected to the intra-area wiring pattern in terms of design and connects to a die or electronic component adjacent to the die, into raster data and generates exposure data; a positional deviation measurement unit that measures a positional deviation of the die relative to a reference position, the exposure data generation unit corrects a formation position of the in-region wiring pattern with respect to the outside-region wiring pattern in accordance with the positional deviation of the die, and also performs a pattern formation position correction involving rotation and a scaling correction along the wiring length direction with respect to the outside-region wiring pattern in accordance with the positional deviation of the die; the exposure data generating unit generates an arc-shaped supplementary wiring pattern that connects the corrected intra-region wiring pattern and the corrected outer-region wiring pattern, the ends of which are separated from each other, and then synthesizes the corrected intra-region wiring pattern, the corrected outer-region wiring pattern, and the generated supplementary wiring pattern to generate exposure data; an exposure apparatus that performs an exposure operation based on the exposure data;

2. An exposure apparatus as described in Claim 1, characterized in that the exposure data generation unit performs correction processing on the intra-area wiring pattern and the extra-area wiring pattern, which are vector data, and converts them into raster data after the correction processing.

3. 3. The exposure apparatus according to claim 1, wherein the exposure data generating unit generates the supplementary wiring pattern by extracting a part of a circular pattern.

4. 4. An exposure apparatus according to claim 3, wherein the exposure data generating unit generates the supplementary wiring pattern by a masking process.

5. 5. An exposure apparatus according to claim 1, wherein the exposure data generating unit generates the supplementary wiring pattern as raster data.

6. An exposure apparatus as described in any one of claims 1 to 5, characterized in that the intra-area wiring pattern and the extra-area wiring pattern are configured as a wiring group in which multiple wirings are arranged.

7. 7. The exposure apparatus according to claim 1, which is used for an exposure process in FO (Fan-Out)-WLP (Wafer-Level Package).

8. converting into raster data a linear intra-area wiring pattern formed in a wiring area having a size equal to or larger than the die to be placed on a support substrate, and a linear out-of-area wiring pattern that is connected to the intra-area wiring pattern in terms of design and connects to a die or electronic component adjacent to the die, and generating exposure data; A method for creating a wiring pattern that measures a positional deviation of the die relative to a reference position, correcting a formation position of the intra-region wiring pattern with respect to the outside-region wiring pattern in accordance with the positional deviation of the die, and performing a pattern formation position correction involving rotation and a scaling correction along the wiring length direction with respect to the outside-region wiring pattern in accordance with the positional deviation of the die; a wiring pattern creating method comprising: generating an arc-shaped supplementary wiring pattern that connects the corrected intra-region wiring pattern and the corrected outside-region wiring pattern, the ends of which are separated from each other; and generating exposure data by combining the corrected intra-region wiring pattern, the corrected outside-region wiring pattern, and the generated supplementary wiring pattern.

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