Spatial partitioning of multi-tenancy graphics processing units

Abstract

A graphics processing unit (GPU) (105) or other device includes multiple shader engines (140-143). The device includes a first front-end (FE) circuit (150) and one or more second FE circuits (151). In a first mode, the first FE circuit is configured to schedule geometry workloads for the shader engines. In a second mode, the first FE circuit is configured to schedule geometry workloads for a first subset of the multiple shader engines, and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the multiple shader engines. Optionally, a partition switch (165) is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the multiple shader engines depending on whether the device is in the first mode or the second mode.

Description

[Background technology]

[0001] A conventional processing system includes processing units, such as a central processing unit (CPU) and a graphics processing unit (GPU), that implement audio, video, and multimedia applications, and possibly general-purpose computing. The physical resources of a GPU include shader engines and fixed-function hardware units used to implement a user-defined, reconfigurable virtual pipeline. For example, a conventional graphics pipeline for processing three-dimensional (3D) graphics is formed from a series of fixed-function hardware block configurations supported by programmable shaders. These configurations are typically specified by a graphics application programming interface (API), such as the Microsoft DX11 / 12 specification or the Khronos Group OpenGL / Vulkan API.

[0002] The present disclosure can be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the following drawings. The use of the same reference numbers in different drawings indicates similar or identical items. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a processing system that performs spatial division in a graphics processing unit (GPU), according to some embodiments. [Figure 2] 1 is a block diagram of a mapping of front-end (FE) circuitry to a set of shader engines (SE) of a GPU operating in a first mode, according to some embodiments. [Figure 3] FIG. 10 is a block diagram of a mapping of FE circuitry to a set of SEs of a GPU operating in a second mode, according to some embodiments. [Figure 4]1 is a block diagram of a GPU including a set of FE circuits configured based on different characteristics of applications that provide instructions for execution by the GPU, according to some embodiments. [Figure 5] FIG. 1 is a block diagram of a mapping of FE circuitry to a set of SEs of a GPU operating at a high level of user experience, according to some embodiments. [Figure 6] FIG. 10 is a block diagram of a mapping of FE circuitry to a set of SEs of a GPU operating at a medium level of user experience, according to some embodiments. [Figure 7] FIG. 10 is a block diagram of a mapping of FE circuitry to a set of SEs of a GPU operating at a low level of user experience, according to some embodiments. [Figure 8] FIG. 2 is a block diagram of a GPU including a set of FE circuits that schedule instructions in time-multiplexed threads for execution by a set of SEs of the GPU, according to some embodiments. [Figure 9] FIG. 10 is a flow diagram of a method for selectively allocating FE circuitry to schedule commands for concurrent execution on a set of SEs, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0004] Processing on a GPU typically begins with an application programming interface (API) call (e.g., a draw call) processed by the CPU. A draw call is a command generated by the CPU 130 and sent to the GPU to instruct the GPU to render an object (or portion of an object) for a frame. A draw call includes information defining the texture, state, shader, rendering object, buffers, etc. used by the GPU to render the object or portion thereof. In response to receiving a draw call, the GPU renders the object to generate pixel values ​​that are provided to the display, which uses the pixel values ​​to display an image representing the rendered object. Objects are represented by primitives such as triangles, patches, or other polygons that contain multiple vertices connected by corresponding edges. An input assembler fetches vertices based on topology information indicated in the draw call. The vertices are provided to the graphics pipeline for shading according to corresponding commands that are stored in a command buffer before execution by the GPU. Commands in a command buffer are written to a queue (or ring buffer), and a scheduler schedules the command buffer at the head of the queue for execution on the GPU.

[0005] The hardware used to implement a GPU is typically configured based on the characteristics of the expected workload. For example, if the workload processed by the GPU is expected to generate graphics at 8K resolution, the GPU processes up to eight primitives per clock cycle to ensure a target quality of service and utilization level. For another example, if the workload processed by the GPU is expected to generate graphics at a significantly lower resolution of 1080p, the GPU ensures a target quality of service and utilization level when processing the workload at the lower resolution of 1080p. While traditional GPUs are optimized for a given type of workload, many GPUs are required to process workloads with varying degrees of complexity and output resolution. For example, a flexible cloud gaming architecture may include a server implementing a set of GPUs to simultaneously run various games at different levels of user experience, potentially ranging from 1080p resolution to 8K resolution, depending on the game application and the experience level requested by the user. While low-complexity or low-resolution games can run on GPUs that are optimized for high complexity or resolution, the difference between the expected complexity or resolution of the optimized GPU and the actual complexity or resolution required by the application often results in underutilization of the resources of a high-performance GPU. For example, serial dependencies between commands in a low-complexity / low-resolution game running on a high-performance GPU reduce the amount of pixel shading that can be performed in parallel, resulting in underutilization of the GPU's resources.

[0006] 1-9 disclose embodiments of a reconfigurable graphics processing unit (GPU) that includes a front-end (FE) circuit and shader engines that are spatially partitioned to execute multiple concurrent graphics streams with different characteristics. The FE circuit fetches primitives for a geometry workload, schedules the geometry workload for execution on the shader engines, and possibly handles serial synchronization, state updates, draw calls, cache activity, and tessellation of the primitives. The shader engines shade the vertices of the primitives (as scheduled by the FE circuit) and shade the generated pixels based on the shaded primitives. In some embodiments, the FE circuit includes multiple FE circuits that selectively schedule geometry workloads for concurrent execution on corresponding subsets of the shader engines. Scheduling workloads using different FE circuits to execute on different subsets of the shader engines is referred to herein as "spatial partitioning" of the shader engines.

[0007] The amount of spatial partitioning available in a reconfigurable GPU depends on the number of independent FE circuits implemented in the FE circuit. For example, if the FE circuit includes two FE circuits, the first FE circuit schedules geometry workloads for all shader engines in a first operating mode. In a second (partitioned) operating mode, the first FE circuit schedules geometry workloads for execution on a first subset of shader engines, and the second FE circuit schedules geometry workloads for execution on a second subset of shader engines concurrently with the execution of geometry workloads on the first subset. In some embodiments, the multiple FE circuits are configured based on different levels of user experience corresponding to different levels of complexity or graphics resolution. For example, a GPU including four shader engines may include a first FE circuit optimized for high complexity / high resolution, two second FE circuits optimized for medium complexity / medium resolution, and a third FE circuit optimized for low complexity / low resolution. Thus, the GPU can be reconfigured to support one high complexity / high resolution application (such as a game offering 8K resolution) using a first FE circuit, two medium complexity / medium resolution applications (such as a game offering 4K resolution) using two second FE circuits, or four low complexity / low resolution applications (such as a game offering 1080p resolution) using the first, second, and third FE circuits. In some embodiments, one or more of the multiple FE circuits support multiple simultaneous threads using time division multiplexing.

[0008] FIG. 1 is a block diagram of a processing system 100 that implements spatial partitioning with a multitenancy graphics processing unit (GPU) 105, according to some embodiments. The processing system 100 includes one or more central processing units (CPUs) 110, 111. While two CPUs 110, 111 are shown in FIG. 1, some embodiments of the processing system 100 include more or fewer CPUs. A scalable data fabric (SDF) 115 supports data flow between endpoints within the processing system 100. Some embodiments of the SDF 115 support data flow between connection points such as peripheral component interface (PCI) physical layers, memory controllers, universal serial bus (USB) hubs, computing and execution units including the GPU 105 and CPUs 110, 111, as well as other endpoints. In the illustrated embodiment, the SDF 115 is connected to an input / output (I / O) hub 120, which is connected to a PCI Express (PCI-E) bus 125 and a NBIF 130. Processing system 100 also includes a scalable control fabric (SCF) 135, which is a control communication plane that communicates system control signals within processing system 100. Examples of system control signals are control signals used to support thermal and power management, testing, security, etc.

[0009] GPU 105 includes a set of shader engines (SEs) 140, 141, 142, and 143 (collectively referred to herein as "SEs 140-143") that are used to execute commands simultaneously or in parallel. Some embodiments of SEs 140-143 are configured to use information from draw calls received from either CPU 110 or 111 to shade vertices of primitives that represent a model of a scene. SEs 140-143 also shade pixels generated based on the shaded primitives and provide the shaded pixels to a display, for example, for presentation to a user via I / O hub 120. While four shader engines are shown in FIG. 1, some embodiments of GPU 105 include more or fewer shader engines. SEs 140-143 are connected to a graphics L2 cache 145 that stores frequently used data and instructions. In some embodiments, L2 cache 145 is connected to one or more L1 caches implemented in SEs 140-143 and to one or more L3 caches (or other last-level caches) implemented in processing system 100. The caches form a cache hierarchy that includes L2 cache 145. Other caches in the cache hierarchy are not shown in FIG. 1 for clarity.

[0010] The front-end (FE) circuitry of the GPU 105 fetches primitives for geometry workloads, schedules the geometry workloads for execution in the shader engines, and potentially handles serial synchronization, state updates, draw calls, cache activity, and primitive tessellation. The FE circuitry within the GPU 105 includes FE circuits 150 and 151, although some embodiments of the FE circuitry are partitioned to include additional FE circuits, as described herein. The FE circuits 150 and 151 include command processors 155 and 156 that receive command buffers for execution in the SEs 140-143. The FE circuits 150 and 151 also include graphics register bus managers (GRBMs) 160 and 161 that function as a hub for register read and write operations, supporting multiple masters and multiple slaves.

[0011] GPU 105 operates in either a first mode or a spatially partitioned second mode. In the first mode, FE circuit 150 schedules geometry workloads to SEs 140-143. In the second mode, FE circuit 150 schedules geometry workloads to a first subset of SEs 140-143, and FE circuit 150 schedules geometry workloads to a second subset of SEs 140-143. The first subset includes SEs 140 and 141, and the second subset includes SEs 142 and 143, although other groupings of SEs 140-143 into subsets are used in some embodiments. GPU 105 includes a partition switch 165 that selectively connects FE circuits 150 and 151 to the first and second subsets of SEs 140-143 depending on whether GPU 105 is operating in the first mode or the second mode. In the illustrated embodiment, partition switch 165 determines the operating state of GPU 105. When GPU 105 is operating in a first mode, partition switch 165 connects FE circuit 150 to SEs 142 and 143, such that FE circuit 150 schedules operations for all SEs 140-143. When GPU 105 is operating in a second mode, partition switch 165 connects FE circuit 151 to SEs 142 and 143, such that FE circuit 150 schedules operations for SEs 140 and 141, and FE circuit 151 schedules operations for SEs 142 and 143.

[0012] FIG. 2 is a block diagram of a mapping 200 of FE circuits 205, 210 to a set of SEs 211, 212, 213, and 214 of a GPU operating in a first mode, according to some embodiments. Mapping 200 illustrates some embodiment mappings of FE circuits 150, 151 to SEs 140-143 of GPU 105 shown in FIG. 1. With the GPU operating in a first mode, FE circuit 205 is mapped to all of SEs 211-214. Thus, FE circuit 205 schedules commands for simultaneous execution on SEs 211-214. FE circuit 210 is not mapped to any of SEs 211-214, and thus does not schedule commands for execution on any of SEs 211-214, as indicated by the dashed outline of the box representing FE circuit 210.

[0013] FIG. 3 is a block diagram of a mapping 300 of FE circuits 305, 310 to a set of SEs 311, 312, 313, and 314 of a GPU operating in a second mode, according to some embodiments. The mapping 300 illustrates some embodiments of the mapping of FE circuits 150, 151 to SEs 140-143 of GPU 105 shown in FIG. 1. With the GPU operating in the second mode, the FE circuit 305 is mapped to a first subset of SEs 311-314, which includes SEs 311 and 312. Thus, the FE circuit 305 schedules commands for execution in SEs 311 and 312. The FE circuit 310 is mapped to a second subset of SEs 311-314, which includes SEs 313 and 314. Thus, the FE circuit 310 schedules commands for execution in SEs 313 and 314. The FE circuits 305, 310 schedule commands for simultaneous execution on corresponding first and second subsets of the SEs 311-314.

[0014] FIG. 4 is a block diagram of a GPU 400 including a set of FE circuits configured based on different characteristics of applications that provide instructions for execution by the GPU, according to some embodiments. GPU 400 includes a set of SEs 401, 402, 403, and 404, collectively referred to herein as "SEs 401-404," which execute instructions simultaneously or in parallel. GPU 400 also includes FE circuits 411, 412, 413, and 414, collectively referred to herein as "FE circuits 411-414." FE circuits 411-414 are configured based on different levels of user experience corresponding to different levels of complexity or graphics resolution. In the illustrated embodiment, FE circuit 411 is configured based on the requirements of an application with high complexity or graphics resolution, such as a game implementing an advanced physics engine or offering 8K resolution. FE circuits 412 and 413 are configured based on the requirements of an application with medium complexity or graphics resolution, such as a game offering 4K resolution. The FE circuit 414 is configured based on the requirements of applications with medium complexity or graphic resolution, such as games offering 1080p resolution.

[0015] The partition switch 415 selectively maps a subset of the FE circuits 411-414 to a corresponding subset of the SEs 401-404. The map indicates the connections between the FE circuits 411-414 and the SEs 401-404, as well as which of the FE circuits 411-414 is responsible for scheduling commands to one or more of the SEs 401-404. Some embodiments of the partition switch 415 selectively map a subset of the FE circuits 411-414 to a corresponding subset of the SEs 401-404 based on characteristics of the application providing the commands for execution on the SEs 401-404. For example, the GPU 400 can operate in one of several modes depending on the characteristics of the application. The partition switch 415 determines the current operating mode based either on signaling associated with the GPU 400 or using other indicators of the application's characteristics. The partition switch 415 then selectively determines the mapping between the SEs 401-404 and the FE circuits 411-414 based on the operating mode.

[0016] FIG. 5 is a block diagram of a mapping 500 of FE circuits 501, 502, 503, and 504 to a set of SEs 511, 512, 513, and 514 of a GPU operating at a high level of user experience, according to some embodiments. The mapping 500 illustrates some embodiment mappings of FE circuits 411-414 to SEs 401-404 of the GPU 400 shown in FIG. 4. The GPU is executing commands provided by applications that require a relatively high level of user experience (e.g., a high level of complexity or graphics resolution). Because the FE circuit 501 supports the high level of user experience, the FE circuit 501 is mapped to the SEs 511-514. The FE circuit 501 schedules commands for simultaneous execution on the SEs 511-514. FE circuits 502-504 are not mapped to SEs 511-514 and thus do not schedule commands for execution on SEs 511-514, as indicated by the dashed lines in the boxes representing FE circuits 502-504.

[0017] FIG. 6 is a block diagram of a mapping 600 of FE circuits 601, 602, 603, and 604 to a set of SEs 611, 612, 613, and 614 of a GPU operating at a medium level of user experience, according to some embodiments. Mapping 600 illustrates some embodiment mappings of FE circuits 411-414 to SEs 401-404 of GPU 400 shown in FIG. 4. The GPU is executing commands provided by an application requiring a medium level of user experience (e.g., medium level of complexity or graphics resolution). FE circuits 602 and 603 support the medium level of user experience. In the illustrated embodiment, FE circuit 602 is mapped to SEs 611 and 612, and FE circuit 603 is mapped to SEs 613 and 614. Thus, FE circuits 602 and 603 schedule commands for concurrent execution on corresponding subsets of SEs 611-614. FE circuits 601, 604 are not mapped to SEs 611-614 and thus do not schedule commands for execution on SEs 611-614, as indicated by the dashed lines in the boxes representing FE circuits 601, 604. However, in some embodiments, FE circuit 601 is mapped to a subset of SEs 611-614 because FE circuit 601 is capable of scheduling commands for applications requiring a medium level of user experience.

[0018] FIG. 7 is a block diagram of a mapping 700 of FE circuits 701, 702, 703, and 704 to a set of SEs 711, 712, 713, and 714 of a GPU operating at a low level of user experience, according to some embodiments. The mapping 700 illustrates some embodiment mappings of FE circuits 411-414 to SEs 401-404 of the GPU 400 shown in FIG. 4. The GPU is executing commands provided by applications requiring a low level of user experience (e.g., low level of complexity or graphics resolution). All of the FE circuits 701-704 are capable of scheduling commands to the SEs 711-714 from applications requiring a low level of user experience. Accordingly, the FE circuits 701-704 are mapped to corresponding SEs 711-714. For example, FE circuit 701 is mapped to (and schedules commands for) SE 711, FE circuit 702 is mapped to (and schedules commands for) SE 712, FE circuit 703 is mapped to (and schedules commands for) SE 713, and FE circuit 704 is mapped to (and schedules commands for) SE 714. FE circuits 701-704 schedule commands for simultaneous execution on corresponding SEs 711-714.

[0019] FIG. 8 is a block diagram of a GPU 800 including a set of FE circuits that schedules instructions in time-multiplexed threads for execution by the GPU's set of SEs, according to some embodiments. GPU 800 represents some embodiments of GPU 105 shown in FIG. 1. The set of FE circuits includes a first FE circuit 805 and a second FE circuit 810, although some embodiments of GPU 800 include more FE circuits in the set. The first FE circuit 805 schedules commands for execution on one or more corresponding SEs, including a first SE 815. In the illustrated embodiment, the first FE circuit 805 schedules commands for a first thread 817 during a first time interval and a third time interval. The first FE circuit 805 also schedules commands for a second thread 818 during a second time interval that is time-multiplexed with the first time interval and the third time interval. The second FE circuit 810 schedules commands for execution on one or more corresponding SEs, including a second SE 820. In the illustrated embodiment, the second FE circuit 810 schedules commands for the third thread 822 during the fourth and fifth time intervals, and the first FE unit 810 schedules commands for the fourth thread 823 during the sixth time interval, which is a time division multiplexed with the fourth and fifth time intervals. Thus, the FE circuits 805 and 810 schedule commands in threads 817, 818, 822, and 823 for simultaneous execution in the SEs 815 and 820.

[0020] 9 is a flow diagram of a method 900 for selectively allocating FE circuitry to schedule commands for concurrent execution on a set of SEs, according to some embodiments. Method 900 is implemented in some embodiments of GPU 800 shown in FIG.

[0021] At block 905, the GPU determines characteristics of one or more workloads (or threads) to be provided for execution on the GPU. In some embodiments, the characteristics include, but are not limited to, the complexity of the workload or the graphics resolution required (or specified or preferred) by the workload. The characteristics are determined based on information provided in the workload (or threads) or using other information to configure the GPU to execute the workload (or threads).

[0022] At decision block 910, the GPU determines whether to execute one or more workloads (or threads) simultaneously. Examples of workloads that execute simultaneously include workloads that have a complexity or graphics resolution equal to or less than the complexity or graphics resolution used to configure multiple FE circuits implemented on the GPU, as described herein. If only a single workload is to be executed by the GPU, method 900 proceeds to block 915. If multiple workloads are to be scheduled simultaneously, method 900 proceeds to block 920.

[0023] At block 915, one FE circuit is allocated to schedule commands for simultaneous execution on the set of SEs. No other FE circuit available in the GPU is allocated to schedule commands for execution on any of the sets of SEs.

[0024] At block 920, a set of FE circuits is assigned to schedule commands for concurrent execution by a corresponding subset of the set of SEs. At block 925, the set of FE circuits schedules the commands for concurrent execution by the corresponding subset. For example, if two FE circuits are assigned, a first FE circuit schedules commands for execution on a first subset of the set of SEs, and a second FE circuit schedules commands for execution on a second subset of the set of SEs. The first and second subsets execute the scheduled commands concurrently.

[0025] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS)-based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0026] In some embodiments, some aspects of the above techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored in or tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the above techniques. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or executed by one or more processors.

[0027] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, that some of the particular activities or devices may not be required, that one or more additional activities may be performed, and that one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will recognize that various modifications and variations can be made without departing from the scope of the invention as set forth in the claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

[0028] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, since the disclosed invention may be modified and practiced in different, but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and that all such variations are considered within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. An apparatus, comprising: Multiple shader engines and a first front-end (FE) circuit and at least one second FE circuit; In a first mode, the first FE circuit is configured to schedule geometry workloads of the plurality of shader engines; In a second mode, the first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines, and the at least one second FE circuit is configured to schedule geometry workloads for a second subset of the plurality of shader engines; an allocation of shader engines to the first FE circuit and the at least one second FE circuit is dynamically controlled based on whether the device is operating in the first mode or the second mode; Device.

2. a partition switch configured to selectively connect the first FE circuit or the at least one second FE circuit to the second subset of the plurality of shader engines depending on whether the device is in the first mode or the second mode.

10. The apparatus of claim 1.

3. in the first mode, the first FE circuitry is configured to schedule geometry workloads for concurrent execution by the multiple shader engines; In the second mode, the first FE circuit is configured to schedule geometry workloads to be executed by the first subset concurrently with execution of geometry workloads scheduled by the at least one second FE circuit for execution on the second subset.

3. The device of claim 1 or 2.

4. the first FE circuit and the at least one second FE circuit are configured based on different levels of user experience corresponding to at least one of complexity or graphic resolution.

3. The device of claim 1 or 2.

5. the first FE circuit is configured based on a first level of user experience corresponding to at least one of a first complexity or a first graphics resolution; the at least one second FE circuit is configured based on at least one second level of user experience corresponding to at least one of a second complexity or a second graphics resolution; At least one of the first complexity or the first graphics resolution is greater than at least one of the second complexity or the second graphics resolution; 5. The apparatus of claim 4.

6. the at least one second FE circuit includes at least one third FE circuit configured based on at least one of a third complexity or a third graphics resolution that is lower than at least one of the first complexity or the first graphics resolution; the at least one second FE circuit includes at least one fourth FE circuit configured based on at least one of a fourth complexity or a fourth graphics resolution that is lower than at least one of the third complexity or the third graphics resolution; 6. The apparatus of claim 5.

7. the first FE circuit is configured to schedule geometry workloads of the plurality of shader engines in the first mode for a first application requiring at least one of the first complexity or the first graphics resolution.

7. The apparatus of claim 6.

8. the first FE circuit and the at least one third FE circuit are configured to schedule geometry workloads of a corresponding subset of the plurality of shader engines for a second application requiring at least one of the third complexity or the third graphics resolution.

8. The apparatus of claim 7.

9. the first FE circuit, the at least one third FE circuit, and the fourth FE circuit are configured to schedule geometry workloads of corresponding subsets of the plurality of shader engines for a third application requiring at least one of the fourth complexity or the fourth graphics resolution.

9. The apparatus of claim 8.

10. at least one of the first FE circuit or the at least one second FE circuit is configured to support multiple simultaneous threads using time division multiplexing; 10. The device of any one of claims 1 to 9.

11. fetching geometry workloads for a plurality of shader engines in a first front-end (FE) circuit and at least one second FE circuit; scheduling the geometry workload in the first FE circuit in a first mode, the first FE circuit scheduling the geometry workload for execution on the plurality of shader engines; scheduling the geometry workload on the first FE circuit and the at least one second FE circuit in a second mode, wherein the first FE circuit schedules the geometry workload for execution on a first subset of the plurality of shader engines and the at least one second FE circuit schedules the geometry workload on a second subset of the plurality of shader engines, and an allocation of shader engines to the first FE circuit and the at least one second FE circuit is dynamically controlled differently between the first mode and the second mode. method.

12. selectively connecting the first FE circuit to the second subset of the plurality of shader engines in the first mode, and selectively connecting the at least one second FE circuit to the second subset of the plurality of shader engines in the second mode. The method of claim 11.

13. In the first mode, scheduling the geometry workload for execution on the plurality of shader engines includes scheduling the geometry workload for concurrent execution by the plurality of shader engines; scheduling the geometry workload for execution on the first subset and the second subset in the second mode includes scheduling the geometry workload for execution concurrently on the first subset and the second subset in the second mode.

13. The method of claim 12.

14. selectively scheduling the geometry workload in the first mode or the second mode based on at least one of a complexity or a graphics resolution of at least one application generating the geometry workload.

14. The method of claim 13.

15. scheduling the geometry workload for execution on the plurality of shader engines in the first mode includes scheduling the geometry workload for execution on the plurality of shader engines in the first mode for a first application requiring at least one of the first complexity or the first graphics resolution.

15. The method of claim 14.

16. In the second mode, scheduling the geometry workload for concurrent execution on the first subset and the second subset of the plurality of shader engines includes scheduling the geometry workload for concurrent execution on the first subset and the second subset of the plurality of shader engines for a second application requiring at least one of a second complexity or a second graphics resolution; at least one of the second complexity or the second graphics resolution is lower than at least one of the first complexity or the first graphics resolution; 16. The method of claim 15.

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