semiconductor memory device

Abstract

To provide a semiconductor storage device that suppresses an increase in chip area.SOLUTION: According to an embodiment, a semiconductor storage device includes: a memory cell MC; a first circuit 60e that stores first data DOPe based on the result of comparing a first bit data V0 of a signal DQ with a voltage VREF in a first latch circuit and outputs a first signal DRe based on the first data; and a second circuit 60o that stores second data DOPo based on the result of comparing a second bit data V1 with a reference voltage in a second latch circuit and outputs a second signal DRo based on the second data. The first circuit compares the first bit data with the reference voltage based on the second data and puts the first latch circuit into a reset state based on the second signal. The second circuit compares the second bit data with the reference voltage based on the first data and puts the second latch circuit into a reset state based on the first signal.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5566941 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a semiconductor memory device that can suppress an increase in chip area. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a nonvolatile memory cell and a first latch circuit, the first circuit receiving first bit data of an input signal based on a first clock signal, storing first data in the first latch circuit based on a result of comparing the first bit data with a reference voltage, and outputting a first signal based on the first data; and a second circuit receiving second bit data of the input signal based on a second clock signal obtained by inverting the first clock signal, storing second data in the second latch circuit based on a result of comparing the second bit data with a reference voltage, and outputting a second signal based on the second data. The first circuit receives the second data and the second signal, compares the first bit data with the reference voltage based on the second data, and resets the first latch circuit based on the second signal. The second circuit receives the first data and the first signal, compares the second bit data with the reference voltage based on the first data, and resets the second latch circuit based on the first signal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a data processing device including a semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram of the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 4] FIG. 4 is a block diagram of an input circuit included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 5 is a block diagram of a DFE circuit 50 and a latch circuit 52 included in the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram of a DFE circuit 50 included in the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 7 is a circuit diagram of an amplifier 60e included in the semiconductor memory device according to the first embodiment. [Figure 8] FIG. 8 is a timing chart of various signals in the DFE circuit 50 included in the semiconductor memory device according to the first embodiment. [Figure 9] FIG. 9 is a state diagram of the DFE circuit 50 at time t0 in the timing chart shown in FIG. [Figure 10] FIG. 10 is a state diagram of the DFE circuit 50 at time t1 in the timing chart shown in FIG. [Figure 11] FIG. 11 is a state diagram of the DFE circuit 50 at time t2 in the timing chart shown in FIG. [Figure 12] FIG. 12 is a state diagram of the DFE circuit 50 at time t3 in the timing chart shown in FIG. [Figure 13] FIG. 13 is a state diagram of the DFE circuit 50 at time t4 in the timing chart shown in FIG. [Figure 14]FIG. 14 is a state diagram of the DFE circuit 50 at time t5 in the timing chart shown in FIG. [Figure 15] FIG. 15 is a state diagram of the DFE circuit 50 at time t6 in the timing chart shown in FIG. [Figure 16] FIG. 16 is a state diagram of the DFE circuit 50 at time t7 in the timing chart shown in FIG. [Figure 17] FIG. 17 is a state diagram of the DFE circuit 50 at time t8 in the timing chart shown in FIG. [Figure 18] FIG. 18 is a state diagram of the DFE circuit 50 at time t9 in the timing chart shown in FIG. [Figure 19] FIG. 19 is a state diagram of the DFE circuit 50 at time t10 in the timing chart shown in FIG. [Figure 20] FIG. 20 is a state diagram of the DFE circuit 50 at time t11 in the timing chart shown in FIG. [Figure 21] FIG. 21 is a state diagram of the DFE circuit 50 at time t12 in the timing chart shown in FIG. [Figure 22] FIG. 22 is a state diagram of the DFE circuit 50 at time t13 in the timing chart shown in FIG. [Figure 23] FIG. 23 is a circuit diagram of an amplifier 60e included in a semiconductor memory device according to a modification of the first embodiment. [Figure 24] FIG. 24 is a block diagram of a DFE circuit 50 and a latch circuit 52 included in the semiconductor memory device according to the second embodiment. [Figure 25] FIG. 25 is a circuit diagram of a DFE circuit 50 included in the semiconductor memory device according to the second embodiment. [Figure 26] FIG. 26 is a circuit diagram of an amplifier 62e included in the semiconductor memory device according to the second embodiment. [Figure 27] FIG. 27 is a timing chart of various signals in the DFE circuit 50 included in the semiconductor memory device according to the second embodiment. [Figure 28]FIG. 28 is a state diagram of the DFE circuit 50 at time t0 in the timing chart shown in FIG. [Figure 29] FIG. 29 is a state diagram of the DFE circuit 50 at time t1 in the timing chart shown in FIG. [Figure 30] FIG. 30 is a state diagram of the DFE circuit 50 at time t2 in the timing chart shown in FIG. [Figure 31] FIG. 31 is a state diagram of the DFE circuit 50 at time t3 in the timing chart shown in FIG. [Figure 32] FIG. 32 is a state diagram of the DFE circuit 50 at time t4 in the timing chart shown in FIG. [Figure 33] FIG. 33 is a state diagram of the DFE circuit 50 at time t5 in the timing chart shown in FIG. [Figure 34] FIG. 34 is a state diagram of the DFE circuit 50 at time t6 in the timing chart shown in FIG. [Figure 35] FIG. 35 is a state diagram of the DFE circuit 50 at time t7 in the timing chart shown in FIG. [Figure 36] FIG. 36 is a state diagram of the DFE circuit 50 at time t8 in the timing chart shown in FIG. [Figure 37] FIG. 37 is a state diagram of the DFE circuit 50 at time t9 in the timing chart shown in FIG. [Figure 38] FIG. 38 is a state diagram of the DFE circuit 50 at time t10 in the timing chart shown in FIG. [Figure 39] FIG. 39 is a state diagram of the DFE circuit 50 at time t11 in the timing chart shown in FIG. [Figure 40] FIG. 40 is a state diagram of the DFE circuit 50 at time t12 in the timing chart shown in FIG. [Figure 41] FIG. 41 is a state diagram of the DFE circuit 50 at time t13 in the timing chart shown in FIG. [Figure 42]FIG. 42 is a circuit diagram of an amplifier 62e included in a semiconductor memory device according to a first modification of the second embodiment. [Figure 43] FIG. 43 is a circuit diagram of an amplifier 62e included in a semiconductor memory device according to a second modification of the second embodiment. [Figure 44] FIG. 44 is a block diagram of a DFE circuit 50 included in the semiconductor memory device according to the third embodiment. [Figure 45] FIG. 45 is a circuit diagram of an amplifier 96e1 included in the semiconductor memory device according to the third embodiment. [Figure 46] FIG. 46 is a circuit diagram of an amplifier 93e included in the semiconductor memory device according to the third embodiment. [Figure 47] FIG. 47 is a timing chart of various signals in the DFE circuit 50 included in the semiconductor memory device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Embodiments will be described below with reference to the drawings. Each embodiment exemplifies an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. All descriptions of one embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded. The technical idea of ​​the present invention is not limited by the shape, structure, arrangement, etc. of components.

[0008] In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. The numbers following the letters constituting the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and that have similar configurations. When there is no need to distinguish between elements indicated by reference numerals containing the same letters, these elements are referred to by reference numerals containing only letters.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Data Processing Device Configuration First, an example of the configuration of a data processing device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the data processing device 1. Note that in the example of Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0010] 1, a data processing device 1 includes a host device 2 and a memory system 3. Note that the host device 2 may be connected to a plurality of memory systems 3.

[0011] The host device 2 is an information processing device (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) the memory system 3 to perform a data write operation or a data read operation.

[0012] The memory system 3 is, for example, a solid state drive (SSD). The memory system 3 is connected to the host device 2.

[0013] 1.1.2 Memory System Configuration Continuing to refer to FIG. 1, an example of the configuration of the memory system 3 will be described.

[0014] 1, the memory system 3 includes a memory controller 10 and a semiconductor memory device 20. The memory system 3 may include a plurality of semiconductor memory devices 20.

[0015] The memory controller 10 issues commands for read operations, write operations, erase operations, etc. to the semiconductor memory device 20 in response to requests (commands) from the host device 2. The memory controller 10 also manages the memory space of the semiconductor memory device 20.

[0016] The semiconductor memory device 20 is, for example, a NAND flash memory. The NAND flash memory includes a plurality of memory cell transistors (hereinafter also referred to as "memory cells") that store data in a nonvolatile manner.

[0017] Next, the internal configuration of the memory controller 10 will be described. The memory controller 10 includes a host interface circuit (host I / F) 11, a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 13, a RAM (Random Access Memory) 14, a buffer memory 15, and a memory interface circuit (memory I / F) 16. These circuits are connected to each other, for example, by an internal bus. Note that each function of the memory controller 10 may be realized by a dedicated circuit, or may be realized by the CPU 12 executing firmware (or a program).

[0018] The host interface circuit 11 is a hardware interface circuit connected to the host device 2. The host interface circuit 11 performs communication between the host device 2 and the memory controller 10 in accordance with an interface standard. The host interface circuit 11 transmits requests and data received from the host device 2 to the CPU 12 and the buffer memory 15, respectively. The host interface circuit 11 also transmits data stored in the buffer memory 15 to the host device 2.

[0019] The CPU 12 is a processor. The CPU 12 controls the overall operation of the memory controller 10. For example, the CPU 12 commands the semiconductor memory device 20 to perform write, read, and erase operations based on requests received from the host device 2. The CPU 12 also manages the memory area of ​​the semiconductor memory device 20.

[0020] The ROM 13 is a non-volatile memory. For example, the ROM 13 is an EEPROM. TM(Electrically Erasable Programmable Read-Only Memory). The ROM 13 is a non-transitory storage medium that stores firmware, programs, etc. For example, the operation of the memory controller 10, which will be described later, is realized by the CPU 12 executing the firmware in the ROM 13.

[0021] The RAM 14 is a volatile memory. For example, the RAM 14 is a dynamic random access memory (DRAM) or a static random access memory (SRAM). The RAM 14 is used as a work area for the CPU 12. The RAM 14 stores firmware for managing the semiconductor storage device 20, various management tables, and the like.

[0022] The buffer memory 15 is a volatile memory. For example, the buffer memory 15 is a DRAM or an SRAM. The buffer memory 15 temporarily stores data that the memory controller 10 reads from the semiconductor memory device 20, data that the memory controller 10 receives from the host device 2, and the like.

[0023] The memory interface circuit 16 is a hardware interface circuit connected to the semiconductor memory device 20. The memory interface circuit 16 transmits and receives data and various control signals to and from the semiconductor memory device 20. More specifically, the memory interface circuit 16 transmits and receives, for example, an 8-bit signal DQ<7:0> and clock signals DQS and bDQS to and from the semiconductor memory device 20. The signal DQ<7:0> is, for example, data, an address, and a command. Hereinafter, when there is no limitation on any of the signals DQ<7:0>, it will be referred to as the signal DQ. The clock signals DQS and bDQS are clock signals used when inputting and outputting data. The clock signal bDQS is an inverted signal of the clock signal DQS.

[0024] The memory interface circuit 16 also transmits, as control signals, for example, a chip enable signal bCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal bWE, and a read enable signal bRE to the semiconductor memory device 20. The memory interface circuit 16 also receives a ready / busy signal bRB from the semiconductor memory device 20.

[0025] The chip enable signal bCE is a signal for enabling the semiconductor memory device 20. The signal bCE is asserted, for example, at a low (“L”) level.

[0026] The command latch enable signal CLE is a signal that indicates that the signal DQ is a command. The signal CLE is asserted, for example, at a high (“H”) level.

[0027] The address latch enable signal ALE is a signal indicating that the signal DQ is an address, and is asserted at, for example, an "H" level.

[0028] The write enable signal bWE is a signal for loading a received signal into the semiconductor memory device 20. The signal bWE is asserted, for example, at the "L" level, at the timing when the semiconductor memory device 20 loads a command and an address. Therefore, each time the signal bWE is toggled, the command and address are loaded into the semiconductor memory device 20.

[0029] The read enable signal bRE is a signal used by the memory controller 10 to read data from the semiconductor memory device 20. For example, when outputting data, the semiconductor memory device 20 generates signals DQS and bDQS based on the signal bRE.

[0030] The ready / busy signal bRB is a signal that indicates whether the semiconductor memory device 20 is in a state where it can or cannot receive the signal DQ from the memory controller 10. The ready / busy signal bRB is set to the “L” level when the semiconductor memory device 20 is in a busy state, for example.

[0031] 1.1.3 Configuration of semiconductor memory device Next, an example of the configuration of the semiconductor memory device 20 will be described with reference to Fig. 2. Fig. 2 is a block diagram of the semiconductor memory device. In the example of Fig. 2, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to these.

[0032] As shown in FIG. 2, the semiconductor memory device 20 includes an input / output circuit 21, a logic control circuit 22, an address register 23, a command register 24, a status register 25, a sequencer 26, a ready / busy circuit 27, a voltage generation circuit 28, a memory cell array 29, a row decoder 30, a sense amplifier 31, a data register 32, and a column decoder 33.

[0033] The input / output circuit 21 is a circuit that inputs and outputs the signal DQ and the clock signals DQS and bDQS to and from the memory controller 10. The input / output circuit 21 is connected to the memory interface circuit 16 of the memory controller 10. The input / output circuit 21 is also connected to the logic control circuit 22, the address register 23, the command register 24, the status register 25, and the data register 32.

[0034] The input / output circuit 21 includes an input circuit 41 and an output circuit 42 .

[0035] The input circuit 41 is a circuit that receives an input signal DQ from the memory controller 10. If the input signal DQ is data DAT, the input circuit 41 receives the input signal DQ based on clock signals DQS and bDQS. Then, the input circuit 41 transmits the data DAT to the data register 32. If the input signal DQ is an address ADD, the input circuit 41 receives the input signal DQ based on a signal bWE. Then, the input circuit 41 transmits the address ADD to the address register 23. If the input signal DQ is a command CMD, the input circuit 41 receives the input signal DQ based on a signal bWE. Then, the input circuit 41 transmits the command CMD to the command register 24.

[0036] The output circuit 42 is a circuit that transmits an output signal DQ to the memory controller 10. The output circuit 42 transmits the output signal DQ to the memory controller 10 together with clock signals DQS and bDQS.

[0037] The logic control circuit 22 is a circuit that performs logic control of the semiconductor memory device 20. The logic control circuit 22 receives, for example, signals bCE, CLE, ALE, bWE, and bRE from the memory controller 10. The logic control circuit 22 is connected to the input / output circuit 21 and the sequencer 26. The logic control circuit 22 controls the input / output circuit 21 and the sequencer 26 based on the received signals.

[0038] The address register 23 is a register that temporarily stores the address ADD. The address register 23 is connected to the input / output circuit 21, the row decoder 30, and the column decoder 33. The address ADD includes a row address RA and a column address CA. The address register 23 transmits the row address RA to the row decoder 30. The address register 23 also transmits the column address CA to the column decoder 33.

[0039] The command register 24 is a register that temporarily stores the command CMD. The command register 24 is connected to the input / output circuit 21 and the sequencer 26. The command register 24 transmits the command CMD to the sequencer 26.

[0040] The status register 25 is a register that temporarily stores status information STS. For example, the status information STS includes information about the results of a write operation, a read operation, an erase operation, etc. The status register 25 is connected to the sequencer 26. For example, the status information STS is transmitted to the memory controller 10 as an output signal DQ.

[0041] The sequencer 26 is a circuit that controls the overall operation of the semiconductor memory device 20. The sequencer 26 is connected to the logic control circuit 22, the address register 23, the command register 24, the status register 25, the ready / busy circuit 27, the voltage generation circuit 28, the row decoder 30, the sense amplifier 31, etc. The sequencer 26 controls the status register 25, the ready / busy circuit 27, the voltage generation circuit 28, the row decoder 30, the sense amplifier 31, etc. The sequencer 26 executes a write operation, a read operation, and an erase operation based on a command CMD.

[0042] The ready / busy circuit 27 is a circuit that generates a ready / busy signal bRB. The ready / busy circuit 27 is connected to the sequencer 26. The ready / busy circuit 27 generates the ready / busy signal bRB under the control of the sequencer 26. The ready / busy circuit 27 transmits the ready / busy signal bRB to the memory controller 10.

[0043] The voltage generation circuit 28 generates various voltages used in write, read, and erase operations under the control of the sequencer 26. The voltage generation circuit 28 supplies the various voltages to the memory cell array 29, row decoder 30, sense amplifier 31, etc.

[0044] The memory cell array 29 is a collection of arranged memory cell transistors. The memory cell array 29 includes a plurality of blocks BLK. A block BLK is a collection of memory cell transistors from which data is erased collectively, for example. In the example of FIG. 2, the memory cell array 29 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 29 is arbitrary.

[0045] The row decoder 30 is a decoding circuit for the row address RA. The row decoder 30 is connected to the address register 23, the sequencer 26, the voltage generating circuit 28, and the memory cell array 29. The row decoder 30 selects one of the blocks BLK based on the result of decoding the row address RA. The row decoder 30 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0046] The sense amplifier 31 is a circuit that writes and reads data DAT. The sense amplifier 31 is connected to the sequencer 26, the voltage generating circuit 28, the memory cell array 29, and the data register 32. During a read operation, the sense amplifier 31 reads the data DAT from the memory cell array 29. During a write operation, the sense amplifier 31 supplies a voltage corresponding to the write data DAT to the memory cell array 29.

[0047] The data register 32 is a register that temporarily stores data DAT. The data register 32 is connected to the input / output circuit 21, the sequencer 26, the sense amplifier 31, and the column decoder 33. The data register 32 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0048] The column decoder 33 is a circuit that decodes the column address CA. The column decoder 33 is connected to the address register 23, the sequencer 26, and the data register 32. The column decoder 33 receives the column address CA from the address register 23. The column decoder 33 selects a latch circuit in the data register 32 based on the decoded result of the column address CA.

[0049] 1.1.4 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 29 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram of the memory cell array 29. Note that the example of Fig. 3 shows the circuit configuration of one block BLK.

[0050] As shown in Fig. 3, a block BLK includes multiple string units SU. A string unit SU is, for example, a collection of multiple NAND strings NS that are collectively selected in a write operation or a read operation. In the example of Fig. 3, the block BLK includes four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary.

[0051] Next, the internal configuration of the string unit SU will be described. The string unit SU includes multiple NAND strings NS. A NAND string NS is a collection of multiple memory cell transistors connected in series. For example, n+1 (n is an integer equal to or greater than 1) NAND strings NS in the string unit SU are connected to n+1 bit lines BL0 to BLn, respectively.

[0052] Next, the internal configuration of the NAND strings NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Fig. 3, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC in the NAND string NS is arbitrary.

[0053] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductive layer for the charge storage layer.

[0054] The select transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of select transistors ST1 and ST2 is arbitrary. It is sufficient that the NAND string NS includes one or more select transistors ST1 and ST2.

[0055] The current paths of the memory cell transistors MC and the select transistors ST1 and ST2 in each NAND string NS are connected in series. More specifically, the current paths of the select transistor ST2, memory cell transistors MC0 to MC7, and select transistor ST1 are connected in series in this order. The drain of the select transistor ST1 is connected to one of the bit lines BL. The source of the select transistor ST2 is connected to a source line SL.

[0056] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each of the string units SU0 to SU3 includes a plurality of memory cell transistors MC0. The control gates of these memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0057] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the string unit SU0 includes multiple select transistors ST1. The gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. Similarly, the gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3.

[0058] The gates of the multiple select transistors ST2 in the same block BLK are commonly connected to one select gate line SGS. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each of the string units SU0 to SU3 includes multiple select transistors ST2. The gates of the multiple select transistors ST2 in the block BLK are commonly connected to one select gate line SGS. Note that, similar to the select gate lines SGD, a different select gate line SGS may be provided for each string unit SU.

[0059] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are connected to a row decoder 30, respectively.

[0060] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address CA is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 31.

[0061] The source line SL is shared among, for example, a plurality of blocks BLK.

[0062] Within one string unit SU, a set of multiple memory cell transistors MC connected to one word line WL is referred to as a "cell unit CU." For example, if the memory cell transistor MC stores one bit of data, the storage capacity of the cell unit CU is defined as "one page of data." Depending on the number of bits of data stored in the memory cell transistor MC, the cell unit CU may have a storage capacity of two or more pages of data.

[0063] 1.1.5 Input circuit configuration Next, an example of the configuration of the input circuit 41 will be described with reference to Fig. 4. Fig. 4 is a block diagram of the input circuit 41.

[0064] As shown in FIG. 4, the input circuit 41 includes eight decision feedback equalizer (DFE) circuits 50_0 to 50_7, a clock signal generating circuit 51, eight latch circuits 52_0 to 52_7, and eight shift registers 53_0 to 53_7.

[0065] Hereinafter, when any of the DFE circuits 50_0 to 50_7 is not specified, it is referred to as a DFE circuit 50. When any of the latch circuits 52_0 to 52_7 is not specified, it is referred to as a latch circuit 52. When any of the shift registers 53_0 to 53_7 is not specified, it is referred to as a shift register 53.

[0066] The DFE circuit 50 is a signal compensation circuit to which the DFE technique is applied. The DFE technique is one of digital signal compensation techniques. The DFE circuits 50_0 to 50_7 compensate for the signal DQ <0> ~DQ <7> and the DFE circuit 50, which correspond to the following: The DFE circuit 50 determines the logic level (High (“H”) level or Low (“L”) level) of the bit data of the input signal (signal DQ). The DFE circuit 50 compensates the input signal by feeding back the bit data whose logic level has been determined to the input of the next bit data.

[0067] For example, the input circuit 41 may not be able to receive the signal DQ in a full swing state due to the influence of the transmission path between the memory controller 10 and the semiconductor memory device 20 or due to increased communication speeds. That is, the input circuit 41 may receive a signal DQ with a smaller amplitude than the signal DQ output by the memory controller 10. The input circuit 41 determines the logic level of the signal DQ by comparing the signal DQ with the reference voltage VREF. Therefore, if the signal DQ is not in a full swing state, the voltage difference between the signal DQ and the voltage VREF becomes small, increasing the possibility of erroneous determination of the logic level of the signal DQ. In such cases, the DFE circuit 50 improves the waveform of the input signal DQ.

[0068] The DFE circuit 50 receives the corresponding signal DQ, a voltage VREF, and clock signals CK and bCK. The voltage VREF is used to determine the logic level of the signal DQ. The clock signals CK and bCK are used to control the timing of capturing the signal DQ. The signal bCK is an inverted signal of the signal CK. For example, the DFE circuit 50 captures (receives) the signal DQ at the rising edges of the signals CK and bCK.

[0069] The DFE circuit 50 has a receiving path corresponding to the even-numbered bit data of the signal DQ and a receiving path corresponding to the odd-numbered bit data. Therefore, the DFE circuit 50 has two output terminals corresponding to the even-numbered bit data of the signal DQ and two output terminals corresponding to the odd-numbered bit data. The four output terminals of the DFE circuit 50 are connected to the four input terminals of the corresponding latch circuits 52. More specifically, the DFE circuits 50_0 to 50_7 are connected to the latch circuits 52_0 to 52_7, respectively.

[0070] The clock signal generation circuit 51 is a circuit that generates signals CK and bCK. The clock signal generation circuit 51 is connected to the DFE circuits 50_0 to 50_7. The clock signal generation circuit 51 transmits the signals CK and bCK to each DFE circuit 50. The clock signal generation circuit 51 receives the signals DQS and bDQS. For example, if the signal DQ is data, the clock signal generation circuit 51 outputs the signal DQS as the signal CK and outputs the signal bDQS as the signal bCK. Furthermore, for example, if the signal DQ is a command or an address, the clock signal generation circuit 51 generates the signals CK and bCK based on the signal bWE received from the logic control circuit 22.

[0071] The latch circuits 52 are circuits that temporarily store the output signals of the corresponding DFE circuits 50. The latch circuits 52 receive, as output signals from the DFE circuits 50, even-numbered bit data and odd-numbered bit data of the signal DQ whose logic level has been determined. The latch circuits 52 have output terminals corresponding to the even-numbered bit data and odd-numbered bit data of the signal DQ. The two output terminals of the latch circuits 52 are connected to two input terminals of the corresponding shift registers 53. More specifically, the latch circuits 52_0 to 52_7 are connected to the shift registers 53_0 to 53_7, respectively.

[0072] The shift register 53 is a circuit that temporarily stores the output signal of the corresponding latch circuit 52. For example, the shift register 53 includes a plurality of flip-flop circuits corresponding to the even-bit data of the signal DQ and a plurality of flip-flop circuits corresponding to the odd-bit data. The shift register 53 may convert the parallelism of the signal DQ from two parallel data, even-bit data and odd-bit data, to output the converted signal. For example, the shift register 53 may output serial data in which even-bit data and odd-bit data are alternately arranged, or may output eight parallel data, consisting of four parallel even-bit data and four parallel odd-bit data. If the signal DQ is data, the shift register 53 sends the signal DQ to the data register 32. If the signal DQ is an address, the shift register 53 sends the signal DQ to the address register 23. If the signal DQ is a command, the shift register 53 sends the signal DQ to the command register 24.

[0073] 1.1.6 Configuration of DFE circuit and latch circuit Next, an example of the configuration of the DFE circuit 50 and the latch circuit 52 will be described with reference to Fig. 5. Fig. 5 is a block diagram of the DFE circuit 50 and the latch circuit 52.

[0074] As shown in FIG. 5, the DFE circuit 50 includes two amplifiers 60e and 60o. The amplifiers 60e and 60o have the same configuration. The DFE circuit 50 supports 2 Time-Interleave (2TI), which divides the receive path into two phases. For example, the amplifier 60e supports the receive path for even-numbered bit data of the signal DQ. The amplifier 60o supports the receive path for odd-numbered bit data of the signal DQ. Hereinafter, when there is no need to specify either the amplifier 60e or 60o, it will be referred to as the amplifier 60.

[0075] The amplifier 60 is an LT-SA (Latch-type Voltage Sense Amplifier) ​​circuit that includes data input terminals DM and bDM, feedback input terminals DF and bDF, a latch control clock input terminal CL, a reset control clock input terminal CR, data output terminals Q and bQ, and a latch completion output terminal R. The LT-SA circuit is a differential amplifier that has a latch circuit that stores output data.

[0076] A signal DQ is input to the terminal DM, and a voltage VREF is input to the terminal bDM.

[0077] The output signal of one amplifier 60 is input (feedback) to the terminals DF and bDF of the other amplifier 60. For example, if one amplifier 60 is amplifier 60e, the other amplifier 60 is amplifier 60o. Also, if one amplifier 60 is amplifier 60o, the other amplifier 60 is amplifier 60e. More specifically, for example, when amplifier 60e receives the kth (k is any even number) bit data of signal DQ, output signals DOPo and DOMo corresponding to the (k-1)th bit data of signal DQ received by amplifier 60o at the immediately previous timing are fed back to the terminals DF and bDF of amplifier 60e, respectively. The terminals DF and bDF of one amplifier 60 are connected to the terminals Q and bQ of the other amplifier 60, respectively. More specifically, the signal DOPo is input to the terminal DF of amplifier 60e from the terminal Q of amplifier 60o. The signal DOMo is input to the terminal bDF of amplifier 60e from the terminal bQ of amplifier 60o. A terminal DF of the amplifier 60o receives a signal DOPe from a terminal Q of the amplifier 60e. A terminal bDF of the amplifier 60o receives a signal DOMe from a terminal bQ of the amplifier 60e.

[0078] The amplifier 60e has a terminal CL that receives the signal CK, and the amplifier 60o has a terminal CL that receives the signal bCK.

[0079] A reset control clock signal output from a terminal R of the other amplifier 60 is input to a terminal CR of one amplifier 60. The reset control clock signal is a signal that notifies the state (latched state or reset state) of the latch circuit in the other amplifier 60. The amplifier 60 resets the latch circuit based on the reset control clock signal. In other words, the latch circuit of one amplifier 60 is reset after the logic level of the signal DQ is determined in the latch circuit of the other amplifier 60. The terminal CR of one amplifier 60 is connected to the terminal R of the other amplifier 60. More specifically, the terminal CR of amplifier 60e is connected to the terminal R of amplifier 60o. The terminal CR of amplifier 60o is connected to the terminal R of amplifier 60e. Hereinafter, the reset control clock signal of amplifier 60o input to the terminal CR of amplifier 60e will be referred to as signal DRo. Furthermore, the reset control clock signal of amplifier 60e input to the terminal CR of amplifier 60o will be referred to as signal DRe.

[0080] The amplifier 60 outputs an inverted signal of the signal DQ from terminals Q and bQ. More specifically, when even-bit data of "H" level is input to terminal DM, the amplifier 60e outputs a signal DOPe of "L" level from terminal Q and a signal DOMe of "H" level from terminal bQ. When even-bit data of "L" level is input to terminal DM, the amplifier 60e outputs a signal DOPe of "H" level from terminal Q and a signal DOMe of "L" level from terminal bQ. Similarly, when odd-bit data of "H" level is input to terminal DM, the amplifier 60o outputs a signal DOPo of "L" level from terminal Q and a signal DOMo of "H" level from terminal bQ. When odd-bit data of "L" level is input to terminal DM, the amplifier 60o outputs a signal DOPo of "H" level from terminal Q and a signal DOMo of "L" level from terminal bQ. When odd-bit data of "L" level is input to terminal DM, the amplifier 60o outputs a signal DOPo of "H" level from terminal Q and a signal DOMo of "L" level from terminal bQ.

[0081] The amplifier 60 outputs a reset control clock signal from terminal R. When the latch circuit is in the reset state, the amplifier 60 outputs a reset completion signal of "H" level. When the latch circuit is in the latch state, the amplifier 60 outputs a reset completion signal of "L" level. More specifically, for example, in the amplifier 60e, when the logic levels of the signals DOPe and DOMe are the same, i.e., when the latch circuit is in the reset state, the reset control clock signal is set to "H" level. On the other hand, when the logic levels of the signals DOPe and DOMe are different, i.e., when the latch circuit is in the latch state, the reset control clock signal is set to "L" level. Similarly, in the amplifier 60o, when the logic levels of the signals DOPo and DOMo are the same, the reset control clock signal is set to "H" level. On the other hand, when the logic levels of the signals DOPo and DOMo are different, the reset control clock signal is set to "L" level.

[0082] Next, the latch circuit 52 will be described. The latch circuit 52 includes two bSR latch circuits 70e and 70o. The bSR latch circuits 70e and 70o have the same configuration. Hereinafter, when there is no need to specify either the bSR latch circuit 70e or 70o, it will be referred to as the bSR latch circuit 70.

[0083] The bSR latch circuit 70e temporarily stores the output signal of the amplifier 60e. The bSR latch circuit 70o temporarily stores the output signal of the amplifier 60o.

[0084] The bSR latch circuit 70 includes a signal input terminal bS, a reset signal input terminal bR, and an output terminal Q. The bSR latch circuit 70 may also include an inverted output terminal bQ.

[0085] When an "L" level signal is input to terminal bS and an "H" level signal is input to terminal bR, the bSR latch circuit 70 outputs an "H" level signal from terminal Q. When an "H" level signal is input to terminal bS and an "L" level signal is input to terminal bR, the bSR latch circuit 70 outputs an "L" level signal from terminal Q. Furthermore, the bSR latch circuit 70 maintains the previous output state while "H" level signals are input to terminals bS and bR.

[0086] The bSR latch circuit 70e has a terminal bS that receives the signal DOPe from the amplifier 60e, a terminal bR that receives the signal DOMe from the amplifier 60e, and a terminal Q that outputs a signal DQe, which is the even-numbered bit data of the signal DQ.

[0087] The bSR latch circuit 70o has a terminal bS that receives the signal DOPo from the amplifier 60o, a terminal bR that receives the signal DOMo from the amplifier 60o, and a terminal Q that outputs a signal DQo, which is odd-numbered bit data of the signal DQ.

[0088] 1.1.7 DFE Circuit Schematic Next, an example of a circuit diagram of the DFE circuit 50 will be described with reference to Figures 6 and 7. Figure 6 is a circuit diagram of the DFE circuit 50. Figure 7 is a circuit diagram of an amplifier 60e.

[0089] As shown in Figure 6, the amplifiers 60e and 60o have the same circuit configuration. The following description focuses on the amplifier 60e. In the following description, either the source or the drain of a transistor will be referred to as one end of the transistor. Furthermore, the other of the source or the drain of a transistor will be referred to as the other end of the transistor.

[0090] As shown in FIG. 7, the amplifier 60e includes p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) (hereinafter also referred to as "PMOS transistors" or "transistors") 101-104, n-channel MOSFETs (hereinafter also referred to as "NMOS transistors" or "transistors") 105-111, a logical sum operation circuit (OR circuit) 112, and an exclusive negative OR operation circuit (XNOR circuit) 113.

[0091] A power supply voltage VDD is applied to one end of the transistor 101. In other words, one end of the transistor 101 is connected to the power supply voltage line. The other end of the transistor 101 is connected to a node ND1. The gate of the transistor 101 is connected to the output terminal of the OR circuit 112.

[0092] A voltage VDD is applied to one end of the transistor 102. The other end of the transistor 102 is connected to a node ND1. The gate of the transistor 102 is connected to a node ND2.

[0093] A voltage VDD is applied to one end of the transistor 103. The other end of the transistor 103 is connected to a node ND2. The gate of the transistor 103 is connected to a node ND1.

[0094] A voltage VDD is applied to one end of the transistor 104. The other end of the transistor 104 is connected to a node ND2. The gate of the transistor 104 is connected to the output terminal of the OR circuit 112.

[0095] One end of the transistor 105 is connected to a node ND1, the other end of the transistor 105 is connected to a node ND3, and the gate of the transistor 105 is connected to a node ND2.

[0096] One end of the transistor 106 is connected to the node ND2, the other end of the transistor 106 is connected to the node ND4, and the gate of the transistor 106 is connected to the node ND1.

[0097] The transistors 102, 103, 105, and 106 form a latch circuit DL. More specifically, the transistors 102 and 105 form a first inverter. The transistors 103 and 106 form a second inverter. The output of the first inverter and the input of the second inverter (node ​​ND1) are connected to a terminal Q. The input of the first inverter and the output of the second inverter (node ​​ND2) are connected to a terminal bQ.

[0098] The transistors 101 and 104 function as a reset circuit for the latch circuit DL. For example, when the output signal of the OR circuit 112 is set to the "L" level, the transistors 101 and 104 are turned on. As a result, the nodes ND1 and ND2 are charged to the "H" level. That is, the latch circuit DL is set to the reset state.

[0099] One end of the transistor 107 is connected to the node ND3, the other end of the transistor 107 is connected to the node ND5, and the gate of the transistor 107 is connected to the terminal DM.

[0100] One end of the transistor 108 is connected to the node ND4, the other end of the transistor 108 is connected to the node ND5, and the gate of the transistor 108 is connected to the terminal bDM.

[0101] One end of the transistor 109 is connected to a node ND3, the other end of the transistor 109 is connected to a node ND5, and the gate of the transistor 109 is connected to a terminal DF.

[0102] Transistor 109 is connected in parallel with transistor 107. The drive capability of transistor 109 is lower than that of transistor 107. For example, when transistors 107 and 109 are in the on state, the current flowing through transistor 109 is smaller than the current flowing through transistor 107. For example, transistor 107 has a structure in which multiple transistors (e.g., 10) of the same size as transistor 109 are connected in parallel.

[0103] One end of the transistor 110 is connected to a node ND4, the other end of the transistor 110 is connected to a node ND5, and the gate of the transistor 110 is connected to a terminal bDF.

[0104] The transistor 110 is connected in parallel with the transistor 108. The drive capability of the transistor 110 is lower than that of the transistor 108. For example, when the transistors 108 and 110 are in the on state, the current flowing through the transistor 110 is smaller than the current flowing through the transistor 108. For example, the transistor 108 has a structure in which multiple transistors (for example, 10) of the same size as the transistor 110 are connected in parallel.

[0105] The transistors 109 and 110 serve to feed back the output signal of the other amplifier 60 to the input signal of one amplifier 60. The operation of the transistors 109 and 110 produces an effect similar to that produced when the voltage value of the voltage VREF fluctuates relative to the voltage value of the signal DQ. For example, when the transistor 109 is on and the transistor 110 is off, this is the same as when the voltage value of the voltage VREF decreases relative to the voltage value of the signal DQ. On the other hand, when the transistor 109 is off and the transistor 110 is on, this is the same as when the voltage value of the voltage VREF increases relative to the voltage value of the signal DQ.

[0106] More specifically, for example, if the bit data of the signal DQ received by the amplifier 60o at the previous timing is at a low level, the amplifier 60o outputs a high-level signal DOPo and a low-level signal DOMo. Therefore, the high-level signal DOPo is input to the terminal DF of the amplifier 60e, and the low-level signal DOMo is input to the terminal bDF. In this case, the transistor 109 is turned on, and the transistor 110 is turned off. In this state, for example, if the high-level bit data of the signal DQ is input to the terminal DM, the transistors 107 and 109 are turned on. This state is similar to a state in which the high-level voltage of the signal DQ rises, turning the transistor 107 into a stronger on state. Therefore, the same effect occurs as when the voltage VREF drops relative to the voltage of the signal DQ. Hereinafter, this state will be referred to as "the voltage VREF drops."

[0107] Furthermore, for example, if the bit data of the signal DQ received by the amplifier 60o at the previous timing is at a "H" level, the amplifier 60o outputs a "L" level signal DOPo and a "H" level signal DOMo. Therefore, a "L" level signal is input to the terminal DF of the amplifier 60e, and a "H" level signal is input to the terminal bDF. In this case, the transistor 109 is turned off, and the transistor 110 is turned on. In this state, for example, if a "L" level bit data of the signal DQ is input to the terminal DM, the transistors 108 and 110 are turned on. This state is similar to a state in which the voltage VREF rises and the transistor 108 is turned on relatively strongly. Therefore, the same effect occurs as when the voltage VREF rises relative to the voltage of the signal DQ. Hereinafter, this state will be referred to as "the voltage VREF rises."

[0108] That is, when the bit data of the immediately preceding signal DQ is at the “L” level, the feedback causes the voltage VREF to decrease in the amplifier 60. On the other hand, when the bit data of the immediately preceding signal DQ is at the “H” level, the feedback causes the voltage VREF to increase in the amplifier 60.

[0109] One end of the transistor 111 is connected to a node ND5. The other end of the transistor 111 is grounded. In other words, the other end of the transistor 111 is connected to a ground voltage line. The gate of the transistor 111 is connected to the output terminal of the OR circuit 112.

[0110] The two input terminals of the OR circuit 112 are connected to the terminal CL and the terminal CR, respectively. The OR circuit 112 outputs an “H” level signal when at least one of the clock signal input from the terminal CL and the reset control clock signal input from the terminal CR is “H” level.

[0111] The two input terminals of the XNOR circuit 113 are connected to node ND1 (terminal Q) and node ND2 (terminal bQ), respectively. The XNOR circuit 113 outputs a completion signal at a low level when one of node ND1 and node ND2 is at a high level and the other is at a low level. In other words, the XNOR circuit 113 outputs a reset control clock signal at a low level when the logical level of the signal DQ captured in the latch circuit DL is established. More specifically, the XNOR circuit 113 of the amplifier 60e outputs a signal DRe at a low level when one of signals DOPe and DOMe is at a low level and the other is at a high level. Similarly, the XNOR circuit 113 of the amplifier 60o outputs a signal DRo at a low level when one of signals DOPo and DOMo is at a low level and the other is at a high level.

[0112] The operation of the amplifier 60e will be briefly described. The latch circuit DL of the amplifier 60e is in a reset state while the OR circuit 112 outputs a low level. More specifically, when the signal CK input from the terminal CL and the signal DRo input from the terminal CR are low, the OR circuit 112 outputs a low level signal. In this case, the transistors 101 and 104 are turned on, and the transistor 111 is turned off. This causes a high level voltage to be applied to the nodes ND1 and ND2. Therefore, the amplifier 60e outputs high level signals DOPe and DOMe. When the output signal of the OR circuit 112 rises from low level to high level, the amplifier 60e stores the even bit data of the signal DQ input from the terminal DM in the latch circuit DL. At this time, the output signals DOPo and DOMo of the amplifier 60o are input to the terminals DF and bDF, respectively. The logical levels of signals DOPe and DOMe are determined based on the results stored in the latch circuit DL. While one of signals DOPe and DOMe is at "H" level and the other is at "L" level, the XNOR circuit 113 outputs a "L" level signal. The amplifier 60e is reset when the OR circuit 112 falls from "H" level to "L" level. More specifically, when the logical level of the odd-numbered bit data of signal DQ at the next timing is determined in the amplifier 60o, signal DRo is set to "L" level. At this time, signal CK is at "L" level, so the amplifier 60e is reset based on signal DRo.

[0113] 1.2 Example of DFE circuit operation Next, an example of the operation of the DFE circuit 50 will be described with reference to Figs. 8 to 22. Fig. 8 is a timing chart of various signals in the DFE circuit 50. Figs. 9 to 22 are state diagrams of the DFE circuit 50 at each time in the timing chart shown in Fig. 8. In this example, a case will be described in which the input signal DQ is data. Note that the following description will focus on the parts where the signal and transistor states change at each time in the timing chart.

[0114] [Time t0] 8, at time t0 before the signal DQ is input, the signal CK is set to the "L" level and the signal bCK is set to the "H" level. The amplifier 60e outputs the signals DOPe and DOMe at the "H" level. As a result, the signal DRe is set to the "H" level. For example, the amplifier 60o outputs the signal DOPo at the "H" level and the signal DOMo at the "L" level. As a result, the signal DRo is set to the "L" level.

[0115] The amplifier 60e receives an "L" level signal CK and an "L" level signal DRo. As a result, the latch circuit DL (reference symbol "Even" in FIG. 8) of the amplifier 60e is set to a reset state (reference symbol "rst" in FIG. 8). Furthermore, the amplifier 60o receives an "H" level signal bCK and an "H" level signal DRe. As a result, the latch circuit DL (reference symbol "Odd" in FIG. 8) of the amplifier 60o is set to a latch state (reference symbol "lat" in FIG. 8).

[0116] 9, since the signal DQ is at the "L" level, the transistors 107 of the amplifiers 60e and 60o are turned off, and the transistors 108 of the amplifiers 60e and 60o are turned on relatively weakly and clamped by the voltage VREF.

[0117] A high-level signal DOPo is input to the terminal DF of the amplifier 60e. This turns on the transistor 109. A low-level signal DOMo is input to the terminal bDF of the amplifier 60e. This turns off the transistor 110. This causes the voltage VREF to drop in the amplifier 60e. Low-level signals CK and DRo are input to the OR circuit 112 of the amplifier 60e. This causes the OR circuit 112 to output a low-level signal. The transistors 101 and 104 of the amplifier 60e are turned on, and the transistor 111 is turned off. This causes the latch circuit DL to be reset. The amplifier 60e outputs high-level signals DOPe and DOMe.

[0118] A high-level signal DOPe is input to the terminal DF of the amplifier 60o. This causes the transistor 109 to be turned on. A high-level signal DOMe is input to the terminal bDF of the amplifier 60o. This causes the transistor 110 to be turned on. High-level signals bCK and DRe are input to the OR circuit 112 of the amplifier 60o. This causes the OR circuit 112 to output a high-level signal. The transistors 101 and 104 of the amplifier 60o are turned off, and the transistor 111 is turned on. This causes the latch circuit DL to be in a latched state. Because the signal DQ is low, the amplifier 60o outputs a high-level signal DOPo and a low-level signal DOMo.

[0119] [Time t1] 8, for example, assume that the even-numbered bit data V0 of the signal DQ is at the "H" level. At time t1, the signal CK rises from the "L" level to the "H" level, and the signal bCK falls from the "H" level to the "L" level. The latch circuit DL of the amplifier 60e is set to a latch state ("lat") based on the rising edge of the signal CK, and captures the even-numbered bit data V0 at the "H" level. Based on the even-numbered bit data V0, the signals DOPe and DOMe begin to transition.

[0120] As shown in FIG. 10, since the even-numbered bit data V0 of the signal DQ is at the "H" level, the transistors 107 of the amplifiers 60e and 60o are turned on.

[0121] An "H" level signal CK is input to the OR circuit 112 of the amplifier 60e. As a result, the OR circuit 112 outputs an "H" level signal. The transistors 101 and 104 of the amplifier 60e are turned off, and the transistor 111 is turned on. This causes the latch circuit DL of the amplifier 60e to enter a latching state. The amplifier 60e captures the even-numbered bit data V0.

[0122] The OR circuit 112 of the amplifier 60o receives the signal bCK at "L" level. Since the signal DRe is at "H" level, the OR circuit 112 continues to output a signal at "H" level.

[0123] [Time t2] As shown in FIG. 8, for example, assume that odd-numbered bit data V1 of signal DQ is at the "L" level. At time t2, the logic levels of signals DOPe and DOMe of amplifier 60e are determined. In other words, the logic level of even-numbered bit data V0 is determined. Because even-numbered bit data V0 is at the "H" level, signal DOPe is set to the "L" level, and signal DOMe is set to the "H" level. This causes signal DRe to be set to the "L" level. In amplifier 60o, because signals DRe and bCK are at the "L" level, a reset operation of latch circuit DL is initiated.

[0124] As shown in FIG. 11, since the odd-numbered bit data V1 of the signal DQ is at the "L" level, the transistors 107 of the amplifiers 60e and 60o are turned off.

[0125] In the amplifier 60e, as a result of receiving the "H" level even-bit data V0, the voltage at node ND1 drops faster than the voltage at node ND2. As a result, in the latch circuit DL, node ND1 is set to "L" level and node ND2 is set to "H" level. Therefore, the signal DOPe is set to "L" level. On the other hand, the signal DOMe is maintained at "H" level. As a result, the amplifier 60e outputs a "L" level signal DRe from the terminal R.

[0126] The amplifier 60o receives feedback of the even-bit data V0 captured by the amplifier 60e. More specifically, a low-level signal DOPe is input to the terminal DF of the amplifier 60o. This turns off the transistor 109. A high-level signal DOMe is input to the terminal bDF of the amplifier 60o. This turns on the transistor 110. This increases the voltage VREF in the amplifier 60o. Furthermore, the low-level signal DRe is input to the amplifier 60o, causing the OR circuit 112 to output a low-level signal. This turns on the transistors 101 and 104 of the amplifier 60o, and turns off the transistor 111. This causes the amplifier 60o to start resetting the latch circuit DL. This means that high-level voltages are applied to the nodes ND1 and ND2. However, at time t2, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPo is maintained at the “H” level and the signal DOMo is maintained at the “L” level, and therefore the signal DRo is maintained at the “L” level.

[0127] [Time t3] 8, at time t3, the reset operation of the latch circuit DL of the amplifier 60o is completed, and the amplifier 60o is placed in a reset state ("rst"). Therefore, the signals DOPo and DOMo are set to the "H" level. As a result, the signal DRo is set to the "H" level.

[0128] 12, in the amplifier 60o, the reset operation of the latch circuit DL is completed, and the nodes ND1 and ND2 are charged to the "H" level. That is, the signals DOPo and DOMo are set to the "H" level. As a result, the amplifier 60o outputs the "H" level signal DRo from the terminal R.

[0129] A high-level signal DOPo is input to the terminal DF of the amplifier 60e. This turns on the transistor 109. A high-level signal DOMo is input to the terminal bDF of the amplifier 60e. This turns on the transistor 110. A high-level signal DRo is input to the OR circuit 112 of the amplifier 60e. The OR circuit 112 continues to output a high-level signal.

[0130] [Time t4] 8, at time t4, signal CK falls from "H" level to "L" level, and signal bCK rises from "L" level to "H" level. The latch circuit DL of amplifier 60o is set to a latch state ("lat") based on the rising edge of signal bCK, and captures odd-numbered bit data V1 at "L" level. Based on the odd-numbered bit data V1, signals DOPo and DOMo begin to transition.

[0131] As shown in FIG. 13, an "H" level signal bCK is input to the OR circuit 112 of the amplifier 60o. As a result, the OR circuit 112 outputs an "H" level signal. The transistors 101 and 104 of the amplifier 60o are turned off, and the transistor 111 is turned on. This causes the latch circuit DL of the amplifier 60e to enter a latching state. The amplifier 60o captures the odd-numbered bit data V1.

[0132] The OR circuit 112 of the amplifier 60e receives the signal CK at the "L" level. Since the signal DRo is at the "H" level, the OR circuit 112 continues to output a signal at the "H" level.

[0133] [Time t5] As shown in FIG. 8, for example, assume that the even-numbered bit data V2 of the signal DQ is at the "L" level. At time t5, the logic levels of the signals DOPo and DOMo of the amplifier 60o are determined. In other words, the logic level of the odd-numbered bit data V1 is determined. Because the odd-numbered bit data V1 is at the "L" level, the signal DOPo is set to the "H" level, and the signal DOMo is set to the "L" level. This causes the signal DRo to be set to the "L" level. In the amplifier 60e, because the signals DRo and CK are at the "L" level, a reset operation of the latch circuit DL is initiated.

[0134] As shown in FIG. 14, since the even-numbered bit data V2 of the signal DQ is at the "L" level, the transistors 107 of the amplifiers 60e and 60o are turned off.

[0135] In the amplifier 60o, as a result of receiving the odd-bit data V1 at the "L" level, the voltage at node ND2 drops faster than the voltage at node ND1. As a result, in the latch circuit DL, node ND1 is set to the "H" level and node ND2 is set to the "L" level. Therefore, the signal DOPo is maintained at the "H" level. On the other hand, the signal DOMo is set to the "L" level. As a result, the amplifier 60o outputs the signal DRo at the "L" level from the terminal R.

[0136] The amplifier 60e receives feedback of the result of the amplifier 60o capturing the odd-numbered bit data V1. More specifically, a high-level signal DOPo is input to the terminal DF of the amplifier 60e. This turns on the transistor 109. A low-level signal DOMo is input to the terminal bDF of the amplifier 60e. This turns off the transistor 110. This causes the voltage VREF to drop in the amplifier 60e. Furthermore, in the amplifier 60e, the low-level signal DRo is input, causing the OR circuit 112 to output a low-level signal. This turns on the transistors 101 and 104 of the amplifier 60e, and turns off the transistor 111. This causes the amplifier 60e to start resetting the latch circuit DL. That is, a high-level voltage is applied to the nodes ND1 and ND2. However, at time t5, the reset operation of the latch circuit DL is not completed, so the signal DOPe is maintained at the “L” level and the signal DOMe is maintained at the “H” level, and therefore the signal DRe is maintained at the “L” level.

[0137] [Time t6] 8, at time t6, the reset operation of the latch circuit DL of the amplifier 60e is completed, and the amplifier 60e is placed in a reset state ("rst"). Therefore, the signals DOPe and DOMe are set to the "H" level. As a result, the signal DRe is set to the "H" level.

[0138] 15, in the amplifier 60e, the reset operation of the latch circuit DL is completed, and the nodes ND1 and ND2 are charged to the "H" level. That is, the signals DOPe and DOMe are set to the "H" level. As a result, the amplifier 60e outputs the "H" level signal DRe from the terminal R.

[0139] A high-level signal DOPe is input to the terminal DF of the amplifier 60o. This turns on the transistor 109. A high-level signal DOMe is input to the terminal bDF of the amplifier 60o. This turns on the transistor 110. A high-level signal DRe is input to the OR circuit 112 of the amplifier 60o. The OR circuit 112 continues to output a high-level signal.

[0140] [Time t7] 8, at time t7, signal CK rises from "L" level to "H" level, and signal bCK falls from "H" level to "L" level. The latch circuit DL of amplifier 60e is set to a latch state ("lat") based on the rising edge of signal CK, and captures even-numbered bit data V2 at "L" level. Based on the even-numbered bit data V2, signals DOPe and DOMe begin to transition.

[0141] As shown in FIG. 16, an "H" level signal CK is input to the OR circuit 112 of the amplifier 60e. As a result, the OR circuit 112 outputs an "H" level signal. The transistors 101 and 104 of the amplifier 60e are turned off, and the transistor 111 is turned on. This causes the latch circuit DL of the amplifier 60e to enter a latching state. The amplifier 60e captures the even-numbered bit data V2.

[0142] The OR circuit 112 of the amplifier 60o receives the signal bCK at the "L" level. Since the signal DRe is at the "H" level, the OR circuit 112 continues to output a signal at the "H" level.

[0143] [Time t8] As shown in FIG. 8, for example, assume that odd-numbered bit data V3 of signal DQ is at the "H" level. At time t8, the logic levels of signals DOPe and DOMe of amplifier 60e are determined. In other words, the logic level of even-numbered bit data V2 is determined. Because even-numbered bit data V2 is at the "L" level, signal DOPe is set to the "H" level, and signal DOMe is set to the "L" level. As a result, signal DRe is set to the "L" level. In amplifier 60o, because signals DRe and bCK are at the "L" level, a reset operation of latch circuit DL is initiated.

[0144] As shown in FIG. 17, since the odd-numbered bit data V3 of the signal DQ is at the "H" level, the transistors 107 of the amplifiers 60e and 60o are turned on.

[0145] In the amplifier 60e, as a result of receiving the "L" level even-bit data V2, the voltage at node ND2 drops faster than the voltage at node ND1. As a result, in the latch circuit DL, node ND1 is set to "H" level and node ND2 is set to "L" level. Therefore, the signal DOPe is maintained at "H" level. On the other hand, the signal DOMe is set to "L" level. As a result, the amplifier 60e outputs a "L" level signal DRe from the terminal R.

[0146] The amplifier 60o receives feedback of the even-bit data V2 captured by the amplifier 60e. More specifically, a high-level signal DOPe is input to the terminal DF of the amplifier 60o. This turns on the transistor 109. A low-level signal DOMe is input to the terminal bDF of the amplifier 60o. This turns off the transistor 110. This causes the voltage VREF to drop in the amplifier 60o. Furthermore, the low-level signal DRe is input to the amplifier 60o, causing the OR circuit 112 to output a low-level signal. This turns on the transistors 101 and 104 of the amplifier 60o, and turns off the transistor 111. This causes the amplifier 60o to start resetting the latch circuit DL. This means that high-level voltages are applied to the nodes ND1 and ND2. However, at time t8, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPo is maintained at the “H” level and the signal DOMo is maintained at the “L” level. Therefore, the signal DRo is maintained at the “L” level.

[0147] [Time t9] 8, at time t9, the reset operation of the latch circuit DL of the amplifier 60o is completed, and the amplifier 60o is placed in a reset state ("rst"). As a result, the signals DOPo and DOMo are set to the "H" level. As a result, the signal DRo is set to the "H" level.

[0148] 18, in the amplifier 60o, the reset operation of the latch circuit DL is completed, and the nodes ND1 and ND2 are charged to the "H" level. That is, the signals DOPo and DOMo are set to the "H" level. As a result, the amplifier 60o outputs the "H" level signal DRo from the terminal R.

[0149] A high-level signal DOPo is input to the terminal DF of the amplifier 60e. This turns on the transistor 109. A high-level signal DOMo is input to the terminal bDF of the amplifier 60e. This turns on the transistor 110. A high-level signal DRo is input to the OR circuit 112 of the amplifier 60e. The OR circuit 112 continues to output a high-level signal.

[0150] [Time t10] 8, at time t10, signal CK falls from "H" level to "L" level, and signal bCK rises from "L" level to "H" level. Based on the rising edge of signal bCK, latch circuit DL of amplifier 60o is set to a latch state ("lat") and captures odd-numbered bit data V3 at "H" level. Based on odd-numbered bit data V3, signals DOPo and DOMo begin to transition.

[0151] As shown in FIG. 19, an "H" level signal bCK is input to the OR circuit 112 of the amplifier 60o. As a result, the OR circuit 112 outputs an "H" level signal. The transistors 101 and 104 of the amplifier 60o are turned off, and the transistor 111 is turned on. This causes the latch circuit DL of the amplifier 60e to enter a latching state. The amplifier 60o captures odd-numbered bit data V3.

[0152] The OR circuit 112 of the amplifier 60e receives the signal CK at the "L" level. Since the signal DRo is at the "H" level, the OR circuit 112 continues to output a signal at the "H" level.

[0153] [Time t11] As shown in FIG. 8, for example, assume that the even-numbered bit data V4 of the signal DQ is at the "H" level. At time t11, the logic levels of the signals DOPo and DOMo of the amplifier 60o are determined. In other words, the logic level of the odd-numbered bit data V3 is determined. Because the odd-numbered bit data V3 is at the "H" level, the signal DOPo is set to the "L" level, and the signal DOMo is set to the "H" level. This causes the signal DRo to be set to the "L" level. In the amplifier 60e, because the signals DRo and CK are at the "L" level, a reset operation of the latch circuit DL is initiated.

[0154] As shown in FIG. 20, since the even-numbered bit data V4 of the signal DQ is at the "H" level, the transistors 107 of the amplifiers 60e and 60o are turned on.

[0155] In the amplifier 60o, as a result of receiving the "H" level odd-bit data V3, the voltage at node ND1 drops faster than the voltage at node ND2. As a result, in the latch circuit DL, node ND1 is set to "L" level and node ND2 is set to "H" level. Therefore, the signal DOPo is changed from "H" level to "L" level. On the other hand, the signal DOMo is maintained at "H" level. As a result, the amplifier 60o outputs the "H" level signal DRo from the terminal R.

[0156] The amplifier 60e receives feedback of the result of the amplifier 60o capturing the odd-numbered bit data V3. More specifically, a low-level signal DOPo is input to the terminal DF of the amplifier 60e, turning the transistor 109 off. A high-level signal DOMo is input to the terminal bDF of the amplifier 60e, turning the transistor 110 on. Therefore, the voltage VREF rises in the amplifier 60o. Furthermore, the low-level signal DRo input to the amplifier 60e causes the OR circuit 112 to output a low-level signal. This turns on the transistors 101 and 104 of the amplifier 60e, and turns off the transistor 111. This causes the amplifier 60e to start resetting the latch circuit DL. That is, a high-level voltage is applied to the nodes ND1 and ND2. However, at time t11, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPe is maintained at the “H” level and the signal DOMe is maintained at the “L” level, and therefore the signal DRe is maintained at the “L” level.

[0157] [Time t12] 8, at time t12, the reset operation of the latch circuit DL of the amplifier 60e is completed, and the amplifier 60e is placed in the reset state ("rst"). Therefore, the signals DOPe and DOMe are set to the "H" level. As a result, the signal DRe is set to the "H" level.

[0158] 21, in the amplifier 60e, the reset operation of the latch circuit DL is completed, and the nodes ND1 and ND2 are charged to the "H" level. That is, the signals DOPe and DOMe are set to the "H" level. As a result, the amplifier 60e outputs the "H" level signal DRe from the terminal R.

[0159] A high-level signal DOPe is input to the terminal DF of the amplifier 60o. This turns on the transistor 109. A high-level signal DOMe is input to the terminal bDF of the amplifier 60o. This turns on the transistor 110. A high-level signal DRe is input to the OR circuit 112 of the amplifier 60o. The OR circuit 112 continues to output a high-level signal.

[0160] [Time t13] 8, at time t13, signal CK rises from "L" level to "H" level, and signal bCK falls from "H" level to "L" level. Based on the rising edge of signal CK, latch circuit DL of amplifier 60e is set to a latch state ("lat") and captures even-numbered bit data V4 at "H" level. Based on the even-numbered bit data V4, signals DOPe and DOMe begin to transition.

[0161] 22, an "H" level signal CK is input to the OR circuit 112 of the amplifier 60e. As a result, the OR circuit 112 outputs an "H" level signal. The transistors 101 and 104 of the amplifier 60e are turned off, and the transistor 111 is turned on. As a result, the amplifier 60e captures the signal DQ.

[0162] The OR circuit 112 of the amplifier 60o receives the signal bCK at the "L" level. Since the signal DRe is at the "H" level, the OR circuit 112 continues to output a signal at the "H" level.

[0163] 1.3 Effects of this embodiment The configuration according to this embodiment makes it possible to provide a semiconductor memory device that can suppress an increase in chip area. This effect will be described in detail.

[0164] For example, DFE technology is known as one of the transmission compensation technologies for high-speed communications. DFE circuits that support DFE technology use 4-time interleaving, which divides the receive path into four phases with a 90-degree phase shift. The DFE circuit is configured to support four receive paths. As a result, the circuit area and power consumption of DFE circuits tend to increase.

[0165] In contrast, in the configuration according to this embodiment, the DFE circuit 50 includes two amplifiers 60 that support two-time interleaving. The amplifiers 60 are LT-SA circuits that include data input terminals DM and bDM, feedback input terminals DF and bDF, a latch control clock input terminal CL, a reset control clock input terminal CR, data output terminals Q and bQ, and a latch completion output terminal R.

[0166] The amplifier 60 can output a reset control clock signal (DRe or DRo) based on the state of the latch circuit DL from the terminal R. In other words, when the logic level of the signal DQ is determined in the latch circuit DL, the amplifier 60 can output a reset control clock signal notifying that fact. One amplifier 60 can receive a reset control clock signal output by the other amplifier 60 from the terminal CR. The amplifier 60 can reset its internal latch circuit DL based on the received reset control clock signal. In other words, one amplifier 60 can perform a reset operation of the latch circuit DL based on the output data of the other amplifier 60. This allows the DFE circuit 50 to realize a DFE that applies two-time interleaving. By applying two-time interleaving, the DFE circuit 50 can suppress increases in circuit area and power consumption. Therefore, the semiconductor memory device can suppress increases in chip area. Furthermore, the semiconductor memory device can suppress increases in power consumption.

[0167] Furthermore, with the configuration according to this embodiment, one amplifier 60 can execute a reset operation of the latch circuit DL based on the output data of the other amplifier 60. Therefore, the reset operation can be performed faster than in the case of 4-time interleaving, in which the reset operation of the latch circuit is executed in synchronization with a clock signal. This allows the semiconductor memory device to increase the communication speed with the memory controller.

[0168] Furthermore, in the configuration according to this embodiment, the amplifier 60 receives one bit of data of the signal DQ from the terminal DM. At this time, one amplifier 60 can feed back the output signal of the other amplifier 60 (output data corresponding to the bit data received by the other amplifier 60 at the immediately preceding timing) via the terminals DF and bDF. This allows the amplifier 60 to vary the voltage VREF relative to the signal DQ. This makes it possible to suppress erroneous determination of the logic level of the signal DQ.

[0169] 1.4 Modification of the first embodiment 1.4.1 Amplifier Configuration Next, a modification of the first embodiment will be described. In this example, the configuration of an amplifier different from that of the first embodiment will be described using FIG. 23. FIG. 23 is a circuit diagram of amplifier 60e. The following description will focus on the differences from the first embodiment. Note that although the following description will focus on amplifier 60e, amplifier 60o has the same configuration as amplifier 60e.

[0170] 23, the amplifier 60e includes PMOS transistors 101 to 104, 121, and 122, NMOS transistors 105 to 111, and an XNOR circuit 113. The amplifier 60e of this example does not include the OR circuit 112 of the amplifier 60e described with reference to FIG. 7 of the first embodiment. Instead, the amplifier 60e of this example additionally includes transistors 121, 122, and 123. The transistors 121, 122, and 123 implement the same function as the OR circuit 112.

[0171] A voltage VDD is applied to one end of the transistor 121. The other end of the transistor 121 is connected to a node ND10. The gate of the transistor 121 is connected to the terminal CR.

[0172] A voltage VDD is applied to one end of the transistor 122. The other end of the transistor 122 is connected to a node ND10. The gate of the transistor 122 is connected to the terminal CR.

[0173] One end of the transistor 123 is connected to the node ND5, the other end of the transistor 123 is grounded, and the gate of the transistor 123 is connected to the terminal CR.

[0174] In this example, one ends of the transistors 101 and 104 are connected to a node ND10. The other configuration is the same as that of the first embodiment shown in FIG.

[0175] 1.4.2 Effects of the Modification of the First Embodiment The configuration according to this modification provides the same effects as those of the first embodiment.

[0176] Furthermore, with the configuration according to this modification, the amplifier 60 can generate a reset signal for the latch circuit DL without providing the OR circuit 112. Since the OR circuit 112 is not sandwiched between the terminal CL and the transistors 101 and 104, the amplifier 60 can suppress delays caused by the OR circuit 112 and operate at higher speeds.

[0177] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, the configurations of the DFE circuit 50 and the latch circuit 52 that are different from those of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0178] 2.1 Configuration of DFE circuit and latch circuit First, an example of the configuration of the DFE circuit 50 and the latch circuit 52 will be described with reference to Fig. 24. Fig. 24 is a block diagram of the DFE circuit 50 and the latch circuit 52.

[0179] As shown in FIG. 24, the DFE circuit 50 includes two amplifiers 62e and 62o. The amplifiers 62e and 62o have the same configuration. As in the first embodiment, the DFE circuit 50 supports two-time interleaving. For example, the amplifier 62e supports even-numbered bit data of the signal DQ. On the other hand, the amplifier 62o supports odd-numbered bit data of the signal DQ. Hereinafter, when there is no need to specify either the amplifier 62e or 62o, it will be referred to as the amplifier 62.

[0180] The amplifier 62 is a DTSA (Double-tail Latch-type Voltage Sense Amplifier) ​​circuit that includes data input terminals DM and bDM, feedback input terminals DF and bDF, a latch control clock input terminal CL, reset control clock input terminals CR and bCR, data output terminals Q and bQ, and latch input signal output terminals DI and bDI.

[0181] A signal DQ is input to the terminal DM, and a voltage VREF is input to the terminal bDM.

[0182] The output signal of one amplifier 62 is input (feedback) to the terminals DF and bDF of the other amplifier 62. For example, when one amplifier 62 is amplifier 62e, the other amplifier 62 is amplifier 62o. Furthermore, when one amplifier 62 is amplifier 62o, the other amplifier 62 is amplifier 62e. More specifically, when amplifier 62e receives the kth bit data of signal DQ, output signals DOPo and DOMo corresponding to the (k-1)th bit data of signal DQ received by amplifier 62o at the immediately previous timing are fed back to the terminals DF and bDF of amplifier 62e, respectively. The terminals DF and bDF of one amplifier 62 are connected to the terminals Q and bQ of the other amplifier 62, respectively. More specifically, the signal DOPo is input to the terminal DF of amplifier 62e from the terminal Q of amplifier 62o. The signal DOMo is input to the terminal bDF of amplifier 62e from the terminal bQ of amplifier 62o. A terminal DF of the amplifier 62o receives a signal DOPe from a terminal Q of the amplifier 62e. A terminal bDF of the amplifier 62o receives a signal DOMe from a terminal bQ of the amplifier 62e.

[0183] The amplifier 62e has a terminal CL that receives the signal CK, and the amplifier 62o has a terminal CL that receives the signal bCK.

[0184] The terminals CR and bCR of one amplifier 62 receive a latch input signal output from the terminals DI and bDI of the other amplifier 62. The latch input signal is a signal input to the latch circuit DL of the amplifier 62. The terminals CR and bCR of one amplifier 62 are connected to the terminals DI and bDI of the other amplifier 62, respectively. More specifically, the terminals CR and bCR of amplifier 62e are connected to the terminals DI and bDI of amplifier 62o, respectively. The terminals CR and bCR of amplifier 62o are connected to the terminals DI and bDI of amplifier 62e, respectively. Hereinafter, the latch input signals of amplifier 62o input to the terminals CR and bCR of amplifier 62e will be referred to as signals DIPo and DIMo, respectively. Furthermore, the latch input signals of amplifier 62e input to the terminals CR and bCR of amplifier 62o will be referred to as signals DIPe and DIMe, respectively.

[0185] The amplifier 62 outputs a non-inverted version of the signal DQ from terminals Q and bQ. More specifically, when even-bit data of "H" level is input to terminal DM, the amplifier 62e outputs a signal DOPe of "H" level from terminal Q and a signal DOMe of "L" level from terminal bQ. When even-bit data of "L" level is input to terminal DM, the amplifier 62e outputs a signal DOPe of "L" level from terminal Q and a signal DOMe of "H" level from terminal bQ. Similarly, when odd-bit data of "H" level is input to terminal DM, the amplifier 62o outputs a signal DOPo of "H" level from terminal Q and a signal DOMo of "L" level from terminal bQ. When odd-bit data of "L" level is input to terminal DM, the amplifier 62o outputs a signal DOPo of "L" level from terminal Q and a signal DOMo of "H" level from terminal bQ.

[0186] Next, the latch circuit 52 will be described. The latch circuit 52 of this embodiment includes two SR latch circuits 72e and 72o. The SR latch circuits 72e and 72o have the same configuration. Hereinafter, unless otherwise specified, the SR latch circuits 72e and 72o will be referred to as the SR latch circuit 72. The SR latch circuit 72e temporarily stores the output signal of the amplifier 62e. The SR latch circuit 72o temporarily stores the output signal of the amplifier 62o. The SR latch circuit 72 includes a signal input terminal S, a reset signal input terminal R, and an output terminal Q. Note that the SR latch circuit 72 may also include an inverted output terminal bQ.

[0187] When an "H" level signal is input to terminal S and an "L" level signal is input to terminal R, the SR latch circuit 72 outputs an "H" level signal to terminal Q. When an "L" level signal is input to terminal S and an "H" level signal is input to terminal R, the SR latch circuit 72 outputs an "L" level signal to terminal Q. Furthermore, the SR latch circuit 72 maintains the previous output state while "L" level signals are input to terminals S and R.

[0188] The SR latch circuit 72e receives the signal DOPe from the amplifier 62e at its terminal S. The SR latch circuit 72e receives the signal DOMe from the amplifier 62e at its terminal R. The SR latch circuit 72e outputs a signal DQe, which is even-numbered bit data of the signal DQ, from its terminal Q.

[0189] The signal DOPo from the amplifier 62o is input to a terminal S of the SR latch circuit 72o. The signal DOMo from the amplifier 62o is input to a terminal R of the SR latch circuit 72o. The SR latch circuit 72o outputs a signal DQo, which is odd-numbered bit data of the signal DQ, from a terminal Q.

[0190] 2.2 DFE circuit diagram Next, an example of a circuit diagram of the DFE circuit 50 will be described with reference to Figures 25 and 26. Figure 25 is a circuit diagram of the DFE circuit 50. Figure 26 is a circuit diagram of an amplifier 62e.

[0191] As shown in Fig. 25, the amplifiers 62e and 62o have the same circuit configuration. The following description focuses on the amplifier 62e.

[0192] As shown in FIG. 26, the amplifier 62e includes an input section 80, a latch section 81, and a negative OR (NOR) circuit 220.

[0193] The input section 80 compares the voltage value of the signal DQ with the voltage VREF. As a result of the comparison, the input section 80 transmits signals DIPe and DIMe to the latch section 81. The input section 80 also outputs the signals DIPe and DIMe from terminals DI and bDI, respectively.

[0194] The latch unit 81 temporarily stores data based on the signals DIPe and DIMe. The latch unit 81 includes a latch circuit DL. The latch circuit DL is reset based on the output signal of the NOR circuit 220. The latch unit 81 outputs signals DOPe and DOMe from terminals Q and bQ, respectively.

[0195] Next, a description will be given of the internal configuration of the input section 80. The input section 80 includes PMOS transistors 201 and 202, and NMOS transistors 203-207.

[0196] A voltage VDD is applied to one end of the transistor 201. The other end of the transistor 201 is connected to a node ND21. The gate of the transistor 201 is connected to the terminal CL.

[0197] A voltage VDD is applied to one end of the transistor 202. The other end of the transistor 202 is connected to a node ND22. The gate of the transistor 202 is connected to the terminal CL.

[0198] One end of the transistor 203 is connected to the node ND21, the other end of the transistor 203 is connected to the node ND23, and the gate of the transistor 203 is connected to the terminal DM.

[0199] One end of the transistor 204 is connected to the node ND22, the other end of the transistor 204 is connected to the node ND23, and the gate of the transistor 204 is connected to the terminal bDM.

[0200] One end of the transistor 205 is connected to the node ND21, the other end of the transistor 205 is connected to the node ND23, and the gate of the transistor 205 is connected to the terminal bDF.

[0201] Transistor 205 is connected in parallel with transistor 203. The drive capability of transistor 205 is lower than that of transistor 203. For example, when transistors 203 and 205 are in the on state, the current flowing through transistor 205 is smaller than the current flowing through transistor 203. For example, transistor 203 has a structure in which multiple transistors (e.g., 10) of the same size as transistor 205 are connected in parallel.

[0202] One end of the transistor 206 is connected to the node ND22. The other end of the transistor 204 is connected to the node ND23. The gate of the transistor 204 is connected to the terminal DF.

[0203] Transistor 206 is connected in parallel with transistor 204. The drive capability of transistor 206 is lower than that of transistor 204. For example, when transistors 204 and 206 are in the on state, the current flowing through transistor 206 is smaller than the current flowing through transistor 204. For example, transistor 204 has a structure in which multiple transistors (e.g., 10) of the same size as transistor 206 are connected in parallel.

[0204] Similar to the transistors 109 and 110 described in the first embodiment, the transistors 205 and 206 function to feed back the output signal of the other amplifier 62 to the input signal of one amplifier 62. The operation of the transistors 205 and 206 produces the same effect as when the voltage value of the voltage VREF fluctuates with respect to the voltage value of the signal DQ. For example, when the transistor 205 is on and the transistor 206 is off, the voltage VREF decreases. On the other hand, when the transistor 205 is off and the transistor 206 is on, the voltage VREF increases.

[0205] One end of the transistor 207 is connected to the node ND23, the other end of the transistor 207 is grounded, and the gate of the transistor 207 is connected to the terminal CL.

[0206] The input unit 80 outputs the voltage at the node ND21 from the terminal DI as a signal DIPe, and outputs the voltage at the node ND22 from the terminal bDI as a signal DIMe.

[0207] Next, a description will be given of the internal configuration of the latch unit 81. The latch unit 81 includes PMOS transistors 208-211 and NMOS transistors 212-217.

[0208] A voltage VDD is applied to one end of the transistor 208. The other end of the transistor 208 is connected to a node ND24. The gate of the transistor 208 is connected to a node ND21. In other words, a signal DIPe is input to the gate of the transistor 208.

[0209] A voltage VDD is applied to one end of the transistor 209. The other end of the transistor 209 is connected to a node ND25. The gate of the transistor 209 is connected to a node ND22. In other words, the signal DIMe is input to the gate of the transistor 209.

[0210] One end of the transistor 210 is connected to a node ND24, the other end of the transistor 210 is connected to a node ND26, and the gate of the transistor 210 is connected to a node ND27.

[0211] One end of the transistor 211 is connected to a node ND25, the other end of the transistor 211 is connected to a node ND27, and the gate of the transistor 211 is connected to a node ND26.

[0212] One end of the transistor 212 is connected to a node ND26, the other end of the transistor 212 is grounded, and the gate of the transistor 212 is connected to a node ND27.

[0213] One end of the transistor 213 is connected to the node ND27, the other end of the transistor 213 is grounded, and the gate of the transistor 213 is connected to the node ND26.

[0214] The transistors 210 to 213 form a latch circuit DL. More specifically, the transistors 210 and 212 form a first inverter. The transistors 211 and 213 form a second inverter. The output of the first inverter and the input of the second inverter (node ​​ND26) are connected to a terminal Q. The input of the first inverter and the output of the second inverter (node ​​ND27) are connected to a terminal bQ.

[0215] The transistor 214 has one end connected to the node ND24, the other end connected to ground, and a gate connected to the output terminal of the NOR circuit 220.

[0216] The transistor 215 has one end connected to a node ND25 and the other end grounded. The gate of the transistor 215 is connected to the output terminal of the NOR circuit 220.

[0217] The transistor 216 has one end connected to the node ND26 and the other end grounded. The transistor 216 has a gate connected to the output terminal of the NOR circuit 220.

[0218] The transistor 217 has one end connected to a node ND27 and the other end grounded. The transistor 217 has a gate connected to the output terminal of the NOR circuit 220.

[0219] The transistors 214 to 217 function as a reset circuit for the latch circuit DL. For example, when the output signal of the NOR circuit 220 is set to the "H" level, the transistors 214 to 217 are turned on. As a result, the nodes ND26 and ND27 are charged to the "H" level. That is, the latch circuit DL is set to the reset state.

[0220] The NOR circuit 220 includes three input terminals and one output terminal. The three input terminals are connected to terminals CL, CR, and bCR, respectively. The NOR circuit 220 outputs a signal at a high level when the signals input to terminals CL, CR, and bCR are at a low level. The NOR circuit 220 outputs a signal at a low level when at least one of the signals input to terminals CL, CR, and bCR is at a high level. The signal output by the NOR circuit 220 of the amplifier 62e corresponds to the signal DRo in the first embodiment. The signal output by the NOR circuit 220 of the amplifier 62o corresponds to the signal DRe in the first embodiment.

[0221] The operation of the amplifier 62e will be briefly described. When the signal CK rises from the "L" level to the "H" level, the input section 80 of the amplifier 62e turns off the transistors 201 and 202 and turns on the transistor 207. In this state, the amplifier 62e receives the signal DQ. Because the transistors 201 and 202 are off, a difference occurs between the rate at which the voltage of the node ND21 drops from the "H" level to the "L" level and the rate at which the voltage of the node ND22 drops from the "H" level to the "L" level, depending on the states of the transistors 203 to 206. For example, when the transistor 203 is on, the voltage of the node ND21 drops faster than the voltage of the node ND22. On the other hand, when the transistor 203 is off, the voltage of the node ND22 drops faster than the voltage of the node ND21. In other words, when signal DQ is at "H" level, signal DIPe transitions from "H" level to "L" level before signal DIMe transitions from "H" level to "L" level. On the other hand, when signal DQ is at "L" level, signal DIMe transitions from "H" level to "L" level before signal DIPe transitions from "H" level to "L" level.

[0222] When the NOR circuit 220 outputs a signal DRo at an "L" level, the transistors 214 to 217 in the latch unit 81 are turned off. In this state, if the signal DQ is at an "H" level, the signal DIPe transitions to an "L" level before the signal DIMe. Then, the transistor 208 is turned on before the transistor 209. As a result, in the latch unit 81, the node ND26 is set to an "H" level and the node ND27 is set to an "L" level. As a result, the signal DOPe is set to an "H" level and the signal DOMe is set to an "L" level. On the other hand, if the signal DQ is at an "L" level, the signal DIMe transitions to an "L" level before the signal DIPe. Then, the transistor 209 is turned on before the transistor 208. As a result, in the latch unit 81, the node ND26 is set to an "L" level and the node ND27 is set to an "H" level. As a result, the signal DOPe is set to the "L" level, and the signal DOMe is set to the "H" level.

[0223] 2.3 Example of DFE circuit operation Next, an example of the operation of the DFE circuit 50 will be described with reference to Figs. 27 to 41. Fig. 27 is a timing chart of various signals in the DFE circuit 50. Figs. 28 to 41 are state diagrams of the DFE circuit at each time in the timing chart shown in Fig. 27. In this example, a case will be described where the input signal DQ is data. Note that the following description will focus on the parts where the signal and transistor states change at each time in the timing chart.

[0224] [Time t0] 27, at time t0 before the signal DQ is input, the signal CK is set to the "L" level and the signal bCK is set to the "H" level. For example, the amplifier 62e outputs the signals DIPe and DIMe at the "H" level and the signals DOPe and DOMe at the "L" level. For example, the amplifier 62o outputs the signals DIPo and DIMo at the "L" level, the signal DOPo at the "H" level, and DOMo at the "L" level.

[0225] The NOR circuit 220 of the amplifier 62e receives the signal CK at a low level and the signals DIPo and DIMo at a low level. As a result, the NOR circuit 220 of the amplifier 62e outputs a signal DRo at a high level. As a result, the latch circuit DL of the amplifier 62e (reference symbol "Even" in FIG. 27) is set to a reset state ("rst"). Furthermore, the NOR circuit 220 of the amplifier 62o receives the signal bCK at a high level and the signals DIPe and DIMe at a high level. As a result, the NOR circuit 220 of the amplifier 62o outputs a signal DRe at a low level. As a result, the latch circuit DL of the amplifier 62e (reference symbol "Odd" in FIG. 27) is set to a latch state ("lat").

[0226] 28, since the signal DQ is at the “H” level, the transistors 203 of the amplifiers 62e and 62o are turned on. The transistors 204 of the amplifiers 62e and 62o are turned on relatively weakly and clamped by the voltage VREF.

[0227] A high-level signal DOPo is input to the terminal DF of the amplifier 62e. This turns on the transistor 206. A low-level signal DOMo is input to the terminal bDF of the amplifier 62e. This turns off the transistor 205. This increases the voltage VREF in the amplifier 62e. Because the signal CK is low, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. This causes the input unit 80 to output high-level signals DIPe and DIMe from the terminals DI and bDI, respectively. The NOR circuit 220 of the amplifier 62e receives a low-level signal CK from the terminal CL, a low-level signal DIPo from the terminal CR, and a low-level signal DIMo from the terminal bCR. This causes the NOR circuit 220 to output a high-level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned on. This puts the latch unit 81 into a reset state. Furthermore, the latch unit 81 receives "H" level signals DIPe and DIMe. This puts the transistors 208 and 209 into an off state. The nodes ND26 and ND27 of the latch unit 81 are discharged. This causes the latch unit 81 to output "L" level signals DOPe and DOMe from the terminals Q and bQ, respectively.

[0228] A low-level signal DOPe is input to the terminal DF of the amplifier 62o. This turns off the transistor 206. A low-level signal DOMe is input to the terminal bDF of the amplifier 62o. This turns off the transistor 205. Because the signal bCK is high, the transistors 201 and 202 of the amplifier 62o are off, and the transistor 207 is on. This causes the input unit 80 to output low-level signals DIPo and DIMo from the terminals DI and bDI, respectively. The NOR circuit 220 of the amplifier 62o receives a high-level signal bCK from the terminal CL, a high-level signal DIPe from the terminal CR, and a high-level signal DIMe from the terminal bCR. This causes the NOR circuit 220 to output a low-level signal DRe. In the latch unit 81, the transistors 214 to 217 are off. As a result, the latch circuit DL of the latch unit 81 is put into a latching state. Furthermore, the latch unit 81 receives the signals DIPo and DIMo at an "L" level. As a result, the transistors 208 and 209 are put into an ON state. For example, when the signal DQ is at an "H" level, the latch unit 81 outputs the signal DOPo at an "H" level from the terminal Q and outputs the signal DOMo at an "L" level from the terminal bQ.

[0229] [Time t1] 27, for example, assume that the even-numbered bit data V0 of the signal DQ is at the "H" level. At time t1, the signal CK rises from the "L" level to the "H" level, and the signal bCK falls from the "H" level to the "L" level. The amplifier 62e is set to a latch state ("lat") based on the rising edge of the signal CK. The signals DIPe, DIMe, DOPe, and DOMe of the amplifier 62e begin to transition based on the even-numbered bit data V0. In the amplifier 62o, the signals DIPo and DIMo are set to the "H" level based on the falling edge of the signal bCK.

[0230] As shown in FIG. 29, since the even-numbered bit data V0 of the signal DQ is at the "H" level, the transistors 203 of the amplifiers 62e and 62o are turned on.

[0231] An "H" level signal CK is input to the amplifier 62e. As a result, the transistors 201 and 202 of the amplifier 62e are turned off, and the transistor 207 is turned on. The signals DIPe and DIMe begin to transition from "H" level to "L" level. The NOR circuit 220 of the amplifier 62e receives an "H" level signal CK from the terminal CL, an "H" level signal DIPo from the terminal CR, and an "H" level signal DIMo from the terminal bCR. As a result, the NOR circuit 220 outputs an "L" level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned off. As a result, the latch circuit DL of the latch unit 81 is in a latched state. Furthermore, the "H" level signals DIPe and DIMe are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Therefore, the latch section 81 continues to output the signals DOPe and DOMe at the "L" level from the terminals Q and bQ, respectively, from the time t0.

[0232] An "L" level signal bCK is input to the amplifier 62o. As a result, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. The input unit 80 outputs "H" level signals DIPo and DIMo. The NOR circuit 220 of the amplifier 62o receives an "L" level signal bCK from the terminal CL, an "H" level signal DIPe from the terminal CR, and an "H" level signal DIMe from the terminal bCR. As a result, the NOR circuit 220 outputs an "L" level signal DRe. Furthermore, the "H" level signals DIPo and DIMo are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Since the latch unit 81 maintains the latched state, it outputs an "H" level signal DOPo from the terminal Q and outputs an "L" level signal DOMo from the terminal bQ.

[0233] [Time t2] As shown in FIG. 27, at time t2, the logic levels of signals DOPe and DOMe are determined based on the voltage difference between signals DIPe and DIMe of amplifier 62e, i.e., the difference in the transition speed from "H" level to "L" level. In other words, the logic level of even-numbered bit data V0 is determined. Amplifier 62e outputs signal DOPe at "H" level and signal DOMe at "L" level. In amplifier 62o, signal DRe is set to "H" level. This initiates a reset operation in amplifier 62o.

[0234] 30, in the amplifier 62e, the signal DIPe transitions to the "L" level before the signal DIMe. Therefore, the transistor 208 is turned on before the transistor 209. As a result, in the latch unit 81, the node ND26 is set to the "H" level and the node ND27 is set to the "L" level. The signal DOPe transitions from the "L" level to the "H" level, and the signal DOMe is maintained at the "L" level. In other words, the amplifier 62e takes in the even-numbered bit data V0 at the "H" level, and as a result, outputs the signal DOPe at the "H" level and the signal DOMe at the "L" level.

[0235] The amplifier 62o receives feedback of the even-numbered bit data V0 captured by the amplifier 62e. More specifically, a high-level signal DOPe is input to the terminal DF of the amplifier 62o. This turns on the transistor 206. A low-level signal DOMe is input to the terminal bDF of the amplifier 62o. This turns off the transistor 205. This increases the voltage VREF in the amplifier 62o. Low-level signals bCK, DIPe, and DIMe are input to the NOR circuit 220 of the amplifier 62o. As a result, the NOR circuit 220 of the amplifier 62o outputs a high-level signal DRe. In the latch unit 81, the transistors 214 to 217 are turned on. The amplifier 62o starts resetting the latch circuit DL. This starts discharging the nodes ND26 and ND27. The NOR circuit 220 of the amplifier 62o can output a high-level signal before the logical levels of the signals DOPe and DOMe are determined in the amplifier 62e. In other words, the amplifier 62o can start a reset operation before the logical level of the signal DQ is determined in the amplifier 62e. However, at time t2, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPo is maintained at high level and the signal DOMo is maintained at low level.

[0236] [Time t3] 27, for example, assume that odd-numbered bit data V1 of signal DQ is at the "L" level. At time t3, the reset operation of latch circuit DL of amplifier 62o is completed, and amplifier 62o is set to the reset state ("rst"). Therefore, signals DOPo and DOMo are set to the "L" level.

[0237] As shown in FIG. 31, since the odd-numbered bit data V1 of the signal DQ is at the "L" level, the transistors 203 of the amplifiers 62e and 62o are turned off.

[0238] In the amplifier 62o, the reset operation of the latch circuit DL is completed, and the nodes ND26 and ND27 are set to the "L" level. That is, the amplifier 62o outputs the "L" level signals DOPo and DOMo.

[0239] A low-level signal DOPo is input to the terminal DF of the amplifier 62e. This turns off the transistor 206. A low-level signal DOMo is input to the terminal bDF of the amplifier 62e. This turns off the transistor 205. High-level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e. The NOR circuit 220 of the amplifier 62e continues to output a low-level signal DRo.

[0240] [Time t4] As shown in FIG. 27, at time t4, the signal CK falls from the "H" level to the "L" level, and the signal bCK rises from the "L" level to the "H" level. In the amplifier 62e, the signals DIPe and DIMe are set to the "H" level based on the falling edge of the signal CK. The amplifier 62o is set to the latch state ("lat") based on the rising edge of the signal bCK. Based on the odd-numbered bit data V1, the signals DIPo, DIMo, DOPo, and DOMo of the amplifier 62o begin to transition. In the amplifier 62e, the signals DIPe and DIMe are set to the "H" level based on the falling edge of the signal CK.

[0241] As shown in FIG. 32, a signal CK of "L" level is input to the amplifier 62e. Therefore, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. The input unit 80 outputs signals DIPe and DIMe of "H" level. The NOR circuit 220 of the amplifier 62e is input with the signal CK of "L" level and the signals DIPo and DIMo of "H" level. Therefore, the NOR circuit 220 of the amplifier 62e continues to output a signal DRo of "L" level. Furthermore, the latch unit 81 is input with the signals DIPe and DIMe of "H" level. Therefore, the transistors 208 and 209 are turned off. Since the latch unit 81 maintains the latched state, it outputs a signal DOPe of "H" level from the terminal Q and outputs a signal DOMe of "L" level from the terminal bQ.

[0242] The amplifier 62o receives an "H" level signal bCK. As a result, the transistors 201 and 202 of the amplifier 62o are turned off, and the transistor 207 is turned on. The signals DIPo and DIMo begin to transition from "H" level to "L" level. The NOR circuit 220 of the amplifier 62o receives "H" level signals bCK, DIPe, and DIMe. As a result, the NOR circuit 220 outputs an "L" level signal DRe. In the latch unit 81, the transistors 214 to 217 are turned off. As a result, the latch circuit DL of the latch unit 81 is in a latched state. Furthermore, the latch unit 81 receives "H" level signals DIPo and DIMo. As a result, the transistors 208 and 209 are turned off. As a result, the latch unit 81 continues to output "L" level signals DOPo and DOMo from the terminals Q and bQ, respectively.

[0243] [Time t5] As shown in FIG. 27, at time t5, the logical levels of signals DOPo and DOMo are determined based on the voltage difference between signals DIPo and DIMo of amplifier 62o, i.e., the difference in the transition speed from "H" level to "L" level. In other words, the logical level of odd-numbered bit data V1 is determined. Signal DOPo is set to "L" level, and signal DOMo is set to "H" level. Therefore, in amplifier 62e, signal DRo is set to "H" level. This initiates a reset operation in amplifier 62e.

[0244] 33, in the amplifier 62o, the signal DIMo transitions to the "L" level before the signal DIPo, and therefore the transistor 209 is turned on before the transistor 208. As a result, in the latch unit 81, the node ND26 is set to the "L" level and the node ND27 is set to the "H" level. As a result, the signal DOPo is maintained at the "L" level, and the signal DOMo transitions from the "L" level to the "H" level. In other words, the amplifier 62o takes in the odd-numbered bit data V1 at the "L" level, and as a result outputs the signal DOPo at the "L" level and the signal DOMo at the "H" level.

[0245] The amplifier 62e receives feedback of the result of the amplifier 62o capturing the odd-numbered bit data V1. More specifically, a low-level signal DOPo is input to the terminal DF of the amplifier 62e. This turns off the transistor 206. A high-level signal DOMo is input to the terminal bDF of the amplifier 62e. This turns on the transistor 205. This causes the voltage VREF to drop in the amplifier 62e. The low-level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e. As a result, the NOR circuit 220 of the amplifier 62e outputs a high-level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned on. The amplifier 62e starts resetting the latch circuit DL. That is, the NOR circuit 220 of the amplifier 62e can output a high-level signal before the logic levels of the signals DOPo and DOMo are determined in the amplifier 62o. In other words, amplifier 62e can start the reset operation before the logical level of signal DQ is determined in amplifier 62o. However, at time t5, the reset operation of latch circuit DL is not completed, so signal DOPe is maintained at the “H” level and signal DOMe is maintained at the “L” level.

[0246] [Time t6] 27, for example, assume that the even-numbered bit data V2 of the signal DQ is at the "L" level. At time t6, the reset operation of the latch circuit DL of the amplifier 62e is completed, and the amplifier 62e is set to the reset state ("rst"). Therefore, the signals DOPe and DOMe are set to the "L" level.

[0247] As shown in FIG. 34, since the even-numbered bit data V2 of the signal DQ is at the "L" level, the transistors 203 of the amplifiers 62e and 62o are turned off.

[0248] In the amplifier 62e, the reset operation of the latch circuit DL is completed, and the nodes ND26 and ND27 are set to the "L" level. That is, the amplifier 62e outputs the "L" level signals DOPe and DOMe.

[0249] A low-level signal DOPe is input to the terminal DF of the amplifier 62o. This turns off the transistor 206. A low-level signal DOMe is input to the terminal bDF of the amplifier 62o. This turns off the transistor 205. High-level signals bCK, DIPe, and DIMe are input to the NOR circuit 220 of the amplifier 62o. The NOR circuit 220 of the amplifier 62o continues to output a low-level signal.

[0250] [Time t7] As shown in FIG. 27, at time t7, signal CK rises from "L" level to "H" level, and signal bCK falls from "H" level to "L" level. The amplifier 62e is set to a latch state ("lat") based on the rising edge of signal CK. Based on even-numbered bit data V2, the signals DIPe, DIMe, DOPe, and DOMe of the amplifier 62e begin to transition. In the amplifier 62o, the signals DIPo and DIMo are set to "H" level based on the falling edge of signal bCK.

[0251] As shown in FIG. 35, an "H" level signal CK is input to the amplifier 62e. As a result, the transistors 201 and 202 of the amplifier 62e are turned off, and the transistor 207 is turned on. The signals DIPe and DIMe begin to transition from "H" level to "L" level. The "H" level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e. As a result, the NOR circuit 220 outputs an "L" level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned off. As a result, the latch circuit DL of the latch unit 81 is in a latched state. Furthermore, the "H" level signals DIPe and DIMe are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Following time t6, the latch unit 81 outputs "L" level signals DOPe and DOMe from the terminals Q and bQ, respectively.

[0252] An "L" level signal bCK is input to the amplifier 62o. As a result, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. The input unit 80 outputs "H" level signals DIPo and DIMo. The "L" level signal bCK and the "H" level signals DIPe and DIMe are input to the NOR circuit 220 of the amplifier 62o. As a result, the NOR circuit 220 outputs an "L" level signal DRe. Furthermore, "H" level signals DIPo and DIMo are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Since the latch unit 81 maintains the latched state, it outputs an "L" level signal DOPo from the terminal Q and outputs an "H" level signal DOMo from the terminal bQ.

[0253] [Time t8] As shown in FIG. 27, at time t8, the logic levels of signals DOPe and DOMe are determined based on the voltage difference between signals DIPe and DIMe of amplifier 62e, i.e., the difference in the transition speed from "H" level to "L" level. In other words, the logic level of even-numbered bit data V2 is determined. Signal DOPe is set to "L" level, and signal DOMe is set to "H" level. In amplifier 62o, signal DRe is set to "H" level. This initiates a reset operation in amplifier 62o.

[0254] 36, in the amplifier 62e, the signal DIMe transitions to the "L" level before the signal DIPe. Therefore, the transistor 209 is turned on before the transistor 208. As a result, in the latch unit 81, the node ND26 is set to the "L" level and the node ND27 is set to the "H" level. The signal DOPe is maintained at the "L" level, and the signal DOMe transitions from the "L" level to the "H" level. In other words, the amplifier 62e takes in the even-numbered bit data V2 at the "L" level, and as a result, outputs the signal DOPe at the "L" level and the signal DOMe at the "H" level.

[0255] The amplifier 62o receives feedback of the result of the amplifier 62e capturing the even-numbered bit data V2. More specifically, a low-level signal DOPe is input to the terminal DF of the amplifier 62o. This turns off the transistor 206. A high-level signal DOMe is input to the terminal bDF of the amplifier 62o. This turns on the transistor 205. This causes the voltage VREF to decrease in the amplifier 62o. The low-level signals bCK, DIPe, and DIMe are input to the NOR circuit 220 of the amplifier 62o. As a result, the NOR circuit 220 of the amplifier 62o outputs a high-level signal DRe. In the latch unit 81, the transistors 214 to 217 are turned on. The amplifier 62o starts a reset operation of the latch circuit DL. However, at time t8, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPo is maintained at the "L" level and the signal DOMo is maintained at the "H" level, and therefore, in the amplifier 62e, the signal DRo is maintained at the "L" level.

[0256] [Time t9] 27, for example, assume that odd-numbered bit data V3 of signal DQ is at the "H" level. At time t9, the reset operation of latch circuit DL of amplifier 62o is completed, and amplifier 62o is set to the reset state ("rst"). Therefore, signals DOPo and DOMo are set to the "L" level.

[0257] As shown in FIG. 37, since the odd-numbered bit data V3 of the signal DQ is at the "H" level, the transistors 203 of the amplifiers 62e and 62o are turned on.

[0258] In the amplifier 62o, the reset operation of the latch circuit DL is completed, and the nodes ND26 and ND27 are set to the "L" level. That is, the amplifier 62o outputs the "L" level signals DOPo and DOMo.

[0259] A low-level signal DOPo is input to the terminal DF of the amplifier 62e. This turns off the transistor 206. A low-level signal DOMo is input to the terminal bDF of the amplifier 62e. This turns off the transistor 205. The high-level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e, and the amplifier 62e continues to output a low-level signal DRo.

[0260] [Time t10] As shown in FIG. 27, at time t10, signal CK falls from "H" level to "L" level, and signal bCK rises from "L" level to "H" level. In amplifier 62e, signals DIPe and DIMe are set to "H" level based on the falling edge of signal CK. Amplifier 62o is set to a latch state ("lat") based on the rising edge of signal bCK. Based on odd-numbered bit data V3, signals DIPo, DIMo, DOPo, and DOMo of amplifier 62o begin to transition. In amplifier 62e, signals DIPe and DIMe are set to "H" level based on the falling edge of signal CK.

[0261] As shown in FIG. 38, a signal CK of "L" level is input to the amplifier 62e. Therefore, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. The input unit 80 outputs signals DIPe and DIMe of "H" level. The NOR circuit 220 of the amplifier 62e is input with the signal CK of "L" level and the signals DIPo and DIMo of "H" level. Therefore, the NOR circuit 220 continues to output the signal DRo of "L" level. Furthermore, the latch unit 81 is input with the signals DIPe and DIMe of "H" level. Therefore, the transistors 208 and 209 are turned off. Since the latch unit 81 maintains the latched state, it outputs a signal DOPe of "L" level from the terminal Q and outputs a signal DOMe of "H" level from the terminal bQ.

[0262] The amplifier 62o receives an "H" level signal bCK. As a result, the transistors 201 and 202 of the amplifier 62o are turned off, and the transistor 207 is turned on. The signals DIPo and DIMo begin to transition from "H" level to "L" level. The NOR circuit 220 of the amplifier 62o receives "H" level signals bCK, DIPe, and DIMe. As a result, the NOR circuit 220 outputs an "L" level signal DRe. In the latch unit 81, the transistors 214 to 217 are turned off. As a result, the latch circuit DL of the latch unit 81 is in a latched state. Furthermore, the latch unit 81 receives "H" level signals DIPo and DIMo. As a result, the transistors 208 and 209 are turned off. As a result, the latch unit 81 continues to output "L" level signals DOPo and DOMo from the terminals Q and bQ, respectively.

[0263] [Time t11] As shown in FIG. 27, at time t11, the logic levels of signals DOPo and DOMo are determined based on the voltage difference between signals DIPo and DIMo of amplifier 62o, i.e., the difference in the transition speed from "H" level to "L" level. In other words, the logic level of odd-numbered bit data V3 is determined. Signal DOPo is set to "H" level, and signal DOMo is set to "L" level. Therefore, in amplifier 62e, signal DRo is set to "L" level. This initiates a reset operation in amplifier 62e.

[0264] 39, in the amplifier 62o, the signal DIPo transitions to the "L" level before the signal DIMo, and therefore the transistor 208 is turned on before the transistor 209. As a result, in the latch unit 81, the node ND26 is set to the "H" level and the node ND27 is set to the "L" level. As a result, the signal DOPo transitions from the "L" level to the "H" level, and the signal DOMo is maintained at the "L" level. In other words, the amplifier 62o takes in the odd-numbered bit data V3 at the "H" level, and as a result outputs the signal DOPo at the "H" level and the signal DOMo at the "L" level.

[0265] The amplifier 62e receives feedback of the result of the amplifier 62o capturing the odd-numbered bit data V3. More specifically, a high-level signal DOPo is input to the terminal DF of the amplifier 62e. This turns on the transistor 206. A low-level signal DOMo is input to the terminal bDF of the amplifier 62e. This turns off the transistor 205. This increases the voltage VREF in the amplifier 62e. Low-level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e. As a result, the NOR circuit 220 of the amplifier 62e outputs a high-level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned on. The amplifier 62e starts resetting the latch circuit DL. However, at time t11, the reset operation of the latch circuit DL has not yet been completed, so the signal DOPe is maintained at the "L" level, and the signal DOMe is maintained at the "H" level.

[0266] [Time t12] 27, for example, assume that the even-numbered bit data V4 of the signal DQ is at the "H" level. At time t12, the reset operation of the latch circuit DL of the amplifier 62e is completed, and the amplifier 62e is set to the reset state ("rst"). Therefore, the signals DOPe and DOMe are set to the "L" level.

[0267] As shown in FIG. 40, since the even-numbered bit data V4 of the signal DQ is at the "H" level, the transistors 203 of the amplifiers 62e and 62o are turned on.

[0268] In the amplifier 62e, the reset operation of the latch circuit DL is completed, and the nodes ND26 and ND27 are set to the "L" level. That is, the amplifier 62e outputs the "L" level signals DOPe and DOMe.

[0269] A low-level signal DOPe is input to the terminal DF of the amplifier 62o. This turns off the transistor 206. A low-level signal DOMe is input to the terminal bDF of the amplifier 62o. This turns off the transistor 205. High-level signals bCK, DIPe, and DIMe are input to the NOR circuit 220 of the amplifier 62o. The NOR circuit 220 of the amplifier 62o continues to output a low-level signal.

[0270] [Time t13] 27, at time t13, the signal CK rises from the "L" level to the "H" level, and the signal bCK falls from the "H" level to the "L" level. The amplifier 62e is set to a latch state ("lat") based on the rising edge of the signal CK. Based on the even bit data V4, the signals DIPe, DIMe, DOPe, and DOMe of the amplifier 62e begin to transition. In the amplifier 62o, the signals DIPo and DIMo are set to the "H" level based on the falling edge of the signal bCK.

[0271] As shown in FIG. 41, an "H" level signal CK is input to the amplifier 62e. As a result, the transistors 201 and 202 of the amplifier 62e are turned off, and the transistor 207 is turned on. The signals DIPe and DIMe begin to transition from "H" level to "L" level. The "H" level signals CK, DIPo, and DIMo are input to the NOR circuit 220 of the amplifier 62e. As a result, the NOR circuit 220 outputs an "L" level signal DRo. In the latch unit 81, the transistors 214 to 217 are turned off. As a result, the latch circuit DL of the latch unit 81 is in a latched state. Furthermore, the "H" level signals DIPe and DIMe are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Following time t6, the latch unit 81 outputs "L" level signals DOPe and DOMe from the terminals Q and bQ, respectively.

[0272] An "L" level signal bCK is input to the amplifier 62o. As a result, the transistors 201 and 202 of the amplifier 62e are turned on, and the transistor 207 is turned off. The input unit 80 outputs "H" level signals DIPo and DIMo. The "L" level signal bCK and the "H" level signals DIPe and DIMe are input to the NOR circuit 220 of the amplifier 62o. As a result, the NOR circuit 220 outputs an "L" level signal DRe. Furthermore, "H" level signals DIPo and DIMo are input to the latch unit 81. As a result, the transistors 208 and 209 are turned off. Since the latch unit 81 maintains the latched state, it outputs an "H" level signal DOPo from the terminal Q and outputs an "L" level signal DOMo from the terminal bQ.

[0273] 2.4 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0274] Furthermore, with the configuration according to this embodiment, the reset operation of the latch circuit DL of the amplifier 62e or 62o can be started before the logic level of the signal DQ is determined in the other amplifier, thereby enabling the DFE circuit 50 to further increase the signal reception speed.

[0275] 2.5 Modification of the second embodiment Next, modifications of the second embodiment will be described. Two examples of amplifier 62e having a different internal configuration from amplifier 62e described with reference to FIG. 26 of the second embodiment will be described. The same applies to amplifier 62o. The following description will focus on the differences from amplifier 62e described with reference to FIG. 26.

[0276] 2.5.1 First variant First, a first modified example of the second embodiment will be described with reference to Fig. 42. Fig. 42 is a circuit diagram of an amplifier 62e.

[0277] As shown in FIG. 42, an amplifier 62e of this example includes an input section 80, a latch section 81, and a negative OR (NOR) circuit 220, similar to the second embodiment.

[0278] The internal configuration of the input section 80 is the same as that of the second embodiment. The signal input to the NOR circuit 220 is the same as that of the second embodiment.

[0279] The latch section 81 of this example includes PMOS transistors 208 to 211, 230, and 231, and NMOS transistors 212 to 217. That is, the latch section 81 has a structure in which the transistors 230 and 231 are added to the latch section 81 described with reference to FIG.

[0280] A voltage VDD is applied to one end of the transistor 230. The other end of the transistor 230 is connected to a node ND24. The gate of the transistor 230 is connected to the output terminal of the NOR circuit 220. In other words, the signal DRo is input to the gate of the transistor 230.

[0281] A voltage VDD is applied to one end of the transistor 231. The other end of the transistor 231 is connected to a node ND25. The gate of the transistor 231 is connected to the output terminal of the NOR circuit 220. In other words, the signal DRo is input to the gate of the transistor 231.

[0282] The connections of the other transistors in the latch section 81 are similar to those of the amplifier 62e described with reference to FIG.

[0283] 2.5.2 Second variant Next, a second modification of the second embodiment will be described with reference to Fig. 43. Fig. 43 is a circuit diagram of an amplifier 62e.

[0284] As shown in FIG. 43, an amplifier 62e of this example includes an input section 80, a latch section 81, and inverters 250-252.

[0285] The internal configuration of the input unit 80 is the same as that of the second embodiment.

[0286] The latch unit 81 of this example includes PMOS transistors 210, 211, and 240, and NMOS transistors 212, 213, 216, 217, 241, and 242.

[0287] A voltage VDD is applied to one end of the transistor 240. The other end of the transistor 240 is connected to a node ND30. The gate of the transistor 240 is connected to the input terminal of the inverter 250.

[0288] One end of the transistor 210 is connected to a node ND30, the other end of the transistor 210 is connected to a node ND26, and the gate of the transistor 210 is connected to a node ND27.

[0289] One end of the transistor 211 is connected to a node ND30, the other end of the transistor 211 is connected to a node ND27, and the gate of the transistor 211 is connected to a node ND26.

[0290] One end of the transistor 216 is connected to the node ND26. The other end of the transistor 216 is connected to the node ND31. The gate of the transistor 216 is connected to the node ND21. In other words, the signal DIPe is input to the gate of the transistor 216.

[0291] One end of the transistor 217 is connected to the node ND27. The other end of the transistor 217 is connected to the node ND31. The gate of the transistor 217 is connected to the node ND22. In other words, the signal DIMe is input to the gate of the transistor 217.

[0292] One end of the transistor 241 is connected to the node ND31, the other end of the transistor 241 is grounded, and the gate of the transistor 241 is connected to the node ND40.

[0293] One end of the transistor 242 is connected to the node ND31, the other end of the transistor 242 is grounded, and the gate of the transistor 242 is connected to the node ND40.

[0294] An input terminal of the inverter 250 is connected to the terminal CL. An output terminal of the inverter 250 is connected to the gate of the transistor 240. The inverter 250 outputs an inverted signal of the signal CK (signal bCK in the case of the amplifier 62o).

[0295] An input terminal of the inverter 251 is connected to the terminal CR. An output terminal of the inverter 251 is connected to the node ND40. The inverter 251 outputs an inverted signal of the signal DIPo (signal DIPe in the case of the amplifier 62o).

[0296] An input terminal of the inverter 252 is connected to the terminal bCR. An output terminal of the inverter 252 is connected to the node ND40. The inverter 252 outputs an inverted signal of the signal DIMo (signal DIMe in the case of the amplifier 62o).

[0297] 2.5.2 Effects of the Modification of the Second Embodiment The configurations according to the first and second modifications of the second embodiment can provide the same effects as the second embodiment.

[0298] Furthermore, in the configuration according to the first modification of the second embodiment, the amplifier 62 includes transistors 230 and 231. The transistors 230 and 231 supply the voltage VDD to the latch circuit DL while the signal DRo is at the "H" level, that is, while the latch circuit DL is in the latching state. As a result, for example, even if the transistors 208 and 209 are in the off state, the voltage VDD is supplied to the latch circuit DL. This improves the stability of data retention in the latch circuit DL.

[0299] Furthermore, in the configuration according to the second modification of the second embodiment, the amplifier 62 includes a transistor 240. This allows the latch circuit DL to operate in synchronization with the signal CK.

[0300] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a configuration of the DFE circuit 50 that is different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0301] 3.1 Configuration 3.1.1 Overall configuration of the DFE circuit Next, an example of the overall configuration of the DFE circuit 50 will be described with reference to FIG. 44. FIG. 44 is a block diagram of the DFE circuit 50. In this embodiment, a case where loop unrolling is applied to the DFE circuit 50 will be described. For example, the DFE circuit 50 described in the first and second embodiments feeds back an output signal corresponding to the bit data of the signal DQ input at the previous timing to the input of the bit data at the next timing. This allows the DFE circuit 50 to achieve the same effect as when the voltage value of the voltage VREF is varied relative to the voltage value of the signal DQ. In contrast, the DFE circuit of this embodiment includes two systems for one bit of data: a receiving unit that receives the signal DQ with the voltage VREF relatively increased in advance, and a receiving unit that receives the signal DQ with the voltage VREF relatively decreased in advance. The DFE circuit 50 compensates the signal DQ by selecting one of the two systems based on the output signal corresponding to the bit data of the signal DQ input at the previous timing.

[0302] 44, the DFE circuit 50 includes four receiving units 91e1, 91e2, 91o1, and 91o2, two multiplexers (MUX) 92e and 92o, and two amplifiers 93e and 93o. Hereinafter, when any of the receiving units 91e1, 91e2, 91o1, and 91o2 is not specified, it will be referred to as a receiving unit 91. When any of the multiplexers 92e and 92o is not specified, it will be referred to as a multiplexer 92. When any of the amplifiers 93e and 93o is not specified, it will be referred to as an amplifier 93.

[0303] The receiving units 91e1 and 91e2 receive even-numbered bit data of the signal DQ. For example, the receiving unit 91e1 receives the signal DQ with a voltage VREF relatively increased with respect to the signal DQ. The receiving unit 91e2 receives the signal DQ with a voltage VREF relatively decreased with respect to the signal DQ. The receiving units 91e1 and 91e2 receive the even-numbered bit data of the signal DQ and the voltage VREF. As a result of receiving the signal DQ, the receiving unit 91e1 transmits signals DSPe1 and DSMe1 to the multiplexer 92e. As a result of receiving the signal DQ, the receiving unit 91e2 transmits signals DSPe2 and DSMe2 to the multiplexer 92e.

[0304] The receiving units 91o1 and 91o2 receive odd-numbered bit data of the signal DQ. For example, the receiving unit 91o1 receives the signal DQ with a voltage VREF relatively increased with respect to the signal DQ. The receiving unit 91o2 receives the signal DQ with a voltage VREF relatively decreased with respect to the signal DQ. The odd-numbered bit data of the signal DQ and the voltage VREF are input to the receiving units 91o1 and 91o2. As a result of receiving the signal DQ, the receiving unit 91o1 transmits signals DSPo1 and DSMo1 to the multiplexer 92o. As a result of receiving the signal DQ, the receiving unit 91o2 transmits signals DSPo2 and DSMo2 to the multiplexer 92o.

[0305] The multiplexer 92e selects one of the receiving units 91e1 and 91e2 based on the output signals DOPo and DOMo of the amplifier 93o. The multiplexer 92e outputs the signals DMPe and DMMe. More specifically, for example, when the signal DOPo is at a low level, the multiplexer 92e outputs the signals DSPe1 and DSMe1 input from the receiving unit 91e1 as the signals DMPe and DMMe. Furthermore, when the signal DOPo is at a high level, the multiplexer 92e outputs the signals DSPe2 and DSMe2 input from the receiving unit 91e2 as the signals DMPe and DMMe. In other words, when the bit data of the signal DQ at the immediately preceding timing is at a high level, the multiplexer 92e selects the signals DSPe1 and DSMe1 corresponding to the signal DQ acquired with the voltage VREF relatively increased. Furthermore, when the bit data of the signal DQ at the immediately preceding timing is at the "L" level, the multiplexer 92e selects the signals DSPe2 and DSMe2 corresponding to the signal DQ captured with the voltage VREF relatively lowered.

[0306] The multiplexer 92o selects one of the receiving units 91o1 and 91o2 based on the output signals DOPe and DOMe of the amplifier 93e. The multiplexer 92o outputs the signals DMPo and DMMo. More specifically, for example, when the signal DOPo is at a low level, the multiplexer 92o outputs the signals DSPo1 and DSMo1 input from the receiving unit 91o1 as the signals DMPo and DMMo. Furthermore, when the signal DOPo is at a high level, the multiplexer 92o outputs the signals DSPo2 and DSMo2 input from the receiving unit 91o2 as the signals DMPo and DMMo. In other words, when the bit data of the signal DQ at the immediately preceding timing is at a high level, the multiplexer 92o selects the signals DSPo1 and DSMo1 corresponding to the signal DQ acquired with the reference voltage VREF relatively increased. Furthermore, when the bit data of the signal DQ at the immediately preceding timing is at the "L" level, the multiplexer 92o selects the signals DSPo2 and DSMo2 corresponding to the signal DQ captured with the reference voltage VREF relatively lowered.

[0307] The amplifier 93 is an LT-SA circuit that includes data input terminals D and bD, a latch control clock input terminal CL, a reset control clock input terminal CR, data output terminals Q and bQ, and a latch completion output terminal R. The amplifier 93 outputs an inverted signal of the input signal. The amplifiers 93e and 93o have the same configuration.

[0308] The amplifier 93e receives the signal DMPe from the multiplexer 92e at its terminal D. The amplifier 93e receives the signal DMMe from the multiplexer 92e at its terminal bD.

[0309] The signal CK is input to a terminal CL of the amplifier 93e.

[0310] A reset control clock signal is input to a terminal CR of the amplifier 93e from a terminal R of the amplifier 93o.

[0311] When an "H" level signal DMPe is input to terminal D and an "L" level signal DMMe is input to terminal bD, amplifier 93e outputs an "L" level signal DOPe from terminal Q and outputs an "H" level signal DOMe from terminal bQ. When an "L" level signal DMPe is input to terminal D and an "H" level signal DMMe is input to terminal bD, amplifier 93e outputs an "H" level signal DOPe from terminal Q and outputs an "L" level signal DOMe from terminal bQ.

[0312] The amplifier 93e outputs a reset control clock signal DRe from a terminal R. More specifically, for example, in the amplifier 93e, when the logical levels of the signals DOPe and DOMe are the same, the signal DRe is set to the "H" level. On the other hand, when the logical levels of the signals DOPe and DOMe are different, the signal DRe is set to the "L" level.

[0313] The amplifier 93o receives the signal DMPo from the multiplexer 92o at its terminal D. The amplifier 93o receives the signal DMMo from the multiplexer 92o at its terminal bD.

[0314] The signal bCK is input to a terminal CL of the amplifier 93o.

[0315] The terminal CR of the amplifier 93o receives the reset control clock signal output from the terminal R of the amplifier 93e.

[0316] When an "H" level signal DMPo is input to terminal D and an "L" level signal DMMo is input to terminal bD, amplifier 93o outputs an "L" level signal DOPo from terminal Q and outputs an "H" level signal DOMo from terminal bQ. When an "L" level signal DMPo is input to terminal D and an "H" level signal DMMo is input to terminal bD, amplifier 93o outputs an "H" level signal DOPo from terminal Q and outputs an "L" level signal DOMo from terminal bQ.

[0317] The amplifier 93o outputs a reset control clock signal DRo from a terminal R. More specifically, for example, in the amplifier 93o, when the logical levels of the signals DOPo and DOMo are the same, the signal DRo is set to the "H" level. On the other hand, when the logical levels of the signals DOPo and DOMo are different, the signal DRo is set to the "L" level.

[0318] 3.1.2 Receiving section configuration Continuing to refer to FIG. 44, an example of the internal configuration of the receiving units 91e1, 91e2, 91o1, and 91o2 will be described.

[0319] First, the receiving unit 91e1 will be described. The receiving unit 91e1 includes adders 94e1 and 95e1, an amplifier 96e1, and a bSR latch circuit 97e1.

[0320] The adder 94e1 outputs a signal VDPe1 whose voltage value is obtained by subtracting a feedback coefficient “α” from the voltage value of the signal DQ. The feedback coefficient “α” is a value smaller than the voltage value of the voltage VREF.

[0321] The adder 95e1 outputs a signal VDMe1 having a voltage value obtained by subtracting the feedback coefficient "-α" from the voltage value of the voltage VREF, that is, by adding the feedback coefficient α.

[0322] The amplifier 96e1 is an LT-SA circuit. The amplifier 96e1 includes data input terminals D and bD, a latch control clock input terminal CL, and data output terminals Q and bQ. The amplifier 96e1 outputs an inverted signal of the input signal.

[0323] The amplifier 96e1 has a terminal D that receives the signal VDPe1 from the adder 94e1 and a terminal bD that receives the signal VDMe1 from the adder 95e1.

[0324] The signal CK is input to the terminal CL of the amplifier 96e1.

[0325] The amplifier 96e1 outputs the signal DOPe1 from the terminal Q. The amplifier 96e1 outputs the signal DOMe1 from the terminal bQ.

[0326] The bSR latch circuit 97e1 temporarily stores the signals DOPe1 and DOMe1, and includes a signal input terminal bS, a reset signal input terminal bR, and output terminals Q and bQ.

[0327] The terminal bS of the bSR latch circuit 97e1 is connected to the terminal Q of the amplifier 96e1. The signal DOPe1 is input to the terminal bS of the bSR latch circuit 97e1.

[0328] The terminal bR of the bSR latch circuit 97e1 is connected to the terminal bQ of the amplifier 96e1. The terminal bR of the bSR latch circuit 97e1 receives the signal DOMe1.

[0329] The terminals Q and bQ of the bSR latch circuit 97e1 are connected to different input terminals of the multiplexer 92e, respectively. The bSR latch circuit 97e1 outputs a signal DSPe1 from the terminal Q. The bSR latch circuit 97e1 outputs a signal DSMe1 from the terminal bQ.

[0330] Next, the receiving unit 91e2 will be described. The receiving unit 91e2 includes adders 94e2 and 95e2, an amplifier 96e2, and a bSR latch circuit 97e2.

[0331] The adder 94e2 outputs a signal VDPe2 having a voltage value obtained by subtracting the feedback coefficient "-α" from the voltage value of the signal DQ.

[0332] The adder 95e2 outputs a signal VDMe1 having a voltage value obtained by subtracting the feedback coefficient "α" from the voltage value of the voltage VREF.

[0333] The amplifier 96e2 is an LT-SA circuit and has the same configuration as the amplifier 96e1.

[0334] The amplifier 96e2 has a terminal D that receives the signal VDPe2 from the adder 94e2 and a terminal bD that receives the signal VDMe2 from the adder 95e2.

[0335] The signal CK is input to the terminal CL of the amplifier 96e2.

[0336] The amplifier 96e2 outputs the signal DOPe2 from the terminal Q. The amplifier 96e2 outputs the signal DOMe2 from the terminal bQ.

[0337] The bSR latch circuit 97e2 temporarily stores the signals DOPe2 and DOMe2. The configuration of the bSR latch circuit 97e2 is the same as that of the bSR latch circuit 97e1.

[0338] The terminal bS of the bSR latch circuit 97e2 is connected to the terminal Q of the amplifier 96e2. The signal DOPe2 is input to the terminal bS of the bSR latch circuit 97e2.

[0339] The terminal bR of the bSR latch circuit 97e2 is connected to the terminal bQ of the amplifier 96e2. The terminal bR of the bSR latch circuit 97e2 receives the signal DOMe2.

[0340] The terminals Q and bQ of the bSR latch circuit 97e2 are connected to different input terminals of the multiplexer 92e, respectively. The bSR latch circuit 97e2 outputs a signal DSPe2 from the terminal Q. The bSR latch circuit 97e2 outputs a signal DSMe2 from the terminal bQ.

[0341] Next, the receiving unit 91o1 will be described. The receiving unit 91o1 includes adders 94o1 and 95o1, an amplifier 96o1, and a bSR latch circuit 97o1.

[0342] The adder 94o1 outputs a signal VDPo1 having a voltage value obtained by subtracting the feedback coefficient "α" from the voltage value of the signal DQ.

[0343] The adder 95o1 outputs a signal VDMo1 having a voltage value obtained by subtracting the feedback coefficient "-α" from the voltage value of the voltage VREF.

[0344] The amplifier 96o1 is an LT-SA circuit and has the same configuration as the amplifier 96e1.

[0345] The amplifier 96o1 receives the signal VDPo1 from the adder 94o1 at its terminal D. The amplifier 96o1 receives the signal VDMo1 from the adder 95o1 at its terminal bD.

[0346] The signal bCK is input to the terminal CL of the amplifier 96o1.

[0347] The amplifier 96o1 outputs the signal DOPo1 from the terminal Q. The amplifier 96o1 outputs the signal DOMo1 from the terminal bQ.

[0348] The bSR latch circuit 97o1 temporarily stores the signals DOPo1 and DOMo1. The configuration of the bSR latch circuit 97o1 is similar to that of the bSR latch circuit 97e1.

[0349] The terminal bS of the bSR latch circuit 97o1 is connected to the terminal Q of the amplifier 96o1. The signal DOPo1 is input to the terminal bS of the bSR latch circuit 97o1.

[0350] The terminal bR of the bSR latch circuit 97o1 is connected to the terminal bQ of the amplifier 96o1. The terminal bR of the bSR latch circuit 97o1 receives the signal DOMo1.

[0351] Terminals Q and bQ of the bSR latch circuit 97o1 are connected to different input terminals of the multiplexer 92o, respectively. The bSR latch circuit 97o1 outputs a signal DSPo1 from the terminal Q. The bSR latch circuit 97o1 outputs a signal DSMo1 from the terminal bQ.

[0352] Next, the receiving unit 91o2 will be described. The receiving unit 91o2 includes adders 94o2 and 95o2, an amplifier 96o2, and a bSR latch circuit 97o2.

[0353] The adder 94o2 outputs a signal VDPo2 whose voltage value is obtained by subtracting the feedback coefficient "-α" from the voltage value of the signal DQ.

[0354] The adder 95o2 outputs a signal VDMo1 having a voltage value obtained by subtracting the feedback coefficient "α" from the voltage value of the voltage VREF.

[0355] The amplifier 96o2 is an LT-SA circuit and has the same configuration as the amplifier 96e1.

[0356] The amplifier 96o2 receives the signal VDPo2 from the adder 94o2 at its terminal D. The amplifier 96o2 receives the signal VDMo2 from the adder 95o2 at its terminal bD.

[0357] The signal bCK is input to the terminal CL of the amplifier 96o2.

[0358] The amplifier 96o2 outputs the signal DOPo2 from terminal Q. The amplifier 96o2 outputs the signal DOMo2 from terminal bQ.

[0359] The bSR latch circuit 97o2 temporarily stores the signals DOPo2 and DOMo2. The configuration of the bSR latch circuit 97o2 is similar to that of the bSR latch circuit 97e1.

[0360] The terminal bS of the bSR latch circuit 97o2 is connected to the terminal Q of the amplifier 96o2. The signal DOPo2 is input to the terminal bS of the bSR latch circuit 97o2.

[0361] The terminal bR of the bSR latch circuit 97o2 is connected to the terminal bQ of the amplifier 96o2. The signal DOMo2 is input to the terminal bR of the bSR latch circuit 97o2.

[0362] Terminals Q and bQ of the bSR latch circuit 97o2 are connected to different input terminals of the multiplexer 92o, respectively. The bSR latch circuit 97o2 outputs a signal DSPo2 from the terminal Q. The bSR latch circuit 97o2 outputs a signal DSMo2 from the terminal bQ.

[0363] 3.1.3 Circuit configuration of amplifier 96e1 Next, an example of the circuit configuration of amplifier 96e1 will be described with reference to Fig. 45. Fig. 45 is a circuit diagram of amplifier 96e1. Amplifiers 96e2, 96o1, and 96o2 have the same circuit configuration. Hereinafter, when there is no need to specify any of amplifiers 96e1, 96e2, 96o1, and 96o2, they will be referred to as amplifier 96.

[0364] As shown in FIG. 45, the amplifier 96e1 includes PMOS transistors 301-304 and NMOS transistors 305-309.

[0365] A voltage VDD is applied to one end of the transistor 301. The other end of the transistor 301 is connected to a node ND51. The gate of the transistor 301 is connected to the terminal CL.

[0366] A voltage VDD is applied to one end of the transistor 302. The other end of the transistor 302 is connected to a node ND51. The gate of the transistor 302 is connected to a node ND52.

[0367] A voltage VDD is applied to one end of the transistor 303. The other end of the transistor 303 is connected to the node ND52. The gate of the transistor 303 is connected to the node ND51.

[0368] A voltage VDD is applied to one end of the transistor 304. The other end of the transistor 304 is connected to a node ND52. The gate of the transistor 304 is connected to the terminal CL.

[0369] One end of the transistor 305 is connected to a node ND51. The other end of the transistor 305 is connected to one end of a transistor 307. The gate of the transistor 305 is connected to a node ND52.

[0370] One end of the transistor 306 is connected to the node ND52. The other end of the transistor 306 is connected to one end of the transistor 308. The gate of the transistor 306 is connected to the node ND51.

[0371] The transistors 302, 303, 305, and 306 form a latch circuit DL. More specifically, the transistors 302 and 305 form a first inverter. The transistors 303 and 306 form a second inverter. The output of the first inverter and the input of the second inverter (node ​​ND51) are connected to a terminal Q. The input of the first inverter and the output of the second inverter (node ​​ND52) are connected to a terminal bQ.

[0372] The other end of the transistor 307 is connected to a node ND53. The gate of the transistor 307 is connected to the terminal D.

[0373] The other end of the transistor 308 is connected to the node ND53. The gate of the transistor 308 is connected to the terminal bD.

[0374] One end of the transistor 309 is connected to the node ND53, the other end of the transistor 309 is grounded, and the gate of the transistor 309 is connected to the terminal CL.

[0375] The operation of the amplifier 96e1 will be briefly described. The amplifier 96e1 is in a reset state while a low-level signal CK is input to the terminal CL. More specifically, transistors 301 and 304 are turned on, and transistor 309 is turned off. This causes a high-level voltage to be applied to nodes ND51 and ND52. As a result, the amplifier 96e1 outputs high-level signals DOPe1 and DOMe1 from terminals Q and bQ, respectively. The amplifier 96e1 stores the result of capturing the signal VDPe1 in the latch circuit DL when the signal CK rises from low to high. The logic levels of the signals DOPe1 and DOMe1 are determined based on the result stored in the latch circuit DL. The amplifier 96e1 is then in a reset state when the signal CK rises from high to low.

[0376] 3.1.4 Circuit configuration of amplifier 93e Next, an example of the circuit configuration of amplifier 93e will be described with reference to Fig. 46. Fig. 43 is a circuit diagram of amplifier 93e. Amplifier 93o has a similar circuit configuration.

[0377] As shown in FIG. 46, the amplifier 93e includes PMOS transistors 321 to 324, NMOS transistors 325 to 329, an OR circuit 330, and an XNOR circuit 331.

[0378] A voltage VDD is applied to one end of the transistor 321. The other end of the transistor 321 is connected to a node ND61. A gate of the transistor 321 is connected to the output terminal of the OR circuit 330.

[0379] A voltage VDD is applied to one end of the transistor 322. The other end of the transistor 322 is connected to the node ND61. The gate of the transistor 322 is connected to the node ND62.

[0380] A voltage VDD is applied to one end of the transistor 323. The other end of the transistor 323 is connected to the node ND62. The gate of the transistor 323 is connected to the node ND61.

[0381] A voltage VDD is applied to one end of the transistor 324. The other end of the transistor 324 is connected to the node ND62. The gate of the transistor 324 is connected to the output terminal of the OR circuit 330.

[0382] One end of the transistor 325 is connected to the node ND61. The other end of the transistor 325 is connected to one end of the transistor 327. The gate of the transistor 325 is connected to the node ND62.

[0383] One end of the transistor 326 is connected to the node ND62. The other end of the transistor 326 is connected to one end of the transistor 328. The gate of the transistor 326 is connected to the node ND61.

[0384] The transistors 322, 323, 325, and 326 form a latch circuit DL. More specifically, the transistors 322 and 325 form a first inverter. The transistors 323 and 326 form a second inverter. The output of the first inverter and the input of the second inverter (node ​​ND61) are connected to a terminal Q. The input of the first inverter and the output of the second inverter (node ​​ND62) are connected to a terminal bQ.

[0385] The other end of the transistor 327 is connected to the node ND63. The gate of the transistor 327 is connected to the terminal D.

[0386] The other end of the transistor 328 is connected to the node ND63. The gate of the transistor 328 is connected to the terminal bD.

[0387] The transistor 329 has one end connected to the node ND63 and the other end grounded. The transistor 329 has a gate connected to the output terminal of the OR circuit 330.

[0388] The two input terminals of the OR circuit 330 are connected to the terminal CL and the terminal CR, respectively. The OR circuit 330 outputs an “H” level signal when at least one of the clock signal input from the terminal CL and the reset control clock signal input from the terminal CR is “H” level.

[0389] The two input terminals of the XNOR circuit 331 are connected to a node ND61 (terminal Q) and a node ND62 (terminal bQ), respectively. The XNOR circuit 331 outputs an "L" level signal when one of the nodes ND61 and ND62 is at "H" level and the other is at "L" level. In other words, the XNOR circuit 331 outputs an "L" level signal when the logical level of the signal captured in the latch circuit DL is determined.

[0390] The operation of the amplifier 93e will be briefly described. The amplifier 93e is in a reset state while the OR circuit 330 outputs a low-level signal. More specifically, the transistors 321 and 324 are turned on, and the transistor 329 is turned off. This causes a high-level voltage to be applied to nodes ND61 and ND62. As a result, the amplifier 93e outputs high-level signals DOPe and DOMe from terminals Q and bQ, respectively. The amplifier 93e stores the result of capturing the signal VDPe1 in the latch circuit DL when the output signal of the OR circuit 330 rises from low to high. The logical levels of the signals DOPe and DOMe are determined based on the result stored in the latch circuit DL. While one of the signals DOPe and DOMe is high and the other is low, the XNOR circuit 331 outputs a low-level signal. The amplifier 93e is reset when the signal CK rises from the "H" level to the "L" level.

[0391] 3.2 Example of DFE circuit operation Next, an example of the operation of the DFE circuit 50 will be described with reference to Fig. 47. Fig. 47 is a timing chart of various signals in the DFE circuit 50.

[0392] [Time t0] As shown in FIG. 47, at time t0 before the signal DQ is input, the signal CK is set to the "L" level, and the signal bCK is set to the "H" level.

[0393] The amplifier 96e1 is in the reset state and outputs signals DOPe1 and DOMe1 at the "H" level. The amplifier 96e2 is in the reset state and outputs signals DOPe2 and DOMe2 at the "H" level. The amplifier 96o1 is in the reset state and outputs signals DOPo1 and DOMo1 at the "H" level. The amplifier 96o2 is in the reset state and outputs signals DOPo2 and DOMo2 at the "H" level.

[0394] The bSR latch circuit 97e1 outputs the signal DSPe1 at the "L" level, and the bSR latch circuit 97e2 outputs the signal DSPe2 at the "L" level.

[0395] Because the signal DQ is at the "L" level, the multiplexer 92e selects the receiving unit 91e2 (bSR latch circuit 97e2) and outputs the "L" level signal DMPe.

[0396] [Time t1] For example, assume that even-numbered bit data V0 of signal DQ is at the “H” level. At time t1, signal CK rises from the “L” level to the “H” level, and signal bCK falls from the “H” level to the “L” level.

[0397] The latch circuits DL of the amplifiers 96e1 and 96e2 capture the even-numbered bit data V0 at the "H" level in response to the rising edge of the signal CK. Based on the even-numbered bit data V0, the signals DOPe1, DOMe1, DOPe2, and DOMe2 start to transition.

[0398] [Time t2] At time t2, the logic levels of the latch circuits DL of the amplifiers 96e1 and 96e2 are determined. As a result, for example, the amplifier 96e1 outputs a signal DOPe1 at a high level and a signal DOMe1 at a low level. Furthermore, for example, the amplifier 96e2 outputs a signal DOPe2 at a low level and a signal DOMe2 at a high level. If the signal DQ is not in a full swing state, the signals DOPe1 and DOPe2 may have different logic levels due to the voltage difference with the voltage VREF. Alternatively, the signals DOPe1 and DOPe2 may have the same logic level.

[0399] The bSR latch circuit 97e1 outputs a low-level signal DSPe1 and a high-level signal DSMe1 based on a high-level signal DOPe1 and a low-level signal DOMe1. The bSR latch circuit 97e2 outputs a high-level signal DSPe2 and a low-level signal DSMe2 based on a low-level signal DOPe2 and a high-level signal DOMe2.

[0400] The multiplexer 92e selects the receiving unit 91e2 (bSR latch circuit 97e2) and outputs the signal DMPe at "H" level and the signal DMMe at "L" level.

[0401] [Time t3] For example, if odd-numbered bit data V1 of signal DQ is at the “L” level, at time t3, signal CK falls from the “H” level to the “L” level, and signal bCK rises from the “L” level to the “H” level.

[0402] The amplifiers 96e1 and 96e2 are reset in response to the falling edge of the signal CK. The amplifier 96e1 outputs the signals DOPe1 and DOMe1 at "H" level. The amplifier 96e2 outputs the signals DOPe2 and DOMe2 at "H" level.

[0403] The amplifiers 96o1 and 96o2 capture the odd-numbered bit data V1 at the "L" level in response to the rising edge of the signal bCK. Based on the odd-numbered bit data V1, the signals DOPo1, DOMo1, DOPo2, and DOMo2 start to transition.

[0404] [Time t4] At time t4, the logic levels of the latch circuits DL of the amplifiers 96o1 and 96o2 are determined. As a result, for example, the amplifier 96o1 outputs a high-level signal DOPo1 and a low-level signal DOMo1. Also, for example, the amplifier 96o2 outputs a low-level signal DOPo2 and a high-level signal DOMo2.

[0405] The bSR latch circuit 97o1 outputs a low-level signal DSPo1 and a high-level signal DSMo1 based on a high-level signal DOPo1 and a low-level signal DOMo1. The bSR latch circuit 97o2 outputs a high-level signal DSPo2 and a low-level signal DSMo2 based on a low-level signal DOPo2 and a high-level signal DOMo2.

[0406] The multiplexer 92o selects the receiving unit 91o2 (bSR latch circuit 97o2) and outputs the signal DMPo at "H" level and the signal DMMo at "L" level.

[0407] [Time t5] For example, assume that even-numbered bit data V2 of signal DQ is at the “L” level. At time t5, signal CK rises from the “L” level to the “H” level, and signal bCK falls from the “H” level to the “L” level.

[0408] The latch circuits DL of the amplifiers 96e1 and 96e2 capture the even-numbered bit data V2 at the "L" level in response to the rising edge of the signal CK. Based on the even-numbered bit data V2, the signals DOPe1, DOMe1, DOPe2, and DOMe2 start to transition.

[0409] The amplifiers 96o1 and 96o2 are reset in response to the falling edge of the signal bCK. The amplifier 96o1 outputs the signals DOPo1 and DOMo1 at "H" level. The amplifier 96o2 outputs the signals DOPo2 and DOMo2 at "H" level.

[0410] The amplifier 93e receives the high-level signal DMPe and the low-level signal DMMe in response to the rising edge of the signal CK. Based on the signals DMPe and DMMe, the signals DOPe and DOMe begin to transition.

[0411] [Time t6] At time t6, the logic levels of the latch circuits DL of the amplifiers 96e1 and 96e2 are determined. As a result, for example, the amplifier 96e1 outputs a high-level signal DOPe1 and a low-level signal DOMe1. Also, for example, the amplifier 96e2 outputs a high-level signal DOPe2 and a low-level signal DOMe2.

[0412] The bSR latch circuit 97e1 outputs a low-level signal DSPe1 and a high-level signal DSMe1 based on a high-level signal DOPe1 and a low-level signal DOMe1. The bSR latch circuit 97e2 outputs a low-level signal DSPe2 and a high-level signal DSMe2 based on a high-level signal DOPe2 and a low-level signal DOMe2.

[0413] The multiplexer 92e selects the receiving unit 91e2 (bSR latch circuit 97e2) and outputs the signal DMPe at "L" level and the signal DMMe at "H" level.

[0414] The logic level of the latch circuit DL of the amplifier 93e is determined. In other words, the logic level of the even-numbered bit data V0 of the signal DQ is determined. As a result, for example, the amplifier 93e outputs a signal DOPe at a low level and a signal DOMe at a high level. The amplifier 93e also outputs a signal DRe at a low level.

[0415] The multiplexer 92o selects the receiving unit 91o1 based on the signal DOPe at "L" level and the signal DOMe at "H" level. The multiplexer 92o outputs the signal DMPo at "L" level and the signal DMMo at "H" level.

[0416] The amplifier 93o receives the signals bCK and DRe at the "L" level, which causes the amplifier 93o to start resetting the latch circuit DL.

[0417] [Time t7] At time t7, the reset operation of the amplifier 93o is completed, and the latch circuit DL is reset. As a result, the amplifier 93o outputs the signals DOPo and DOMo at "H" level. The amplifier 93o outputs the signal DRo at "H" level.

[0418] [Time t8] For example, suppose that odd-numbered bit data V3 of signal DQ is at the “H” level. At time t8, signal CK falls from the “H” level to the “L” level, and signal bCK rises from the “L” level to the “H” level.

[0419] The amplifiers 96e1 and 96e2 are reset in response to the falling edge of the signal CK. The amplifier 96e1 outputs the signals DOPe1 and DOMe1 at "H" level. The amplifier 96e2 outputs the signals DOPe2 and DOMe2 at "H" level.

[0420] The amplifiers 96o1 and 96o2 capture the "H" level odd-numbered bit data V3 based on the rising edge of the signal bCK. Based on the odd-numbered bit data V3, the signals DOPo1, DOMo1, DOPo2, and DOMo2 start to transition.

[0421] The amplifier 93o receives the signal DMPo at the "L" level and the signal DMMo at the "H" level based on the rising edge of the signal bCK. Based on the signals DMPo and DMMo, the signals DOPo and DOMo start to transition.

[0422] [Time t9] At time t9, the logic levels of the latch circuits DL of the amplifiers 96o1 and 96o2 are determined. As a result, for example, the amplifier 96o1 outputs a high-level signal DOPo1 and a low-level signal DOMo1. Also, for example, the amplifier 96o2 outputs a low-level signal DOPo2 and a high-level signal DOMo2.

[0423] The bSR latch circuit 97o1 outputs a low-level signal DSPo1 and a high-level signal DSMo1 based on a high-level signal DOPo1 and a low-level signal DOMo1. The bSR latch circuit 97o2 outputs a high-level signal DSPo2 and a low-level signal DSMo2 based on a low-level signal DOPo2 and a high-level signal DOMo2.

[0424] The logic level of the latch circuit DL of the amplifier 93o is determined. In other words, the logic level of the odd-numbered bit data V1 of the signal DQ is determined. As a result, for example, the amplifier 93o outputs a high-level signal DOPo and a low-level signal DOMo. The amplifier 93o also outputs a low-level signal DRo.

[0425] The amplifier 93e receives the signals CK and DRo at "L" level, which causes the amplifier 93e to start resetting the latch circuit DL.

[0426] [Time t10] At time t10, the reset operation of the amplifier 93e is completed, and the latch circuit DL is reset. As a result, the amplifier 93e outputs the signals DOPe and DOMe at "H" level. The amplifier 93e also outputs the signal DRe at "H" level.

[0427] The multiplexer 92o selects the receiving unit 91o2 and outputs the signal DMPo at "H" level and the signal DMMo at "L" level.

[0428] [Time t11] For example, assume that even-numbered bit data V4 of signal DQ is at the “H” level. At time t11, signal CK rises from the “L” level to the “H” level, and signal bCK falls from the “H” level to the “L” level.

[0429] The latch circuits DL of the amplifiers 96e1 and 96e2 capture the even-numbered bit data V4 at the "H" level in response to the rising edge of the signal CK. Based on the even-numbered bit data V4, the signals DOPe1, DOMe1, DOPe2, and DOMe2 start to transition.

[0430] The amplifiers 96o1 and 96o2 are reset in response to the falling edge of the signal bCK. The amplifier 96o1 outputs the signals DOPo1 and DOMo1 at "H" level. The amplifier 96o2 outputs the signals DOPo2 and DOMo2 at "H" level.

[0431] The amplifier 93e receives the signal DMPe at the "L" level and the signal DMMe at the "H" level based on the rising edge of the signal CK. Based on the signals DMPe and DMMe, the signals DOPe and DOMe start to transition.

[0432] 3.3 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0433] Furthermore, with the configuration according to this embodiment, it is possible to omit the operation of feeding back the output signal to the input signal, thereby enabling the DFE circuit 50 to further increase the signal reception speed.

[0434] 4. Modifications, etc. The semiconductor memory device according to the embodiment includes a first circuit (60e) including a nonvolatile memory cell (MC) and a first latch circuit (DL), receiving first bit data (V0) of an input signal (DQ) based on a first clock signal (CK), storing first data (DOPe) in the first latch circuit based on a result of comparing the first bit data with a reference voltage (VREF), and outputting a first signal (DRe) based on the first data, and a second circuit (60o) including a second latch circuit (DL), receiving second bit data (V1) of the input signal (DQ) based on a second clock signal (bCK) obtained by inverting the first clock signal, storing second data (DOPo) in the second latch circuit based on a result of comparing the second bit data with a reference voltage (VREF), and outputting a second signal (DRo) based on the second data. The first circuit receives the second data and the second signal, compares the first bit data with the reference voltage based on the second data, and resets the first latch circuit based on the second signal. The second circuit receives the first data and the first signal, compares the second bit data with a reference voltage based on the first data, and resets the second latch circuit based on the first signal.

[0435] By applying the above-described embodiment, it is possible to provide a semiconductor memory device that can suppress an increase in chip area.

[0436] For example, in the third embodiment, the DTSA circuit can be applied to the amplifier 93 or the amplifier 96.

[0437] 7 of the first embodiment, the input terminals DM, bDM, DF, and bDF of the amplifier 60 are each connected to the gates of an NMOS transistor, but the circuit configuration of the amplifier 60 is not limited to this. For example, the amplifier 60 may have a circuit configuration in which the input terminals DM, bDM, DF, and bDF are each connected to a PMOS transistor. That is, the differential amplifier section of the amplifier 60 may be configured with PMOS transistors. The same applies to the other amplifiers 62, 93, and 96.

[0438] Also, for example, in the above embodiment, the memory interface circuit 16 may have the same configuration as the input circuit 41.

[0439] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0440] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0441] 1...data processing device, 2...host device, 3...memory system, 10...memory controller, 11...host interface circuit, 12...CPU, 13...ROM, 14...RAM, 15...buffer memory, 16...memory interface circuit, 20...semiconductor memory device, 21...input / output circuit, 22...logic control circuit, 23...address register, 24...command register, 25...status register, 26...sequencer, 27...ready / busy circuit, 28...voltage generation circuit, 29...memory cell array, 30...row decoder, 31...sense amplifier, 32...data register, 33...column decoder, 41...input circuit, 42...output circuit, 50...DFE circuit, 51...clock signal generation circuit, 52...latch circuit, 53...shift register, 60, 60e, 60o, 62, 62e, 62o, 93, 93e, 93o, 96, 96e1, 96e2, 96o1, 96o2...amplifiers, 70, 70e, 70o, 97e1, 97e2, 97o1, 97o2...bSR latch circuit, 72, 72e, 72o...SR latch circuit, 80...input section, 81...latch section, 91, 91e1, 91e2, 91o1, 91o2...receiving section, 92, 92e, 92o...multiplexer, 94e1, 94e2, 94o1, 94o2, 95e1, 95e2, 95o1, 95o2...adder, 101 to 111, 121 to 123, 201 to 217, 230 , 231, 240 to 242, 301 to 309, 321 to 329...transistors, 112, 220, 330...OR circuits, 113, 331...XNOR circuits, 220...NOR circuits, 250 to 252...inverters, BLK0 to BLK3...blocks, MC0 to MC7...memory cell transistors, SGD0 to SGD3...select gate lines, ST1, ST2...select transistors, SU0 to SU3...string units, WL0 to WL7...word lines.

Claims

1. a nonvolatile memory cell; a first circuit including a first latch circuit, receiving first bit data of an input signal based on a first clock signal, storing first data based on a result of comparing the first bit data with a reference voltage in the first latch circuit, and outputting a first signal based on the first data; a second circuit including a second latch circuit, receiving second bit data of the input signal based on a second clock signal obtained by inverting the first clock signal, storing second data based on a result of comparing the second bit data with the reference voltage in the second latch circuit, and outputting a second signal based on the second data; Equipped with the first circuit receives the second data and the second signal, compares the first bit data with the reference voltage based on the second data, and resets the first latch circuit based on the second signal; the second circuit receives the first data and the first signal, compares the second bit data with the reference voltage based on the first data, and resets the second latch circuit based on the first signal; Semiconductor memory device.

2. the first latch circuit is set to the reset state when the second data is stored in the second latch circuit in the second circuit; 2. The semiconductor memory device according to claim 1.

3. the first signal has a different logic level when the first latch circuit is in the reset state from when the first data is stored in the first latch circuit; 2. The semiconductor memory device according to claim 1.

4. a nonvolatile memory cell; a first circuit including a first latch circuit, receiving first bit data of an input signal based on a first clock signal, storing first data in the first latch circuit based on a result of comparing the first bit data with a reference voltage, and outputting a first signal; a second circuit including a second latch circuit, receiving second bit data of the input signal based on a second clock signal obtained by inverting the first clock signal, and storing second data in the second latch circuit and outputting a second signal based on a result of comparing the second bit data with the reference voltage; Equipped with the first circuit receives the second data and the second signal, compares the first bit data with the reference voltage based on the second data, and resets the first latch circuit based on the second signal; the second circuit receives the first data and the first signal, compares the second bit data with the reference voltage based on the first data, and resets the second latch circuit based on the first signal; Semiconductor memory device.

5. the first latch circuit is set to the reset state when the second bit data is compared with the reference voltage in the second circuit; 5. The semiconductor memory device according to claim 4.

6. the first latch circuit determines a logic level of the first data based on a change in a voltage value of a third signal corresponding to the result of comparing the first bit data with the reference voltage; 5. The semiconductor memory device according to claim 4.

7. a nonvolatile memory cell; a first circuit that receives first bit data of an input signal based on a first clock signal, and outputs a first signal based on a result of comparing a value obtained by subtracting a coefficient from the first bit data with a value obtained by adding the coefficient to a reference voltage; a second circuit that receives the first bit data of the input signal based on the first clock signal, and outputs a second signal based on a result of comparing a value obtained by adding the coefficient to the first bit data with a value obtained by subtracting the coefficient from the reference voltage; a third circuit that receives second bit data of the input signal based on a second clock signal obtained by inverting the first clock signal, and outputs a third signal based on a result of comparing a value obtained by subtracting the coefficient from the second bit data with a value obtained by adding the coefficient to the reference voltage; a fourth circuit that receives the second bit data of the input signal based on the second clock signal, and outputs a fourth signal based on a result of comparing a value obtained by adding the coefficient to the second bit data with a value obtained by subtracting the coefficient from the reference voltage; a first multiplexer that outputs either the first signal or the second signal as a fifth signal; a second multiplexer that outputs either the third signal or the fourth signal as a sixth signal; a fifth circuit that receives the fifth signal based on the first clock signal and outputs first data based on the fifth signal; a sixth circuit that receives the sixth signal based on the second clock signal and outputs second data based on the sixth signal; A semiconductor memory device comprising:

8. the fifth circuit includes a first latch circuit that stores the first data and outputs a seventh signal based on the first data; the sixth circuit includes a second latch circuit that stores the second data, and outputs an eighth signal based on the second data; the first latch circuit is reset based on the eighth signal; the second latch circuit is reset based on the seventh signal; 8. The semiconductor memory device according to claim 7.

9. the first multiplexer selects either the third signal or the fourth signal based on the second data.

8. The semiconductor memory device according to claim 7.

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