Semiconductor module, semiconductor device, and vehicle

Abstract

The present invention prevents progress of peeling on an interface between a lead bonded to an electrode on a semiconductor element by a bonding material and a sealing material. A semiconductor module (2) includes: a circuit board (5) on which a semiconductor element (510) is mounted; a lead (7) that is bonded to an electrode on an upper surface of the semiconductor element by a bonding material; and a sealing material (9) that seals the semiconductor element and the lead. The lead has a plurality of recessed sections (720) on an upper surface (710) that is the opposite side from a lower surface facing the electrode, on a bonding section (701) bonded to the electrode, the recessed sections each having a polygonal shape in which a bottom surface in a plan view has a side extending in a direction that is not orthogonal to any of the sides of the bonding section. Each of the plurality of recessed sections has return parts (727) protruding from wall surfaces (721, 722, 723).

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module, a semiconductor device, and a vehicle. [Background technology]

[0002] Some power conversion devices, such as inverter devices, include semiconductor devices having circuit boards on which semiconductor elements, such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), FWDs (Free Wheeling Diodes), etc. The circuit board includes a wiring board in which a conductor pattern is provided on the surface of an insulating substrate, and circuit components, such as semiconductor elements, that are arranged on the wiring board.

[0003] In this type of semiconductor device, a conductive plate called a lead or the like may be used as a conductive member that electrically connects electrodes of the semiconductor element provided on the surface (top surface) opposite to the surface facing the wiring board to the conductor pattern of the wiring board.

[0004] In semiconductor devices in which leads are used to electrically connect electrodes of a semiconductor element to a conductor pattern on a wiring board, various measures have been proposed to prevent peeling at the interface between the leads and the sealing material.

[0005] For example, Patent Document 1 describes a semiconductor device in which the side walls of dimples formed on a lead frame have inwardly protruding burrs, and the dimples are connected by grooves.

[0006] Furthermore, for example, Patent Document 2 describes a semiconductor device in which at least four return portions are formed by partly protruding the inner peripheral wall of each of a plurality of dimples formed on a lead frame. Furthermore, for example, Patent Document 3 describes a semiconductor device in which a plurality of dimples formed on a lead frame are each formed with a return portion by partly protruding the inner peripheral wall of each of the dimples, and the plurality of dimples include two types of dimples with return portions oriented in different directions.

[0007] Furthermore, for example, Patent Document 4 describes a semiconductor device in which a large dimple that opens onto the main surface and a small dimple that opens onto the inner surface of the large dimple are formed on at least one main surface of a die pad in a lead frame.

[0008] Furthermore, for example, Patent Document 5 describes a semiconductor device in which a plurality of rectangular recesses are arranged vertically and horizontally at approximately equal intervals on the surface of a metal plate to which a semiconductor element is fixed, in a region other than the semiconductor element mounting region. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 4086774 [Patent Document 2] Patent No. 6408431 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-005124 [Patent Document 4] Japanese Patent Application Laid-Open No. 2015-060889 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-186622 Summary of the Invention [Problem to be solved by the invention]

[0010] In the structure for preventing peeling at the interface between the lead and the encapsulant in the semiconductor device described above, the depressions called dimples formed on the surface of the lead have walls parallel to the sides of the lead in a plan view, or are arranged in a direction perpendicular to the sides of the lead. Therefore, if peeling occurs in the encapsulant at a position that corresponds to the side of the lead in a plan view, the peeling often progresses in a direction perpendicular to that side.

[0011] The present invention has been made in view of the above points, and one of its objects is to prevent the progression of peeling at the interface between the sealing material and the leads joined to the electrodes of the semiconductor element by the joining material. [Means for solving the problem]

[0012] A semiconductor module according to one embodiment of the present invention comprises a circuit board on which a semiconductor element is mounted, leads joined to electrodes on the upper surface of the semiconductor element by a bonding material, and a sealing material that seals the semiconductor element and the leads, wherein the leads have a plurality of polygonal recesses on their upper surface opposite to the lower surface facing the electrode at the bonding portion where the leads are bonded to the electrodes, the recesses having sides whose bottom surfaces in a planar view extend in a direction that is not perpendicular to any of the sides of the bonding portion, and each of the plurality of recesses has a return portion that protrudes from a wall surface. [Effects of the Invention]

[0013] According to the present invention, it is possible to prevent the progression of peeling at the interface between the sealing material and the leads joined to the electrodes of the semiconductor element by the joining material. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a top view illustrating a configuration example of a semiconductor device according to an embodiment; [Figure 2] 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along line AA'. [Figure 3] 2 is an enlarged partial top view of a region R in FIG. 1. FIG. [Figure 4] 4A and 4B are cross-sectional views of the part shown in FIG. 3 taken along lines BB', CC', and DD'. [Figure 5] FIG. 2 is a top view illustrating a first step in an example of a method for forming a recess. [Figure 6] 6A and 6B are cross-sectional views taken along lines BB', CC', and DD' in FIG. 5. [Figure 7] FIG. 10 is a top view illustrating a second step in an example of a method for forming a recess. [Figure 8] 8A and 8B are cross-sectional views taken along lines BB', CC', and DD' in FIG. 7. [Figure 9] FIG. 4 is a top view illustrating recesses formed by the first and second steps. [Figure 10] FIG. 10 is a top view illustrating a third step in an example of a method for forming a recess. [Figure 11] 11A and 11B are cross-sectional views taken along lines BB', CC', and DD' in FIG. 10. [Figure 12] FIG. 10 is a top view illustrating a conventional example of a recess for preventing peeling at the interface between the first bonding portion of the lead and the sealing material. [Figure 13] 13 is a cross-sectional view of the part shown in FIG. 12 taken along line EE'. FIG. [Figure 14] 10A and 10B are top views illustrating a second example of a method for forming a return portion on the wall surface of a recess. [Figure 15] FIG. 10 is a perspective view illustrating a third example of a method for forming a return portion on the wall surface of a recess. [Figure 16] 16A and 16B are cross-sectional views showing examples of recesses and additional recesses formed using the punch illustrated in FIG. 15. [Figure 17] 1 is a schematic plan view showing an example of a vehicle to which a semiconductor device according to the present invention is applied; DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The X, Y, and Z axes in each of the referenced figures are shown for the purpose of defining planes and directions in the illustrated semiconductor device, etc., and are orthogonal to each other and form a right-handed system. In the following description, the X direction may be referred to as the left-right direction, the Y direction as the front-back direction, and the Z direction as the up-down direction. Furthermore, a plane containing the X and Y axes may be referred to as the XY plane, a plane containing the Y and Z axes as the YZ plane, and a plane containing the Z and X axes as the ZX plane. These directions (front-back, left-right, up-down directions) and planes are terms used for convenience of explanation, and their correspondence with the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor device. For example, the heat dissipation surface (cooler side) of a semiconductor device will be referred to as the bottom side, and the opposite side will be referred to as the top side. Furthermore, in this specification, a planar view refers to the top or bottom surface (XY plane) of a semiconductor device, etc., viewed from the Z direction. Furthermore, the aspect ratios and the size relationships between the components in each drawing are merely shown schematically and do not necessarily correspond to the relationships in the actually manufactured semiconductor device, etc. For the sake of convenience of explanation, it is assumed that the size relationships between the components may be exaggerated.

[0016] The semiconductor devices exemplified in the following description are applied to power conversion devices such as inverters for industrial or automotive motors, etc. Therefore, in the following description, detailed descriptions of configurations, functions, operations, etc. that are the same as or similar to those of known semiconductor devices will be omitted.

[0017] Fig. 1 is a top view showing an example of the configuration of a semiconductor device according to an embodiment. Fig. 2 is a cross-sectional view of the semiconductor device of Fig. 1 taken along line A-A'. In Fig. 1, the sealing material filled in the case is omitted. In Fig. 2, hatching showing the cross section of the sealing material filled in the case is omitted.

[0018] 1 and 2, the semiconductor device 1 according to this embodiment is configured by placing a semiconductor module 2 on the upper surface of a cooler 3. Note that the cooler 3 is an optional configuration relative to the semiconductor module 2.

[0019] The cooler 3 dissipates heat from the semiconductor module 2 to the outside and has an overall rectangular parallelepiped shape. Although not specifically shown, the cooler 3 is configured by providing multiple fins on the underside of a flat base and housing these fins in a water jacket. However, the cooler 3 is not limited to this and can be modified as appropriate.

[0020] The semiconductor module 2 includes a base 4, a circuit board 5, a case 6, leads 7, bonding materials S1 to S4, bonding wires 8, and a sealing material 9.

[0021] The base 4 is a substrate on which the circuit board 5 is mounted, and the base 4 with the circuit board 5 mounted thereon is attached to the underside of the case 6 with the surface on which the circuit board 5 is mounted facing upward. The case 6 includes a rectangular annular insulating member 601 with openings on the top and bottom, main terminals 602 and 603 integrated with the insulating member 601, and a plurality of control terminals 604. The circuit board 5 mounted on the base 4 is accommodated in the hollow portion of the insulating member 601 of the case 6. The base 4 is a metal plate such as a copper plate, and conducts heat generated by the circuit board 5 to the cooler 3. This type of base 4 may also be called a heat sink or heat dissipation layer. The base 4, which is a heat sink, may be disposed on the top surface of the cooler 3 via a thermally conductive material such as thermal grease or thermal compound. The base 4 may also be omitted.

[0022] Circuit board 5 includes wiring board 500 and semiconductor element 510 mounted on the upper surface of wiring board 500. Wiring board 500 includes insulating substrate 501, conductor patterns 502 and 503 provided on the upper surface of insulating substrate 501, and conductor pattern 504 provided on the lower surface of insulating substrate 501. Wiring board 500 may be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate. Wiring board 500 may also be called a laminated substrate.

[0023] The insulating substrate 501 is not limited to a specific substrate. The insulating substrate 501 may be a ceramic substrate formed from a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3) and zirconium oxide (ZrO2). The insulating substrate 501 may be, for example, a substrate formed from an insulating resin such as epoxy resin, a substrate formed by impregnating a base material such as glass fiber with an insulating resin, or a substrate formed by coating the surface of a flat metal core with an insulating resin.

[0024] Conductive patterns 502 and 503 provided on the upper surface of insulating substrate 501 are conductive members used as wiring members in circuit board 5, and conductive pattern 504 provided on the lower surface of insulating substrate 501 is a conductive member used as a heat dissipation member that conducts heat generated in circuit board 5 to base 4. These conductive patterns 502 to 504 are formed of metal plates such as copper or aluminum. Conductive pattern 504 provided on the lower surface of insulating substrate 501 is joined to the upper surface of base 4 with a bonding material S1 such as solder. Conductive patterns 502 and 503 provided on the upper surface of insulating substrate 501 may also be called conductor layers, conductor plates, or wiring patterns. Conductive pattern 504 provided on the lower surface of insulating substrate 501 may also be called a heat dissipation layer, heat dissipation plate, or heat dissipation pattern.

[0025] As described above, the conductor patterns 502 and 503 provided on the upper surface of the insulating substrate 501 are conductive members used as wiring members in the circuit board 5. In the semiconductor module 2 illustrated in FIGS. 1 to 4, a semiconductor element 510 is mounted on the upper surface of the first conductor pattern 502. The semiconductor element 510 has a first main electrode (not shown) provided on the lower surface thereof joined to the first conductor pattern 502 by a bonding material S2.

[0026] A second main electrode (not shown) and a control electrode 512 are provided on the upper surface of the semiconductor element 510. These electrodes are electrically insulated by an insulating layer (not shown) formed on the upper surface of the semiconductor element 510. The insulating layer may be a surface protection film such as a passivation film formed on the upper surface of the semiconductor element 510. The second main electrode is electrically connected to a second conductor pattern 503 provided on the upper surface of the insulating substrate 501 via a lead 7. The lead 7 includes a first bonding portion 701, a second bonding portion 702, and a wiring portion 703 connecting the first bonding portion 701 and the second bonding portion 702. The first bonding portion 701 is electrically connected to the second main electrode of the semiconductor element 510 by a bonding material S3. The second bonding portion 702 is bonded to the second conductor pattern 503 of the wiring board 500 by a bonding material S4. A control electrode 512 on the upper surface of the semiconductor element 510 is electrically connected to a control terminal 604 provided on the case 6 by a bonding wire 8 .

[0027] In the semiconductor module 2 illustrated in FIGS. 1 and 2, the first conductor pattern 502 is electrically connected to a first main terminal 602 provided on the case 6, and the second conductor pattern 503 is electrically connected to a second main terminal 603 provided on the case 6. The method for electrically connecting the first conductor pattern 502 to the first main terminal 602 and the second conductor pattern 503 to the second main terminal 603 may be any known connection method and is not limited to a specific method. Furthermore, the shapes and positions of the main terminals 602 and 603 on the case 6, and the number and positions of the control terminals 604, etc., are not limited to those illustrated and can be changed as appropriate. Furthermore, the case 6 of the semiconductor module 2 of this embodiment may be provided with a third main terminal, etc. (not shown).

[0028] In this embodiment, the semiconductor element 510 is configured by, for example, an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0029] The semiconductor elements mounted on the upper surface of wiring board 500 are not limited to a specific type. Semiconductor elements serving as switching elements, such as IGBTs and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and semiconductor elements serving as diode elements, such as FWDs, may be mounted on the upper surface of wiring board 500. Alternatively, a reverse blocking (RB)-IGBT or the like, which has sufficient voltage resistance against reverse bias, may be used as the semiconductor elements. The semiconductor elements are formed, for example, on a semiconductor substrate made of silicon (Si), silicon carbide (SiC), or the like, in a rectangular shape in a plan view. The shape, number, and location of the semiconductor elements may be changed as appropriate. The layout of the conductor patterns serving as wiring members provided on the upper surface of wiring board 500 may be changed depending on the type, shape, number, and location of the semiconductor elements to be mounted.

[0030] If the switching element in the semiconductor element 510 is an IGBT element, the second main electrode on the upper surface may be called an emitter electrode, and the first main electrode on the lower surface may be called a collector electrode. If the switching element in the semiconductor element 510 is a MOSFET element, the second main electrode on the upper surface may be called a source electrode, and the first main electrode on the lower surface may be called a drain electrode. The control electrode 512 provided on the upper surface of the semiconductor element 510 may include a gate electrode and an auxiliary electrode. For example, the auxiliary electrode may be an auxiliary emitter electrode or auxiliary source electrode electrically connected to the second main electrode and serving as a reference potential for the gate potential. The auxiliary electrode may be a temperature sense electrode electrically connected to a temperature sensor and measuring the temperature of the semiconductor element 510. Such electrodes formed on the upper surface of the semiconductor element 510 (the control electrode 512 including the second main electrode, gate electrode, and auxiliary electrode) may be collectively referred to as upper surface electrodes.

[0031] The lead 7 described above is formed by bending a metal plate such as a copper plate, and may also be called a lead frame or a metal wiring plate. An insulating layer is formed on the upper surface of the semiconductor element 510 so as to surround a second main electrode that is electrically connected to the first joint portion 701 of the lead 7. The insulating layer surrounding the second main electrode restricts the spreading of the bonding material S3 that bonds the second main electrode to the first joint portion 701 of the lead 7 within a plane (XY plane) when melted.

[0032] An end portion of the wiring portion 703 of the lead 7 on the first bonding portion 701 side is connected to one side surface of the first bonding portion 701 and is bent from that side surface in the direction opposite to the bottom surface of the first bonding portion 701 (in other words, the surface of the first bonding portion 701 that faces the second main electrode of the semiconductor element 510). Similarly, an end portion of the wiring portion 703 of the lead 7 on the second bonding portion 702 side is connected to one side surface of the second bonding portion 702 and is bent from that side surface in the direction opposite to the bottom surface of the second bonding portion 702 (in other words, the surface of the second bonding portion 702 that faces the conductor pattern 503).

[0033] The semiconductor element 510, leads 7, bonding wires 8, etc. housed in the case 6 are sealed with a sealing material 9. The sealing material 9 may be a single insulating material or a combination of multiple types of insulating materials with different compositions (properties).

[0034] 1, in the semiconductor device 1 of the present embodiment, for example, a plurality of recesses are provided on the upper surface (the surface opposite to the surface facing the semiconductor element 510) of the first bonding portion 701 of the lead 7 to prevent peeling at the interface between the first bonding portion 701 and the sealing material 9. A first example of the plurality of recesses provided on the upper surface of the first bonding portion 701 will be described below with reference to FIGS. 3 and 4.

[0035] Fig. 3 is an enlarged partial top view of region R in Fig. 1. Fig. 4 is a cross-sectional view taken along line B-B', line C-C', and line D-D' of the portion shown in Fig. 3. The sealant 9 filled in the case 6 is omitted in Fig. 3. Furthermore, each cross-sectional view in Fig. 4 shows only a portion of the upper surface of the first bonding portion 701 and a portion of the sealant 9, and hatching showing a cross section of the sealant 9 filled in the case 6 is omitted.

[0036] On the upper surface 710 of the first joint 701 illustrated in Fig. 3, a plurality of recesses 720, each having a triangular bottom, are arranged in a hexagonal lattice (also called a triangular lattice) with primitive translation vectors set in the U and V directions. In Fig. 3, the U direction is the direction rotated -30 degrees with respect to the X direction (a direction rotated 30 degrees counterclockwise), and the V direction is the direction opposite to the Y direction, but the U and V directions are not limited to specific directions. Furthermore, although Fig. 3 shows the bottom of each recess 720 as an equilateral triangle, the planar shape of the bottom is not limited to this and may be a substantially equilateral triangle with rounded corners.

[0037] The plurality of recesses 720 are arranged such that one wall surface (wall surface 722 in FIG. 3) is oriented substantially parallel to the side (and the opposite side 711) of the upper surface 710 of the first joint portion 701 to which the wiring portion 703 is connected. Further, the plurality of recesses 720 have corners 724 facing the wall surface 721 perpendicular to the U direction, which have a first orientation positioned on the +U direction side as viewed from the wall surface 721, and a second orientation positioned on the −U direction side as viewed from the wall surface 721.

[0038] The recess 720 has return portions 727 projecting in the directions of the opposing corners 724, 725, and 726 formed on each of the three wall surfaces 721, 722, and 723 (see FIG. 4). The return portion 727 is provided by forming additional recesses (hereinafter referred to as “additional recesses”) 730 shallower than the depth of the recess 720 at each of the portions constituting the wall surfaces 721, 722, and 723 of the recess 720 in the lead 7 (the first joint portion 701). That is, the recess 720 is expanded outward in plan view by the additional recesses 730 formed on each of the wall surfaces 721, 722, and 723, and the return portion 727 projects toward the corner facing each wall surface at the position where the additional recess 730 is formed. The additional recess 730 illustrated in FIG. 3 can be formed using the mold used for forming the recess 720, as will be described later.

[0039] Furthermore, in the first example of the plurality of recesses 720, for example, as shown in FIG. 4, the combinations of the depth of the recess 720 and the depth of the additional recess 730 (in other words, the position in the depth direction of the return portion 727) are roughly classified into three types. In the first combination, as shown in the cross-sectional view taken along line B-B' in FIG. 4, the recess 720 has a depth D1 and the additional recess 730 has a depth D2 (< D1). In the second combination, as shown in the cross-sectional view taken along line C-C' in FIG. 4, the recess 720 has a depth D1 and the additional recess 730 has a depth D3 (< D2). In the third combination, as shown in the cross-sectional view taken along line D-D' in FIG. 4, the recess 720 has a depth D2 and the additional recess 730 has a depth D3. The depths D1, D2, and D3 are not limited to specific depths. The depths D1, D2, and D3 may be, for example, 100 μm, 50 μm, and 25 μm, respectively.

[0040] The amount of protrusion of the return portion 727 formed on the wall surfaces 721, 722, and 723 of the recess 720 from each wall surface depends on the depth of the additional recess 730. For example, the amount of protrusion L1 of the return portion 727 formed by the additional recess 730 having a depth D2 is larger than the amount of protrusion L2 of the return portion 727 formed by the additional recess 730 having a depth D3 (< D2).

[0041] When the upper surface 710 of the first bonding portion 701 of the lead 7 has the above-described multiple recesses 720, the sealing material 9 on the first bonding portion 701 fills the recesses 720, thereby increasing the contact area between the upper surface 710 of the first bonding portion 701 and the sealing material 9. Furthermore, since the return portions 727 protrude from each wall surface of the recess 720, the portion of the sealing material 9 inside the recess 720 is less likely to come out of the recess 720. Therefore, peeling at the interface between the first bonding portion 701 of the lead 7 and the sealing material 9 is less likely to occur compared to the conventional example described later with reference to FIGS. 12 and 13 . The recesses 720 formed in the lead 7 for the purpose of preventing peeling of the sealing material 9 may be referred to as roughening holes. Furthermore, the process of forming the recesses 720 in the lead 7 may be referred to as roughening treatment.

[0042] Next, an example of a method for forming the recess 720 having the return portion 727 described above with reference to FIGS. 3 and 4 on the upper surface 710 of the first bonding portion 701 of the lead 7 will be described with reference to FIGS. 5 to 11.

[0043] FIG. 5 is a top view illustrating a first step in an example of a method for forming a recess. FIG. 6 is a cross-sectional view taken along line B-B', line C-C', and line D-D' in FIG. 5. FIG. 7 is a top view illustrating a second step in an example of a method for forming a recess. FIG. 8 is a cross-sectional view taken along line B-B', line C-C', and line D-D' in FIG. 7. FIG. 9 is a top view illustrating recesses formed in the first and second steps. FIG. 10 is a top view illustrating a third step in an example of a method for forming a recess. FIG. 11 is a cross-sectional view taken along line B-B', line C-C', and line D-D' in FIG. 10. The top views of FIGS. 5, 7, and 10 show a state in which a die (punch 10 described below) for forming a recess 720 or an additional recess 730 in the corresponding step is pressed against the first bonding portion 701 of the lead 7, and the triangle indicated by the dotted line indicates the shape of the punch 10.

[0044] In one example of the method, a first step is performed in which some of the plurality of triangular prism-shaped recesses 720 are formed on the upper surface 710 of the first bonding portion 701 of the lead 7. In the first step, as illustrated in FIGS. 5 and 6, among the recesses 720 arranged in a hexagonal lattice pattern, only recesses 720 are formed that are adjacent in a positional relationship represented by a primitive translation vector and in which two adjacent equilateral triangles are oriented such that the distance between their parallel sides is shorter than the distance between the corners opposite the parallel sides. In other words, in the first step, six recesses 720 arranged in a ring in a positional relationship represented by a primitive translation vector are formed so as to be convex toward the center of a regular hexagon connecting the formation positions of the six recesses 720, and no recesses 720 are formed in the center of the regular hexagon.

[0045] In the first step, as illustrated in Fig. 6, the recess 720 having a depth D1 is formed by the punch 10. The depth D1 is, for example, 100 µm.

[0046] After the first step, a second step is performed to form the remaining recesses 720 among the plurality of triangular prism-shaped recesses 720 and additional recesses 730 for some of the recesses 720 formed in the first step. As illustrated in FIG. 7 , the second step is performed by shifting the relative positions of the punch 10 used in the first step and the first joint portion 701 of the lead 7 in a plan view by a direction and distance corresponding to the primitive translation vector in the U direction. At this time, by arranging the recesses 720 formed in the first step as described above with reference to FIG. 5 , some of the punches 10 move to positions where no recesses 720 were formed in the first step. Furthermore, by arranging the bottom surfaces (equilateral triangles) of the recesses 720 formed in the first step as described above with reference to FIG. 5 , the bottom surface (equilateral triangle) of the punch 10 moved to the position where the recesses 720 were formed in the first step is oriented opposite to the bottom surface (equilateral triangle) of the recesses 720. That is, the corners of the bottom surface of the punch 10 that has been moved to the position where the recesses 720 were formed in the first step are positioned outside the recesses 720. Therefore, the punch 10 used in the first step can form triangular prism-shaped recesses 720 that were not formed in the first step, and additional recesses 730 for some of the triangular prism-shaped recesses 720 that were formed in the first step, as illustrated in Fig. 9. At this time, the bottom surfaces of the additional recesses 730 are triangular.

[0047] 8, in the second step, the recesses 720 and the additional recesses 730 having a depth D2 shallower than the depth D1 are formed by the punch 10. The depth D2 is, for example, 50 μm.

[0048] When the second step is completed, as illustrated in FIG. 9, the triangular prism-shaped recesses 720 without the additional recesses 730 and the recesses 720 having the return portions 727 with the additional recesses 730 formed therein are arranged in a hexagonal lattice pattern. At this time, the recesses 720 having the return portions 727 have a depth D1 as shown in the cross-sectional views taken along the line B-B' in FIGS. 4 and 8, and have the return portions 727 with a protrusion amount L1 at positions corresponding to the depth D2 of the additional recesses 730. Further, among the recesses 720 without the return portions 727, the recesses 720 formed in the first step have a depth D1 as shown in the cross-sectional views taken along the line C-C' in FIGS. 4 and 8. Also, the recesses 720 formed in the second step have a depth D2 (<D1) as shown in the cross-sectional views taken along the line D-D' in FIGS. 4 and 8. Furthermore, the bottom surface of the additional recesses 730 is triangular.

[0049] After the second step, a third step of forming the additional recesses 730 in the plurality of triangular prism-shaped recesses 720 in which the additional recesses 730 were not formed in the second step is performed. As illustrated in FIG. 10, the third step is performed by further shifting the relative position between the punch 10 and the first joint portion 701 of the lead 7 used in the first and second steps in a direction and by a distance corresponding to the basic translation vector in the U direction in a plan view. At this time, by setting the recesses 720 formed in the first step in the arrangement described above with reference to FIG. 5, the punch 10 moves to the positions of the recesses 720 in which the additional recesses 730 were not formed in the second step. Also, by setting the orientation of the bottom surface (equilateral triangle) of the recesses 720 formed in the first step in the orientation described above with reference to FIG. 5, the orientation of the bottom surface (equilateral triangle) of the punch 10 that has moved to the positions of the recesses 720 in which the additional recesses 730 were not formed in the third step becomes opposite to the orientation of the bottom surface (equilateral triangle) of the recesses 720. That is, the corners on the bottom surface of the punch 10 that has moved to the positions where the recesses 720 were formed in the first or second step are in a state of being located outside the recesses 720. Therefore, the additional recesses 730 can be formed in all of the triangular prism-shaped recesses 720 in which the additional recesses 730 were not formed by the punch 10 used in the first and second steps.

[0050] 11, the additional recess 730 having a depth D3 shallower than the depth D2 is formed by the punch 10. The depth D3 is, for example, 25 μm.

[0051] The method described above with reference to Figures 5 to 11 is merely one example of a method for forming a recess 720 on the upper surface 710 of the first bonding portion 701 of the lead 7, the recess 720 having three wall surfaces 721, 722, 723, and each of the three wall surfaces 721, 722, 723 having a return portion 727.

[0052] Fig. 12 is a top view illustrating a conventional example of a recess for preventing peeling at the interface between the first bonding portion of the lead and the sealing material. Fig. 13 is a cross-sectional view taken along line E-E' of the portion shown in Fig. 12. Fig. 12 shows a region corresponding to region R in Fig. 1. Fig. 13 shows only the portion related to peeling at the interface between the first bonding portion of the lead and the sealing material, and omits hatching that shows a cross section of the coating agent and sealing resin as sealing material 9.

[0053] 12 and 13, recesses 740 with rectangular bottoms are provided in a square lattice pattern on the top surface 710 of the first bonding portion 701 of the lead 7 as recesses for preventing peeling at the interface with the sealing material 9. The wall surfaces of the recesses 740 are composed of wall surfaces that are approximately parallel to the side of the top surface 710 of the first bonding portion 701 to which the wiring portion 703 is connected (and the side 711 on the opposite side), and wall surfaces that are approximately perpendicular to the side 711. Furthermore, the return portion 727 described above with reference to FIGS. 3 to 11 is not formed on the wall surfaces of the recesses 740.

[0054] 12 and 13, the conventional semiconductor device using the leads 7 includes, as the encapsulant 9, a coating agent 901 that coats the semiconductor element 510 and the leads 7 (first bonding portions 701), and an encapsulating resin 902 that encapsulates the semiconductor element 510 and the leads 7 coated with the coating agent 901. The coating agent 901 may be, for example, an insulating material such as PA (polyamide). The encapsulating resin 902 may be, for example, an epoxy resin, a silicone gel, or the like.

[0055] When the second main electrode (not shown) on the upper surface of the semiconductor element 510 and the first bonding portion 701 of the lead 7 are bonded with a bonding material S3 such as solder, a portion (excess) of the bonding material S3 creeps up the side surface of the first bonding portion 701 (such as the side surface 712 in FIG. 13 ), creating a fillet, as illustrated in FIG. 13 . Therefore, there is a section of the coating agent 901 in contact with the bonding material S3 between the section of the coating agent 901 that contacts the semiconductor element 510 and the section of the coating agent 901 that contacts the upper surface 710 of the first bonding portion 701 of the lead 7. Furthermore, at the interface between the coating agent 901 and the bonding material S3, the difference in thermal expansion coefficient between the coating agent 901 and the bonding material S3 is large, which can cause a large change in stress due to the thermal history of the semiconductor device, resulting in peeling. The peeling that occurs at the interface between the coating agent 901 and the bonding material S3 progresses to the interface between the coating agent 901 and the upper surface 710 of the first bonding portion 701 of the lead 7. At the interface between the coating agent 901 and the upper surface 710 of the first bonding portion 701 of the lead 7, stress due to a difference in thermal expansion coefficient or the like increases in a direction perpendicular to the side of the upper surface 710 of the first bonding portion 701, and delamination progresses in this direction (in the example of FIG. 13 , it progresses in the −Y direction from the position of the side 711). Therefore, as illustrated in FIG. 12 , if all of the wall surfaces of the recess 740 provided on the upper surface 710 of the first bonding portion 701 are wall surfaces perpendicular to one of the sides of the upper surface 710, delamination is likely to occur at the interface between the wall surface of the recess 740 and the coating agent 901, and the progress of delamination may not be prevented. If delamination at the interface between the coating agent 901 and the upper surface 710 of the first bonding portion 701 of the lead 7 progresses, cracks may occur in the encapsulating material 9 (the coating agent 901 and the encapsulating resin 902), which may cause the semiconductor device to malfunction.

[0056] In contrast, the recess 720 of the present embodiment described above with reference to FIGS. 3 to 11 has a triangular prism shape, and therefore necessarily has wall surfaces that are not perpendicular to the sides of the upper surface 710 of the first bonding portion 701 of the lead 7. Therefore, compared to the recess 740 illustrated in FIG. 12, which has only wall surfaces perpendicular to one of the sides of the upper surface 710, peeling is less likely to occur at the interface between the wall surface of the recess 720 and the sealing material 9, and the effectiveness of preventing the progression of peeling is high. Furthermore, the recess 720 of the present embodiment has return portions 727 that protrude from the wall surface toward the opposing corners, so that the portion of the sealing material 9 (such as the coating agent 901) that has entered the recess 720 is less likely to come out of the recess 720. Therefore, the semiconductor device 1 according to the present embodiment is more effective in preventing the progression of peeling at the interface between the upper surface 710 of the first bonding portion 701 of the lead 7 and the sealing material 9, and can prevent failures due to cracks in the sealing material 9, etc.

[0057] Furthermore, as described above with reference to Figure 3, by arranging the recesses 720 whose bottom surfaces (equilateral triangles) are oriented in a first direction and the recesses 720 whose bottom surfaces are oriented in a second direction in a hexagonal lattice pattern, the change in the interface between the sealing material 9 and the wall surface of the recess 720 in a direction perpendicular to the side of the upper surface 710 of the first joint portion 701 of the lead 7 can be made more complex, thereby further increasing the effect of preventing the progression of peeling at the interface.

[0058] The method for forming the return portions 727 on the wall surfaces 721, 722, and 723 of the recess 720 is not limited to the method described above with reference to FIGS. 5 to 11 , and other methods may be used. For example, the punch (pressing die) used to form the triangular prism-shaped recess 720 in the first step, the punch used to form the recess 720 and the additional recess 730 in the second step, and the punch used to form the additional recess 730 in the third step may be different punches. Furthermore, for example, the recess 720 having the return portions 727 may be formed by using a first punch (pressing die) to form the recess 720 of a first depth on the upper surface 710 of the first bonding portion 701 of the lead 7, and then using a second punch (pressing die) to form the additional recess 730 of a second depth shallower than the first depth for all of the recess 720. Such a forming method is effective, for example, when the number of triangular prism-shaped recesses 720 to be formed on the upper surface 710 of the first bonding portion 701 is small. When the process of forming the recess 720 and the process of forming the additional recess 730 are performed once each, the orientation of the bottom surface (equilateral triangle) of the recess 720 may be a single orientation, or may have a first orientation and a second orientation as described above.

[0059] Fig. 14 is a top view illustrating a second example of a method for forming a return portion on the wall surface of a recess. Fig. 15 is a perspective view illustrating a third example of a method for forming a return portion on the wall surface of a recess. Fig. 16 is a cross-sectional view illustrating an example of a recess and an additional recess formed using the punch illustrated in Fig. 15.

[0060] The method for forming the return portion 727 protruding toward the corners of the wall surfaces 721, 722, and 723 of the triangular prism-shaped recess 720 is not limited to the press working using the triangular prism-shaped punch 10 described above. For example, the additional recess 730 for forming the return portion 727 may be formed by press working using a punch having a Y-shaped bottom surface 11 in a plan view, as indicated by the dotted line in FIG. 14 . When using this type of punch, the ratio W2 / W1 of the side length W1 in a plan view of the triangular prism-shaped recess 720 formed by the punch 10 to the side dimension W2 of the additional recess 730 to be formed can be set to any value. Therefore, for example, by adjusting the ratio W2 / W1 and the depth of the additional recess 730, the return portion 727 with the desired protrusion amount L3 can be formed. The shape of the return portion 727 in a plan view can also be adjusted by adjusting the ratio W2 / W1 and the depth of the additional recess 730. As a result, for example, the area of ​​the return portion 727 in a planar view becomes larger (i.e., the flow path of the sealant from the opening end side of the recess 720 to the bottom surface becomes narrower), preventing the sealant 9 from being insufficiently filled between the return portion 727 and the bottom surface of the recess 720.

[0061] Furthermore, the punch 10 used to form the recess 720 and the additional recess 730 may have a bottom surface that is triangular pyramidal convex, as illustrated in FIG. 15 . When such a punch 10 is used, the bottom surface of the recess 720 has a triangular pyramidal convex shape, as illustrated in FIG. 16 , which increases the contact area between the sealing material 9 and the bottom surface of the recess 720. Similarly, the contact area between the sealing material 9 and the bottom surface of the additional recess 730 increases. Furthermore, by forming the additional recess 730 using a punch 10 whose bottom surface is triangular pyramidal convex, for example, the protruding direction of the return portion 727 is inclined by an angle θ toward the bottom surface from the direction perpendicular to the wall surfaces 721, 722, and 723, thereby further enhancing the effect of the return portion 727 in preventing the sealant 9 from slipping out of the recess 720.

[0062] The recess 720 described above has a bottom surface that is an equilateral triangle in plan view. However, the bottom surface of the recess 720 in plan view is not limited to an equilateral triangle and may be another triangular shape. The bottom surface of the recess 720 in plan view is not limited to a triangular shape and may be a polygonal shape having sides that extend in a direction that is not perpendicular to any of the sides of the first bonding portion 701 of the lead 7. When the recess 720 or the additional recess 730 is formed using the punch 10 having a convex bottom surface described above with reference to FIGS. 15 and 16 , the shape of the bottom surface of the punch 10 is not limited to the convex triangular pyramid shape described above and may be another convex shape.

[0063] The recesses 720 having the return portions 727 on the wall surfaces described in the above embodiment may be arranged in a hexagonal lattice pattern over the entire upper surface 710 of the first bonding portion 701 of the lead 7, or may not be arranged in a specific region of the upper surface 710. Furthermore, the recesses 720 are not limited to being formed on the upper surface 710 of the first bonding portion 701 of the lead 7, and may also be formed on the upper surface of the second bonding portion 702, for example.

[0064] As described above, the semiconductor device 1 including the semiconductor module 2 of this embodiment can be applied to a power conversion device such as an inverter for an in-vehicle motor. A vehicle to which the semiconductor device 1 of the present invention is applied will be described with reference to Fig. 17 .

[0065] Fig. 17 is a schematic plan view showing an example of a vehicle to which the semiconductor device according to the present invention is applied. Vehicle 2001 shown in Fig. 17 is, for example, a four-wheeled vehicle having four wheels 2002. Vehicle 2001 may be, for example, an electric vehicle in which the wheels are driven by a motor or the like, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor.

[0066] Vehicle 2001 includes drive unit 2003 that applies power to wheels 2002, and control device 2004 that controls drive unit 2003. Drive unit 2003 may be configured with at least one of an engine, a motor, or a hybrid of an engine and a motor, for example.

[0067] The control device 2004 controls (for example, controls power) the above-described drive unit 2003. The control device 2004 includes the above-described semiconductor device 1. The semiconductor device 1 may be configured to control power to the drive unit 2003.

[0068] In the semiconductor module 2 of the semiconductor device 1 used in this type of vehicle 2001, if the first bonding portion 701 of the lead 7 described above is bonded to an electrode on the top surface of the semiconductor element (for example, the second main electrode of the semiconductor element 510) with the bonding material S3, it is possible to prevent the progression of peeling at the interface between the sealing material 9 and the top surface 710 of the first bonding portion 701. This makes it possible to reduce the frequency of inspection and replacement of the semiconductor device 1 used in the vehicle 2001.

[0069] The vehicle to which the semiconductor device 1 is applied is not limited to the four-wheeled vehicle as exemplified in Fig. 17. The vehicle to which the semiconductor device 1 is applied includes railway vehicles and the like.

[0070] Although the present embodiment and modifications have been described above, other embodiments may be combinations of the above embodiments and modifications in whole or in part.

[0071] Furthermore, the present embodiment is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the scope of the claims covers all embodiments that may fall within the scope of the technical idea.

[0072] The features of the above embodiment will be summarized below.

[0073] The semiconductor module according to the above embodiment comprises a circuit board on which a semiconductor element is mounted, leads joined to electrodes on the upper surface of the semiconductor element by a bonding material, and a sealing material that seals the semiconductor element and the leads, and the leads have, on their upper surface opposite to the lower surface facing the electrode at the bonding portion joined to the electrode, a plurality of recesses whose bottom surface in a planar view is polygonal and has sides extending in a direction that is not perpendicular to any of the sides of the bonding portion, and each of the plurality of recesses has a return portion that protrudes from a wall surface.

[0074] In the semiconductor module according to the above embodiment, the recess has a triangular bottom surface in a plan view, an additional recess that extends outward from the wall surface of the recess and is shallower than the depth of the recess to the bottom surface, and the return portion protrudes from the wall surface at the position of the bottom surface of the additional recess.

[0075] In the semiconductor module according to the above embodiment, the recesses are arranged in a hexagonal lattice pattern in a planar view, and include recesses whose triangular bottom surfaces in a planar view have a first orientation and recesses whose bottom surfaces have a second orientation opposite to the first orientation.

[0076] In the semiconductor module according to the above embodiment, the bottom surface of the additional recess is triangular in plan view.

[0077] In the semiconductor module according to the above embodiment, the plurality of recesses include a plurality of types of recesses having different combinations of the depth to the bottom surface and the depth to the bottom surface of the additional recesses.

[0078] In the semiconductor module according to the above embodiment, the bottom surface of the additional recess is rectangular in plan view.

[0079] In the semiconductor module according to the above embodiment, at least one of the bottom surface of the recess and the bottom surface of the additional recess has a concave shape.

[0080] The semiconductor device according to the above embodiment includes the above semiconductor module, and a cooler disposed on the surface of the circuit board of the semiconductor module opposite to the surface on which the semiconductor element is mounted.

[0081] The vehicle according to the above embodiment includes the above semiconductor module or semiconductor device. [Industrial Applicability]

[0082] As described above, the present invention has the effect of being able to prevent the progression of peeling at the interface between the upper surface of the joint portion of the lead that is joined to the electrode of the semiconductor element and the sealing material, and is particularly useful for industrial or electrical semiconductor modules, semiconductor devices, and vehicles.

[0083] This application is based on Japanese Patent Application No. 2022-161588, filed October 6, 2022, the contents of which are incorporated herein in their entirety.

Claims

1. a circuit board on which a semiconductor element is mounted; a lead bonded to an electrode on the upper surface of the semiconductor element by a bonding material; a sealing material that seals the semiconductor element and the leads; Equipped with the lead has, on an upper surface of a joint portion joined to the electrode opposite a lower surface facing the electrode, a plurality of recesses, each of which has a polygonal shape in a plan view and has sides extending in a direction that is not perpendicular to any of the sides of the joint portion; Each of the plurality of recesses has a protruding portion protruding from a wall surface. Semiconductor module.

2. the recess has a triangular bottom surface in a plan view, and includes an additional recess that extends from the wall surface outward of the recess and is shallower than the depth of the recess to the bottom surface, The return portion protrudes from the wall surface at the position of the bottom surface of the additional recess. The semiconductor module according to claim 1 .

3. The recesses are arranged in a hexagonal lattice pattern in a plan view, and include recesses whose triangular bottom surfaces are oriented in a first direction in a plan view and recesses whose triangular bottom surfaces are oriented in a second direction opposite to the first direction. The semiconductor module according to claim 2 .

4. The bottom surface of the additional recess is triangular in plan view. The semiconductor module according to claim 2 .

5. The plurality of recesses include a plurality of types of recesses having different combinations of the depth to the bottom surface and the depth to the bottom surface of the additional recesses. The semiconductor module according to claim 4 .

6. The bottom surface of the additional recess is rectangular in plan view. The semiconductor module according to claim 2 .

7. At least one of the bottom surface of the recess and the bottom surface of the additional recess has a concave shape. The semiconductor module according to claim 2 .

8. A semiconductor module according to any one of claims 1 to 7; a cooler disposed on a surface of the circuit board of the semiconductor module opposite to a surface on which the semiconductor element is mounted; A semiconductor device comprising:

9. A vehicle comprising the semiconductor module according to any one of claims 1 to 7.

10. A vehicle equipped with the semiconductor device described in claim 8.

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