Photodetector, method for manufacturing photodetector, and electronic device

Abstract

Provided is a light detecting device with which it is possible to suppress a decrease in a saturated charge accumulation amount. The light detecting device comprises: a first semiconductor layer which includes a photoelectric conversion portion, and of which one surface is a light-incident surface and another surface is a first surface; a second semiconductor layer which is stacked on the first surface and which has a charge accumulating region; and a gate electrode which is adjacent to the second semiconductor layer across an insulating film, and which is capable of forming a channel that communicates in the stacking direction of the first semiconductor layer and the second semiconductor layer between the photoelectric conversion portion and the charge accumulating region.

Description

[Technical Field]

[0001] The present technology (technology related to the present disclosure) relates to a photodetector, a method for manufacturing a photodetector, and an electronic device, and particularly to a photodetector having a charge accumulation region, a method for manufacturing a photodetector, and an electronic device. [Background technology]

[0002] In order to control the timing of signal charge readout for each pixel, image sensors may temporarily store the signal charge obtained by photoelectric conversion using a photodiode (PD) in a charge storage region such as a floating diffusion (FD) region via a transfer channel having a transfer gate (TG).

[0003] Various ideas have been proposed for the transfer path of signal charges from the PD to the FD region. For example, in Patent Document 1, the width of the TG in a planar view of the image sensor is expanded from the PD to the FD region, thereby concentrating the transfer path in the FD region. In Patent Document 2, the TG is formed using a fin-type transistor, thereby extending the transfer path toward the silicon substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-17753 [Patent Document 2] Japanese Patent Application Publication No. 2017-27982 Summary of the Invention [Problem to be solved by the invention]

[0005] In the general image sensors described above, the FD region and transfer channel are formed in the same semiconductor substrate as the PD, which can impair the volume of the PD and reduce the amount of saturated charge storage in the pixel as the pixel becomes smaller.

[0006] The present technology aims to provide a photodetector capable of suppressing a decrease in the amount of accumulated saturated charge, a method for manufacturing a photodetector, and an electronic device. [Means for solving the problem]

[0007] A photodetector according to one aspect of the present technology includes a first semiconductor layer having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is a first surface; a second semiconductor layer stacked on the first surface and having a charge accumulation region; and a gate electrode adjacent to the second semiconductor layer via an insulating film, capable of forming a channel between the photoelectric conversion unit and the charge accumulation region in the stacking direction of the first semiconductor layer and the second semiconductor layer.

[0008] A method for manufacturing a photodetector according to one aspect of the present technology includes preparing a first semiconductor layer, stacking a second semiconductor layer on a first surface of the first semiconductor layer, the first surface being the surface opposite to the light incident surface side, partitioning the second semiconductor layer into an island shape in a planar view, and forming a gate electrode in a region adjacent to the second semiconductor layer via an insulating film, the gate electrode being capable of forming a channel that runs in the stacking direction of the first semiconductor layer and the second semiconductor layer between a photoelectric conversion unit provided in the first semiconductor layer and a charge accumulation region provided in the second semiconductor layer.

[0009] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a chip layout diagram showing an example of a configuration of a photodetector according to a first embodiment of the present technology. [Figure 2] 1 is a block diagram showing an example of the configuration of a photodetector according to a first embodiment of the present technology; [Figure 3] 1 is an equivalent circuit diagram of a pixel of a photodetector according to a first embodiment of the present technology. [Figure 4A] 1 is a longitudinal sectional view of a photodetector according to a first embodiment of the present technology. [Figure 4B] 4B is a cross-sectional view showing a cross section of the photodetector when viewed along the AA cutting line in FIG. 4A. FIG. [Figure 4C] 4B is a cross-sectional view showing a cross section of the photodetector when viewed in cross section along the line BB in FIG. 4A. FIG. [Figure 5] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a photodetector according to a first embodiment of the present technology. [Figure 6] 6 is a cross-sectional view showing a process subsequent to FIG. 5. [Figure 7A] 7A to 7C are cross-sectional process views showing the cross sections following FIG. 6. [Figure 7B] 7A to 7C are cross-sectional process views showing vertical sections following FIG. 6. [Figure 8A] 7B is a cross-sectional view showing the process steps, following FIG. 7A. [Figure 8B] 7B is a cross-sectional view showing a longitudinal section of the process. [Figure 9] 8C is a cross-sectional view showing a process subsequent to FIG. 8B. [Figure 10] 10A to 10C are cross-sectional views showing the process steps following FIG. 9. [Figure 11] 11A to 11C are cross-sectional views showing the process steps following FIG. 10. [Figure 12] 12A to 12C are cross-sectional views of the process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a process subsequent to FIG. 12. [Figure 14] 14 is a cross-sectional view showing a process subsequent to FIG. 13. [Figure 15] FIG. 10 is a longitudinal sectional view of a photodetector according to a comparative example. [Figure 16A] 10 is a longitudinal sectional view of a photodetector according to a second modified example of the first embodiment of the present technology. FIG. [Figure 16B] 16B is a cross-sectional view showing a cross section of the photodetector when viewed along the line BB in FIG. 16A. [Figure 17A]10 is a longitudinal sectional view of a photodetector according to a third modified example of the first embodiment of the present technology. FIG. [Figure 17B] 17B is a cross-sectional view showing a cross section of the photodetector when viewed along the AA cutting line in FIG. 17A. FIG. [Figure 17C] 17B is a cross-sectional view showing a cross section of the photodetector when viewed in cross section along the line BB in FIG. 17A. FIG. [Figure 18A] 10 is a longitudinal sectional view of a photodetector according to a fourth modified example of the first embodiment of the present technology. FIG. [Figure 18B] 18B is a cross-sectional view showing a cross section of the photodetector when viewed in cross section along the AA cutting line in FIG. 18A. FIG. [Figure 19A] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a photodetector according to a fifth modified example of the first embodiment of the present technology. [Figure 19B] 19B is a cross-sectional view showing a process subsequent to FIG. 19A. [Figure 20] 10 is a longitudinal sectional view of a photodetector according to Example 1 of a second embodiment of the present technology. FIG. [Figure 21] FIG. 10 is a longitudinal sectional view of a photodetector according to Example 2 of the second embodiment of the present technology. [Figure 22] FIG. 10 is a longitudinal sectional view of a photodetector according to Example 3 of the second embodiment of the present technology. [Figure 23] FIG. 10 is a longitudinal sectional view of a photodetector according to Example 4 of the second embodiment of the present technology. [Figure 24] FIG. 10 is a longitudinal sectional view of a photodetector according to a third embodiment of the present technology. [Figure 25] FIG. 10 is a longitudinal sectional view of a photodetector according to a fourth embodiment of the present technology. [Figure 26] FIG. 10 is a diagram showing a schematic configuration of an electronic device according to a fifth embodiment of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0012] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0014] The explanation will be given in the following order. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment

[0015] [First embodiment] In this first embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0016] <Overall configuration of the photodetector> First, the overall configuration of the photodetector 1 will be described. As shown in Fig. 1, the photodetector 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in plan. That is, the photodetector 1 is mounted on the semiconductor chip 2. As shown in Fig. 26, the photodetector 1 takes in image light (incident light 106) from an object via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the signal as a pixel signal.

[0017] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes a square pixel region 2A located in the center of a two-dimensional plane including an X direction and a Y direction that intersect with each other, and a peripheral region 2B located outside the pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 26. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other on the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (the thickness direction or stacking direction of the photodetector 1 and each layer that constitutes it).

[0019] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] <Logic circuit> 2, the semiconductor chip 2 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complenentary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0022] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to the pixels. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0023] The horizontal drive circuit 6 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0024] The output circuit 7 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signals. Examples of signal processing that can be used include buffering, black level adjustment, column variation correction, and various types of digital signal processing.

[0025] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] <pixel> 3 is an equivalent circuit diagram showing an example of the configuration of pixel 3. Pixel 3 includes a photoelectric conversion element PD, a charge accumulation region FD that accumulates (holds) signal charges photoelectrically converted by this photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by this photoelectric conversion element PD to the charge accumulation region FD. Pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0028] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor driving line among the pixel driving lines 10 (see FIG. 2).

[0029] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0030] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are configured as MOSFETs having, for example, a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. These transistors may also be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride film (Si3N4 film) or a stacked film of a silicon nitride film, a silicon oxide film, or the like.

[0031] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0032] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain region electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0033] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0034] <<Specific configuration of the photodetector>> Next, a specific configuration of the photodetector 1 will be described with reference to FIGS. 4A, 4B, and 4C.

[0035] <Layer structure of photodetector> As shown in Figure 4A, the photodetector 1 (semiconductor chip 2) includes a first semiconductor layer 20 having a photoelectric conversion section described below and a first surface S1 and a second surface S2 located opposite to each other, a second semiconductor layer 30 having a third surface S3 and a fourth surface S4 located opposite to each other, stacked on the first surface S1, and having a charge storage region described below, a first wiring layer 40 superimposed on the surface (fourth surface S4) opposite to the surface (third surface S3) of the second semiconductor layer 30 facing the first semiconductor layer 20, a second wiring layer 50 superimposed on the surface (fifth surface S5) opposite to the surface of the first wiring layer 40 facing the second semiconductor layer 30, and a third semiconductor layer 60 superimposed on the surface (sixth surface S6) of the second wiring layer 50 facing the first wiring layer 40. Such a stacked structure can be realized, for example, by stacking a second semiconductor layer 30 and a first wiring layer 40 on a first semiconductor layer 20, stacking a second wiring layer 50 on a third semiconductor layer 60, and then overlapping and bonding the fifth surface S5 of the first wiring layer 40 and the sixth surface S6 of the second wiring layer 50.

[0036] Here, the second surface S2 side, which is one surface of the first semiconductor layer 20, is called the light incident surface or back surface, and the other surface of the first semiconductor layer 20, i.e., the first surface S1, which is the surface opposite to the second surface S2, is sometimes called the element formation surface or main surface. Furthermore, the photodetector 1 (semiconductor chip 2) includes a light collecting layer 70 laminated on the second surface S2.

[0037] <Light-collecting layer> Although not limited to this, the light-collecting layer 70 has a laminated structure in which, for example, an insulating layer 71, a light-shielding layer 72, a planarizing film 73, a color filter 74, and an on-chip lens 75 are laminated in this order from the second surface S2 side.

[0038] (insulating layer) The insulating layer 71 is an insulating film laminated on the second surface S2 side of the first semiconductor layer 20 by, for example, a CVD (Chemical Vapor Deposition) method. The insulating layer 71 can be made of, for example, a material such as silicon oxide (SiO2), although it is not limited thereto.

[0039] (light shielding layer) The light-shielding layer 72 is laminated on the insulating layer 71. The light-shielding layer 72 is disposed in the boundary region of the pixels 3, and blocks stray light leaking in from adjacent pixels. This light-shielding layer 72 may be made of any material that blocks light, but may also be made of a metal film such as aluminum (Al), tungsten (W), or copper (Cu), which has strong light-shielding properties and can be precisely processed by microfabrication, for example, etching.

[0040] (Planarization film) The planarization film 73 is provided so as to cover the insulating layer 71 and the light-shielding layer 72, and planarizes the surface on which the color filter 74 is provided.

[0041] (Color filter) The color filter 74 separates the color of the incident light that is incident from the light incident surface side of the photodetector 1 and passes through the on-chip lens 75, and supplies the color-separated incident light to the pixels 3. The color filter 74 has multiple types of filters that separate different colors, such as, but not limited to, red, blue, and green. The color filter 74 then supplies light of a different color to each pixel.

[0042] (On-chip lens) The on-chip lens 75 has a function of focusing incident light onto the photoelectric conversion unit 22. This on-chip lens 75 is disposed for each pixel 3. The on-chip lens 75 can be made of an organic material such as, but not limited to, a styrene-based resin, an acrylic-based resin, a styrene-acrylic-based resin, or a siloxane-based resin.

[0043] <First semiconductor layer> The first semiconductor layer 20 is made of a single-crystal silicon substrate. As shown in Fig. 4A, the first semiconductor layer 20 has a semiconductor region 21 of a first conductivity type, for example, a p-type, and a semiconductor region 22 of a second conductivity type, for example, an n-type, buried inside the semiconductor region 21.

[0044] (Photoelectric conversion area) The first semiconductor layer 20 has island-shaped photoelectric conversion regions 23 partitioned by isolation regions 25. That is, the photoelectric conversion regions 23 are separated from each other by the isolation regions 25. Furthermore, a semiconductor region 21c of a conductivity type different from that of the semiconductor region 22, for example, a p-type, is provided between the semiconductor region 22 and the isolation region 25. The photoelectric conversion region 23 is provided for each pixel 3. The number of pixels 3 is not limited to the number shown in the figure.

[0045] The photoelectric conversion region 23 includes the semiconductor region 21 and semiconductor region 22 described above. When light is incident on the semiconductor region 22, the semiconductor region 22 photoelectrically converts the incident light and generates signal charges. Hereinafter, this semiconductor region 22 will be referred to as the photoelectric conversion section 22. The photoelectric conversion element PD shown in FIG. 3 is configured in a region including the semiconductor region 21 and photoelectric conversion section 22 shown in FIG. 4A. In addition, the photoelectric conversion section 22 shown in FIG. 4A functions as the source region of the transfer transistor TR shown in FIG. 3.

[0046] (separation area) The isolation region 25 has a trench structure in which grooves 24 are formed in the first semiconductor layer 20 and the second semiconductor layer 30 and a material such as an insulating material is buried in the grooves 24. The isolation region 25 is provided so as to penetrate between the fourth surface S4 of the second semiconductor layer 30 and the second surface S2 of the first semiconductor layer 20. In other words, the isolation region 25 is FTI (Full Trench Isolation).

[0047] <Second semiconductor layer> 4A, the second semiconductor layer 30 is a semiconductor layer stacked on the first surface S1. The second semiconductor layer 30 has a stacked structure in which a first layer 31 and a second layer 32 are stacked in this order from the first surface S1. The first layer 31 is a silicon germanium (SiGe) layer epitaxially grown on the first surface S1, and is a semiconductor region of a first conductivity type, for example, p-type. The second layer 32 is a silicon (Si) layer epitaxially grown on the surface of the first layer 31 opposite to the first semiconductor layer 20 side.

[0048] (Device formation area) The second semiconductor layer 30 has island-shaped element formation regions 33 partitioned by isolation regions 25. The element formation regions 33 are provided for each pixel 3. The element formation regions 33 include the first layer 31 and second layer 32 described above. More specifically, the element formation region 33 has a channel portion 34 formed by the first layer 31 and an accumulation portion 35 formed by the second layer 32. A transfer gate electrode 38 is also provided in the element formation region 33.

[0049] (Storage section) The accumulation unit 35 has a semiconductor region 36 of a first conductivity type, for example, p-type, and a semiconductor region 37 of a second conductivity type, for example, n-type. The semiconductor region 37 has the same conductivity type as the photoelectric conversion unit 22, i.e., the second conductivity type. The semiconductor region 37 is a floating diffusion region that temporarily accumulates signal charges transferred from the photoelectric conversion unit 22. Hereinafter, this semiconductor region 37 will be referred to as the charge accumulation region 37. The charge accumulation region 37 shown in FIG. 4A functions as the drain region of the transfer transistor TR shown in FIG. 3.

[0050] As described above, the element formation region 33 of the second semiconductor layer 30 has the channel portion 34 and the accumulation portion 35 in this order from the first semiconductor layer 20 side. That is, the element formation region 33 has a stacked structure in which the channel portion 34 and the accumulation portion 35 are stacked in this order from the first semiconductor layer 20 side. The charge accumulation region 37 is provided only in the accumulation portion 35 of the channel portion 34 and the accumulation portion 35. That is, the charge accumulation region 37 is provided at a position near the surface of the second semiconductor layer 30 opposite to the first semiconductor layer 20 side.

[0051] The charge accumulation region 37 is surrounded by a semiconductor region 36 of a conductivity type different from that of the charge accumulation region 37. Surrounding the charge accumulation region 37 with the semiconductor region 36 prevents noise from flowing into the charge accumulation region 37. Furthermore, the semiconductor region 36 is interposed between the charge accumulation region 37 and the channel portion 34. A portion of the charge accumulation region 37 faces the fourth face S4.

[0052] (Channel section) 4A, the channel portion 34 is provided between the accumulation portion 35 and the first semiconductor layer 20 in the Z direction. As shown in FIG. 4C, the channel portion 34 is located inside the accumulation portion 35 in a planar view. That is, the diameter of the channel portion 34 is set smaller than the diameter of the accumulation portion 35 in a planar view. Note that the diameter refers to the distance between the side surfaces, and does not matter what the planar shapes of the channel portion 34 and the accumulation portion 35 are.

[0053] The channel portion 34 shown in Fig. 4A can function as the channel of the transfer transistor TR shown in Fig. 3. More specifically, the channel portion 34 is modulated from the side surface 34a by a transfer gate electrode 38, which will be described later. Here, the side surface 34a of the channel portion 34 is a surface facing in a direction intersecting the stacking direction (Z direction).

[0054] (transfer gate electrode) 4A functions as the gate electrode of the transfer transistor TR shown in Fig. 3. The transfer gate electrode 38 is adjacent to the channel section 34, the accumulation section 35, and the first surface S1 of the first semiconductor layer 20, via an insulating film 39 that functions as a gate insulating film of the transfer transistor TR. The transfer gate electrode 38 extends along the thickness direction of the second semiconductor layer 30, and is a gate electrode that can form a channel that communicates with the photoelectric conversion section 22 and the charge accumulation region 37 in the stacking direction (thickness direction) of the first semiconductor layer 20 and the second semiconductor layer 30.

[0055] The transfer gate electrode 38 also includes a first portion 381 adjacent to the side surface 35a of the accumulation portion 35 via the insulating film 39, and a second portion 382 adjacent to the side surface 34a of the channel portion 34 via the insulating film 39. The inner diameter of the second portion 382 is set smaller than the inner diameter of the first portion 381. Note that the inner diameter is the distance between inner circumferential surfaces sandwiching the center, and does not matter what the planar shape of the transfer gate electrode 38 is.

[0056] The transfer transistor TR transfers signal charges obtained by photoelectric conversion in the photoelectric conversion unit 22 to the charge accumulation region 37. More specifically, the transfer transistor TR forms a channel by modulating the potential of the semiconductor region in accordance with the gate-source voltage. More specifically, the transfer transistor TR forms a channel by modulating the potential of the semiconductor region spanning the semiconductor region 21, the channel unit 34, and the semiconductor region 36 of the accumulation unit 35. As a result, the transfer transistor TR transfers signal charges via the channel from the photoelectric conversion unit 22, which functions as the source region, to the charge accumulation region 37, which functions as the drain region.

[0057] 4B and 4C, the transfer gate electrode 38 surrounds the entire circumferential area of ​​the element formation region 33 of the second semiconductor layer 30 in a plan view. The transfer gate electrode 38 modulates the element formation region 33 from the side surface. More specifically, the transfer gate electrode 38 surrounds the accumulation portion 35 and the channel portion 34 in a plan view, and is adjacent to the side surface 35a of the accumulation portion 35, the lower surface 35b of the accumulation portion 35, the side surface 34a of the channel portion 34, and the first surface S1 via an insulating film 39. The transfer gate electrode 38 modulates the potential of the semiconductor region via these surfaces in accordance with the gate-source voltage.

[0058] The channel portion 34 is modulated from the entire circumferential area by the side surface 34a, so a wider area is modulated compared to when it is not surrounded. Furthermore, the channel portion 34 is etched from the side surface 34a side, thereby reducing the diameter. As a result, the channel portion 34 is modulated, for example, up to the vicinity of the center, more preferably up to the center, although this is not limited to this. The channel portion 34 is modulated from the transfer gate electrode 38 along a direction perpendicular to the Z direction.

[0059] The transfer gate electrode 38 is made of, for example, a metal such as aluminum (Al) or copper (Cu), or a material such as polysilicon (Poly-Si). Although not limited to this, it is assumed here that the transfer gate electrode 38 is made of aluminum (Al).

[0060] <1st wiring layer> 4A, the first wiring layer 40 includes an interlayer insulating film 41, a metal layer 42, a first connection pad 43, a contact 44, and a via 45. The metal layer 42 and the first connection pad 43 are stacked with the interlayer insulating film 41 interposed therebetween as shown. One end of the contact 44 in the Z direction is connected to the charge accumulation region 37. The other end of the contact 44 in the Z direction may be connected to the metal layer 42. The via 45 connects the metal layers 42 to each other and between the metal layer 42 and the first connection pad 43. The first connection pad 43 faces the fifth surface S5 of the first wiring layer 40.

[0061] <Second wiring layer> The second wiring layer 50 includes an interlayer insulating film 51, a metal layer 52, a second connection pad 53, and a via 54. The metal layer 52 and the second connection pad 53 are stacked with the interlayer insulating film 51 interposed therebetween, as shown in the figure. The via 54 connects the metal layers 52 to each other and to the second connection pad 53. The second connection pad 53 faces the sixth surface S6 of the second wiring layer 50 and is joined to the first connection pad 43. This electrically connects the metal layers of the first wiring layer 40 and the second wiring layer 50 to each other. In addition, the second wiring layer 50 may be provided with a gate electrode 55 of a transistor provided in the third semiconductor layer 60.

[0062] <Third semiconductor layer> The third semiconductor layer 60 is made of, for example, but not limited to, a single crystal silicon substrate. The third semiconductor layer 60 is provided with pixel transistors of the readout circuit 15. Furthermore, but not limited to, the third semiconductor layer 60 may also be provided with transistors that constitute the logic circuit 13. Although not limited to, these transistors will be described here as being provided in positions closer to the second wiring layer 50 side of the third semiconductor layer 60.

[0063] <effect> The operation of the photodetector 1 will be described below. When light is irradiated onto the on-chip lens 75 side of the photodetector 1, photoelectric conversion is performed in the photoelectric conversion unit 22, generating signal charges. Then, the transfer transistor TR is turned on, modulating the potential of the semiconductor region between the photoelectric conversion unit 22 and the charge accumulation region 37, i.e., the potential of the semiconductor region 21a, the channel region 34, and the semiconductor region 36, to form a channel extending in the Z direction. Then, the signal charges are transferred from the photoelectric conversion unit 22 to the charge accumulation region 37 through the formed channel. At this time, as shown in FIG. 4A , the electron transfer path R from the photoelectric conversion unit 22 to the charge accumulation region 37 is along the extension direction of the transfer gate electrode 38, i.e., the Z direction. The charge accumulation region 37 is connected to the contact 44, and the signal charges are transferred thereto via the contact 44.

[0064] In the photodetector 1, the charge accumulation regions 37 are electrically isolated from each other. As shown in Fig. 3, each charge accumulation region 37 is connected to one readout circuit 15, and signal charges are read out independently from each charge accumulation region 37. Therefore, the signal charges may be transferred by modulating all of the channel portions 34 simultaneously (global shutter operation) or by modulating the channel portions 34 sequentially (rolling shutter operation).

[0065] <Method for manufacturing a photodetector> A manufacturing method of the photodetector 1 will be described below with reference to FIGS. 5 to 14. First, as shown in FIG. 5, a first semiconductor layer 20 made of silicon is prepared. A second semiconductor layer 30 is epitaxially grown on a first surface S1, which is the surface of the first semiconductor layer 20 opposite the light incident surface. More specifically, a first layer 31 and a second layer 32 as the second semiconductor layer 30 are epitaxially grown on the first surface S1 in this order. At this time, the first layer 31 and the second layer 32 are stacked while maintaining their crystallinity. Note that when stacking the first layer 31 and the second layer 32, impurities are added to the layers. More specifically, p-type silicon germanium is deposited on the first surface S1 as the first layer 31. Then, p-type silicon is deposited on the first layer 31, i.e., on the surface of the first layer 31 opposite the first semiconductor layer 20, as the second layer 32.

[0066] Generally, when materials with different lattice patterns are stacked together, the film thickness must be thinner than the critical film thickness (the film thickness at which stacking faults occur) in order to suppress the occurrence of stacking faults. Here, two types of materials, silicon and silicon germanium, are used, and the film thickness of the silicon germanium must be thinner than the critical film thickness. Here, although not limited to this, for example, when the germanium content in the silicon germanium is 10% (Si 0.9 Ge 0.1 In this case, since the critical thickness of silicon germanium is about 30 nm, it is sufficient to form the silicon germanium film to a thickness less than 30 nm.

[0067] 6, impurities are implanted into the first semiconductor layer 20 to form p-type semiconductor regions 21a and 21b and an n-type semiconductor region 22a. These semiconductor regions are formed in the order of semiconductor region 21a, semiconductor region 22a, and semiconductor region 21b along the Z direction from the first surface S1 side.

[0068] Thereafter, as shown in FIGS. 7A and 7B , grid-shaped grooves 30a recessed in the Z direction are formed in the second semiconductor layer 30 using known lithography and etching techniques. The grooves 30a penetrate the second semiconductor layer 30 in the thickness direction, and more specifically, extend to the interface between the first layer 31 and the first semiconductor layer 20. This divides the second semiconductor layer 30 into island-shaped element formation regions 33 in a planar view. A sacrificial layer 30b is then embedded in the grooves 30a. The material constituting this sacrificial layer 30b has etching selectivity with respect to the materials constituting the first semiconductor layer 20, the second semiconductor layer 30, and the isolation region 25. In other words, the material constituting the sacrificial layer 30b has a higher etching rate than the material constituting the isolation region 25. Additionally, unnecessary portions of the sacrificial layer 30b may be removed using known etch-back techniques.

[0069] 8A and 8B, lattice-shaped grooves 24 recessed in the Z direction are formed in the region where the sacrificial layer 30b is provided using known lithography and etching techniques. The grooves 24 penetrate the sacrificial layer 30b in the thickness direction and reach the semiconductor region 21b of the first semiconductor layer 20. This divides the first semiconductor layer 20 into island-shaped photoelectric conversion regions 23 in a plan view.

[0070] Next, as shown in Fig. 9, impurities are introduced into the sidewalls of the trenches 24 using a known plasma doping technique. As a result, p-type semiconductor regions 21c are formed along the sidewalls of the trenches 24. These semiconductor regions 21c function as pinning layers. The p-type semiconductor region 21 includes these semiconductor regions 21a, 21b, and 21c. The remaining portion of the semiconductor region 22a surrounded by the semiconductor region 21 corresponds to the n-type semiconductor region 22.

[0071] 10, a material such as an insulating material is filled into the trenches 24 to form isolation regions 25. Furthermore, using known lithography and ion implantation techniques, impurities are implanted into the second layer 32 of the element formation region 33 to form n-type semiconductor regions, i.e., charge accumulation regions 37. The portion of the second layer 32 that remains as a p-type semiconductor region corresponds to a semiconductor region 36.

[0072] Thereafter, the sacrificial layer 30b is removed as shown in FIG. 11 . Then, as shown in FIG. 12 , the first layer 31 in the element formation region 33 is selectively etched. More specifically, the first layer 31 of the first semiconductor layer 20, the first layer 31, and the second layer 32 is selectively etched by utilizing the difference in etching rate with the selected etchant among the material constituting the first semiconductor layer 20, the material constituting the first layer 31, and the material constituting the second layer 32. Here, the material constituting the first layer 31 is silicon germanium, which has a higher etching rate with the selected etchant than the silicon constituting the first semiconductor layer 20 and the second layer 32. Furthermore, at this time, the material constituting the first layer 31 is etched from the surface facing in a direction perpendicular to the stacking direction, i.e., the side surface 31a. In other words, the material constituting the first layer 31 is etched in a direction perpendicular to the stacking direction of the first layer 31. The first layer 31 after etching corresponds to the channel section 34. Furthermore, this process causes the side surface 31a to recede. Therefore, as shown in the vertical cross section of FIG. 12, the groove 30a has a shape in which the portion adjacent to the channel portion 34 widens in a direction perpendicular to the Z direction.

[0073] Next, as shown in FIG. 13 , an insulating film 39m constituting the insulating film 39 and a gate material 38m constituting the transfer gate electrode 38 are sequentially stacked in this order on the exposed surfaces of the first semiconductor layer 20 and the second semiconductor layer 30. As a result, the gate material 38m is embedded in the trench 30a via the insulating film 39m. In this first embodiment, aluminum, a metal, is stacked as the gate material 38m. Metals have good embedding properties. Therefore, even if the portion of the trench 30a adjacent to the channel portion 34 expands in a direction perpendicular to the Z direction, the gate material 38m can be embedded satisfactorily.

[0074] 14, unnecessary portions of the insulating film 39m and the gate material 38m are removed using a known method such as, but not limited to, etch-back. Through these steps, a transfer gate electrode 38 is formed in a region adjacent to the second semiconductor layer 30 (the first layer 31 and the second layer 32) via the insulating film 39. The transfer gate electrode 38 can form a channel that runs in the stacking direction of the first semiconductor layer 20 and the second semiconductor layer 30, between the photoelectric conversion unit 22 provided in the first semiconductor layer 20 and the charge accumulation region 37 provided in the second semiconductor layer 30. Note that the step of removing unnecessary portions of the insulating film 39m may be performed before stacking the gate material 38m.

[0075] 4A is then formed. The contacts 44 of the first wiring layer 40 are formed so that one end in the Z direction is electrically connected to the charge accumulation region 37. Then, the first semiconductor layer 20 is polished from the light incident surface side by a CMP (Chemical Mechanical Polishing) method or the like to make it thinner, and then the light collecting layer 70 is formed on the light incident surface side.

[0076] Thereafter, the fifth surface S5 of the first wiring layer 40 is superimposed and bonded to a sixth surface S6 of a separately prepared second wiring layer 50 laminated on the third semiconductor layer 60. This nearly completes the photodetector 1. The photodetector 1 is formed in each of a plurality of chip formation regions defined by scribe lines (dicing lines) on the semiconductor substrate. Then, the plurality of chip formation regions are individually divided along the scribe lines to form semiconductor chips 2 on which the photodetector 1 is mounted.

[0077] <<Major Effects of the First Embodiment>> Below, the main effects of the first embodiment will be described, but before that, a photodetector 1' according to a comparative example will be described with reference to FIG.

[0078] In the photodetector 1′, the charge accumulation region 27 of a second conductivity type, for example, n-type, is provided in the first semiconductor layer 20, similar to the photoelectric conversion section 22. That is, the charge accumulation region 27 is a region of the first semiconductor layer 20, similar to the photoelectric conversion section 22. Since both the charge accumulation region 27 and the photoelectric conversion section 22 are provided in the first semiconductor layer 20, the transfer channel of the transfer transistor TR is also formed in the first semiconductor layer 20.

[0079] In the photodetector device 1', the charge storage region 27, the transfer channel, and the photoelectric conversion section 22 are all formed within the first semiconductor layer 20, which reduces the volume occupied by the photoelectric conversion section 22 within the first semiconductor layer 20, and as the pixel becomes smaller, the saturated charge storage amount (Qs) within the pixel may decrease.

[0080] One method for suppressing the decrease in Qs is to expand the region occupied by the photoelectric conversion section 22 along the thickness direction of the first semiconductor layer 20. However, this method requires implanting impurities deep into the first semiconductor layer 20 in the thickness direction to form the photoelectric conversion section 22. In this case, the impurities must be implanted into the first semiconductor layer 20 with high energy. Injecting impurities with high energy can cause defects in the semiconductor layer, which can degrade noise characteristics such as white spots and dark current. Furthermore, the depth to which the impurities can be implanted in the thickness direction of the first semiconductor layer 20 depends on the device used to implant the impurities.

[0081] Another method for suppressing the decrease in Qs is to increase the difference in impurity concentration between the semiconductor region 21 of a first conductivity type, for example, p-type, and the photoelectric conversion unit 22 of a second conductivity type, for example, n-type, thereby deepening the potential of the photoelectric conversion unit 22. In this case, the signal charge must first be transferred from a deep potential position in the photoelectric conversion unit 22 along a transfer path R1 shown in FIG. 15 toward the semiconductor region 26 of the first conductivity type, for example, p-type, provided near the first surface S1. Then, the signal charge is transferred toward the charge accumulation region 27 along a transfer path R2 different from the transfer path R1.

[0082] However, simply deepening the potential of the photoelectric conversion unit 22 could result in poor transfer of signal charges. More specifically, poor transfer of signal charges along the transfer path R1 could occur. To prevent such poor transfer, it was necessary to control the amount of modulation of the potential of the semiconductor layer by the transfer gate electrode TG of the transfer transistor TR so that the modulation would reach a deeper position in the photoelectric conversion unit 22. However, increasing the amount of modulation of the potential of the semiconductor layer could degrade the controllability of the transfer of signal charges. This will be explained in more detail below.

[0083] In the photodetector 1', the transfer gate electrode TG and the charge accumulation region 27 are adjacent to each other, and therefore dark current noise may occur due to strong charges generated when the transfer gate electrode TG is controlled (when the transfer transistor TR is on during modulation). More specifically, there is a large difference in impurity concentration between the p-type semiconductor region 26 and the n-type charge accumulation region 27, and strong charges generated when the transfer gate electrode TG adjacent to the charge accumulation region 27 is controlled may affect this difference, resulting in dark current noise. The pn junction potential between the semiconductor region 26 and the charge accumulation region 27 changes depending on whether the transfer transistor TR is on or off, affecting the noise characteristics.

[0084] Furthermore, even when the semiconductor region is not modulated, i.e., when the transfer transistor TR is turned off, there is a possibility that a leakage current will flow toward the charge accumulation region 27. More specifically, in the photodetector 1′, both the charge accumulation region 27 and the photoelectric conversion unit 22 are formed in the first semiconductor layer 20 and are formed by impurity implantation, so the boundary between them is not clear, and even when the semiconductor layer is not modulated, there is a possibility that signal charges will flow as a leakage current into the charge accumulation region 27. As a result, there is a possibility that the S / N ratio will deteriorate in the photodetector 1′.

[0085] As described above, in the photodetector 1', if the pixels are made smaller, it may become difficult to ensure both Qs and transfer characteristics.

[0086] In contrast to this, in the photodetector 1 according to the first embodiment of the present technology, a first layer 31 and a second layer 32 are stacked in this order as the second semiconductor layer 30 on the first semiconductor layer 20, the first layer 31 serves as a channel portion 34 in which a channel of the transfer transistor TR is formed, and the second layer 32 is provided with a charge accumulation region 37. In this way, the channel portion 34 in which a channel is formed and the charge accumulation region 37 are provided in a region other than the first semiconductor layer 20, so that a reduction in the volume of the photoelectric conversion unit 22 can be suppressed. This makes it possible to suppress a reduction in Qs even when the pixel 3 is miniaturized.

[0087] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the photoelectric conversion unit 22, the channel unit 34, and the charge accumulation region 37 are provided in this order along the Z direction. Therefore, the direction in which signal charges are collected from a deep potential position in the photoelectric conversion unit 22 coincides with the direction in which the collected signal charges are transferred to the charge accumulation region 37; in other words, both directions are along the transfer path R in Fig. 4A , allowing the signal charges to flow smoothly.

[0088] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the material constituting the channel section 34 is different from the material constituting the photoelectric conversion section 22 and the charge accumulation region 37. Therefore, in addition to potential control by the transfer transistor TR, the difference in band structure between the different materials is utilized to suppress the flow of signal charges. In addition, because the photoelectric conversion section 22, the channel section 34, and the charge accumulation region 37 are provided in separate semiconductor layers, their boundaries are clearly defined. Therefore, when the transfer transistor TR is in the off state, the flow of signal charges can be further suppressed. This makes it possible to suppress the occurrence of leakage current.

[0089] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the transfer gate electrode 38 is provided so as to surround the channel portion 34 in plan view. As a result, the channel portion 34 is modulated from the entire circumferential area of ​​the side surface 34a, and therefore a wider area is modulated. This allows the flow of signal charges to proceed smoothly.

[0090] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the diameter of the channel portion 34 is smaller than the diameter of the accumulation portion 35. Furthermore, the inner diameter of the second portion 382 of the transfer gate electrode 38, which is adjacent to the side surface 34a of the channel portion 34, is smaller than the inner diameter of the first portion 381, which is adjacent to the side surface 35a of the accumulation portion 35 via the insulating film 39. This allows for better control of modulation of the channel portion 34. More specifically, the channel portion 34 can be subjected to modulation control up to the vicinity of its center, more preferably up to its center. This allows for smoother signal charge flow and easier control to stop the flow of signal charge. Additionally, since the diameter of the accumulation portion 35 is larger than the diameter of the channel portion 34, the area occupied by the charge accumulation region 37 can be prevented from becoming smaller. This prevents a decrease in the amount of signal charge accumulated in the charge accumulation region 37.

[0091] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the charge accumulation region 37 and the transfer gate electrode 38 are relatively far apart. This reduces the influence of control of the transfer gate electrode 38 on the charge accumulation region 37 and the pn junction between the n-type charge accumulation region 37 and the surrounding p-type semiconductor region 36.

[0092] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the charge accumulation region 37 is surrounded by the semiconductor region 36 having a conductivity type different from that of the charge accumulation region 37. This prevents electrons generated by defects at the interface of the semiconductor region from flowing into the charge accumulation region 37 as dark current.

[0093] [Modification 1 of the First Embodiment] A first modification of the first embodiment of the present technology will be described below. The photodetector 1 according to the first modification of the present first embodiment differs from the photodetector 1 according to the first embodiment described above in the materials constituting the first semiconductor layer 20 and the second semiconductor layer 30. The other configuration of the photodetector 1 is basically the same as that of the photodetector 1 according to the first embodiment described above. Note that components that have already been described are given the same reference numerals and their description will be omitted. Note that in the first modification of the present first embodiment, FIGS. 4A to 4C of the first embodiment are also used.

[0094] (Materials constituting the first semiconductor layer) Changing the material constituting the photoelectric conversion section 22 changes the sensitivity to the wavelength of light. Therefore, the material constituting the first semiconductor layer 20 (photoelectric conversion section 22) can be selected depending on the wavelength of light to be detected. For example, by selecting a material specialized for light such as visible light or infrared light, the photodetector 1 can detect light of the desired wavelength. The material constituting the first semiconductor layer 20 is not limited to, but for example, silicon can be used to detect visible light, and silicon germanium can be used to detect infrared light.

[0095] (Materials that make up the first layer) The material constituting the first layer 31 may be selected from materials that can be combined with the material constituting the first semiconductor layer 20 and that can selectively etch the first layer 31. The material constituting the first layer 31 may be selected, for example, from the viewpoint of crystal structure and lattice number, although it is not limited thereto. More specifically, a material that can be epitaxially grown on the material constituting the first semiconductor layer 20 may be selected, for example, from the viewpoint of crystal structure and lattice number, although it is not limited thereto.

[0096] The thickness of the first layer 31 may be determined, for example, depending on the combination of the material constituting the first semiconductor layer 20 and the material constituting the first layer 31. Generally, the greater the difference in lattice number between the materials, the thinner the critical thickness will be. Therefore, the thickness may be adjusted depending on the materials to be combined.

[0097] (Materials that make up the second layer) The material constituting the second layer 32 can be a material that can be combined with the material constituting the first layer 31 and that can selectively etch the first layer 31.

[0098] <Example> Hereinafter, some examples of combinations of the material constituting the first semiconductor layer 20, the material constituting the channel section 34, and the material constituting the charge storage region 37 will be shown, although the combinations are not limited to these.

[0099] Example 1 The combination of the material constituting the first semiconductor layer 20, the material constituting the channel portion 34, and the material constituting the charge accumulation region 37 is a combination of group IV semiconductors containing a group IV element. Although not limited to this, typical group IV elements include carbon (C), silicon (Si), germanium (Ge), and tin (Sn). In the first embodiment described above, the combination of the material constituting the first semiconductor layer 20, the material constituting the channel portion 34, and the material constituting the charge accumulation region 37 is also a combination of group IV semiconductors. Note that other combinations of group IV semiconductors include the combinations shown in Examples 2 to 4 below.

[0100] Example 2 The first semiconductor layer 20 and the charge accumulation region 37 are made of silicon germanium, and the channel portion 34 is made of silicon. By changing the etchant, the etching rate of the silicon that makes up the channel portion 34 can be made higher than the etching rate of the silicon germanium that makes up the first semiconductor layer 20 and the charge accumulation region 37. Furthermore, because the photoelectric conversion portion 22 is made of silicon germanium, it can be applied to a photodetector 1 that detects light other than visible light, more specifically, infrared light.

[0101] Example 3 The first semiconductor layer 20, the channel portion 34, and the charge accumulation region 37 are all made of silicon. Here, the impurity concentration of the silicon making up the channel portion 34 is different from the impurity concentration of the silicon making up the first semiconductor layer 20 and the charge accumulation region 37. By changing the impurity concentration, the etching rate of the material making up the channel portion 34 can be made higher than the etching rate of the material making up the first semiconductor layer 20 and the charge accumulation region 37 in a selected etchant. Therefore, in the step of selectively etching the first layer 31 in FIG. 12 , the channel portion 34 can be formed by selectively etching the first layer 31. Because the first semiconductor layer 20, the channel portion 34, and the charge accumulation region 37 are all made of silicon, the increase in the amount of material making up the photodetector 1 can be suppressed, and the manufacturing process can be simplified.

[0102] Furthermore, even when all of the semiconductor layers, the first semiconductor layer 20, the first layer 31, and the second layer 32, are made of silicon, the boundaries between the first semiconductor layer 20, the first layer 31, and the second layer 32 are clearly defined. More specifically, the boundaries between the impurity concentrations are clearly defined. Because the boundaries between the impurity concentrations are clearly defined, when the transfer transistor TR is in the off state, the flow of signal charges across the boundaries can be suppressed. This can suppress the occurrence of leakage current.

[0103] Example 4 The first semiconductor layer 20, the channel portion 34, and the charge accumulation region 37 are all made of silicon. Here, the surface of the material constituting the channel portion 34 that faces in a direction perpendicular to the stacking direction has a higher etching rate with the selected etchant than the first surface S1 of the material constituting the first semiconductor layer 20. Therefore, in the step of selectively etching the first layer 31 in FIG. 12 , the channel portion 34 can be formed by selectively etching the first layer 31.

[0104] More specifically, the first surface S1 of the first semiconductor layer 20 and the side surface 31a of the first layer 31 shown in Fig. 12 have different plane orientations of silicon crystal. Therefore, the side surface 31a can be selectively etched with respect to the first surface S1 by anisotropic etching that utilizes the anisotropy of the plane orientation with respect to a selected etchant. Furthermore, because the first semiconductor layer 20, the channel section 34, and the charge accumulation region 37 are all made of silicon, it is possible to suppress an increase in the number of materials constituting the photodetector 1, and the manufacturing process can be simplified.

[0105] Furthermore, even when all of the semiconductor layers, the first semiconductor layer 20, the first layer 31, and the second layer 32, are made of silicon, the boundaries between the first semiconductor layer 20, the first layer 31, and the second layer 32 are clearly defined. More specifically, the boundaries between the impurity concentrations are clearly defined. Because the boundaries between the impurity concentrations are clearly defined, when the transfer transistor TR is in the off state, the flow of signal charges across the boundaries can be suppressed. This can suppress the occurrence of leakage current.

[0106] Example 5 The combination of the material constituting the first semiconductor layer 20, the material constituting the channel portion 34, and the material constituting the charge storage region 37 is a combination of III-V compound semiconductors containing a group III element and a group V element. Representative group III elements include, but are not limited to, boron (B), aluminum (Al), gallium (Ga), and indium (In). Representative group V elements include, but are not limited to, nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).

[0107] As an example of a combination of III-V compound semiconductors, the first semiconductor layer 20 can be made of indium gallium arsenide (InGaAs), and the channel section 34 and charge storage region 37 can be made of indium phosphide (InP), although this is not limited thereto. Indium gallium arsenide and indium phosphide can be lattice-matched. This reduces the generation of defects during stacking, thereby suppressing noise generation. Furthermore, when electrons are used as signal charges, the conduction band of indium phosphide relative to the conduction band of indium gallium arsenide acts as a barrier for electrons, thereby suppressing leakage in the channel.

[0108] Example 6 The combination of the material forming the first semiconductor layer 20, the material forming the channel section 34, and the material forming the charge storage region 37 is a combination of a group IV semiconductor and a group III-V compound semiconductor.

[0109] <<Major Effects of Modification 1 of First Embodiment>> The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0110] Furthermore, in the photodetector 1 according to the first modification of the first embodiment, the material constituting the first semiconductor layer 20, the material constituting the channel section 34, and the material constituting the charge accumulation region 37 can be individually selected, thereby increasing the design options for the photodetector 1. For example, by changing the material constituting the first semiconductor layer 20 in which the photoelectric conversion section 22 is provided, the photodetector 1 can detect light of different wavelengths. Even in such a case, the channel section 34 can be selectively etched by changing the manufacturing method.

[0111] [Modification 2 of the First Embodiment] Modification 2 of the first embodiment of the present technology shown in Fig. 16A and Fig. 16B will be described below. The photodetector 1 according to Modification 2 of the present first embodiment differs from the photodetector 1 according to the first embodiment described above in that a plurality of channel portions is provided, but the configuration of the photodetector 1 is otherwise basically the same as that of the photodetector 1 according to the first embodiment described above. Note that components that have already been described are given the same reference numerals, and description thereof will be omitted. Note that a cross-sectional view showing the cross-sectional structure along the AA cutting line in Fig. 16A is the same as Fig. 4B, and therefore will not be shown here.

[0112] (Channel section) As shown in FIG. 16A, the photodetector 1 has a plurality of channel portions 34 for each element formation region 33 (pixel 3). The channel portions 34 are provided for each accumulation portion 35, spaced apart from one another in a planar view. FIG. 16B shows an example in which the photodetector 1 has four channel portions 341, 342, 343, and 344. However, the number of channel portions is not limited to this and may be two or more. The channel portions 341, 342, 343, and 344 are surrounded by transfer gate electrodes 38 in the entire circumferential direction. When modulated by the transfer gate electrodes 38, the channel portions 341, 342, 343, and 344 function as channels for transferring signal charges between one photoelectric conversion portion 22 and one charge accumulation region 37. When the channel portions 341, 342, 343, and 344 are not to be distinguished from one another, they are simply referred to as channel portions 34. The dimension of the diameter 34 b of the channel portion 34 is not particularly limited as long as a plurality of channel portions 34 can be accommodated within one element formation region 33 . Here, the region through which signal charges flow in the channel portion 34 is basically a portion close to the side surface (periphery) of the channel portion 34, that is, a region close to the insulating film 39 that functions as the gate insulating film of the transfer transistor TR. Therefore, by increasing the area of ​​the side surface of the channel portion 34, the region through which signal charges flow, that is, the effective channel region, can be increased. In the second modification of the first embodiment, by providing multiple channel portions 34 for one accumulation portion 35, the side surface area is increased compared to when there is one channel portion 34, and the effective channel region is increased. Therefore, in the second modification of the first embodiment, the amount of signal charges that flow can be increased compared to when there is one channel portion 34.

[0113] Furthermore, by setting the diameter 34b of the channel portion 34 to a few tens of nanometers or less, the quantum confinement effect can be utilized. More specifically, although depending on the semiconductor material, the quantum confinement effect can be utilized by setting the diameter 34b to, for example, 20 nm or less. By narrowing the diameter 34b of the channel portion 34 in this way, the quantum confinement effect can further suppress the generation of leakage current when the transfer transistor TR is in the off state. Furthermore, by utilizing this quantum confinement effect, the channel can be turned off even when no impurities are implanted into the channel portion 34. Here, narrowing the diameter 34b of the channel portion 34 also narrows the region used as the channel, thereby reducing the amount of signal charge flowing through one channel portion 34. However, since multiple channel portions 34 are provided, a reduction in the overall amount of flowing signal charge is suppressed.

[0114] <<Major Effects of Modification 2 of First Embodiment>> The photodetector 1 according to the second modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0115] Furthermore, in the second modification of the first embodiment, by providing a plurality of channel portions 34 for one accumulation portion 35, the side surface area is increased compared to when there is one channel portion 34, and the effective channel region is increased. This makes it possible to increase the amount of signal charge that flows compared to when there is one channel portion 34. Furthermore, in the photodetector 1 according to the second modification of the first embodiment, the width 34b of the channel portion 34 is set to several tens of nanometers or less, and therefore the quantum confinement effect can further suppress the flow of signal charges when the transfer transistor TR is in the off state. That is, in addition to controlling factors other than the gate-source voltage of the transfer transistor TR, the shape of the channel portion 34 can be used to control the flow of signal charges, or more specifically, to stop the flow of signal charges. This can further suppress the occurrence of leakage current.

[0116] [Modification 3 of the First Embodiment] Modification 3 of the first embodiment of the present technology shown in Figures 17A, 17B, and 17C will be described below. The photodetector 1 according to Modification 3 of the present first embodiment differs from the photodetector 1 according to the first embodiment described above in that a single contact 44a is shared by a plurality of charge accumulation regions 37; otherwise, the configuration of the photodetector 1 is basically the same as that of the first embodiment described above. Note that components that have already been described are assigned the same reference numerals, and descriptions thereof will be omitted.

[0117] In the photodetector 1, pixels 3 share one contact 44a. That is, charge accumulation regions 37 provided in different pixels 3 are electrically connected to one another via one contact 44a. FIG. 17B shows an example in which four pixels 3a, 3b, 3c, and 3d, i.e., four charge accumulation regions 37a, 37b, 37c, and 37d, share one contact 44a. However, the number of charge accumulation regions sharing one contact 44a is not limited to this and may be two or more. Note that, when there is no need to distinguish between the pixels 3a, 3b, 3c, and 3d, they will simply be referred to as pixel 3 without distinction. Furthermore, when there is no need to distinguish between the charge accumulation regions 37a, 37b, 37c, and 37d, they will simply be referred to as charge accumulation regions 37 without distinction.

[0118] The signal charges are transferred by sequentially modulating the channel portions 345, 346, 347, and 348 (see FIG. 17C) of the pixels 3a, 3b, 3c, and 3d one by one. Even if multiple charge storage regions 37 share a single contact 44a, by sequentially modulating the channel portions 345, 346, 347, and 348 one by one, the signal charges can be transferred without mixing between pixels. Note that when there is no need to distinguish between the channel portions 345, 346, 347, and 348, they will simply be referred to as channel portion 34.

[0119] <<Major Effects of Modification 3 of First Embodiment>> The photodetector 1 according to the third modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0120] Furthermore, in the photodetector 1 according to the third modification of the first embodiment, other methods for driving the transfer of signal charges can be employed, which increases the design options for the photodetector 1.

[0121] 17B and 17C, the charge accumulation region 37 and the channel portion 34 are provided near the contact 44a in plan view, but are not limited thereto and may be provided at the positions shown in Fig. 4B and 4C. In that case, the area of ​​the contact 44a in plan view may be increased to an extent that it can be shared by the charge accumulation regions.

[0122] [Fourth Modification of the First Embodiment] A fourth modification of the first embodiment of the present technology shown in FIGS. 18A and 18B will be described below. The photodetector 1 according to the fourth modification of the first embodiment differs from the first embodiment described above in that the diameter of the accumulation section and the diameter of the channel section are the same, and the configuration of the photodetector 1 is otherwise basically the same as that of the first embodiment described above. Note that components that have already been described are given the same reference numerals, and their description will be omitted. Note that a cross-sectional view showing the cross-sectional structure along the BB section line in FIG. 18A is the same as FIG. 4C, and therefore will not be shown here.

[0123] The photodetector 1 has a storage section 351. As shown in Fig. 18A, a diameter 351c of the storage section 351 is set to be the same as the diameter of the channel section .

[0124] 7A and 7B, the groove 30a may be formed so that the diameter of the island-shaped element formation region 33 becomes equal to the width 351c. In addition, the step of selectively etching the first layer 31 shown in FIG. 12 is not performed.

[0125] The inner diameter of the second portion 382 of the transfer gate electrode 38 is the same as the inner diameter of the first portion 381.

[0126] <<Major Effects of Modification 4 of First Embodiment>> The photodetector 1 according to the fourth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0127] Furthermore, the photodetector 1 according to the fourth modification of the first embodiment does not perform a step of selectively etching the first layer 31. Therefore, when selecting the material constituting the first semiconductor layer 20, the material constituting the channel section 34, and the material constituting the charge accumulation region 37, there is no need to consider the etching rate for selectively etching the first layer 31, which widens the range of material choices.

[0128] In the fourth variant of the first embodiment, the second semiconductor layer 30 is composed of two semiconductor layers, the first layer 31 and the second layer 32, but this is not limited to this and it may be composed of a single semiconductor layer.

[0129] In addition, in the fourth modification of the first embodiment, the diameter of the accumulation portion 351 is set to the same dimension as the diameter of the channel portion 34, but this is not limitative. The diameter of the channel portion 34 may be set to the same dimension as the diameter of the accumulation portion 35 of the first embodiment, or the diameters of the channel portion 34 and the accumulation portion 35 may be set to dimensions other than those described above.

[0130] [Fifth Modification of the First Embodiment] 19A and 19B, a fifth modification of the first embodiment of the present technology will be described below. The photodetector 1 according to the fifth modification of the first embodiment differs from the first embodiment described above in the process of laminating the first layer 31 and the second layer 32, but the rest of the configuration of the photodetector 1 is basically the same as that of the first embodiment described above. Note that components that have already been described are assigned the same reference numerals and descriptions thereof will be omitted.

[0131] First, as shown in FIG. 19A, a semiconductor layer 201 is prepared separately from the first semiconductor layer 20, and the second layer 32 and the first layer 31 are epitaxially grown on the semiconductor layer 201 in this order. Next, as shown in FIG. 19B, the exposed surface of the first layer 31 is placed on the first surface S1 of the first semiconductor layer 20, and the two are bonded together. Thereafter, the semiconductor layer 201 is peeled off from the second layer 32. In this way, the first layer 31 and the second layer 32 are stacked on the first surface S1 in this order. As a result, the first semiconductor layer 20 on which the second semiconductor layer 30 is epitaxially grown is obtained, as shown in FIG. 5.

[0132] <<Major Effects of Modification 5 of First Embodiment>> The photodetector 1 according to the fifth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0133] [Second embodiment] A second embodiment of the present technology will be described below. The photodetector 1 according to this second embodiment differs from the photodetector 1 according to the first embodiment described above in the structure separating the pixels 3, but the other configuration of the photodetector 1 is basically the same as that of the photodetector 1 according to the first embodiment described above. Note that components that have already been described are assigned the same reference numerals and descriptions thereof will be omitted.

[0134] <Example> Hereinafter, several examples of separation between pixels 3 will be described, although the separation is not limited to these.

[0135] Example 1 20, the first semiconductor layer 20 of the photodetector 1 has a semiconductor region 21c1 of a second conductivity type, for example, a p-type semiconductor region. The semiconductor region 21c1 is formed by introducing impurities into the first semiconductor layer 20 using a known ion implantation technique.

[0136] Example 2 21, the photodetector 1 has an isolation region 25a and an isolation region 25b. Of these, the isolation region 25a separates the element formation regions 33. The isolation region 25a is a shallow trench isolation (STI) provided to penetrate between the third face S3 and the fourth face S4 of the second semiconductor layer 30.

[0137] On the other hand, the isolation region 25b separates the photoelectric conversion regions 23 from one another. The isolation region 25 is a DTI (Deep Trench Isolation) provided in the first semiconductor layer 20 from the second surface S2 side, and does not penetrate the first semiconductor layer 20. The element formation region 33 also has a p-type semiconductor region 21c formed using a known plasma doping technique. At least a portion of the p-type semiconductor region 21 functions as an isolation region (impurity isolation region) that separates the photoelectric conversion regions 23 (photoelectric conversion units 22) from one another.

[0138] Example 3 22, Example 3 is a combination of Example 1 and Example 2. The first semiconductor layer 20 of the photodetector 1 has the semiconductor region 21c1 described in Example 1. Furthermore, the photodetector 1 has the isolation region 25a and isolation region 25b described in Example 2. At least a part of the p-type semiconductor region 21 functions as an isolation region (impurity isolation region) that separates the photoelectric conversion regions 23 (photoelectric conversion units 22) from each other.

[0139] Example 4 23, the photodetector 1 has the isolation region 25a described in Example 3. Furthermore, the first semiconductor layer 20 of the photodetector 1 has a semiconductor region 21c2 (21) of a second conductivity type, for example, a p-type, instead of trench isolation. The semiconductor region 21c2 is an isolation region (impurity isolation region) that separates the photoelectric conversion regions 23 from each other, and is formed by introducing impurities into the first semiconductor layer 20 using a known ion implantation technique.

[0140] <<Major Effects of the Second Embodiment>> The photodetector 1 according to the second embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0141] [Third embodiment] A third embodiment of the present technology shown in FIG. 24 will be described below. The photodetector 1 according to this third embodiment is a combination of Modification 2 of the first embodiment and Example 3 of the second embodiment. In this respect, the photodetector 1 according to this third embodiment differs from the photodetector 1 according to the first embodiment. Other than that, the configuration of the photodetector 1 is basically the same as that of the photodetector 1 according to the first embodiment. Note that components that have already been described are assigned the same reference numerals, and descriptions thereof will be omitted.

[0142] The configuration of the second semiconductor layer 30 is the same as the configuration of the second semiconductor layer 30 described in Modification 2 of the first embodiment above, and the photodetector 1 has a plurality of channel portions 34 that are spaced apart from each other in a planar view. The isolation structure between the pixels 3 is the same as the isolation structure described in Example 3 of the second embodiment above, and the photodetector 1 has isolation region 25a, isolation region 25b, and semiconductor region 21c1.

[0143] <<Major Effects of the Third Embodiment>> The photodetector 1 according to the third embodiment also provides the same effects as the photodetector 1 according to the second modification of the first embodiment described above.

[0144] Furthermore, in the photodetector 1 according to the third embodiment, the pixels 3 are separated from each other by the separation region 25b, which is a DTI, instead of the separation region 25, which is an FTI, thereby simplifying the manufacturing process and further reducing manufacturing costs.

[0145] [Fourth embodiment] A fourth embodiment of the present technology shown in FIG. 25 will be described below. The photodetector 1 according to the fourth embodiment is a combination of Modification 3 of the first embodiment and Example 3 of the second embodiment. In this respect, the photodetector 1 according to the fourth embodiment differs from the photodetector 1 according to the first embodiment. Other than that, the configuration of the photodetector 1 is basically the same as that of the photodetector 1 according to the first embodiment. Note that components that have already been described are assigned the same reference numerals, and descriptions thereof will be omitted.

[0146] The configuration of the second semiconductor layer 30 is the same as the configuration of the second semiconductor layer 30 described in the above-mentioned Modification 3 of the first embodiment, and in the photodetector 1, one contact 44a is shared between the pixels 3. The isolation structure between the pixels 3 is the same as the isolation structure described in the above-mentioned Example 3 of the second embodiment, and the photodetector 1 has isolation region 25a, isolation region 25b, and semiconductor region 21c1.

[0147] <<Major Effects of the Fourth Embodiment>> The photodetector 1 according to the fourth embodiment also provides the same effects as the photodetector 1 according to the third modification of the first embodiment described above.

[0148] Furthermore, in the photodetector 1 according to the fourth embodiment, the pixels 3 are separated from each other by the separation region 25b, which is a DTI, instead of the separation region 25, which is an FTI, thereby simplifying the manufacturing process and further reducing manufacturing costs.

[0149] [Fifth embodiment] <Applications to electronic devices> Next, an electronic device according to a fifth embodiment of the present technology will be described with reference to Fig. 26. The electronic device 100 according to the fifth embodiment includes a photodetector (solid-state imaging device) 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 of the fifth embodiment illustrates an embodiment in which the above-described photodetector 1 is used as the photodetector 101 in an electronic device (for example, a camera).

[0150] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the photodetector 101. This causes signal charges to accumulate in the photodetector 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the photodetector 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the photodetector 101 and the shutter operation of the shutter device 103. The photodetector 101 transfers signals based on the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the photodetector 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0151] With this configuration, the electronic device 100 of the fifth embodiment can suppress a decrease in the amount of saturated charge stored in the photodetector 101, thereby improving the image quality of the video signal.

[0152] The electronic device 100 to which the photodetector 1 can be applied is not limited to a camera, but may also be applied to other electronic devices. For example, the photodetector 1 may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone.

[0153] Furthermore, the photodetector 101 may be the photodetector 1 according to any one of the first to fourth embodiments and their modifications and examples, or a combination of two or more of them.

[0154] [Other embodiments] As described above, the present technology has been described by the first to fifth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0155] For example, it is possible to combine the technical concepts described in the embodiments, modifications, and examples from the first embodiment to the fifth embodiment. For example, various combinations according to the technical concepts of each embodiment are possible, such as applying the materials described in each example of Modification 1 of the first embodiment to Modifications 2 to 5 of the first embodiment, each modification of the second embodiment, the third embodiment, and the fourth embodiment.

[0156] This technology can be applied to not only solid-state imaging devices as image sensors, but also to photodetection devices in general, including distance measuring sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measuring sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until the reflected light is received. The light-receiving pixel structure of this distance measuring sensor can employ the structure of pixel 3 described above.

[0157] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0158] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0159] The present technology may be configured as follows. (1) a first semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is a first surface; a second semiconductor layer stacked on the first surface and having a charge storage region; a gate electrode that is adjacent to the second semiconductor layer via an insulating film and that can form a channel that runs between the photoelectric conversion unit and the charge accumulation region in a stacking direction of the first semiconductor layer and the second semiconductor layer; A photodetector comprising: (2) The photodetector according to (1), wherein the charge accumulation region is provided at a position near a surface of the second semiconductor layer opposite to the first semiconductor layer side. (3) the second semiconductor layer has a laminated structure in which a channel section and an accumulation section are laminated in this order from the first semiconductor layer side, The photodetector according to (1), wherein the charge accumulation region is provided only in the accumulation section of the channel section and the accumulation section. (4) The photodetector according to (3), wherein the diameter of the channel portion is smaller than the diameter of the storage portion. (5) the gate electrode includes a first portion adjacent to a side surface of the storage portion via the insulating film, and a second portion adjacent to a side surface of the channel portion via the insulating film, (6) The photodetector according to (4), wherein the inner diameter of the second portion is smaller than the inner diameter of the first portion. The photodetector according to (4), wherein the material constituting the channel portion has a higher etching rate in any etchant than the material constituting the first semiconductor layer and the material constituting the accumulation portion. (7) The photodetector device of (4), wherein a surface of the material constituting the channel portion that faces in a direction perpendicular to the stacking direction has a higher etching rate in any etchant than the first surface of the material constituting the first semiconductor layer. (8) The photodetector according to any one of (3) to (7), wherein a combination of a material constituting the first semiconductor layer, a material constituting the channel region, and a material constituting the accumulation region is a combination of group IV semiconductors or a combination of group III-V compound semiconductors. (9) The photodetector according to any one of (3) to (8), wherein a plurality of the channel portions are provided for one of the accumulation portions and are spaced apart from each other in a plan view. (10) The photodetector according to any one of (1) to (9), wherein the gate electrode surrounds the second semiconductor layer over the entire circumferential area in a plan view. (11) the photoelectric conversion units are separated from each other by an isolation region, The photodetector according to any one of (1) to (10), wherein the isolation region includes at least one of an insulating material and a semiconductor region doped with impurities. (12) providing a first semiconductor layer; a second semiconductor layer is laminated on a first surface of the first semiconductor layer, the first surface being the surface opposite to the light incident surface side; The second semiconductor layer is partitioned into islands in a plan view, a gate electrode capable of forming a channel that passes through the stacking direction of the first semiconductor layer and the second semiconductor layer between the photoelectric conversion part provided in the first semiconductor layer and the charge accumulation region provided in the second semiconductor layer, in a region adjacent to the second semiconductor layer via an insulating film; A method for manufacturing a photodetector. (13) a first layer and a second layer are stacked in this order on the first surface as the second semiconductor layer; After dividing the second semiconductor layer into islands in a plan view, selectively etching the first layer of the first semiconductor layer, the first layer, and the second layer in a direction perpendicular to a stacking direction of the first layer; The method for manufacturing a photodetector according to (12), wherein the gate electrode is formed in a region adjacent to the first layer and the second layer via the insulating film. (14) a light detection device; and an optical system that forms an image of image light from a subject on the light detection device, The photodetector device a first semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is a first surface; a second semiconductor layer stacked on the first surface and having a charge storage region; a gate electrode that is adjacent to the second semiconductor layer via an insulating film and that is capable of forming a channel that passes through the stacking direction of the first semiconductor layer and the second semiconductor layer between the photoelectric conversion unit and the charge accumulation region; electronic equipment. [Explanation of symbols]

[0160] 1. Photodetector 2. Semiconductor chips 2A Pixel area 2B Peripheral Area 3 pixels 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control Circuit 10 pixel drive lines 11 Vertical signal line 12 Horizontal signal line 13 Logic Circuits 15 Readout circuit 20 First semiconductor layer 21, 21a, 21b, 21c, 21c1, 21c2 Semiconductor region 22 Photoelectric conversion unit 23 Photoelectric conversion region 25,25a,25b Separation area separation area separation area 30 Second semiconductor layer 31 1st layer 31a side 32 2nd layer 33 Device formation area 34 Channel section 34a side 34b diameter 34b width 35 Storage Unit 35a side 35b Bottom side 36 Semiconductors 37,37a,37b,37c,37d Charge storage area 38 Transfer gate electrode 39 Insulating Film 40 1st wiring layer 44,44a Contact 50 2nd wiring layer 60 Third semiconductor layer 70 Light-harvesting layer 100 Electronic equipment 102 Optical Lenses (Optical Systems)

Claims

1. a first semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is a first surface; a second semiconductor layer stacked on the first surface and having a charge storage region; a gate electrode adjacent to the second semiconductor layer via an insulating film, capable of forming a channel between the photoelectric conversion unit and the charge accumulation region, the channel extending in a stacking direction of the first semiconductor layer and the second semiconductor layer; Equipped with the second semiconductor layer has a laminated structure in which a channel portion and an accumulation portion are laminated in this order from the first semiconductor layer side, the charge storage region is provided only in the storage portion of the channel portion and the storage portion, the diameter of the channel portion is smaller than the diameter of the reservoir portion; the gate electrode includes a first portion adjacent to a side surface of the storage portion via the insulating film, and a second portion adjacent to a side surface of the channel portion via the insulating film, The inner diameter of the second portion is smaller than the inner diameter of the first portion. Light detection device.

2. 2. The photodetector according to claim 1, wherein the charge accumulation region is provided at a position near a surface of the second semiconductor layer opposite to the first semiconductor layer side.

3. 2. The photodetector according to claim 1, wherein the material constituting the channel section has a higher etching rate in a given etchant than the material constituting the first semiconductor layer and the material constituting the storage section.

4. 2. The photodetector according to claim 1, wherein a surface of the material constituting the channel portion that faces in a direction perpendicular to the stacking direction has a higher etching rate in any etchant than the first surface of the material constituting the first semiconductor layer.

5. 2. The photodetector device according to claim 1, wherein a combination of a material constituting the first semiconductor layer, a material constituting the channel portion, and a material constituting the accumulation portion is a combination of group IV semiconductors or a combination of group III-V compound semiconductors.

6. The photodetector according to claim 1 , wherein a plurality of said channel sections are provided for one of said storage sections, said channel sections being spaced apart from each other in a plan view.

7. The photodetector according to claim 1 , wherein the gate electrode surrounds the second semiconductor layer over an entire circumferential area in a plan view.

8. the photoelectric conversion units are separated from each other by an isolation region, 2. The photodetector device of claim 1, wherein the isolation region comprises at least one of an insulating material and an impurity-doped semiconductor region.

9. providing a first semiconductor layer; a second semiconductor layer is stacked on a first surface of the first semiconductor layer, the first surface being the surface opposite to the light incident surface side; The second semiconductor layer is partitioned into islands in a plan view, forming a gate electrode capable of forming a channel that passes through a stacking direction of the first semiconductor layer and the second semiconductor layer between a photoelectric conversion unit provided in the first semiconductor layer and a charge accumulation region provided in the second semiconductor layer in a region adjacent to the second semiconductor layer via an insulating film; a first layer and a second layer are stacked in this order on the first surface as the second semiconductor layer; After dividing the second semiconductor layer into islands in a plan view, the first layer of the first semiconductor layer, the first layer, and the second layer is selectively etched in a direction perpendicular to a stacking direction of the first layer; forming the gate electrode in a region adjacent to the first layer and the second layer with the insulating film interposed therebetween; A method for manufacturing a photodetector.

10. a light detection device; and an optical system that forms an image of image light from a subject on the light detection device, The photodetector device a first semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is a first surface; a second semiconductor layer stacked on the first surface and having a charge storage region; a gate electrode that is adjacent to the second semiconductor layer via an insulating film and that is capable of forming a channel that passes through the first semiconductor layer and the second semiconductor layer in a stacking direction between the photoelectric conversion unit and the charge accumulation region; the second semiconductor layer has a laminated structure in which a channel portion and an accumulation portion are laminated in this order from the first semiconductor layer side, the charge storage region is provided only in the storage portion of the channel portion and the storage portion, the diameter of the channel portion is smaller than the diameter of the reservoir portion; the gate electrode includes a first portion adjacent to a side surface of the storage portion via the insulating film, and a second portion adjacent to a side surface of the channel portion via the insulating film, The inner diameter of the second portion is smaller than the inner diameter of the first portion. electronic equipment.

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