semiconductor memory device

Abstract

To provide a semiconductor storage device that can mitigate deterioration of reading speed while reducing reading failures even if a read wiring is connected in common to two types of storage circuits that have different storage capacities.SOLUTION: A semiconductor storage device according to an embodiment comprises: a first storage circuit; a second storage circuit with a storage capacity smaller than that of the first storage circuit; a read wiring that is connected to the first and second storage circuits in common; a sense amplifier that compares a voltage of a first bit signal input from the first storage circuit via the reading wiring or of a second bit signal input from the second storage circuit via the reading wiring with a reference voltage; and a read adjustment circuit that changes at least one of an operation timing of the sense amplifier and the reference voltage in accordance with the first and second bit signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] Some semiconductor memory devices are equipped with two types of memory circuits with different memory capacities (sizes) and a sense amplifier. The sense amplifier determines the bit value (0 or 1) indicated by the output signal based on the result of comparing the voltage of the output signal of each memory circuit with a reference voltage.

[0003] In the semiconductor memory device described above, when the output signals of the memory circuits are read out through a common line, the signal waveforms may differ between the memory circuits due to differences in memory capacity. Therefore, if the reference voltage is set based on the memory circuit with the larger memory capacity, for example, the sense amplifier may erroneously read the bit value of the memory circuit with the smaller memory capacity.

[0004] On the other hand, if the reference voltage is set based on the memory circuit with the smaller memory capacity, the operation of the sense amplifier will be delayed, which may result in a decrease in the speed at which bit values ​​are read. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-156085 Summary of the Invention [Problem to be solved by the invention]

[0006] An embodiment of the present invention provides a semiconductor memory device that can reduce read errors and improve the decrease in read speed even when a read wiring is commonly connected to two types of memory circuits with different memory capacities. [Means for solving the problem]

[0007] A semiconductor memory device according to one embodiment includes a first memory circuit, a second memory circuit having a smaller memory capacity than the first memory circuit, a readout wiring commonly connected to the first memory circuit and the second memory circuit, a sense amplifier that compares the voltage of a first bit signal input from the first memory circuit via the readout wiring or a second bit signal input from the second memory circuit via the readout wiring with a reference voltage, and a readout adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in accordance with the first bit signal and the second bit signal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing a schematic circuit configuration of a first memory circuit. [Figure 3] FIG. 2 is a diagram illustrating an example of a circuit configuration of a first read adjustment circuit. [Figure 4] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a comparative example. [Figure 5] 10 is a timing chart of a read operation of a semiconductor memory device according to a comparative example. [Figure 6] 4 is a timing chart of a read operation of the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 10 is a block diagram showing a schematic configuration of a semiconductor memory device according to a second embodiment. [Figure 8] 10 is a timing chart of a read operation of the semiconductor memory device according to the second embodiment. [Figure 9] FIG. 10 is a block diagram showing a schematic configuration of a semiconductor memory device according to a third embodiment. [Figure 10] 10 is a timing chart of a read operation of the semiconductor memory device according to the third embodiment. [Figure 11] FIG. 10 is a block diagram showing a configuration of a second selection circuit according to a first modified example. [Figure 12]10 is a timing chart of a selection operation of a second selection circuit according to a first modification. [Figure 13] FIG. 10 is a block diagram showing a configuration of a second selection circuit according to a second modification. [Figure 14] FIG. 10 is a block diagram showing a configuration of a second selection circuit according to a third modified example. [Figure 15] FIG. 10 is a block diagram showing a configuration of a second selection circuit according to a fourth modified example. [Figure 16] 13 is a timing chart of a selection operation of a second selection circuit according to a fourth modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0010] (First embodiment) 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device 1 shown in FIG. 1 includes a memory unit 10, a sense amplifier 20, a power supply circuit 30, and a first read adjustment circuit 40.

[0011] The memory unit 10 includes a first memory circuit 11, a second memory circuit 12, a transfer transistor M, and a global bit line GBL. The first memory circuit 11 is a memory cell array that stores user data and is called, for example, a User Material area. The second memory circuit 12 is a memory cell array that stores data used when reading data from the first memory circuit 11 and is called, for example, an IFR (InFormation Register) area.

[0012] Fig. 2 is a diagram showing a schematic circuit configuration of the first memory circuit 11. As shown in Fig. 2, a plurality of memory cells 111 are arranged in a matrix in the first memory circuit 11. Each memory cell 111 is disposed near the intersection of a word line WL1 for writing data and a local bit line LBL1 for reading data.

[0013] For example, a nonvolatile memory element can be applied to the memory cell 111. However, the memory cell 111 is not limited to a nonvolatile memory element, and may be another memory element such as an SRAM (Static Random Access Memory).

[0014] The second memory circuit 12 has the same circuit configuration as the above-described first memory circuit 11. However, the storage capacity of the second memory circuit 12 is smaller than the storage capacity of the first memory circuit 11. That is, the number of memory cells 111 in the second memory circuit 12 is smaller than the number of memory cells 111 in the first memory circuit 11.

[0015] The semiconductor memory device 1 according to this embodiment is provided with a plurality of first memory circuits 11 and one second memory circuit 12. However, the number of each memory cell array is not particularly limited.

[0016] The transfer transistor M is provided between the local bit line LBL1 and the global bit line GBL. When the transfer transistor M is turned on based on the control of a control circuit (not shown), the bit value stored in the memory cell 111 of the first storage circuit 11 is output to the global bit line GBL. For example, a MOS transistor can be used as the transfer transistor M.

[0017] In addition, a transfer transistor M is also provided between the local bit line LBL2 and the global bit line GBL of the second memory circuit 12. When this transfer transistor M is turned on based on the control of a control circuit (not shown), the bit value stored in the memory cell 111 of the second memory circuit 12 is output to the global bit line GBL.

[0018] The global bit line GBL corresponds to a read wiring commonly connected to the first memory circuit 11 and the second memory circuit 12. A first bit signal indicating the bit value stored in the first memory circuit 11 or a second bit signal indicating the bit value stored in the second memory circuit 12 is input to the sense amplifier 20 via the global bit line GBL.

[0019] A global bit line GBL is connected to a first input terminal of the sense amplifier 20. A power supply circuit 30 is connected to a second input terminal of the sense amplifier 20. The sense amplifier 20 compares the voltage of the first or second bit signal with a reference voltage Vref and amplifies the voltage difference. When the voltage of the first or second bit signal is smaller than the reference voltage Vref, the sense amplifier 20 outputs a bit value of "1." Conversely, when the voltage of the first or second bit signal is greater than the reference voltage Vref, the sense amplifier 20 outputs a bit value of "0."

[0020] The power supply circuit 30 generates the reference voltage Vref and outputs it to the sense amplifier 20. The potential of the reference voltage Vref may be the same as or different from the power supply voltage VDD. When the potential of the reference voltage Vref is higher than the power supply voltage VDD, the power supply circuit 30 is configured as a boost circuit. On the other hand, when the potential of the reference voltage Vref is lower than the power supply voltage VDD, the power supply circuit 30 is configured as a step-down circuit.

[0021] The first read adjustment circuit 40 is a circuit that changes the operation timing of the sense amplifier 20 in response to the first bit signal or the second bit signal, and has a first delay circuit 41, a second delay circuit 42, and a first selection circuit 43. The operation timing is the timing at which the sense amplifier 20 performs an operation of comparing the voltage of the first bit signal or the second bit signal with a reference voltage Vref.

[0022] 3 is a diagram showing an example of the circuit configuration of the first read adjustment circuit 40. The first delay circuit 41, the second delay circuit 42, and the first selection circuit 43 will be described below with reference to FIG.

[0023] When a clock signal CLK, which is a reference signal for the operation timing of the sense amplifier 20, is input from an oscillator (not shown), the first delay circuit 41 outputs a first delay signal SAE1, which is delayed by a first time with respect to the input clock signal CLK, to the sense amplifier 20. As shown in FIG. 3, the first delay circuit 41 is composed of, for example, an even number of inverters 411 connected in series with each other.

[0024] When the clock signal CLK is input from the oscillator, the second delay circuit 42 shown in FIG. 3 outputs a second delay signal SAE2, which is delayed by a second time relative to the input clock signal, to the sense amplifier 20. The second time is shorter than the first time. As shown in FIG. 3, the first delay circuit 41 is configured, for example, with an even number of inverters 421 connected in series. However, because the second time is shorter than the first time, the number of inverters 421 is smaller than the number of inverters 411 in the first delay circuit 41.

[0025] The first selection circuit 43 selects the first delay circuit 41 or the second delay circuit 42 based on an address signal ADR from a control circuit (not shown). As shown in Fig. 3, the first selection circuit 43 is configured with, for example, an N-channel MOS transistor 431 connected to the first delay circuit 41 and a P-channel MOS transistor 432 connected to the second delay circuit 42.

[0026] An address signal ADR is input to each gate of the MOS transistor 431 and the MOS transistor 432. The level of this address signal ADR indicates that the input signal to the sense amplifier 20 is a first-bit signal of the first memory circuit 11 or a second-bit signal of the second memory circuit 12.

[0027] When the address signal ADR is at a high level, it indicates that the input signal to the sense amplifier 20 is a first-bit signal. In this case, the MOS transistor 431 is turned on and the MOS transistor 432 is turned off. As a result, the clock signal CLK is input to the first delay circuit 41 via the MOS transistor 431, and the first delay signal SAE1 is input to the sense amplifier 20.

[0028] On the other hand, when the address signal ADR is at a low level, this indicates that the input signal to the sense amplifier 20 is a second-bit signal. In this case, the MOS transistor 431 is turned off and the MOS transistor 432 is turned on. As a result, the clock signal CLK is input to the second delay circuit 42 via the MOS transistor 432, and the second delay signal SAE2 is input to the sense amplifier 20.

[0029] In this embodiment, the first selection circuit 43 is arranged in a stage preceding the first delay circuit 41 and the second delay circuit 42. However, the first selection circuit 43 may be arranged in a stage following the first delay circuit 41 and the second delay circuit 42. In this case, too, the first selection circuit 43 can select the first delay circuit 41 or the second delay circuit 42 in accordance with the input signal of the sense amplifier 20.

[0030] Here, a semiconductor memory device according to a comparative example to be compared with the semiconductor memory device 1 according to the first embodiment described above will be described.

[0031] 4 is a block diagram showing a schematic configuration of a semiconductor memory device according to a comparative example. In this comparative example, the same components as those in the semiconductor memory device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0032] The semiconductor memory device 100 according to this comparative example is provided with a delay circuit 400 instead of the first read adjustment circuit 40. The delay circuit 400 outputs a delay signal SAE, which has a constant delay time relative to the clock signal CLK, to the sense amplifier 20, regardless of whether the input signal to the sense amplifier 20 is the first bit signal from the first memory circuit 11 or the second bit signal from the second memory circuit 12.

[0033] 5 is a timing chart of a read operation of a semiconductor memory device 100 according to a comparative example. In the semiconductor memory device 100 shown in FIG. 5, let us assume that the sense amplifier 20 compares the voltage of an input signal with a reference voltage Vref11 based on a delayed signal SAE11 that is delayed by a time td11 relative to the clock signal CLK. At this time, if the input signals to the sense amplifier 20 are a first bit signal BS10 indicating a bit value of "0" in the first memory circuit 11 and a first bit signal BS11 indicating a bit value of "1," a sufficient voltage difference can be ensured between the voltage of each first bit signal and the reference voltage Vref11, making it unlikely that a read error will occur in the bit value.

[0034] However, when the input signals to the sense amplifier 20 are the second bit signal BS20 indicating a bit value of "0" in the second memory circuit 12 and the second bit signal BS21 indicating a bit value of "1", the voltage difference between the voltage of the second bit signal BS20 and the reference voltage Vref11 becomes insufficient, which increases the possibility that the bit value of "0" will be erroneously read as a bit value of "1" in the sense amplifier 20.

[0035] Therefore, in the semiconductor memory device 100 according to this comparative example, the output voltage of the power supply circuit 30 is set to a reference voltage Vref12 that is lower than the reference voltage Vref11. Furthermore, the delay circuit 400 outputs a delayed signal SAE12 to the sense amplifier 20, which is delayed by a time td12 that is longer than the time td11. In this case, a sufficient voltage difference between the voltage of the second bit signal BS20 and the reference voltage Vref12 is ensured, thereby reducing read errors of the bit value. However, the delay time relative to the clock signal CLK is lengthened, which reduces the read speed of the bit value.

[0036] FIG. 6 is a timing chart of a read operation of the semiconductor memory device 1 according to the first embodiment. In this embodiment, as described above, when the input signal of the sense amplifier 20 is the first bit signals BS10 and BS11 from the first memory circuit 11, the sense amplifier 20 compares the voltages of the first bit signals BS10 and BS11 with the reference voltage Vref at a timing delayed by a first time td1 relative to the clock signal CLK. Since the first time td1 is equivalent to the time td11 in the comparative example, a sufficient voltage difference is ensured between the voltages of the first bit signals BS10 and BS11 and the reference voltage Vref. Therefore, read errors of the bit values ​​are unlikely to occur. Furthermore, when reading the first bit signals BS10 and BS11, the delay time relative to the clock signal CLK is shorter than in the comparative example, which improves the read speed of the bit values ​​of the first bit signals BS10 and BS11.

[0037] On the other hand, when the input signal to the sense amplifier 20 is the second bit signals BS20 and BS21 from the second memory circuit 12, the sense amplifier 20 compares the voltages of the second bit signals BS20 and BS21 with the reference voltage Vref at a timing delayed by a second time td2 relative to the clock signal CLK. At this time, the second time td2 is shorter than the first time td1. Therefore, the voltage difference between the voltage of the second bit signal BS20 and the reference voltage Vref is greater than the first time td1. This ensures a sufficient voltage difference, reducing read errors of bit values.

[0038] Furthermore, when reading out the second bit signals BS20 and BS21, the delay time relative to the clock signal CLK is shorter than in the comparative example, which makes it possible to improve the read speed of the second bit signals BS20 and BS21. Note that in this embodiment, the voltage difference between the voltage of the second bit signal BS21 and the reference voltage Vref tends to be smaller than at the first time td1, but this voltage difference is sufficiently ensured so that no read failure of the bit value occurs even at the second time td2.

[0039] (Second embodiment) 7 is a block diagram showing a schematic configuration of a semiconductor memory device according to the second embodiment. In this embodiment, the same components as those in the semiconductor memory device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0040] The semiconductor memory device 2 according to this embodiment differs from the first embodiment in that it includes a delay circuit 400 and a second read adjustment circuit 50. The delay circuit 400 outputs a delay signal SAE, which has a constant delay time relative to the clock signal CLK, to the sense amplifier 20, regardless of whether the input signal to the sense amplifier 20 is the first bit signals BS10, BS11 or the second bit signals BS20, BS21.

[0041] The second read adjustment circuit 50 has a first power supply circuit 31, a second power supply circuit 32, and a second selection circuit 33. Each circuit will be described below.

[0042] The first power supply circuit 31 generates a first reference voltage Vref1 and outputs it to the sense amplifier 20. The potential of the first reference voltage Vref1 is set to, for example, 91% (VDD×0.91) of the power supply voltage VDD. Therefore, the first power supply circuit 31 is configured as a step-down circuit that steps down the power supply voltage VDD.

[0043] The second power supply circuit 32 generates a second reference voltage Vref2 and outputs it to the sense amplifier 20. The potential of the second reference voltage Vref2 is set to, for example, 90% (VDD×0.90) of the power supply voltage VDD. In other words, the second reference voltage Vref2 is lower than the first reference voltage Vref1. The second power supply circuit 32 is also configured as a step-down circuit that steps down the power supply voltage VDD.

[0044] The second selection circuit 33 selects the first power supply circuit 31 or the second power supply circuit 32 based on an address signal ADR from a control circuit (not shown). Similar to the first selection circuit 43 (see FIG. 3), the second selection circuit 33 is composed of an N-channel MOS transistor 431 and a P-channel MOS transistor 432. In this embodiment, the first power supply circuit 31 is connected to the MOS transistor 431. On the other hand, the second power supply circuit 32 is connected to the MOS transistor 432.

[0045] In the second read adjustment circuit 50, when a high-level address signal ADR is input to the second selection circuit 33, the MOS transistor 431 is turned on and the MOS transistor 432 is turned off. As a result, the first reference voltage Vref1 is input to the sense amplifier 20.

[0046] Conversely, when a low-level address signal ADR is input to the second selection circuit 33, the MOS transistor 431 is turned off and the MOS transistor 432 is turned on. As a result, the second reference voltage Vref2 is input to the sense amplifier 20.

[0047] FIG. 8 is a timing chart of a read operation of the semiconductor memory device 2 according to the second embodiment. In this embodiment, when the input signal of the sense amplifier 20 is the first bit signals BS10 and BS11 from the first memory circuit 11, the sense amplifier 20 compares the voltages of the first bit signals BS10 and BS11 with the first reference voltage Vref1 at a timing delayed by a time td relative to the clock signal CLK. Since the time td is the same as the first time td1 in the first embodiment, a sufficient voltage difference is ensured between the voltages of the first bit signals BS10 and BS11 and the reference voltage Vref. This reduces read errors of bit values. Furthermore, since the delay time relative to the clock signal CLK is shorter when reading the first bit signals BS10 and BS11 than in the comparative example, the read speed of the first bit signals BS10 and BS11 can be improved.

[0048] On the other hand, when the input signal to the sense amplifier 20 is the second bit signals BS20 and BS21 from the second memory circuit 12, the sense amplifier 20 also compares the voltages of the second bit signals BS20 and BS21 with the second reference voltage Vref2 with a timing delayed by time td relative to the clock signal CLK. At this time, the second reference voltage Vref2 is lower than the first reference voltage Vref1. Therefore, the voltage difference between the voltage of the second bit signal BS20 and the reference voltage Vref is greater than the first reference voltage Vref1. This ensures a sufficient voltage difference, thereby reducing read errors of bit values.

[0049] Furthermore, when reading out the second bit signals BS20 and BS21, the delay time relative to the clock signal CLK is shorter than in the comparative example, which makes it possible to improve the read speed of the second bit signals BS20 and BS21. Note that, in this embodiment as well, the voltage difference between the voltage of the second bit signal BS21 and the reference voltage Vref tends to be smaller than the first reference voltage Vref1, but this voltage difference is sufficiently ensured so that no read errors occur in the bit values ​​even with the second reference voltage Vref2.

[0050] (Third embodiment) 9 is a block diagram showing a schematic configuration of a semiconductor memory device according to the third embodiment. The semiconductor memory device 3 according to this embodiment includes both the first read adjustment circuit 40 described in the first embodiment and the second read adjustment circuit 50 described in the second embodiment. The configuration of each read adjustment circuit has been described in the first and second embodiments, so a description thereof will be omitted.

[0051] FIG. 10 is a timing chart of a read operation of the semiconductor memory device 3 according to the third embodiment. In this embodiment, when the input signal of the sense amplifier 20 is the first bit signals BS10 and BS11 from the first memory circuit 11, the sense amplifier 20 compares the voltages of the first bit signals BS10 and BS11 with the first reference voltage Vref1 at a timing delayed by a first time td1 from the clock signal CLK. At this time, a sufficient voltage difference is ensured between the voltages of the first bit signals BS10 and BS11 and the reference voltage Vref. This reduces read errors of bit values. Furthermore, the read speed of the first bit signals BS10 and BS11 can be improved compared to the comparative example.

[0052] On the other hand, when the input signal to the sense amplifier 20 is the second bit signals BS20, BS21 from the second memory circuit 12, the sense amplifier 20 compares the voltages of the second bit signals BS20, BS21 with the second reference voltage Vref2 at a timing delayed by a second time td2 from the clock signal CLK. At this time, since the second reference voltage Vref2 is lower than the first reference voltage Vref1, it is possible to ensure a sufficient voltage difference between the voltage of the second bit signal BS20 and the reference voltage Vref, thereby reducing read errors of bit values.

[0053] Furthermore, when reading out the second bit signals BS20 and BS21, the delay time relative to the clock signal CLK is shorter than when reading out the first bit signals BS10 and BS11, which makes it possible to improve the read speed of the second bit signals BS20 and BS21. Note that in this embodiment as well, the voltage difference between the voltage of the second bit signal BS21 and the second reference voltage Vref2 tends to be smaller than the first reference voltage Vref1, but this voltage difference is sufficiently ensured so that read errors do not occur even with the second reference voltage Vref2.

[0054] (First Modification) Fig. 11 is a block diagram showing the configuration of a second selection circuit according to Modification 1. The second selection circuit 33a shown in Fig. 11 includes inverters 301 to 304, a first switching element 311 to a fourth switching element 314, a first capacitance element 321, and a second capacitance element 322.

[0055] The inverters 301 to 304 are connected in series in this order. The address signal ADR is input to the input terminal of the inverter 301 in the front stage.

[0056] The first switching element 311 and the third switching element 313 are, for example, N-channel MOS transistors, while the second switching element 312 and the fourth switching element 314 are, for example, P-channel MOS transistors.

[0057] The first switching element 311 and the second switching element 312 are a pair of switching elements connected in parallel with each other between the first power supply circuit 31 and the second input terminal 202 of the sense amplifier 20. The gate of the first switching element 311 is connected to the output terminal of the last-stage inverter 304. The gate of the second switching element 312 is connected to the output terminal of the middle-stage inverter 303.

[0058] The third switching element 313 and the fourth switching element 314 are a pair of switching elements connected in parallel with each other between the second power supply circuit 32 and the second input terminal 202 of the sense amplifier 20. The gate of the third switching element 313 is connected to the output terminal of the inverter 303 in common with the gate of the second switching element 312. The gate of the fourth switching element 314 is connected to the output terminal of the inverter 304 in common with the gate of the first switching element 311.

[0059] One end of the first capacitance element 321 is grounded, and the other end of the first capacitance element 321 is connected to the second input terminal 202 of the sense amplifier 20.

[0060] One end of the second capacitance element 322 is connected to the output terminal of the inverter 302. The other end of the second capacitance element 322 is connected to the second input terminal 202 of the sense amplifier 20.

[0061] The capacitance value Ccoup of the second capacitance element 322 is smaller than the capacitance value Cref of the first capacitance element 321. The capacitance ratio between the capacitance value Ccoup and the capacitance value Cref is set based on the voltage ratio between the output voltage of the first power supply circuit 31, i.e., the first reference voltage Vref1, and the output voltage of the second power supply circuit 32, i.e., the second reference voltage Vref2. For example, if the first reference voltage Vref1 is set to 91% (VDD×0.91) of the power supply voltage VDD and the second reference voltage Vref2 is set to 90% (VDD×0.90) of the power supply voltage VDD, the capacitance ratio between the capacitance value Cref and the capacitance value Ccoup is set to 90:1.

[0062] 12 is a timing chart of the selection operation of the second selection circuit 33a according to the first modification. Here, the operation when the address signal ADR changes from low level to high level will be described.

[0063] When the address signal ADR input to the inverter 301 changes from low to high, first, the potential at one end of the second capacitance element 322 connected to the middle inverter 02 becomes high. Therefore, due to the coupling effect between the first capacitance element 321 and the second capacitance element 322, the voltage VREF at the second input terminal 202 of the sense amplifier 20 increases from the second reference voltage Vref2 by the capacitance ratio between the first capacitance element 321 and the second capacitance element 322. In other words, the voltage VREF increases from the second reference voltage Vref2 to the first reference voltage Vref1.

[0064] Next, the low-level address signal ADR input from the output terminal of the inverter 303 turns on the second switching element 312 and turns off the third switching element 313 .

[0065] Next, the first switching element 311 is turned on and the fourth switching element 314 is turned off by the high-level address signal ADR input from the output terminal of the inverter 304. As a result, the power supply circuit connected to the second input terminal 202 of the sense amplifier 20 is switched from the second power supply circuit 32 to the first power supply circuit 31.

[0066] Next, based on the timing of the delayed signal SAE, the sense amplifier 20 compares the signal voltage input to the first input terminal 201 from the first memory circuit 11 through the global bit line GBL with the first reference voltage Vref1 input to the second input terminal 202. The sense amplifier 20 reads out the first bit signal BS10 or the first bit signal BS11 depending on the comparison result.

[0067] According to the present modification described above, the switching speed of the reference voltage is accelerated by the coupling effect between the first capacitance element 321 and the second capacitance element 322. This makes it possible to further increase the speed of the read operation of the bit signal.

[0068] (Second Modification) 13 is a block diagram showing the configuration of a second selection circuit according to Modification 2. Circuit elements similar to those in the second selection circuit 33a according to Modification 1 described above are given the same reference numerals, and detailed description thereof will be omitted.

[0069] The second selection circuit 33b shown in FIG. 13 differs from the second selection circuit 33a in that the gates of the second switching element 312 and the third switching element 313 are connected to the output terminal of the inverter 301 in the front stage.

[0070] The second selection circuit 33b also differs from the second selection circuit 33a in that the gates of the first switching element 311 and the fourth switching element 314 are connected to the output terminal of the inverter 302 in the middle stage.

[0071] In the second selection circuit 33b configured as described above, when the address signal ADR input to the inverter 301 changes from low level to high level, first, the low-level address signal ADR input from the output terminal of the inverter 301 turns on the second switching element 312 and turns off the third switching element 313.

[0072] Next, the first switching element 311 is turned on and the fourth switching element 314 is turned off by the high-level address signal ADR input from the output terminal of the inverter 302. As a result, the power supply circuit connected to the second input terminal 202 of the sense amplifier 20 is switched from the second power supply circuit 32 to the first power supply circuit 31.

[0073] Next, the potential of one end of the second capacitance element 322 connected to the output terminal of the inverter 304 becomes high. Therefore, similar to the first modification, due to the coupling effect between the first capacitance element 321 and the second capacitance element 322, the voltage VREF of the second input terminal of the sense amplifier 20 increases from the second reference voltage Vref2 by the capacitance ratio between the first capacitance element 321 and the second capacitance element 322. In other words, the voltage VREF increases from the second reference voltage Vref2 to the first reference voltage Vref1.

[0074] Next, based on the timing of the delayed signal SAE, the sense amplifier 20 compares the signal voltage input to the first input terminal 201 from the first memory circuit 11 through the global bit line GBL with the first reference voltage Vref1 input to the second input terminal 202. The sense amplifier 20 reads out the first bit signal BS10 or the first bit signal BS11 depending on the comparison result.

[0075] According to the present modification described above, the second selection circuit 33b switches the reference voltage after selecting the power supply circuit. At this time, as in the first modification, the speed at which the reference voltage is switched is accelerated by the coupling effect between the first capacitance element 321 and the second capacitance element 322. This makes it possible to further speed up the operation of reading bit signals.

[0076] (Third Modification) 14 is a block diagram showing the configuration of a second selection circuit according to Modification 3. Circuit elements similar to those in the second selection circuit 33b according to Modification 2 described above are given the same reference numerals, and detailed description thereof will be omitted.

[0077] 14, the number of inverters is half that of the second selection circuit 33b according to the second modification. That is, the second selection circuit 33c according to this modification has inverters 301 and 302, but does not have inverters 303 and 304. Therefore, the output terminal of the last-stage inverter 302 is connected to the gate of the first switching element 311, the gate of the fourth switching element 314, and one end of the second capacitance element 322.

[0078] In the second selection circuit 33c configured as described above, when the address signal ADR input to the inverter 301 changes from low level to high level, first, the low-level address signal ADR input from the output terminal of the inverter 301 turns on the second switching element 312 and turns off the third switching element 313.

[0079] Next, the first switching element 311 is turned on and the fourth switching element 314 is turned off by the high-level address signal ADR input from the output terminal of the inverter 302. As a result, the power supply circuit connected to the second input terminal 202 of the sense amplifier 20 is switched from the second power supply circuit 32 to the first power supply circuit 31.

[0080] Simultaneously with the switching of the power supply circuit, the potential of one end of the second capacitance element 322 connected to the output terminal of the inverter 302 becomes high. Therefore, similar to the second modification, the coupling effect between the first capacitance element 321 and the second capacitance element 322 causes the voltage VREF of the second input terminal of the sense amplifier 20 to increase from the second reference voltage Vref2 by the capacitance ratio between the first capacitance element 321 and the second capacitance element 322. In other words, the voltage VREF rises from the second reference voltage Vref2 to the first reference voltage Vref1.

[0081] Next, based on the timing of the delayed signal SAE, the sense amplifier 20 compares the signal voltage input to the first input terminal 201 from the first memory circuit 11 through the global bit line GBL with the first reference voltage Vref1 input to the second input terminal 202. The sense amplifier 20 reads out the first bit signal BS10 or the first bit signal BS11 depending on the comparison result.

[0082] According to this modification described above, as in the second modification, the switching speed of the reference voltage is accelerated by the coupling effect between the first capacitive element 321 and the second capacitive element 322. This makes it possible to speed up the read operation of the bit signal. Furthermore, in this modification, the second selection circuit 33c simultaneously selects the power supply circuit and switches the reference voltage. This makes it possible to further speed up the read operation of the bit signal.

[0083] (Fourth Modification) 15 is a block diagram showing the configuration of the second selection circuit according to Modification 4. In the above-described first to third modifications, the first to fourth switching elements 311 to 314 are driven by the inverters 301 to 304.

[0084] 15, in a second selection circuit 33d according to this modification, each switching element is driven by a drive circuit 600. The drive circuit 600 is a circuit that controls all of the switching elements 311 to 314 to be in a non-selected state in which neither the first power supply circuit 31 nor the second power supply circuit 32 is selected when the level of the address signal ADR, which is an input signal, changes from low level (“0”) to high level (“1”) or from high level to low level. The drive circuit 600 is also a circuit that controls all of the switching elements 311 to 314 to be in a non-selected state in which neither the first power supply circuit 31 nor the second power supply circuit 32 is selected when the delayed address signal ADRd changes from low level (“0”) to high level (“1”) or from high level to low level while all of the switching elements 311 to 314 are in a non-selected state, and after the delayed address signal ADRd changes further, one of the switching elements 311 to 314 is in a selected state in which the first power supply circuit 31 or the second power supply circuit 32 is selected. Here, the delayed address signal ADRd is a delayed signal obtained by delaying the address signal ADR. The configuration of the drive circuit 600 will be described below.

[0085] The driving circuit 600 is provided with inverters 601 to 606 connected in series to one another. An address signal ADR is input to the inverter 601 at the front stage. The inverter 606 at the last stage is connected to the inverter 301.

[0086] The drive circuit 600 is also provided with inverters 611 to 617 connected in series to one another. An address signal ADR is input to the front-stage inverter 611. The output terminal of the middle-stage inverter 614 is connected to the input terminal of a NAND circuit 622.

[0087] The NAND circuit 622 outputs the result of a NOR operation between the address signal ADR and the output signal of the inverter 614. The output signal indicating the operation result is inverted by the inverter 618 and input to the NAND circuit 622.

[0088] The NAND circuit 622 outputs the result of a NAND operation between the output signal of the inverter 618 and the output signal of the inverter 617. The output signal indicating the operation result is input to the NAND circuit 625.

[0089] The drive circuit 600 also includes inverters 631 to 636 connected in series. An address signal ADR is input to the front-stage inverter 631. The address signal ADR is inverted by the inverter 631 and input to the NAND circuit 623. The output signal of the middle-stage inverter 634 is also input to the NAND circuit 623.

[0090] The NAND circuit 623 outputs the result of a NAND operation between the output signal of the inverter 631 and the output signal of the inverter 634. The output signal indicating the operation result is input to the NAND circuit 624. The output signal of the inverter 636 is also input to the NAND circuit 624.

[0091] The NAND circuit 624 outputs the result of the NAND operation between the output signal of the NAND circuit 623 and the output signal of the inverter 636. The output signal indicating the operation result is input to the NAND circuit 625.

[0092] The NAND circuit 625 outputs the result of a NAND operation between the output signal of the NAND circuit 622 and the output signal of the NAND circuit 624. The output signal indicating the operation result is input to a NOR circuit 652. The output signal of the NAND circuit 625 is inverted by an inverter 641 and input to a NAND circuit 651.

[0093] The NAND circuit 651 outputs the result of a NAND operation between the output signal of the inverter 606 and the output signal of the inverter 641. The output signal indicating the operation result is input to the gate of the second switching element 312. The output signal of the NAND circuit 651 is inverted by the inverter 661. This inverted signal is input to the gate of the first switching element 311 as the selection signal SEL1.

[0094] The NOR circuit 652 outputs the result of a NOR operation performed on the output signal of the inverter 606 and the output signal of the NAND circuit 625. The output signal indicating the operation result is input to the gate of the third switching element 313 as a selection signal SEL2. The output signal of the NOR circuit 652 is inverted by an inverter 662. This inverted signal is input to the gate of the fourth switching element 314.

[0095] 16 is a timing chart of the selection operation of the second selection circuit 33d according to the fourth modification. Here, the operation when the address signal ADR changes from low level to high level will be described.

[0096] At the timing when the address signal ADR input to the inverter 301 changes from low to high, the selection signal SEL1 is at low level and the selection signal SEL2 is at high level, so that the first switching element 311 and the second switching element 312 are in the off state and the third switching element 313 and the fourth switching element 314 are in the on state.

[0097] Next, when the delayed address signal ADRd, obtained by delaying the address signal ADR by the inverters 601 to 606 and the inverters 301 to 304, changes from low to high, the potential at one end of the second capacitance element 322 becomes high. Therefore, due to the coupling effect between the first capacitance element 321 and the second capacitance element 322, the voltage VREF at the second input terminal 202 of the sense amplifier 20 increases from the second reference voltage Vref2 by the capacitance ratio between the first capacitance element 321 and the second capacitance element 322. In other words, the voltage VREF increases from the second reference voltage Vref2 to the first reference voltage Vref1.

[0098] At the timing when the delayed address signal ADRd changes from low to high, the selection signal SEL1 remains low while the selection signal SEL2 changes from high to low due to the NOR and NAND operations in the drive circuit 600. As a result, the first switching element 311 and the second switching element 312 remain off, and the third switching element 313 and the fourth switching element 314 also turn off. As a result, the power supply circuit connected to the second input terminal of the sense amplifier 20 is not selected.

[0099] When a predetermined time has elapsed since the selection signal SEL2 changed from high to low, the selection signal SEL1 changes from low to high. At this time, the delayed address signal ADRd and the selection signal SEL2 maintain a high level. This causes the first switching element 311 and the second switching element 312 to be turned on. As a result, the first power supply circuit 31 is connected to the second input terminal 202 of the sense amplifier 20.

[0100] Thereafter, as in the other modified examples described above, the sense amplifier 20 compares, based on the timing of the delayed signal SAE, the signal voltage input to the first input terminal 201 from the first memory circuit 11 through the global bit line GBL with the first reference voltage Vref1 input to the second input terminal 202. The sense amplifier 20 reads out the first bit signal BS10 or the first bit signal BS11 depending on the comparison result.

[0101] According to this modification described above, as in the other modifications, the switching speed of the reference voltage is accelerated by the coupling effect between the first capacitance element 321 and the second capacitance element 322. This makes it possible to further speed up the read operation of the bit signal. Furthermore, in this modification, the drive circuit 600 for the first switching element 311 to the fourth switching element 314 is provided independently of the second capacitance element 322. This improves the controllability of the operation of each switching element.

[0102] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0103] 1 to 3: Semiconductor memory device 11: 1st memory circuit 12:Second memory circuit 20: Sense amplifier 31: 1st power supply circuit 32:Second power supply circuit 33, 33a to 33d: second selection circuit 40: First readout adjustment circuit 41: First delay circuit 42: Second delay circuit 43: First selection circuit 50: Second readout adjustment circuit 301~304: Inverter 311: First switching element 312: Second switching element 313: Third switching element 314: Fourth switching element 321: First capacitance element 322: second capacitance element 600:Drive circuit GBL: Global bit line (read wiring)

Claims

1. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to a middle-stage inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to an inverter in a stage subsequent to the middle inverter among the plurality of inverters, A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

2. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to an output terminal of an inverter in a stage preceding the last inverter among the plurality of inverters, A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

3. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to the output terminal of the last-stage inverter, A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

4. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; a drive circuit that drives the switching element, the drive circuit controls the switching element to be in a non-selection state in which neither the first power supply circuit nor the second power supply circuit is selected at a time when the input signal changes from a low level to a high level or from a high level to a low level, and the drive circuit controls the switching element to be in a selection state in which the first power supply circuit or the second power supply circuit is selected after a delay signal, which is obtained by delaying the input signal while the switching element is in a non-selection period, changes from a low level to a high level or from a high level to a low level, and the delay signal changes; A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

5. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first delay circuit that delays the operation timing by a first time with respect to a clock signal; a second delay circuit that delays the operation timing with respect to the clock signal by a second time that is shorter than the first time; a first selection circuit that selects the first delay circuit when the first bit signal is input to the sense amplifier, and selects the second delay circuit when the second bit signal is input to the sense amplifier; a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to a middle-stage inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to an inverter in a stage subsequent to the middle inverter among the plurality of inverters, A semiconductor device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

6. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first delay circuit that delays the operation timing by a first time with respect to a clock signal; a second delay circuit that delays the operation timing with respect to the clock signal by a second time that is shorter than the first time; a first selection circuit that selects the first delay circuit when the first bit signal is input to the sense amplifier, and selects the second delay circuit when the second bit signal is input to the sense amplifier; a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to an output terminal of an inverter in a stage preceding the last inverter among the plurality of inverters, A semiconductor device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

7. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first delay circuit that delays the operation timing by a first time with respect to a clock signal; a second delay circuit that delays the operation timing with respect to the clock signal by a second time that is shorter than the first time; a first selection circuit that selects the first delay circuit when the first bit signal is input to the sense amplifier, and selects the second delay circuit when the second bit signal is input to the sense amplifier; a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; the switching element is connected to the output terminal of the last-stage inverter, A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

8. A first memory circuit; a second memory circuit having a memory capacity smaller than that of the first memory circuit; a readout wiring commonly connected to the first memory circuit and the second memory circuit; a sense amplifier that compares a voltage of a first bit signal input from the first memory circuit via the readout wiring or a voltage of a second bit signal input from the second memory circuit via the readout wiring with a reference voltage; a read adjustment circuit that changes at least one of the operation timing of the sense amplifier and the reference voltage in response to the first bit signal and the second bit signal; Equipped with The readout adjustment circuit a first delay circuit that delays the operation timing by a first time with respect to a clock signal; a second delay circuit that delays the operation timing with respect to the clock signal by a second time that is shorter than the first time; a first selection circuit that selects the first delay circuit when the first bit signal is input to the sense amplifier, and selects the second delay circuit when the second bit signal is input to the sense amplifier; a first power supply circuit that outputs a first reference voltage; a second power supply circuit that outputs a second reference voltage that is lower than the first reference voltage; a second selection circuit that selects the first power supply circuit when the first bit signal is input to the sense amplifier, and selects the second power supply circuit when the second bit signal is input to the sense amplifier; and The second selection circuit a plurality of inverters connected in series with each other; a switching element that switches the connection destination of the sense amplifier between the first power supply circuit and the second power supply circuit; a first capacitance element having one end connected to the input terminal of the sense amplifier and the other end grounded; a second capacitance element having one end connected to the output terminal of the last inverter among the plurality of inverters and the other end connected to the input terminal; a drive circuit that drives the switching element, the drive circuit controls the switching element to be in a non-selection state in which neither the first power supply circuit nor the second power supply circuit is selected at a time when the input signal changes from a low level to a high level or from a high level to a low level, and the drive circuit controls the switching element to be in a selection state in which the first power supply circuit or the second power supply circuit is selected after a delay signal, which is obtained by delaying the input signal while the switching element is in a non-selection period, changes from a low level to a high level or from a high level to a low level, and the delay signal changes; A semiconductor memory device, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

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