Semiconductor device and power conversion device

Abstract

A semiconductor device and a power conversion device according to the present disclosure each comprise: a drift layer (20) of a first conductivity type; a gate electrode (60) which is arranged so as to face a well region (30) of a second conductivity type and a source region (40) of the first conductivity type, with a gate insulating film (50) being interposed therebetween; a source electrode (80) which is arranged on an interlayer insulating film (55) that is provided so as to cover the gate electrode (60), and which is connected to the well region (30) and the source region (40); a first isolation region (21) of the first conductivity type, the first isolation region (21) being arranged in an active region, in which a plurality of MOSFETs each containing the well region (30), the source region (40) and the gate electrode (60) are arranged in the drift layer (20), while being connected to the drift layer (20) and forming a Schottky connection with the source electrode (80); and a surge conduction region (301) which is arranged in the active region over an area that is larger than a first width of the well region (30) when viewed in plan, and which has a region that cuts off the connection between the source electrode (80) and the drift layer (20). Due to this configuration, breakage of the gate insulating film (50) caused by a surge current flowing through the semiconductor device is suppressed, thereby enabling the achievement of a semiconductor device and a power conversion device, each of which has a high surge resistance.

Description

[Technical Field]

[0001] The present disclosure particularly relates to a semiconductor device made of silicon carbide and a power conversion device using the same. [Background technology]

[0002] There is a semiconductor device in which both a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) region and an SBD (Schottky barrier diode) region are formed in an active region. In such a semiconductor device, for example, Patent Document 1 discloses a structure in which the Schottky junction formation region, which is a junction between an n-type and a metal electrode, is subdivided by regular p-type implantation regions, thereby reducing the Schottky junction electric field and the leakage current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2020-161841 (Figure 6) Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, when a large current called a surge current flows through the SBD, the SBD generates heat due to the large resistance of the SBD, which is a result of the SBD's conduction principle, and this can lead to breakdown of the gate oxide film. This makes it difficult to obtain a semiconductor device and power conversion device with high surge resistance.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a power conversion device that are highly surge-resistant and that suppress breakdown of a gate oxide film due to a surge current flowing through the semiconductor device. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a first conductivity type drift layer, a gate electrode provided to face a second conductivity type well region and a first conductivity type source region via a gate insulating film, a source electrode provided on an interlayer insulating film provided to cover the gate electrode and connected to the well region and the source region, and a plurality of MOSFETs each including a well region, a source region, and a gate electrode are disposed in the drift layer. have a territory a first isolation region of a first conductivity type provided in the active region and connected to the drift layer and making a Schottky contact with the source electrode; Areas where multiple locations are located, or outside areas where multiple locations are located Provided in the active region , So and a surge current-carrying region having a region for cutting off the connection between the source electrode and the drift layer. The distance between the two first separation regions provided adjacent to one end side and the other end side of the surge current-carrying region is greater than the distance between the two first separation regions adjacent to each other in the active region outside the surge current-carrying region. .

[0007] The power conversion device of the present disclosure includes a main conversion circuit that has the semiconductor device of the present disclosure and converts and outputs input power, and a control circuit that outputs a control signal for controlling the main conversion circuit. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to obtain a semiconductor device and a power conversion device that are highly surge-resistant, by suppressing breakdown of a gate oxide film caused by a surge current flowing through the semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 5] 1 is a plan view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 7] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 8] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 9] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 10] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 11] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 12] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 13] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 14] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 15] 2A to 2C are explanatory diagrams of a method for manufacturing the semiconductor device in the first embodiment. [Figure 16] 1 is a plan view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 17] 1 is a plan view schematically illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 18] 10 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment. FIG. [Figure 19] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fifth embodiment. [Figure 23] FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a fifth embodiment. [Figure 24] FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a fifth embodiment. [Figure 25] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 26] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 27] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 28] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 29] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 30] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. [Figure 31] FIG. 13 is a schematic diagram showing a schematic configuration of a power conversion system to which a power conversion device according to a sixth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, n-type and p-type refer to the conductivity types of semiconductors. In this disclosure, the first conductivity type is referred to as n-type and the second conductivity type as p-type. However, the first conductivity type may also be referred to as p-type and the second conductivity type as n-type. Furthermore, n-type indicates that its impurity concentration is lower than that of n-type, and n+ type indicates that its impurity concentration is higher than that of n-type. Similarly, p-type indicates that its impurity concentration is lower than that of p-type, and p+ type indicates that its impurity concentration is higher than that of p-type. Unless otherwise specified, the terms pn junction and pn diode may be used interchangeably. The application of a voltage equal to or greater than the threshold voltage to a pn diode may be expressed as the pn diode being turned on or the pn junction being turned on. The application of a voltage equal to or greater than the threshold voltage to a gate electrode may be expressed as the gate being turned on.

[0011] Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same, and detailed description thereof may be omitted.

[0012] <First Embodiment> The semiconductor device according to this embodiment will now be described. First, the configuration of the semiconductor device will be described.

[0013] Fig. 1 is a schematic plan view showing a general configuration of a semiconductor device according to the first embodiment. Fig. 1 corresponds to a top view of an SBD-integrated SiC-MOSFET. In Fig. 1, a gate pad 81 is formed on part of the top surface of the SBD-integrated SiC-MOSFET, and a source electrode 80 is formed adjacent to this. Gate wiring 82 is also formed extending from the gate pad 81.

[0014] 2 is a schematic plan view showing the general configuration of a semiconductor device according to the first embodiment. Here, FIG. 2 corresponds to FIG. 1 showing mainly semiconductor layers with electrode layers such as source electrode 80 seen through, and shows an example in which three surge current-carrying regions 301 are provided. The semiconductor device shown in FIG. 2 is called a "stripe type" because unit cell regions, each having a MOSFET region formed on either side of an SBD region, are arranged in a stripe pattern. The stripe type semiconductor device will be described below.

[0015] 2, unit cell regions each consisting of an n-type first isolation region 21 roughly corresponding to an SBD and a p-type first well region 30 roughly corresponding to a MOSFET are repeatedly arranged in one direction in a plan view. The region in which multiple SBD-integrated MOSFETs are formed is called the active region together with a surge current-carrying region 301, which will be described later, and the region formed on the periphery of the active region and including a gate pad 81 formation region in which a p-type second well region 31 and the like are formed is called the termination region.

[0016] Fig. 3 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. Fig. 3 shows a cross section in a direction perpendicular to the longitudinal direction of the stripe from the source electrode 80 in Fig. 1 to the gate wiring 82 on the periphery of the semiconductor device.

[0017] 3, drift layer 20 made of n-type silicon carbide is formed on the surface of semiconductor substrate 10 made of n-type low-resistance silicon carbide. Second well region 31 made of p-type silicon carbide is provided in the surface layer portion of drift layer 20 at a position including the region where gate wiring 82 described in FIG. 1 is provided, as shown in the cross-sectional view of FIG.

[0018] 4 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. Here, Fig. 4 shows a cross section in a direction perpendicular to the longitudinal direction of the stripe, including the surge current carrying region 301 in Fig. 2.

[0019] 4, surge current-carrying region 301 includes auxiliary region 302 made of p-type silicon carbide and formed in a surface layer portion of drift layer 20. Auxiliary region 302 is located between Schottky electrode 71 and drift layer 20, and forms a p-n junction with drift layer 20 in the conduction path from source electrode 80 to drain electrode 84. This prevents Schottky electrode 71 from being connected to n-type silicon carbide in this region. "Connected" refers to a state in which no p-n junction is present in the conduction path, and a Schottky current can flow in the vertical or horizontal direction of the cross section of the semiconductor device.

[0020] 1, first well regions 30 made of p-type silicon carbide and formed in stripes are provided in the surface layer of drift layer 20. The first well regions 30 may be connected to each other, or a plurality of separated first well regions 30 may be provided.

[0021] In the surface layer portion of each first well region 30, a source region 40 made of n-type silicon carbide is formed at a position inward from the outer periphery of the first well region 30 by a predetermined distance.

[0022] In the surface layer portion of each first well region 30, a contact region 35 made of p-type low-resistance silicon carbide is formed further inside the source region 40, and further inside thereof, a first separating region 21 made of silicon carbide and having a stripe shape in a plan view is formed to penetrate the first well region 30. The first separating region 21 is of the same n-type as the drift layer 20, and the n-type impurity concentration of the first separating region 21 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0023] A Schottky electrode 71 having a stripe shape in a plan view is formed on the surface side of this first separating region 21, and is Schottky-connected to the first separating region 21. Here, it is desirable that the Schottky electrode 71 is formed so as to include at least the corresponding first separating region 21 when viewed from above.

[0024] An ohmic electrode 70 is formed on the surfaces of the source region 40 and the contact region 35, and a source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 35.

[0025] The region of the drift layer 20 between adjacent first well regions 30 forms an n-type second separating region 22. The n-type impurity concentration of the second separating region 22 may be the same as, or higher or lower than, the n-type impurity concentration of the drift layer 20. A gate insulating film 50 made of silicon oxide is formed on the surfaces of adjacent first well regions 30, the second separating region 22 therebetween, and the source regions 40 in each first well region 30. A gate electrode 60 made of polycrystalline silicon is formed on the gate insulating film 50 at least above the first well region 30. The surface portion of the first well region 30 facing the gate electrode 60 via the gate insulating film 50 is called a channel region.

[0026] A second well region 31 is formed outside the first well region 30 at the outermost periphery of the semiconductor device, and a third separating region 23 is formed between the first well region 30 and the second well region 31. The third separating region 23 is of the same n-type as the drift layer 20, and the n-type impurity concentration of the third separating region 23 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20. In addition, a gate insulating film 50 is also formed on the second well region 31, and on top of the gate insulating film 50, a gate electrode 60 is formed that is electrically connected to the gate electrode 60 formed on the first well region 30.

[0027] A silicon carbide conductive layer 45 made of silicon carbide is formed in a certain percentage of the upper portion of the second well region 31. The silicon carbide conductive layer 45 is n-type and has a lower resistance and a higher impurity concentration than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the second well region 31, and forms a pn junction with the p-type second well region 31. The silicon carbide conductive layer 45 is formed across a width equal to or greater than half the width of the second well region 31 in the lateral cross section. The portion where the silicon carbide conductive layer 45 is formed across a width equal to or greater than half the width of the second well region 31 in the lateral cross section does not need to cover the entire cross section, and may cover only a portion of the cross section.

[0028] An interlayer insulating film 55 made of silicon oxide is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. A p-type silicon carbide JTE region 38 is formed on the outer periphery of the second well region 31, i.e., on the opposite side to the first well region 30. The impurity concentration of the JTE region 38 is lower than the impurity concentration of the second well region 31. An FLR (Field Limiting Ring) may be formed instead of the JTE region 38. Alternatively, the JTE region 38 and the FLR may be combined.

[0029] A field insulating film 51 having a thickness larger than that of the gate insulating film 50 or the gate insulating film 50 is formed on the second well region 31 and the silicon carbide conductive layer 45. An opening, i.e., a termination region contact hole 91, is formed in a part of the gate insulating film 50 or the field insulating film 51 on the surface of the silicon carbide conductive layer 45, and through this opening, the silicon carbide conductive layer 45 is ohmically connected to the source electrode 80 formed thereon via the termination region ohmic electrode 72.

[0030] Termination region contact hole 91 penetrates field insulating film 51 and interlayer insulating film 55, and makes an ohmic connection between silicon carbide conductive layer 45 and source electrode 80. No ohmic connection is made between silicon carbide conductive layer 45 and second well region 31. In addition, silicon carbide conductive layer 45 has a width greater than the diameter of termination region contact hole 91. Here, it is assumed that the second well region 31 is not in direct ohmic contact with the source electrode 80 .

[0031] In the active region, the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 are connected to the source electrode 80 via active region contact holes 90 formed through the interlayer insulating film 55 and the gate insulating film 50. The active region contact holes 90 include a first active region contact hole 90A formed outside the surge conducting region 301 and at the end of the surge conducting region 301, and a second active region contact hole 90B formed opposite the auxiliary region 302 of the surge conducting region 301. A drain electrode 84 is formed on the back surface of the semiconductor substrate 10 .

[0032] When the plane orientation of the first main surface of the semiconductor substrate 10 is a (0001) plane having an off-angle in the <11-20> direction, the striped first well region 30 may be formed parallel to the <11-20> direction or parallel to a direction perpendicular to the off-direction.

[0033] The surge conducting region 301, a feature of the present invention, is provided in the active region and is formed over an area larger than the first width of the first well region 30 in a plan view, and has a region that cuts off the connection between the source electrode 80 and the drift layer 20. That is, the surge conducting region 301 has both vertical and horizontal lengths larger than the first width, which is the shorter width of the first well region 30. Furthermore, the area of ​​the surge conducting region 301 is sufficiently small compared to the entire active region, and is covered by the source electrode 80 in a plan view. From these points, the surge conducting region 301 can be clearly distinguished from the second well region 31, which has a large area, is formed below the gate pad 81 around the active region, and is also formed in an area not covered by the source electrode 80.

[0034] The surge conducting region 301 can be defined as a region where no first separating region 21 contacting the Schottky electrode 71 is formed and which is sandwiched between the first separating regions 21. Here, sandwiched refers to a case where the first separating regions 21 are adjacent to the entire periphery of the surge conducting region 301 in a plan view, and a case where a plurality of first separating regions 21 are periodically arranged at the end in the stripe direction as shown in FIG. 2, that is, a case where the first separating regions 21 have adjacent and non-adjacent portions.

[0035] The separation distance between two first separating regions 21 provided adjacent to one end and the other end of surge conducting region 301 is greater than the separation distance between two adjacent first separating regions 21 in the active region outside surge conducting region 301. Here, it can be said that the separation distance between two first separating regions 21 provided adjacent to one end and the other end of surge conducting region 301 corresponds to or almost corresponds to the lateral width of surge conducting region 301 in Figures 2 and 4.

[0036] When one surge current-carrying region 301 is formed in the active region, the position where it is disposed is not limited, but it can be disposed in the central region of the active region in plan view, i.e., so that the distance from the termination region to surge current-carrying region 301 is about 1 / 4 of the vertical or horizontal length of the semiconductor device. In this way, when a surge current flows through the semiconductor device, the heat generated by the surge current can be widely dispersed throughout the entire semiconductor device.

[0037] Furthermore, when two or more surge conducting regions 301 are formed in the active region, their positions are not limited, but it is preferable that the surge conducting regions 301 are uniformly distributed across the entire semiconductor device in a plan view, that is, the surge conducting regions 301 are formed so as to be periodically or equidistantly spaced in at least one direction of the semiconductor device in a plan view. In this way, when a surge current flows through the semiconductor device, the surge current tends to flow uniformly across the surface of the semiconductor device without any bias, and damage or destruction of components such as the gate insulating film 50 is suppressed.

[0038] An auxiliary region 302 may be formed in the surge current-carrying region 301, or a hole-filling auxiliary region 303 (described later) may be formed. Fig. 4 shows an example in which two auxiliary regions 302 are formed. The auxiliary region 302 has the second conductivity type, is a region that cuts off the connection between the source electrode 80 and the drift layer 20, and has a second width that is larger than the first width of the first well region 30.

[0039] In this embodiment, the auxiliary region 302 is formed by replacing the n-type first separating region 21 with a p-type layer and combining it with the two first well regions 30. The auxiliary region 302 is formed so as to cover the periodically formed active region second contact holes 90B, that is, so as to be larger than the diameter of the active region second contact holes 90B. In this layout, the width of the auxiliary region 302 is necessarily larger than the width of the first well region 30. Two examples of the advantages of this layout are given below.

[0040] First, in the surge conducting region 301, the gate electrodes 60 and the active region contact holes 90 can be formed at the same pitch as in the surrounding region. This allows the gate electrodes 60 and the active region contact holes 90 to be arranged at equal intervals in the semiconductor device, improving the uniformity of the processing. Furthermore, at the end of the surge conducting region 301 in the stripe direction, it is no longer necessary to interrupt or branch the gate electrodes 60 and the active region contact holes 90, further improving the uniformity of the processing.

[0041] Next, the gate electrode 60 is configured to penetrate the surge conducting region 301. That is, the gate electrode 60 is formed continuously inside and outside the surge conducting region 301 in a plan view. In this way, when a gate potential propagates through the gate electrode 60, the propagation of the gate potential can be uninterrupted even in the surge conducting region 301. This increases the area in which the MOSFET functions, that is, the area that can be effectively utilized, particularly in a stripe-type semiconductor device. Furthermore, when the gate electrode 60 is configured to penetrate the surge conducting region 301, the delay in the propagation of the gate potential is smaller than when the gate electrode 60 is formed to bypass the surge conducting region 301. This enables high-speed switching and suppresses local concentration of the switching current in the semiconductor device. Here, the gate electrode 60 may not be provided in the surge conducting region 301 in a plan view.

[0042] Here, in the active region first contact hole 90A that penetrates the interlayer insulating film 55, the source electrode 80 is connected to the first well region 30, the source region 40, the first separating region 21, and the Schottky electrode 71, respectively, via the active region first contact hole 90A. In the active region second contact hole 90B that penetrates the interlayer insulating film 55, the source electrode 80 is connected to the auxiliary region 302 and the Schottky electrode 71 via the active region second contact hole 90B, but is not connected to the drift layer 20. In other words, the auxiliary region 302 separates the source electrode 80 from the drift layer 20 at the active region second contact hole 90B that penetrates the interlayer insulating film 55. Here, a pn diode formed by a junction between the auxiliary region 302 and the drift layer 20 is sandwiched between the Schottky electrode 71 and the drift layer 20, and the Schottky electrode 71 and the drift layer 20 are separated in this portion, and no Schottky junction is formed.

[0043] As another feature of the present embodiment, the surge conducting region 301 is adjacent to the auxiliary region 302 or the first well region 30, connected to the drift layer 20, facing the gate electrode 60 via the gate insulating film 50, and including a second isolated region 22 of the first conductivity type adjacent to the channel region. In FIG. 4 , the surge conducting region 301 includes the second isolated region 22 sandwiched between two adjacent auxiliary regions 302 and between the auxiliary region 302 and the first well region 30. Here, the source region 40 is provided in the surface layer of the auxiliary region 302, and the gate insulating film 50 and the gate electrode 60 are formed on the region spanning from the second isolated region 22 to the source region 40. That is, a channel structure is formed in the auxiliary region 302 similar to the channel structure formed in the active region other than the surge conducting region 301.

[0044] The distance between the source region 40 and the second separating region 22 in the channel structure is called the channel length. The channel length in the auxiliary region 302 is preferably equal to the channel length in the active region other than the surge current-carrying region 301. If the channel length in the auxiliary region 302 is made too short, a short channel effect will cause current to begin flowing through the channel even at a low gate voltage, lowering the threshold voltage of the entire semiconductor device and making the semiconductor device more susceptible to malfunction. Conversely, if the channel length in the auxiliary region 302 is made too long, the current flowing through the channel will be small, making it difficult to achieve the effects described below.

[0045] For the same reason, it is preferable that the impurity concentration in the channel portion of the auxiliary region 302 is the same as the impurity concentration in the channel portion of the active region other than the surge conducting region 301. In addition, it is preferable that the thickness of the gate insulating film 50 in the channel structure of the auxiliary region 302 is the same as the thickness of the gate insulating film 50 in the active region other than the surge conducting region 301. In this way, it is possible to suppress a decrease in the gate dielectric strength voltage and a decrease in the channel current.

[0046] The above is a description of the stripe type semiconductor device.

[0047] Fig. 5 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment. The semiconductor device in Fig. 5 has a different configuration from the stripe-type SiC-MOSFET with integrated SBD shown in Fig. 2. The semiconductor device has unit cell regions, each having a MOSFET region surrounding an SBD region, repeatedly arranged vertically and horizontally in a plan view, and is called a "lattice type." The lattice type semiconductor device will be described below.

[0048] 5, unit cell regions each consisting of an n-type first isolation region 21 roughly corresponding to an SBD and a p-type first well region 30 roughly corresponding to a MOSFET are repeatedly arranged vertically and horizontally in a plan view. The region combining the region in which the SBD-integrated MOSFET is formed and the surge current carrying region 301 is called the active region, and the region formed on the periphery of the active region and including the gate pad 81 forming region in which the p-type second well region 31 and the like are formed is called the termination region.

[0049] 6 is a cross-sectional view showing a schematic configuration of the semiconductor device in the embodiment 1. Here, FIG. 6 shows a cross section from the source electrode 80 in FIG. 1 to the gate wiring 82 on the periphery of the semiconductor device.

[0050] 6, drift layer 20 made of n-type silicon carbide is formed on the surface of semiconductor substrate 10 made of n-type low-resistance silicon carbide. Second well region 31 made of p-type silicon carbide is provided in the surface layer portion of drift layer 20 at a position substantially corresponding to the region where gate wiring 82 described in FIG. 1 is provided, as shown in the cross-sectional view of FIG.

[0051] In the active region below the region where the source electrode 80 described with reference to FIG. 1 is provided, a plurality of first well regions 30 made of p-type silicon carbide are provided in the surface layer portion of the drift layer 20.

[0052] In the surface layer portion of each first well region 30, a source region 40 made of n-type silicon carbide is formed at a position inward from the outer periphery of the first well region 30 by a predetermined distance.

[0053] In the surface layer portion of each first well region 30, a contact region 35 made of low-resistance p-type silicon carbide is formed further inside the source region 40, and further inside that, a first separating region 21 made of silicon carbide is formed penetrating the first well region 30. The first separating region 21 is of the same n-type as the drift layer 20, and the n-type impurity concentration of the first separating region 21 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0054] A Schottky electrode 71 is formed on the surface side of this first separating region 21, making a Schottky connection with the first separating region 21. Here, it is desirable that the Schottky electrode 71 is formed so as to include at least the corresponding first separating region 21 when viewed from above.

[0055] An ohmic electrode 70 is formed on the surface of the source region 40, and a source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 35.

[0056] The region of the drift layer 20 between adjacent first well regions 30 forms an n-type second separating region 22. The n-type impurity concentration of the second separating region 22 may be the same as, or higher or lower than, the n-type impurity concentration of the drift layer 20. A gate insulating film 50 made of silicon oxide is formed on the surfaces of adjacent first well regions 30, the second separating region 22 therebetween, and the source regions 40 in each first well region 30. A gate electrode 60 made of polycrystalline silicon is formed on the gate insulating film 50 at least above the first well region 30. The surface portion of the first well region 30 facing the gate electrode 60 via the gate insulating film 50 is called a channel region.

[0057] A second well region 31 is formed outside the first well region 30 at the outermost periphery of the semiconductor device, and a third separating region 23 is formed between the first well region 30 and the second well region 31. The third separating region 23 is of the same n-type as the drift layer 20, and the n-type impurity concentration of the third separating region 23 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20. In addition, a gate insulating film 50 is also formed on the second well region 31, and on top of the gate insulating film 50, a gate electrode 60 is formed that is electrically connected to the gate electrode 60 formed on the first well region 30.

[0058] A silicon carbide conductive layer 45 made of silicon carbide is formed in a certain percentage of the upper portion of the second well region 31. The silicon carbide conductive layer 45 is n-type and has a lower resistance and a higher impurity concentration than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the second well region 31, and forms a pn junction with the p-type second well region 31. The silicon carbide conductive layer 45 is formed across a width equal to or greater than half the width of the second well region 31 in the lateral cross section. The portion where the silicon carbide conductive layer 45 is formed across a width equal to or greater than half the width of the second well region 31 in the lateral cross section does not need to cover the entire cross section, and may cover only a portion of the cross section.

[0059] An interlayer insulating film 55 made of silicon oxide is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. A p-type silicon carbide JTE region 38 is formed on the outer periphery of the second well region 31, i.e., on the opposite side to the first well region 30. The impurity concentration of the JTE region 38 is lower than the impurity concentration of the second well region 31. An FLR (Field Limiting Ring) may be formed instead of the JTE region 38. Alternatively, the JTE region 38 and the FLR may be combined.

[0060] A field insulating film 51 having a thickness larger than that of the gate insulating film 50 or the gate insulating film 50 is formed on the second well region 31 and the silicon carbide conductive layer 45. An opening, i.e., a termination region contact hole 91, is formed in a part of the gate insulating film 50 or the field insulating film 51 on the surface of the silicon carbide conductive layer 45, and through this opening, the silicon carbide conductive layer 45 is ohmically connected to the source electrode 80 formed thereon via the termination region ohmic electrode 72.

[0061] Termination region contact hole 91 penetrates field insulating film 51 and interlayer insulating film 55, and makes an ohmic connection between silicon carbide conductive layer 45 and source electrode 80. No ohmic connection is made between silicon carbide conductive layer 45 and second well region 31. In addition, silicon carbide conductive layer 45 has a width greater than the diameter of termination region contact hole 91. Here, it is assumed that the second well region 31 is not in direct ohmic contact with the source electrode 80 .

[0062] In the active region, the ohmic electrode 70 , the Schottky electrode 71 and the contact region 35 are connected to the source electrode 80 via an active region contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50 . A drain electrode 84 is formed on the back surface of the semiconductor substrate 10 .

[0063] Fig. 7 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. Fig. 7 shows a surge conducting region 301, an auxiliary region 302, an active region contact hole 90 formed in the surge conducting region 301, and the like. The configurations of the surge conducting region 301 and the auxiliary region 302 in Fig. 7 are the same as those of the stripe-type semiconductor device shown in Fig. 4, and therefore a description thereof will be omitted.

[0064] The above is a description of the lattice type semiconductor device.

[0065] Here, we will explain the common features of both stripe-type and lattice-type semiconductor devices. The region of the active region closest to the termination region may have a high-area-density SBD structure, such as a folded structure. The region of the termination region closest to the active region may also have a high-area-density SBD structure at the termination region, such as a region with many SBDs, such as JBS. A sense cell for sensing current may also be provided inside the active region. By making the concentration of n-type impurities in the second isolation region 22 higher than the concentration of n-type impurities in the drift layer 20, the on-resistance can be reduced.

[0066] Next, a method for manufacturing an SiC-MOSFET with built-in SBD, which is the semiconductor device of this embodiment, will be described with reference to the explanatory diagrams of FIGS.

[0067] First, a 1×10 SiO 2 film was deposited by chemical vapor deposition (CVD) on a semiconductor substrate 10 made of n-type, low-resistance silicon carbide having a first main surface with a (0001) plane orientation having an off-angle and a polytype of 4H. 15 cm -3 That's it, 1 x 10 17 cm -3 Drift layer 20 made of n-type silicon carbide with the following impurity concentration and a thickness of 5 μm or more and 50 μm or less is epitaxially grown.

[0068] Next, an implantation mask is formed using photoresist or the like in a predetermined region on the surface of the drift layer 20, and Al (aluminum), a p-type impurity, is ion-implanted. At this time, the depth of the Al ion implantation is set to about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20. The impurity concentration of the implanted Al is 1×10 17 cm -3 That's it, 1 x 10 19 cm -3The impurity concentration is set to the range below and is higher than the impurity concentration of the drift layer 20. The implantation mask is then removed. The region implanted with Al ions in this step becomes the first well region 30 in the active region and the second well region 31 in the termination region.

[0069] Furthermore, at a position different from the first well region 30, an implantation mask is formed using photoresist or the like in a predetermined region on the surface of the drift layer 20, and Al (aluminum), a p-type impurity, is ion-implanted. At this time, the depth of the Al ion implantation is set to about 0.5 μm or more and 3 μm or less so as not to exceed the thickness of the drift layer 20. The impurity concentration of the implanted Al is 1×10 17 cm -3 That's it, 1 x 10 19 cm -3 or less and is higher than the impurity concentration of the drift layer 20. Then, the implantation mask is removed. The region implanted with Al ions in this step becomes the auxiliary region 302.

[0070] A channel portion will be formed in the surface of the auxiliary region 302 in a later process, and the threshold voltage of the channel portion of the auxiliary region 302 only needs to be equal to or higher than the threshold voltage of the channel portion of the active region other than the surge conducting region 301, and preferably the same. Therefore, the p-type impurity concentration in the surface of the auxiliary region 302 should be equal to or higher than the p-type impurity concentration in the surface of the first well region 30. One way to achieve this is to form the auxiliary region 302 simultaneously with the first well region 30. This method allows the p-type impurity concentrations in the surfaces of the auxiliary region 302 and the first well region 30 to be the same, thereby reducing the number of processes.

[0071] Next, an implantation mask is formed using photoresist or the like, and Al ions, which are p-type impurities, are implanted into the surface of the drift layer 20 in the termination region. At this time, the depth of the Al ion implantation is set to about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20. The impurity concentration of the implanted Al ions is 1×10 16 cm -3 That's it, 1 x 10 18 cm -3The impurity concentration is set to the range below, which is higher than the impurity concentration of the drift layer 20 and lower than the impurity concentrations of the first well region 30 and the auxiliary region 302. Then, the implantation mask is removed. The region into which Al is ion-implanted by this process becomes the JTE region 38. Similarly, a predetermined region is implanted with 1×10 Al, which is higher than the impurity concentration of the first well region 30 or the auxiliary region 302. 16 cm -3 That's it, 1 x 10 18 cm -3 The contact region 35 is formed by ion implanting Al with an impurity concentration in the following range.

[0072] Next, an implantation mask is formed using photoresist or the like so that predetermined locations inside the first well region 30 and the auxiliary region 302 on the surface of the drift layer 20 are opened, and N (nitrogen) as an n-type impurity is ion-implanted. The depth of N ion implantation is shallower than the thickness of the first well region 30. The impurity concentration of the ion-implanted N is 1×10 18 cm -3 That's it, 1 x 10 21 cm -3 The range is as follows, and exceeds the p-type impurity concentration of the first well region 30 and the auxiliary region 302. The region that exhibits n-type among the regions into which N is implanted in this step becomes the source region 40.

[0073] Similarly, an implantation mask is formed using photoresist or the like so that a predetermined location inside the second well region 31 of the termination region is opened, and N (nitrogen), an n-type impurity, is ion-implanted. The depth of N ion implantation is shallower than the thickness of the first well region 30. The impurity concentration of the ion-implanted N is 1×10 18 cm -3 That's it, 1 x 10 21 cm -3 The concentration of the impurity is within the following range, and exceeds the p-type impurity concentration of the first well region 30 and the auxiliary region 302. Of the regions into which N is implanted in this step, the region exhibiting n-type impurity becomes the silicon carbide conductive layer 45. The thickness of the silicon carbide conductive layer 45 only needs to be smaller than the thickness of the second well region 31.

[0074] Silicon carbide conductive layer 45 and source region 40 may be formed in the same process with the same thickness and impurity concentration, or silicon carbide conductive layer 45 and source region 40 may be formed in different processes with different thicknesses and different impurity concentrations.

[0075] Next, annealing is performed in a heat treatment device in an inert gas atmosphere such as argon (Ar) gas at a temperature of about 1300°C or higher and 1900°C or lower for about 30 seconds or higher and 1 hour or lower. This annealing electrically activates the implanted N and Al ions. In the active region after the ion implantation, a cross section not including the surge current carrying region 301 and a cross section including the surge current carrying region 301 are shown in FIGS. 8 and 9, respectively.

[0076] Next, using a CVD method, photolithography technology, or the like, a field insulating film 51 is formed on the semiconductor layer in a region excluding the active region roughly corresponding to the region where the first well region 30 is formed and the surge current carrying region 301. The field insulating film 51 has a thickness of approximately 0.5 μm or more and 2 μm or less, which is larger than the thickness of the gate insulating film 50, and is made of silicon oxide.

[0077] Next, the silicon carbide surface not covered by field insulating film 51 is thermally oxidized to form a silicon oxide film of the desired thickness, i.e., gate insulating film 50. Subsequently, a conductive polycrystalline silicon film is formed on gate insulating film 50 and field insulating film 51 by low-pressure CVD, and this is patterned to form gate electrode 60. Next, interlayer insulating film 55 made of silicon oxide and having a thickness greater than that of gate insulating film 50 is formed by low-pressure CVD. Cross sections of the active region that have been processed up to this stage, excluding surge conducting region 301 and including surge conducting region 301, are shown in Figures 10 and 11, respectively.

[0078] Next, an active region contact hole 90 is formed, which penetrates interlayer insulating film 55 and gate insulating film 50 and reaches contact region 35 and source region 40 in the active region, and a termination region contact hole 91 is formed, which penetrates interlayer insulating film 55 and gate insulating film 50 and reaches silicon carbide conductive layer 45 in the termination region. However, at this stage, the insulating film is left in the area inside active region contact hole 90 and termination region contact hole 91 where Schottky electrode 71 will be formed.

[0079] Next, a metal film primarily composed of Ni is formed by sputtering or the like, followed by heat treatment at a temperature of approximately 600°C to 1100°C. This reacts the Ni-based metal film with the silicon carbide layer inside active region contact hole 90 and termination region contact hole 91, forming silicide between the silicon carbide layer and the metal film. Next, the remaining metal film, excluding the silicide formed by the reaction, is removed by wet etching. The remaining silicide becomes ohmic electrode 70 and termination ohmic electrode 72. Cross sections of the active region after this process are shown in Figures 12 and 13, respectively, excluding surge current-carrying region 301 and including surge current-carrying region 301.

[0080] Next, a metal film mainly composed of Ni is formed on the back surface (second main surface) of semiconductor substrate 10, and heat treatment is performed to form a back surface ohmic electrode (not shown) on the back surface of semiconductor substrate 10. Next, a resist mask 99 is formed, and interlayer insulating film 55 and gate insulating film 50 above first separation region 21 and auxiliary region 302 are removed, as well as interlayer insulating film 55 at a position that will become gate contact hole 95. As a removal method, wet etching is used, which does not damage the surface of the silicon carbide layer that will become the Schottky interface, but dry etching can also be used. Cross sections of the active region that have been processed up to this stage, excluding surge conducting region 301 and including surge conducting region 301, are shown in FIGS. 14 and 15, respectively.

[0081] Next, after removing the resist mask 99, a metal film that will become the Schottky electrode 71 is deposited by sputtering or the like, and then patterned with photoresist or the like to form the Schottky electrode 71 on the first separating region 21 in the active region contact hole 90. The material for the Schottky electrode 71 may be Ti, Mo, or the like. The Schottky electrodes 71 may be patterned so as to be formed separately in each active region contact hole 90, or may be formed on one surface of the source electrode 80. The Schottky electrodes 71 and the source electrode 80 can be patterned together, thereby reducing the number of steps.

[0082] Next, wiring metal such as Al is formed by sputtering or vapor deposition on the surface of the substrate that has been processed up to this point, and then processed into a predetermined shape by photolithography to form a source electrode 80 that contacts the source-side ohmic electrode 70, the termination ohmic electrode 72, and the Schottky electrode 71, as well as a gate pad 81 and gate wiring 82 that contact the gate electrode 60. In addition, a drain electrode 84 that is a metal film is formed on the surface of the backside ohmic electrode (not shown).

[0083] In this manner, the semiconductor device of this embodiment shown in FIGS. 1 to 7 can be manufactured.

[0084] Next, the operation of the SBD-integrated SiC-MOSFET, which is the semiconductor device of this embodiment, will be explained. Here, using a semiconductor device whose semiconductor material is 4H-type silicon carbide as an example, we will briefly explain four states in normal operation and one abnormal state. When the semiconductor material is 4H-type silicon carbide, the built-in potential of the pn junction is approximately 2 V.

[0085] The first state in normal operation is a state in which a high voltage is applied to the drain electrode 84 relative to the source electrode 80, and a positive voltage equal to or greater than the threshold voltage is applied to the gate electrode 60, hereinafter referred to as the "on state."

[0086] In the on state, an inversion channel is formed in the channel region, and a path is formed through which electrons, which are carriers, flow between the n-type source region 40 and the n-type second separating region 22. On the other hand, an electric field (reverse bias) is applied to the Schottky junction formed at the contact portion between the first separating region 21 and the Schottky electrode 71 in a direction that makes it difficult for a current to flow through the Schottky junction, i.e., in the reverse direction, so that no current flows.

[0087] Electrons flowing from the source electrode 80 to the drain electrode 84 follow an electric field formed by a positive voltage applied to the drain electrode 84, and reach the drain electrode 84 from the source electrode 80 via the ohmic electrode 70, the source region 40, the channel region, the second separation region 22, the drift layer 20, and the semiconductor substrate 10. Therefore, by applying a positive voltage to the gate electrode 60, an on-current flows from the drain electrode 84 to the source electrode 80.

[0088] The voltage applied between source electrode 80 and drain electrode 84 at this time is called the on-voltage. The value obtained by dividing the on-voltage by the density of the on-current is called the on-resistance, and the on-resistance is equal to the total resistance of the path along which electrons flow from source electrode 80 to drain electrode 84. The product of the on-resistance and the square of the on-current is equal to the conduction loss consumed by the MOSFET when it is conducting, so a low on-resistance is preferable.

[0089] In this embodiment, a channel structure is formed in the surge conducting region 301, so that in the on-state, the surge conducting region 301 can serve as a path for electrons flowing from the source electrode 80 to the drain electrode 84. Therefore, the surge conducting region 301 can contribute to reducing the on-resistance.

[0090] The second state of normal operation is where a high voltage is applied to the drain electrode 84 relative to the source electrode 80 and a voltage below the threshold voltage is applied to the gate electrode 60, hereafter referred to as the "off state."

[0091] In the off state, there are no inversion carriers in the channel region, so no on-state current flows, and the high voltage that is applied to a load such as an inverter in the on state is applied between the source electrode 80 and the drain electrode 84 of the MOSFET.

[0092] An electric field is applied in the same direction as in the on state to the Schottky junction formed at the contact between first separation region 21 and Schottky electrode 71, so ideally no current flows. However, a much stronger electric field than in the on state is applied, so a leakage current may occur. A large leakage current increases heat generation in the MOSFET and may thermally destroy the MOSFET and the module using the MOSFET. Therefore, it is preferable to keep the electric field applied to the Schottky junction low in order to reduce the leakage current.

[0093] The third state during normal operation is a state in which a low voltage is applied to the drain electrode 84 relative to the source electrode 80, i.e., a back-EMF voltage is applied to the MOSFET, and a voltage below the threshold is applied to the gate electrode 60, causing a reflux current to flow from the source electrode 80 to the drain electrode 84. Hereinafter, this state will be referred to as the "asynchronous rectification state."

[0094] In the asynchronous rectification state, in the active region other than the surge conducting region 301, a forward electric field (forward bias) is applied to the Schottky junction formed at the contact portion between the first separation region 21 and the Schottky electrode 71, and a unipolar current consisting of an electron current flows from the Schottky electrode 71 toward the n-type first separation region 21. Here, the freewheeling current component of the freewheeling diode is mainly this unipolar component. In addition, the source electrode 80 and the first well region 30 are at the same potential via the ohmic electrode 70.

[0095] As a result, a forward bias is also applied to the pn junction between the p-type first well region 30 and the n-type drift layer 20. Here, the pn junction is formed in parallel with the above-mentioned Schottky junction, and the threshold voltage of the Schottky junction is lower than the threshold voltage of the pn junction. Therefore, when changing from the off state to the asynchronous rectification state, the reflux current mainly flows via the Schottky junction, and it is possible to prevent the reflux current from flowing via the pn junction.

[0096] In addition, even when the voltage applied between the source electrode 80 and the drain electrode 84 exceeds the built-in potential of the p-n junction, only a unipolar current can flow through the Schottky junction. This is because the voltage applied between the source electrode 80 and the drain electrode 84 causes a unipolar current to flow in the drift layer 20, causing a voltage drop in the drift layer 20, and the voltage applied to the p-n junction is the voltage applied between the source electrode 80 and the drain electrode 84 minus this voltage drop, preventing a unipolar current from flowing through the p-n junction. Therefore, a voltage exceeding the built-in potential of the p-n junction can be applied between the source electrode 80 and the drain electrode 84.

[0097] Thus, incorporating an SBD into a semiconductor device such as a MOSFET can suppress the flow of bipolar forward current through the p-n junction, even during asynchronous rectification. If a bipolar current flows through the p-n junction and a basal plane dislocation or other initiation point is present at this location, stacking faults will expand. Because stacking faults block current flowing in the thickness direction of the semiconductor device, the expansion of stacking faults increases the on-resistance, potentially leading to thermal runaway and device failure. By incorporating an SBD into a semiconductor device, bipolar current can be suppressed from flowing through the p-n junction during reflux, improving the reliability of the semiconductor device.

[0098] On the other hand, in the asynchronous rectification state, the first separation region 21 connected to the Schottky electrode 71 does not exist in the surge conduction region 301, so that a unipolar current does not easily flow. The unipolar current flowing into the drift layer 20 via the junction between the Schottky electrode 71 and the first separation region 21 adjacent to the surge conduction region 301 diffuses in the planar direction within the drift layer 20 and flows into the drift layer 20 within the surge conduction region 301. The current density of this unipolar current is smaller than the current density of the unipolar current flowing in regions other than the surge conduction region 301.

[0099] Therefore, the bipolar current flowing through the pn junction in surge conducting region 301 is larger than the bipolar current flowing through the pn junction in the active region other than surge conducting region 301. Therefore, stacking faults may expand in surge conducting region 301, increasing the on-resistance of the semiconductor device. However, if the area of ​​surge conducting region 301 is set to 10% or less of the entire semiconductor device, even if stacking faults expand throughout surge conducting region 301, the increase in on-resistance of the semiconductor device can be suppressed to approximately 10% or less. Generally, a design margin of about 20% is provided for on-resistance in consideration of manufacturing variations in on-resistance and thermal resistance. Therefore, by setting surge conducting region 301 to 20% or less of the active region, and more preferably 10% or less, thermal runaway breakdown due to increased on-resistance can be avoided.

[0100] The fourth state during normal operation is a state in which a low voltage is applied to the drain electrode 84 relative to the source electrode 80, i.e., a back-electromotive force is applied to the MOSFET, and a voltage equal to or greater than the threshold voltage is applied to the gate electrode 60, causing a reflux current to flow from the source electrode 80 to the drain electrode 84. Hereinafter, this state will be referred to as the "synchronous rectification state."

[0101] In the synchronous rectification state, a unipolar current flows through the Schottky electrode 71 and a unipolar current flows through the channel. In this embodiment, the channel is also formed on the surface of the auxiliary region 302, i.e., in the surge current-carrying region 301, so that a channel current also flows in the surge current-carrying region 301, and this channel current carries the unipolar current. Therefore, even if the surge current-carrying region 301 does not have a junction between the Schottky electrode 71 and the first separation region 21, it is possible to prevent the pn junction in the surge current-carrying region 301 from turning on.

[0102] The flow of channel current even in the surge current-carrying region 301 has a significant effect in suppressing heat concentration during synchronous rectification. First, taking inverter operation as an example, the operating time in synchronous rectification state accounts for approximately half of the carrier period, and is expected to be a long time of tens of microseconds to several milliseconds. This is much longer than the operating time in asynchronous rectification state, which is expected to be a short time of several hundred nanoseconds to several microseconds. If current continues to flow through the pn junction for such a long time, it will cause localized heat generation. This is because bipolar current causes conductivity modulation compared to unipolar current, which has the effect of reducing drift resistance.

[0103] In the region where the bipolar current flows, the resistance decreases, and a larger current flows than in the region where only the unipolar current flows. As a result, the local temperature in the region where the bipolar current flows rises, further increasing the conductivity modulation, and a positive feedback loop occurs in which current concentration occurs. This can result in degradation of reliability, such as cracks at the electrode junction and destruction of the gate insulating film 50. The structure shown in this embodiment can suppress the operation of the pn junction in the surge current-carrying region 301 even during synchronous rectification, thereby avoiding localized heat generation and achieving high reliability.

[0104] The abnormal state is a state in which a surge current flows between the source electrode 80 and the drain electrode 84, and this will be explained. This refers to a state in which a current exceeding the rated current flows from the source electrode 80 to the drain electrode 84 momentarily, such as when an inverter malfunctions or when the converter is turned on. In many cases, it is assumed that an OFF signal is applied to the gate electrode 60, and no current flows through the channel region. Even in such a case, the semiconductor device must not fail due to heat generation, and the allowable current at this time is called surge resistance. To increase surge resistance, it is essential to provide a low-resistance region to allow the surge current to flow and reduce heat generation in the semiconductor device.

[0105] However, because such abnormal states occur infrequently, they are not recognized as problems, or are difficult to recognize as problems.

[0106] From the viewpoint of increasing surge resistance, it is preferable to use bipolar current, which is greatly affected by conductivity modulation. When a surge current starts to flow in the semiconductor device, surge current-carrying region 301 does not include first separation region 21 connected to Schottky electrode 71, and therefore unipolar current does not easily flow therethrough. Therefore, compared to active regions other than surge current-carrying region 301, pn junctions are more likely to turn on, and current flow by bipolar current is more likely to begin therethrough.

[0107] In this state, if the surge current increases over time and reaches a large current exceeding the rated current, the bipolar current flowing from the surge current-carrying region 301 increases, causing holes to diffuse from the surge current-carrying region 301 toward the active region outside it. In the active region outside the surge current-carrying region 301, the resistance of the drift layer 20 decreases, the unipolar current density increases, and the pn junction turns on. Then, holes diffuse further toward the outer region, turning on the pn diode in that region. In other words, when a surge current occurs, the surge current-carrying region 301 starts to spread and spreads to the surrounding area, turning on pn diodes one after another toward the outside of the surge current-carrying region 301.

[0108] As a result, the pn diodes are turned on over a wide range of the semiconductor device, resulting in a bipolar conduction state, which suppresses heat generation in the semiconductor device. In other words, the allowable surge current can be increased, and surge resistance can be improved.

[0109] In this way, the surge current-carrying region 301 not only increases the current that can flow through the surge current-carrying region 301, but also changes the characteristics of a wide range of the semiconductor device through a chain reaction. Therefore, it is not necessary for one or more surge current-carrying regions 301 to occupy too large an area of ​​the semiconductor device. On the other hand, the surge current-carrying region 301 may cause bipolar operation during asynchronous rectification, which may lead to reliability degradation due to the expansion of stacking faults. Therefore, the area or total area of ​​the surge current-carrying region 301 in a plan view should be 20% or less, preferably 10% or less, of the overall area of ​​the semiconductor device. This can suppress characteristic degradation due to the expansion of stacking faults and the resulting thermal runaway, thereby improving surge resistance.

[0110] When multiple surge conducting regions 301 are formed, the separation distance between any two surge conducting regions 301 may be at least three times the width of the surge conducting region 301, and preferably at least ten times the width. Here, the width of the surge conducting region 301 corresponds to the separation distance between two first separating regions 21 provided adjacent to one end and the other end of the surge conducting region 301. If the separation distance is at least three times the width of the surge conducting region 301, the proportion of the surge conducting region 301 in the entire semiconductor device can be 10% or less, even if the surge conducting region 301 is formed in a square shape. Furthermore, if the separation distance is at least ten times the width of the surge conducting region 301, the proportion of the surge conducting region 301 in the entire semiconductor device can be 10% or less, even if the surge conducting region 301 is formed in a rectangular shape that crosses the active region from end to end.

[0111] In order for the surge conducting region 301 to effectively act as a starting point for pn diode operation when a surge current begins to flow through the semiconductor device, it is important to reduce the density of the unipolar current diffusing from outside the surge conducting region 301 into the surge conducting region 301. This unipolar current density is strongly dependent on the distance from the surge conducting region 301 to the connection between the Schottky electrode 71 and the first separating region 21, and decreases as this distance increases. Therefore, it is preferable to form the surge conducting region 301 wide, and it needs to be at least larger than the separation distance between adjacent first separating regions 21 in the active region outside the surge conducting region 301. In other words, the surge conducting region 301 is formed over an area larger than the first width of the first well region 30 in a plan view.

[0112] In this embodiment, an active region second contact hole 90B is formed in the surge current-carrying region 301 to connect the source electrode 80 and the auxiliary region 302. With this configuration, when a surge current flows through the semiconductor device, the surge current can pass through a short path in the vertical direction of the cross section and with a relatively small resistance, meaning that a large surge current can flow.

[0113] Furthermore, to further increase surge resistance, it is preferable to form multiple surge conduction regions 301 and arrange them evenly across the entire active region. That is, as described in the explanation of the stripe-type configuration of this embodiment, it is preferable to provide the surge conduction regions 301 periodically or at equal intervals in at least one direction of the semiconductor device in a plan view. In this way, when a surge current flows through the semiconductor device and the ON operation of pn diodes starts from the surge conduction region 301 and chains to the surroundings, the ON operation of pn diodes can be chained evenly across the entire semiconductor device. This also makes it possible to distribute heat generation locations in the semiconductor device.

[0114] Furthermore, when the semiconductor device is a lattice type, the corners of the chip in the termination region may be as shown in the schematic plan view of the semiconductor device according to the first embodiment in Fig. 16. In Fig. 16, a surge current-carrying region 301 may be provided.

[0115] Furthermore, when the semiconductor device is a lattice type, the corners of the gate pad 81 may be as shown in the schematic plan view of the semiconductor device according to the first embodiment shown in Fig. 17. In Fig. 17, the gate pad 81 is formed in a location where a large second well region 31 is formed. In Fig. 17, a surge current-carrying region 301 may be provided.

[0116] <Embodiment 2> 18 is a cross-sectional view showing a schematic configuration of a semiconductor device according to embodiment 2. This embodiment differs from embodiment 1 in that it does not have a second isolated region 22 of the first conductivity type that is adjacent to auxiliary region 302 or first well region 30, is connected to drift layer 20, and faces gate electrode 60 via gate insulating film 50. In other words, second isolated region 22 is not formed in surge current-carrying region 301, and auxiliary region 302 is formed continuously. Otherwise, the configuration is the same as that of embodiment 1.

[0117] In the surge current carrying region 301 of this embodiment, the region including the first well region 30, the first isolation region 21, and the second isolation region 22 is replaced with an auxiliary region 302.

[0118] In this way, no channel is formed in the surge conducting region 301, and therefore, whether the gate is turned on or off in the semiconductor device, the pn diode consisting of the auxiliary region 302 in the surge conducting region 301 and the drift layer 20 turns on, and this makes it easier for the on operation of the pn diode to propagate outside the surge conducting region 301, thereby improving the surge resistance.

[0119] <Third Embodiment> 19 is a cross-sectional view showing a schematic configuration of a semiconductor device according to embodiment 3. This embodiment differs from embodiment 1 in that first isolation region 21 of surge current-carrying region 301 is replaced with p-type hole-filling assist region 303, but the other configurations are the same.

[0120] In the surge current carrying region 301 of this embodiment, the combined region of the first well region 30 and the hole filling auxiliary region 303 is replaced with an auxiliary region 302 .

[0121] In this way, it is possible to eliminate the junction between Schottky electrode 71 and first separation region 21 in surge current-carrying region 301, and form a pn diode. These effects are similar to those described in the first and second embodiments.

[0122] The hole-filling assist region 303 may be formed by a p-type ion implantation process, and if it is formed simultaneously with the JTE region 38 or the contact region 35, an increase in the number of processes can be avoided.

[0123] <Fourth Embodiment> 20 is a cross-sectional view showing a schematic configuration of a semiconductor device according to embodiment 4. In this embodiment, unlike embodiment 2, the auxiliary region 302 is not formed in the surge conducting region 301, and the first well region 30, the source region 40, the gate electrode 60, etc. are arranged in the same manner as in the active region around the surge conducting region 301.

[0124] By not forming auxiliary region 302 and active region second contact hole 90B, the connection between Schottky electrode 71 and first separation region 21 is cut off. Since active region second contact hole 90B does not exist in surge conducting region 301, the effect achieved in this embodiment is the same as that in embodiment 2.

[0125] Up to this point, we have described a unit cell structure in which an SBD and a MOSFET are integrated in the active region. However, the SBD and the MOSFET may also be arranged in parallel within the unit cell formed in the active region.

[0126] <Fifth Embodiment> Fig. 21 is a plan view schematically illustrating a configuration of a semiconductor device according to a fifth embodiment. Fig. 21 mainly illustrates a portion of the silicon carbide semiconductor portion in Fig. 1. In the semiconductor device shown in Fig. 21, in an active region, striped gate trenches GT in which transistors are formed and striped Schottky trenches ST in which Schottky electrodes 71 are embedded are arranged parallel to each other and alternately. In addition, a second well region 31 is formed in a termination region around the active region.

[0127] 22 is a schematic plan view showing a schematic configuration of a semiconductor device according to the fifth embodiment, illustrating an enlarged view of an active region of the semiconductor device. A first connection region 36 and a second connection region 37 made of p-type silicon carbide are formed at regular intervals on the sides of the gate trench GT and the Schottky trench ST, respectively. In the surge current-carrying region 301, a hole-filling assist region 303 is formed between adjacent second connection regions 37 on the sides of the Schottky trench ST.

[0128] The termination region of the semiconductor device may be formed in the same manner as a planar type MOSFET with an integrated SBD, or may have a different structure to suit a trench type. Here, only the active region will be described.

[0129] Fig. 23 is a cross-sectional view showing a schematic configuration of a semiconductor device according to embodiment 5. Fig. 23 shows a cross section of a portion of Fig. 22 where the hole-filling assist region 303 is formed in the surge current-carrying region 301 and the first connection region 36 and the second connection region 37 are not formed.

[0130] Fig. 24 is a cross-sectional view showing a schematic configuration of a semiconductor device according to embodiment 5. Fig. 24 shows a cross section of a portion of Fig. 22 where hole-filling assist region 303 is formed in surge current-carrying region 301 and where first connection region 36 and second connection region 37 are formed.

[0131] 23 and 24, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistance silicon carbide. A first well region 30 made of p-type silicon carbide is formed in a surface layer portion of drift layer 20.

[0132] A source region 40 made of n-type silicon carbide is formed in a surface layer portion on the first well region 30. A low-resistance p-type contact region 35 is formed adjacent to the source region 40 in a surface layer portion on the first well region 30.

[0133] In the active region, a gate trench GT is formed, penetrating the source region 40 and the first well region 30 to reach the drift layer 20. In addition, a Schottky trench ST is formed in another location, penetrating the source region 40 and the first well region 30 to reach the drift layer 20.

[0134] The gate trenches GT and the Schottky trenches ST are arranged alternately and parallel to each other. The gate trenches GT and the Schottky trenches ST are formed to the same depth, but the depths of the two may be different. Furthermore, the gate trenches GT and the Schottky trenches ST may be formed to the same width, or the widths of the two may be different.

[0135] A gate electrode 60 is formed in the gate trench GT via a gate insulating film 50 made of silicon oxide. The gate electrode 60 is made of polycrystalline silicon with a high impurity concentration and low resistance. An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60. A Schottky electrode 71 and a source electrode 80 are formed in the Schottky trench ST, and the Schottky electrode 71 is formed in contact with the drift layer 20 and is Schottky-connected to the drift layer 20.

[0136] A p-type first protection region 32 is formed in the drift layer 20 below the gate trench GT. A p-type second protection region 33 is formed in the drift layer 20 below the Schottky trench ST. The first protection region 32 and the second protection region 33 have the same depth and the same impurity concentration. The first protection region 32 and the first well region 30 are connected by a p-type first connection region 36. The second protection region 33 and the first well region 30 are connected by a p-type second connection region 37.

[0137] An ohmic electrode 70 is formed on the surface of the source region 40, and a source electrode 80 connected to the ohmic electrode 70, a Schottky electrode 71, and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 35. The source electrode 80 is also connected to the Schottky electrode 71 in the Schottky trench ST.

[0138] A region along the side surface of the gate trench GT in the first well region 30, which faces the gate electrode 60 via the gate insulating film 50, is called a channel region. A Schottky diode is formed in a region on the side surface of the Schottky trench ST where the Schottky electrode 71 and the drift layer 20 are in contact with each other. A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10.

[0139] In this embodiment, the first separating region 21 contacts the side surface of the Schottky trench ST and corresponds to a region between the first well region 30 contacting the Schottky trench ST and the second protection region 33. The second separating region 22 contacts the side surface of the gate trench GT and corresponds to a region between the first well region 30 contacting the gate trench GT and the first protection region 32.

[0140] 23 and 24, first separation region 21 is replaced with a filling auxiliary region 303 that contacts the side surface of Schottky trench ST. Furthermore, Schottky electrode 71 is prevented from being connected to n-type first separation region 21 by p-type filling auxiliary region 303.

[0141] The second well region 31 in the termination region may be formed to the same depth as the first well region 30 in the active region, or may be formed to the same depth as the first protection region 32 and the second protection region 33 in the active region, that is, to the depth of the bottoms of the gate trench GT and the Schottky trench ST. A low-resistance n-type silicon carbide conductive layer 45 may be formed in a surface layer portion of the second well region 31. Furthermore, the second well region 31 may not be in direct ohmic contact with the source electrode 80.

[0142] Next, a method for manufacturing a trench-type SiC-MOSFET with built-in SBD, which is the semiconductor device of this embodiment, will be described with reference to the explanatory diagrams of Figures 25 to 30. Here, a cross section of a portion where surge current-carrying region 301 is formed and first connection region 36 and second connection region 37 are not formed is shown.

[0143] First, a semiconductor substrate 10 is prepared, which is made of n-type, low-resistance silicon carbide and has a first main surface with a plane orientation of (0001) having an off-angle and a polytype of 4H. Then, a drift layer 20 made of n-type silicon carbide is epitaxially grown on the semiconductor substrate 10 by a CVD method. The impurity concentration of the drift layer 20 is 1×10 15 cm -3 That's it, 1 x 10 17 cm -3 The thickness is about 5 μm or more and 50 μm or less.

[0144] Next, Al, a p-type impurity, is ion-implanted into the surface of the drift layer 20. At this time, the depth of the Al ion implantation is set to about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20. The impurity concentration of the implanted Al is 1×10 17 cm-3 That's it, 1 x 10 19 cm -3 The impurity concentration is in the range of about 0.1 to 1.0 V, and is higher than the impurity concentration of the drift layer 20. The region into which Al ions are implanted in this step becomes the first well region 30. In the termination region, this region becomes the second well region 31. The first well region 30 may be formed on the drift layer 20 by an epitaxial method.

[0145] Next, a 1×10 impurity concentration is added to a predetermined region of the surface layer of the first well region 30 so that the impurity concentration is higher than that of the first well region 30. 16 cm -3 That's it, 1 x 10 18 cm -3 The contact region 35 is formed by ion-implanting Al with an impurity concentration in the range of about 1×10. Furthermore, N, an n-type impurity, is ion-implanted into a predetermined region in the surface layer of the first well region 30 on the surface of the drift layer 20. The depth of the N ion implantation is shallower than the thickness of the first well region 30. Furthermore, the impurity concentration of the implanted N ions is 1×10 18 cm -3 That's it, 1 x 10 21 cm -3 or less, which exceeds the p-type impurity concentration of the first well region 30. Of the regions into which N is implanted in this step, the region that exhibits n-type will become the source region 40. A cross-sectional view of the active region at this stage is shown in FIG.

[0146] Next, a gate trench GT is formed in the area where the source region 40 is formed, and a Schottky trench ST is formed in the area where the source region 40 and the contact region 35 are not formed. By ion-implanting Al, which is a p-type impurity, into the bottoms of the gate trench GT and the Schottky trench ST, a first protection region 32 is formed at the bottom of the gate trench GT, and a second protection region 33 is formed at the bottom of the Schottky trench ST. The impurity concentrations of the first protection region 32 and the second protection region 33 are 1×10 17 cm -3 That's it, 1 x 10 19 cm -3 The range should be within the following range.

[0147] The first connection region 36 and the second connection region 37, which are formed to contact the gate trench GT and the Schottky trench ST, may be formed by oblique ion implantation, in which ions of p-type impurities such as Al are obliquely implanted from a direction perpendicular to the extension direction of each trench in a plan view. The impurity concentrations of the first connection region 36 and the second connection region 37 are 1×10 17 cm -3 That's it, 1 x 10 19 cm -3 The range should be within the following range.

[0148] The hole filling assist region 303, which is a feature of the present invention, may be formed by oblique ion implantation, in which ions of p-type impurities such as Al are obliquely implanted from a direction perpendicular to the extension direction of each trench in a plan view, similar to the first connection region 36 and the second connection region 37. The impurity concentration in the first connection region 36 and the second connection region 37 is 1×10 17 cm -3 That's it, 1 x 10 19 cm -3 The hole-filling assist region 303 may be formed simultaneously with the first connection region 36 or the second connection region 37, and when the first connection region 36 and the second connection region 37 are formed simultaneously, the hole-filling assist region 303 may also be formed simultaneously with the first connection region 36 and the second connection region 37. Forming the hole-filling assist region 303 in this manner reduces the number of steps and facilitates manufacturing.

[0149] Here, if the plane orientation of the first main surface of the semiconductor substrate 10 is a (0001) plane having an off-axis angle in the <11-20> direction, the gate trench GT and Schottky trench ST in the active region can both be formed parallel to the <11-20> direction. In this manner, the plane orientation of the trench sidewalls on both sides of the gate trench GT is not affected by the off-axis direction of the substrate, and therefore the threshold voltage of the MOSFET in the gate trench GT is not affected by the off-axis direction of the substrate, thereby reducing variations in the threshold voltage of the MOSFET. Furthermore, the plane orientation of the trench sidewalls on both sides of the Schottky trench ST is not affected by the off-axis direction of the substrate, and therefore variations in the barrier height of the Schottky interface of the Schottky trench ST can be reduced.

[0150] Next, the substrate is annealed in a heat treatment device in an inert gas atmosphere such as Ar gas at a temperature of 1300°C to 1900°C for 30 seconds to 1 hour. This annealing electrically activates the implanted N and Al ions. A cross-sectional view of the active region at this stage is shown in Figure 26.

[0151] Subsequently, as shown in the cross-sectional view of FIG. 27, the inside of the Schottky trench ST is filled with a protective insulating film 52 such as silicon oxide.

[0152] Next, the silicon carbide surface not covered by the protective insulating film 52 is thermally oxidized to form a silicon oxide film, which is the gate insulating film 50, of the desired thickness. Subsequently, a conductive polycrystalline silicon film is formed on the gate insulating film 50 by low-pressure CVD, and this is patterned to form the gate electrode 60. Next, an interlayer insulating film 55 made of silicon oxide and having a thickness larger than that of the gate insulating film 50 is formed by low-pressure CVD. Subsequently, the interlayer insulating film 55 and the gate insulating film 50 are removed by wet etching so as to expose the contact region 35 and the source region 40 in the active region. A cross-sectional view of the active region at this stage is shown in Figure 28.

[0153] Next, after the interlayer insulating film 55 and gate insulating film 50 are removed to expose the source region 40 and contact region 35, a metal film primarily composed of Ni is formed by sputtering or the like, and then heat treatment is performed at a temperature of approximately 600°C or higher and 1100°C or lower to react the metal film primarily composed of Ni with the silicon carbide layer and form silicide between the silicon carbide layer and the metal film. Next, the remaining metal film other than the silicide formed by the reaction is removed by wet etching. As a result, the remaining silicide becomes the ohmic electrode 70. A cross-sectional view of the active region after the process up to this stage is shown in Figure 29.

[0154] Next, the protective insulating film 52 in the Schottky trench ST is removed using hydrofluoric acid or the like, and a Schottky electrode 71 is formed in the Schottky trench ST. The Schottky electrode 71 may be made of a material such as Ti or Mo. Next, a source electrode 80 mainly made of Al is formed so as to connect to the Schottky electrode 71 and the ohmic electrode 70. The gate pad 81 and gate wiring 82 may be formed simultaneously with the source electrode 80. FIG. 30 shows a cross-sectional view of the active region after the processes up to the stage where the source electrode 80 is formed have been completed.

[0155] Furthermore, a drain electrode 84 made of a metal film is formed on the surface of a backside ohmic electrode (not shown) formed on the backside of the substrate. In this manner, the semiconductor device of this embodiment, the cross-sectional views of which are shown in Figures 23 and 24, can be manufactured.

[0156] The operation of the trench-type SiC-MOSFET with an SBD, which is the semiconductor device of this embodiment, and the effect of surge current-carrying region 301 on that operation are similar to the operation of the planar-type SiC-MOSFET with an SBD described above and the effect of surge current-carrying region 301 on that operation, and therefore a description thereof will be omitted.

[0157] <Sixth Embodiment> In this embodiment, the semiconductor device according to the first to fifth embodiments is applied to a power conversion device, and a power conversion system including this power conversion device is configured. Although the present invention is not limited to a specific power conversion device, an example of a three-phase inverter will be described below.

[0158] FIG. 31 is a schematic diagram showing a schematic configuration of a power conversion system to which a power conversion device 200 according to the sixth embodiment is applied.

[0159] The power conversion system shown in Fig. 31 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of elements, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0160] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 31 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal to the drive circuit 202 to control the drive circuit 202.

[0161] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0162] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 100 into AC power, which is supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. However, the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. Each switching element of the main conversion circuit 201 is a semiconductor device according to any one of the first to fifth embodiments. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0163] To increase the current that the power conversion device 200 can handle, the main conversion circuit 201 has multiple switching elements, in other words, multiple semiconductor devices, which can be connected in parallel in the main conversion circuit 201. Here, if multiple, preferably all, switching elements are made of semiconductor devices with surge current-carrying regions 301, pn diodes will not operate in multiple or all of the switching elements even when a surge current flows through the power conversion device 200, preventing current from concentrating in a small number of switching elements. MOSFETs with built-in SBDs that function as freewheeling diodes can also be used as switching elements.

[0164] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0165] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state at each point in time. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0166] In addition, when a return current flows in the reverse direction through each switching element, the control circuit 203 turns on the gate, except for a short dead time. In other words, when a return current flows through the semiconductor device, the control circuit 203 outputs a control signal for applying an on-voltage to the gate electrode 60 of the semiconductor device. This allows a unipolar current to flow through the channel in the surge current-carrying region 301, preventing heat from concentrating in the surge current-carrying region 301.

[0167] In the power conversion device 200 according to this embodiment, the semiconductor devices according to the first to fifth embodiments are applied as the switching elements of the main conversion circuit 201, so that the power conversion device 200 can be realized with low loss and improved reliability of high-speed switching.

[0168] In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices 200. In the present embodiment, the two-level power conversion device 200 is described, but the present invention may also be applied to a three-level or multi-level power conversion device 200, and when power is supplied to a single-phase load, the present invention may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present invention can also be applied to a DC / DC converter or an AC / DC converter.

[0169] Furthermore, the power conversion device 200 to which the present invention is applied is not limited to cases in which the above-mentioned load 300 is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0170] In the semiconductor devices of the first to fifth embodiments, aluminum (Al) is used as the p-type impurity, but the p-type impurity may be boron (B) or gallium (Ga). The n-type impurity may be phosphorus (P) instead of nitrogen (N). The gate insulating film 50 does not have to be an oxide film such as SiO2, but may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. Although silicon oxide obtained by thermally oxidizing silicon carbide is used as the gate insulating film 50, silicon oxide of a deposited film obtained by a CVD method may also be used. Furthermore, although specific examples of the crystal structure, the plane orientation of the main surface, the off-angle, and each implantation condition have been described, the applicable range is not limited to these numerical ranges.

[0171] The semiconductor device may also be a MOSFET having a superjunction structure with an SBD built in.

[0172] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0173] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0174] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, it is assumed that the material in question may contain other additives, such as alloys, unless a contradiction arises.

[0175] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that one component is provided, that component may be provided in "one or more" instances.

[0176] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0177] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0178] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art. [Explanation of symbols]

[0179] 10 semiconductor substrate, 20 drift layer, 21 first separation area, 22 second separation area, 30 first well region, 31 second well region, 32 1st protection area, 33 Second protected area, 35 contact area, 36 first connection area, 37 second connection area, 38 JTE area, 40 source regions, 45 silicon carbide conductive layer; 50 gate insulating film, 51 field insulating film, 52 protective insulating film, 55 Interlayer insulating film, 60 gate electrode, 70 ohmic electrodes, 71 Schottky electrode, 72 termination ohmic electrode, 80 source electrode, 81 gate pad, 82 gate wiring, 84 drain electrode, 90 active area contact holes, 90A active region first contact hole, 90B active region second contact hole, 91 termination region contact hole, 95 gate contact holes, 99 resist mask, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load, 301 Surge current area, 302 auxiliary area, 303 Fill-in-the-blank auxiliary area, GT gate trench, ST Schottky Trench.

Claims

1. a drift layer of a first conductivity type; a gate electrode provided to face the well region of the second conductivity type and the source region of the first conductivity type via a gate insulating film; a source electrode provided on an interlayer insulating film provided so as to cover the gate electrode and connected to the well region and the source region; a first isolation region of a first conductivity type that is connected to the drift layer in an active region having a region in which a plurality of MOSFETs, each including the well region, the source region, and the gate electrode, are arranged in the drift layer, and that is Schottky-connected to the source electrode; a surge current-carrying region provided in the region where the plurality of transistors are arranged or in the active region outside the region where the plurality of transistors are arranged, the surge current-carrying region having a region that cuts off connection between the source electrode and the drift layer; Equipped with a separation distance between two of the first separation regions provided adjacent to one end side and the other end side of the surge conduction region is greater than a separation distance between two of the first separation regions adjacent to each other in the active region outside the surge conduction region; Semiconductor device.

2. The surge current-carrying region is formed over an area larger than a first width of the well region in a plan view. The semiconductor device according to claim 1 .

3. the surge current-carrying region is provided at a position covered by the source electrode in a plan view; 3. The semiconductor device according to claim 1.

4. The first separation area is not formed in the surge current carrying area.

3. The semiconductor device according to claim 1.

5. a total area of ​​the surge current-carrying regions in a plan view is 10% or less of the entire area of ​​the semiconductor device in a plan view; 3. The semiconductor device according to claim 1.

6. A plurality of the surge current-carrying regions are formed, a separation distance between any two of the surge current-carrying regions is 10 times or more a separation distance between two of the first separation regions provided adjacent to one end side and the other end side of the surge current-carrying region, respectively; 3. The semiconductor device according to claim 1.

7. A plurality of the surge current-carrying regions are formed, The surge current-carrying regions are provided periodically or at equal intervals in at least one direction of the semiconductor device in a plan view.

3. The semiconductor device according to claim 1.

8. the gate electrode is formed continuously inside and outside the surge current-carrying region in a plan view; 3. The semiconductor device according to claim 1.

9. the gate electrode is not provided in the surge current-carrying region in a plan view; 3. The semiconductor device according to claim 1.

10. The surge current carrying area is at least one auxiliary region of a second conductivity type, which is a region that cuts off connection between the source electrode and the drift layer and has a second width that is larger than the first width; The semiconductor device according to claim 2 .

11. the auxiliary region separates the source electrode and the drift layer at a second contact hole that penetrates the interlayer insulating film; The semiconductor device according to claim 10.

12. The source electrode is the well region, the source region, and the first isolation region are connected to each other via first contact holes that penetrate the interlayer insulating film; the first contact hole is connected to the auxiliary region through a second contact hole that penetrates the interlayer insulating film, and is not connected to the drift layer; The semiconductor device according to claim 10.

13. The surge current carrying area is a second isolation region of the first conductivity type adjacent to the auxiliary region or the well region, connected to the drift layer, and facing the gate electrode with the gate insulating film interposed therebetween; the source region is provided on a surface layer of the auxiliary region, and the gate insulating film and the gate electrode are formed thereon; The semiconductor device according to claim 10.

14. The surge current carrying area is the first conductivity type second isolation region is not provided, the second isolation region being adjacent to the auxiliary region or the well region, connected to the drift layer, and facing the gate electrode with the gate insulating film interposed therebetween; The semiconductor device according to claim 10.

15. A semiconductor device as described in claim 1 or claim 2, further comprising a contact region formed on the surface of the well region, having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region, and connected to the source electrode.

16. a main conversion circuit including the semiconductor device according to claim 1 or 2, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the main conversion circuit; A power conversion device comprising:

17. the control circuit outputs the control signal for applying an on-voltage to the gate electrode of the semiconductor device when a reflux current flows through the semiconductor device. The power converter according to claim 16.

18. the main conversion circuit has a plurality of the semiconductor devices, and the plurality of semiconductor devices are connected in parallel with each other; The power converter according to claim 16.

19. The semiconductor device is used for all switching elements connected in parallel in the main conversion circuit. The power converter according to claim 16.

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