Semiconductor device manufacturing method and jig set

Abstract

To suppress the generation of an electric malfunction.SOLUTION: A lead frame positioning jig tool 13 into which a lead frame open part is penetrated is arranged so as to be opposite to an insulation circuit board so that the lead frame open part is corresponded to a bonding part 5a of a lead frame in a plan view. Next, a columnar is formed, and a pressing force jig 15 having a pressing surface 15a1 in a tip end is inserted into the lead frame open part, and the bonding part 5a of the lead frame is pressed to the insulation circuit board side with the pressing surface 15a1. Thus, a semiconductor chip 4 is pressed by the pressing force jig 15 via the bonding part 5a of the lead frame. Even if a warping occurs in the semiconductor chip 4 due to a difference between the insulation circuit board and a thermal expansion coefficient when heating bonding members 7b and 7c, it is pressed by the pressing force jig 15, and the warping is corrected.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a jig set. [Background technology]

[0002] Semiconductor devices include power devices and are used as power conversion devices. The power devices include semiconductor chips. The semiconductor chips are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Such semiconductor devices include at least a semiconductor module and a heat sink to which the semiconductor module is bonded. The semiconductor module may include a semiconductor chip, an insulating circuit board to which the semiconductor chip is bonded, and a lead frame bonded to the semiconductor chip. In manufacturing such semiconductor devices, a positioning jig is used to bond the semiconductor module to a predetermined area of ​​the heat sink. Furthermore, a weight (weight) is placed on the positioning jig.

[0003] The following is an example of using a jig in manufacturing. For example, a base steel is positioned and placed in a recess of a tray, and a first jig with a first cutout hole formed on the base steel is placed in the recess. Solder and a substrate are sequentially stacked on the base steel positioned in the first cutout hole. A second jig with a second cutout hole is further fitted into the first cutout hole, and solder and chips are sequentially stacked on the substrate positioned in the second cutout hole, and a weight is fitted into the second cutout hole (see, for example, Patent Document 1).

[0004] In addition, both ends of the lead terminals protruding from the metal block are attached to the base of the jig. above The side of the metal block is set but The lead terminal is fixed by the lower part of a pair of clamping members of the jig, thereby fixing the lead terminal at a predetermined height (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-238638 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-187245 Summary of the Invention [Problem to be solved by the invention]

[0006] When joining a semiconductor module to a heat sink with solder, the solder is heated to melt. During this process, the insulating circuit board, semiconductor chip, and lead frame have different thermal expansion coefficients, which can cause the semiconductor chip to warp. If the lead frame is joined to a warped semiconductor chip, the thickness of the solder joining the semiconductor chip to the lead frame becomes uneven. This can cause electrical problems in the semiconductor chip, even if the semiconductor chip and lead frame are electrically connected, leading to reduced reliability of the semiconductor device.

[0007] The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device and a jig set in which the occurrence of electrical defects is suppressed. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a preparation step of preparing a conductive plate, a semiconductor chip disposed on the conductive plate via a first bonding material, and a connection terminal having a bonding portion disposed on the semiconductor chip via a second bonding material, the connection terminal including the bonding portion; a first jig arrangement step of arranging a first guide jig having a first guide hole passing therethrough, facing the conductive plate so that the first guide hole corresponds to the bonding portion in a plan view; and a first pressing step of inserting a columnar pressing jig having a pressing portion at a lower end into the first guide hole and pressing the bonding portion of the connection terminal toward the conductive plate with the pressing portion. The pressing jig further includes a locking portion above the pressing portion, and in the first pressing step, the locking portion of the pressing jig is locked to the first guide jig, and the pressing portion presses the joint portion.A method for manufacturing a semiconductor device is provided.

[0009] According to another aspect of the present invention, there is provided a jig set for use in the above-described method for manufacturing a semiconductor device. [Effects of the Invention]

[0010] The above-described semiconductor device manufacturing method and jig set can manufacture semiconductor devices that suppress the occurrence of electrical defects and prevent a decrease in reliability. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a side view of a semiconductor device according to a first embodiment. [Figure 2] 3 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] 4 is a flowchart of a semiconductor unit manufacturing process included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view showing a step of setting an insulating circuit substrate included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 5] 3 is a plan view showing a step of setting an insulating circuit substrate included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 6] 3 is a cross-sectional view showing a semiconductor chip setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 7] 3 is a plan view showing a semiconductor chip setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 8] 4 is a cross-sectional view showing a lead frame setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 9] 3 is a plan view showing a lead frame setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 10] 4 is a cross-sectional view showing a pressing jig setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 11] 10A to 10C are cross-sectional views showing a semiconductor unit manufacturing process in a semiconductor device manufacturing method according to a reference example. [Figure 12] 4 is a flowchart of a bonding step included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 4A to 4C are cross-sectional views showing a step of setting a heat sink included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 14] 4 is a plan view showing a step of setting a heat sink included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 15] 4A to 4C are cross-sectional views illustrating a step of fixing a heat sink included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 16] 4 is a plan view showing a step of fixing a heat sink included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 17] 1 is a cross-sectional view (part 1) illustrating a semiconductor unit positioning step included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 18] 1 is a plan view (part 1) showing a semiconductor unit positioning step included in a bonding step in the manufacturing method of the semiconductor device according to the first embodiment; [Figure 19] 10 is a cross-sectional view (part 2) illustrating a semiconductor unit positioning step included in the bonding step of the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 20] 10 is a plan view (part 2) showing the semiconductor unit positioning step included in the bonding step of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 21] 4A to 4C are cross-sectional views showing a spacer jig setting step included in the bonding step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 22] 10 is a plan view showing a spacer jig setting step included in the bonding step of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 23] 4 is a cross-sectional view showing a weight setting step included in the bonding step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 24] 10 is a plan view showing a weight setting step included in the bonding step of the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 25] 4 is a cross-sectional view showing a pressing jig setting step included in the bonding step of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 26] 10 is a plan view showing a pressing jig setting step included in the bonding step of the semiconductor device manufacturing method according to the first embodiment. FIG. [Figure 27] FIG. 10 is a cross-sectional view showing a weight setting step included in the bonding step in the manufacturing method of the semiconductor device according to the second embodiment. [Figure 28] 10 is a cross-sectional view showing a pressing jig setting step included in the bonding step of the semiconductor device manufacturing method according to the second embodiment. FIG. [Figure 29] 10 is a plan view showing a pressing jig setting step included in the bonding step of the semiconductor device manufacturing method according to the second embodiment. FIG. [Figure 30] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 31] FIG. 10 is a perspective view of a semiconductor unit included in a semiconductor device according to a third embodiment. [Figure 32] FIG. 11 is a cross-sectional view showing a weight setting step included in the bonding step in the manufacturing method of the semiconductor device according to the third embodiment. [Figure 33] FIG. 11 is a plan view showing a weight setting step included in the bonding step in the manufacturing method of the semiconductor device according to the third embodiment. [Figure 34] 10A and 10B are cross-sectional views showing a pressing jig setting step included in the bonding step in the semiconductor device manufacturing method according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "top" refers to the upward (+Z direction) direction in the semiconductor device 1 of FIG. 1. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "bottom" refers to the downward (-Z direction) direction in the semiconductor device 1 of FIG. 1. Similar orientations will be used in other drawings as necessary. The term "high position" refers to the upper (+Z side) position in the semiconductor device 1 of FIG. 1. Similarly, the term "low position" refers to the lower (-Z side) position in the semiconductor device 1 of FIG. 1. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to a vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component that is contained in an amount of 80 vol % or more.

[0013] In addition, in the drawings used in the following description of the embodiments, reference numerals are used to designate components that first appear, and the reference numerals of the components may be omitted in subsequent drawings. In such cases, the first-appearing drawing may be referenced.

[0014] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to FIG. 1. FIG. 1 is a side view of the semiconductor device according to the first embodiment. The semiconductor device 1 includes at least a heat sink 6 and a semiconductor unit 2. The semiconductor device 1 may have a case surrounding the semiconductor unit 2 provided on the heat sink 6. In this case, the semiconductor unit 2 within the case is sealed with a sealing member, and the lead frame 5 extends vertically upward. Alternatively, the semiconductor device 1 may have the back surface of the heat sink 6 exposed, the semiconductor unit 2 on the heat sink 6 sealed with a sealing member, and the lead frame 5 extends vertically upward. Here, the minimum configuration of the semiconductor device 1 is shown.

[0015] The heat sink 6 has a rectangular shape in a plan view. The corners of the heat sink 6 may be rounded or chamfered. A fixing groove 6a may be formed on the back surface of the heat sink 6. The fixing groove 6a will be described later ( FIG. 13 ). Such a heat sink 6 is made of a metal with excellent thermal conductivity. This metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. The surface of the heat sink 6 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. A semiconductor unit 2 is disposed in the center of the front surface of the heat sink 6 via a bonding member 7a. Note that this embodiment exemplifies a case in which one semiconductor unit 2 is disposed on the heat sink 6. However, this is not limiting, and multiple semiconductor units 2 may be disposed. In the case of multiple semiconductor units 2, the semiconductor units 2 may be disposed in a single row, or in n rows and m columns depending on the number of semiconductor units 2.

[0016] The semiconductor unit 2 further includes an insulating circuit board 3, a semiconductor chip 4, and a lead frame 5 stacked in this order via bonding members 7b and 7c. The bonding members 7b and 7c have the same composition as the bonding member 7a.

[0017] The insulating circuit board 3 is rectangular in plan view. The insulating circuit board 3 has an insulating plate 3a, a circuit pattern 3b formed on the front surface of the insulating plate 3a, and a metal plate 3c formed on the back surface of the insulating plate 3a. The outer shapes of the circuit pattern 3b and the metal plate 3c are smaller than the outer shapes of the insulating plate 3a in plan view, and are formed inside the insulating plate 3a. Note that the shape and number of the circuit patterns 3b are merely examples.

[0018] The insulating plate 3a has a rectangular shape in a plan view. The corners of the insulating plate 3a may be chamfered with a C-shape or an R-shape. Such an insulating plate 3a is made of ceramics with good thermal conductivity. The ceramics may be made of a material containing aluminum oxide, aluminum nitride, or silicon nitride as a main component, for example. The thickness of the insulating plate 3a is 0.2 mm or more and 2.0 mm or less.

[0019] The circuit pattern 3b is formed over the entire surface of the insulating plate 3a except for the edges. Preferably, in a plan view, the end of the circuit pattern 3b facing the outer periphery of the insulating plate 3a overlaps the end of the metal plate 3c on the outer periphery side of the insulating plate 3a. This maintains a stress balance between the insulating circuit board 3 and the metal plate 3c on the back surface of the insulating plate 3a. Damage to the insulating plate 3a such as excessive warping and cracking is suppressed. The thickness of the circuit pattern 3b is 0.1 mm or more and 2.0 mm or less. The circuit pattern 3b is made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these. The surface of the circuit pattern 3b may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The circuit pattern 3b is formed by plating a metal on the front surface of the insulating plate 3a. layer This metal layer The insulating plate 3a is obtained by subjecting the insulating plate 3a to a process such as etching. Alternatively, the circuit pattern 3b may be cut out from a metal plate in advance and then pressed onto the front surface of the insulating plate 3a. Note that the circuit pattern 3b is only an example. The number, shape, size, etc. of the circuit patterns may be selected as needed.

[0020] The metal plate 3c has a rectangular shape in a plan view. The corners may be, for example, C-chamfered or R-chamfered. The metal plate 3c is smaller than the insulating plate 3a and is formed on the entire back surface of the insulating plate 3a except for the edges. The metal plate 3c is mainly composed of a metal with excellent thermal conductivity. The metal may be, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 3c is 0.1 mm or more and 2.0 mm or less. The metal plate may be plated to improve its corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0021] For example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used as the insulating circuit board 3 having such a configuration. The insulating circuit board 3 dissipates heat generated in a semiconductor chip 4 (described later) by conducting it to the back side of the insulating circuit board 3 via the circuit pattern 3b, insulating plate 3a, and metal plate 3c. The insulating circuit board 3 is joined to the heat sink 6 by a joining member 7a.

[0022] The bonding members 7a are made of lead-free solder. The lead-free solder mainly contains at least one of the following alloys: a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. The bonding members 7a may further contain additives. The additives are, for example, nickel, germanium, cobalt, or silicon. The inclusion of additives in the bonding members 7a improves the wettability, gloss, and bonding strength of the bonding members 7a, thereby improving reliability.

[0023] The semiconductor chip 4 is mainly composed of silicon, silicon carbide, or gallium nitride. The semiconductor chip 4 includes a switching element or a diode element. The switching element is, for example, an IGBT or a power MOSFET. If the semiconductor chip 4 is an IGBT, it has a collector electrode as a main electrode on the back surface and a gate electrode and an emitter electrode as main electrodes on the front surface. If the semiconductor chip 4 is a power MOSFET, it has a drain electrode as a main electrode on the back surface and a gate electrode and a source electrode as main electrodes on the front surface. The diode element is, for example, a free wheeling diode (FWD) such as an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode. Such a semiconductor chip 4 has a cathode electrode as a main electrode on the back surface and an anode electrode as a main electrode on the front surface.

[0024] Alternatively, the semiconductor chip 4 may be an RC (Reverse Conducting)-IGBT. An RC-IGBT is a chip that combines an IGBT, which is a switching element, and an FWD, which is a diode element. Such a semiconductor chip 4 has, for example, a collector electrode (positive electrode) and an anode electrode as main electrodes on the back surface, and a gate electrode as a control electrode and an emitter electrode (negative electrode) and a cathode electrode as main electrodes on the front surface.

[0025] The back side of the semiconductor chip 4 is bonded to the circuit pattern 3b by a bonding member 7b. The bonding member 7b may be lead-free solder, like the bonding member 7a, and may have the same composition as the bonding member 7a. Alternatively, the bonding member 7b may be a bonding material containing nano-sized metal particles (a metal particle sintered body). The metal particles may be, for example, sintered silver particles. Metal particle sintered bodies include nano-sized sintered bodies and micro-sized sintered bodies. The nano-sized sintered body is a porous metal body in which metal particles with an average particle diameter of approximately 1 nm or more and 200 nm or less are sintered and bonded to each other. The micro-sized sintered body is a porous metal body in which metal particles with an average particle diameter of approximately 1 nm or more and 10 μm or less are sintered and bonded to each other. There are also mixed particle sintered bodies in which nano-sized and micro-sized particles are mixed. The pre-sintered bonding material (fine metal sintered body bonding material) may be a bonding material in which the metal particle surfaces are covered with an organic substance to prevent aggregation and improve dispersibility in the solvent, forming a paste, or a bonding material in which the metal particles are a paste made of silver oxide and a reducing solvent with reducing properties. The thickness of the bonding member 7b (before thermal bonding) can be 0.05 mm or more and 0.30 mm or less. A thickness of 0.10 mm or more and 0.20 mm or less is particularly preferable. This range satisfies the bonding strength, minimizes scattering, and reduces thermal resistance. The thickness of the semiconductor chip 4 is, for example, 180 μm or more and 220 μm or less, with an average of approximately 200 μm.

[0026] The lead frame 5 is, for example, a wiring member that electrically connects the semiconductor chip 4 (particularly the main electrodes on the front surface) and the circuit pattern 3b with external terminals, etc. In this embodiment, the lead frame 5 is shown as being joined to the semiconductor chip 4. The lead frame 5 includes a joint portion 5a and a wiring portion 5b. The joint portion 5a and the wiring portion 5b are each flat and are connected to form, for example, an L-shape when viewed from the side.

[0027] The lead frame 5 is made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The thickness of the lead frame 5 is preferably 0.20 mm or more and 4.00 mm or less, and more preferably 0.50 mm or more and 1.50 mm or less. To improve corrosion resistance, a plating material may be formed on the surface of the lead frame 5 by, for example, a plating process. The plating material may be, for example, nickel or a nickel alloy. The shape of the lead frame 5 in this embodiment is merely an example. The back side of the lead frame 5 is also bonded to a predetermined semiconductor chip 4 by a bonding member 7c. Like the bonding member 7a, the bonding member 7c is lead-free solder and may have the same composition as the bonding member 7a.

[0028] Next, a method for manufacturing such a semiconductor device 1 will be described with reference to FIG. 2. FIG. 2 is a flowchart of the method for manufacturing a semiconductor device according to the first embodiment. First, a preparation step is performed to prepare components required for the semiconductor device 1 (step S10). Examples of the required components include a semiconductor chip 4, an insulating circuit board 3, a lead frame 5, and a heat sink 6. In addition, for example, a case, a sealing member, etc. may be prepared.

[0029] Next, a semiconductor unit manufacturing process is carried out in which a semiconductor chip 4 is bonded to the prepared insulating circuit board 3, and a lead frame 5 is further bonded to the semiconductor chip 4 to manufacture a semiconductor unit 2 (step S11). Here, in the semiconductor unit manufacturing process, the insulating circuit board 3, the semiconductor chip 4, and the lead frame 5 are respectively bonded with bonding members 7b and 7c. Details of this semiconductor unit manufacturing process will be described later. Next, a bonding process is carried out in which the semiconductor unit 2 manufactured in this way is bonded to a heat sink 6 (step S12). Details of the bonding process will be described later.

[0030] Next, an accommodation step is performed in which the heat sink 6 and semiconductor unit 2 thus bonded are accommodated in a case (step S13). Next, a wiring step is performed in which the semiconductor chip 4 of the semiconductor unit 2 accommodated in the case is electrically connected to the insulating circuit board 3 by bonding wires (step S14). Note that the accommodation step may be performed after the wiring step. Finally, an encapsulation step is performed in which the semiconductor unit 2 on the heat sink 6 accommodated in the case is encapsulated with an encapsulating member (step S15). Through the above steps, the semiconductor device 1 (excluding the bonding wires, encapsulating member, and case) shown in FIG. 1 is obtained.

[0031] Next, the semiconductor unit manufacturing process in step S11 of the flowchart in Fig. 2 will be described with reference to Fig. 3. Fig. 3 is a flowchart of the semiconductor unit manufacturing process included in the semiconductor device manufacturing method of the first embodiment.

[0032] First, a setting step is performed in which the insulating circuit board 3 is set in the board fixing jig 11 (step S11a). Step S11a will be described with reference to FIGS. 4 and 5. FIG. 4 is a cross-sectional view showing the insulating circuit board setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment, and FIG. 5 is a plan view showing the insulating circuit board setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment. Note that FIG. 4 is a cross-sectional view taken along the dashed dotted line YY in FIG. 5.

[0033] The substrate fixing jig 11 is a jig for arranging and fixing the insulating circuit board 3 in a predetermined position. The substrate fixing jig 11 includes a frame portion 11a and a bottom portion 11c. The bottom portion 11c is flat and configured to be larger in area than the insulating circuit board 3 in a plan view. The frame portion 11a is formed integrally with the front surface of the bottom portion 11c. The frame portion 11a surrounds a fixing region 11b that is formed in a recessed shape corresponding to the shape (rectangular) of the insulating circuit board 3 in a plan view. It is preferable that the height of the fixing region 11b is approximately equal to the height of the insulating circuit board 3.

[0034] 4 and 5, the insulating circuit board 3 is set in the fixing region 11b of the substrate fixing jig 11. This prevents the insulating circuit board 3 from being misaligned in the X and Y directions (horizontal direction). At this time, the upper surface of the frame portion 11a of the substrate fixing jig 11 and the upper surface of the insulating circuit board 3 (the upper surface of the circuit pattern 3b) are flush with each other. This allows the chip positioning jig 12, which will be described later, to be properly positioned on the frame portion 11a and the insulating circuit board 3.

[0035] Next, a setting step is performed in which the semiconductor chip 4 is set on the insulating circuit board 3 (step S11b). Step S11b will be described with reference to FIGS. 6 and 7. FIG. 6 is a cross-sectional view showing the semiconductor chip setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment, and FIG. 7 is a plan view showing the semiconductor chip setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment. Note that FIG. 6 is a cross-sectional view taken along the dashed dotted line YY in FIG. 7.

[0036] In step S11a, the chip positioning jig 12 is set on the substrate fixing jig 11 and the insulating circuit board 3. The chip positioning jig 12 includes a chip frame portion 12a including a chip opening portion 12c and a fixing portion 12b. The chip frame portion 12a is flat. When the chip positioning jig 12 is placed on the substrate fixing jig 11, the chip opening portion 12c is formed in the chip frame portion 12a so as to face the mounting position of the semiconductor chip 4 on the insulating circuit board 3.

[0037] The fixing portion 12b is formed on the back surface of the chip frame portion 12a. The fixing portion 12b is formed with a convex cross section so as to fit into the gap between the frame portion 11a of the substrate fixing jig 11 and the circuit pattern 3b when the chip positioning jig 12 is placed on the substrate fixing jig 11. The fixing portion 12b is formed continuously in an annular shape on the back surface of the chip frame portion 12a so as to fit between the outside of the circuit pattern 3b of the insulating circuit board 3 and the frame portion 11a.

[0038] Such a chip positioning jig 12 is mounted on the substrate fixing jig 11 and the insulating circuit board 3, and as shown in Figures 6 and 7, the semiconductor chip 4 is set on the insulating circuit board 3 (circuit pattern 3b) through the chip opening 12c and via the bonding member 7b. Due to the chip opening 12c of this chip positioning jig 12, the semiconductor chip 4 is restrained from moving (shifting) in horizontal directions (X and Y directions) relative to the mounting direction (+Z direction) in which the semiconductor chip 4 is mounted on the insulating circuit board 3. In this case, the clearance between the edge of the chip opening 12c and the edge of the semiconductor chip 4 is preferably 0.30 mm or more and 1.00 mm or less.

[0039] The back surface of the chip positioning jig 12 (chip frame 12a) is arranged to cover the area (protected area) of the circuit pattern 3b other than the mounting area where the semiconductor chip 4 is arranged. By covering the protected area of ​​the circuit pattern 3b with the chip positioning jig 12, scattering of the bonding material 7b that bonds the circuit pattern 3b and the semiconductor chip 4 can be suppressed.

[0040] Next, a setting step is performed in which the lead frame 5 is set on the semiconductor chip 4 (step S11c). Step S11c will be described with reference to FIGS. 8 and 9. FIG. 8 is a cross-sectional view showing the lead frame setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment, and FIG. 9 is a plan view showing the lead frame setting step included in the semiconductor unit manufacturing step of the semiconductor device manufacturing method of the first embodiment. Note that FIG. 8 is a cross-sectional view taken along the dashed dotted line YY in FIG. 9.

[0041] A lead frame positioning jig 13, which also serves as a guide jig, is placed on the chip positioning jig 12. The lead frame positioning jig 13 may be a weight. The lead frame positioning jig 13 includes a lead frame frame portion 13a with a lead frame opening 13c that functions as a guide hole. The lead frame frame portion 13a is flat. The lead frame frame portion 13a has a lead frame opening 13c formed therein. When the lead frame positioning jig 13 is placed on the chip positioning jig 12, the lead frame opening 13c faces the mounting position of the lead frame 5 for the main electrode of the semiconductor chip 4. The lead frame opening 13c has, for example, a rectangular shape in plan view. Such lead frame opening 13c is surrounded on all four sides by lead frame inner wall portions 13c1. Therefore, the lead frame positioning jig 13 blocks everything except the lead frame 5 in plan view. Furthermore, the lead frame positioning jig 13 may be sized so that it can be placed on the chip positioning jig 12 in plan view. Through the lead frame opening 13c of the lead frame positioning jig 13, the joint portion 5a of the lead frame 5 is connected to the joint member 7c. On semiconductor chip 4 Place.

[0042] Next, a setting step is performed in which pressing jig 15 is set in lead frame opening 13c of lead frame positioning jig 13 (step S11d). Step S11d will be described with reference to FIG. 10. FIG. 10 is a cross-sectional view showing the pressing jig setting step included in the semiconductor unit manufacturing process of the semiconductor device manufacturing method of the first embodiment. Note that FIG. 10 is a cross-sectional view corresponding to FIG. 8.

[0043] The pressing jig 15 is inserted into the lead frame opening 13c of the lead frame positioning jig 13 and set. The pressing jig 15 includes a pressing body 15a and a locking portion 15b. The pressing body 15a is columnar. The pressing body 15a is shaped to match the shape of the lead frame opening 13c in a plan view. correspondence It is sufficient if the lead frame opening 13c has a rectangular pillar shape. CylinderThe tip of the pressing body 15a is provided with a pressing surface 15a1, which serves as a pressing portion that contacts the front surface of the bonding portion 5a of the lead frame 5 when the pressing jig 15 is set. As shown in FIG. 10, the pressing surface 15a1, which serves as a pressing portion, is flat and parallel to the front surface of the bonding portion 5a. The tip of the pressing body 15a is only required to have the pressing surface 15a1, and the spire-shaped tip may have a shape cut perpendicular to the extension direction of the pressing body 15a (spire-shaped cross section). Alternatively, the pressing portion may be semispherical without including a flat surface. The pressing body 15a also has a locking portion 15b formed above the pressing surface 15a1. The locking portion 15b is formed in a ring shape continuously along the outer periphery of the end of the pressing body 15a opposite to the pressing surface 15a1. When the pressing jig 15 is set in the lead frame opening 13c, the locking portion 15b is locked in the lead frame opening 13c. The locking portion 15b need only prevent the pressing jig 15 from dropping excessively, and does not have to be formed continuously in a ring shape along the outer periphery of the end opposite to the pressing surface 15a1 of the pressing main body 15a. It may also be formed discontinuously in a ring shape.

[0044] When such pressing jig 15 is set in lead frame opening 13c, pressing surface 15a1 comes into contact with the front surface of joint 5a of lead frame 5. Pressing jig 15 presses joint 5a toward insulating circuit board 3 with pressing surface 15a1 due to its own weight. However, locking portion 15b prevents pressing jig 15 from applying excessive pressure to joint 5a. This prevents damage to the main electrodes on the front surface of semiconductor chip 4.

[0045] In this way, the substrate fixing jig 11, the chip positioning jig 12, the lead frame positioning jig 13, and the pressing jig 15 constitute the manufacturing jig set 10. The substrate fixing jig 11, the chip positioning jig 12, and the lead frame positioning jig 13 of the manufacturing jig set 10 may be made of a material with excellent heat resistance, such as carbon.

[0046] Next, the bonding process is carried out (step S11e). The bonding portion 5a of the lead frame 5 is pressed against the insulating circuit board 3 by the pressing jig 15 and heated. This melts the bonding members 7b and 7c. Furthermore, the semiconductor chip 4 warps due to the difference in thermal expansion coefficient with the insulating circuit board 3. At this time, the semiconductor chip 4 is pressed by the pressing jig 15 via the bonding portion 5a, and the warpage of the semiconductor chip 4 is corrected.

[0047] At this time, the insulating circuit board 3 is prevented from being misaligned in the X and Y directions by the substrate fixing jig 11, and is prevented from being misaligned in the Z direction by the chip positioning jig 12. The semiconductor chip 4 is also prevented from being misaligned in the X and Y directions by the chip positioning jig 12. Furthermore, the semiconductor chip 4 and the lead frame 5 are prevented from being misaligned in the Z direction by the pressing jig 15.

[0048] The circuit pattern 3b, semiconductor chip 4, and bonding portion 5a are generally parallel. Therefore, the thicknesses of bonding members 7b between the insulating circuit board 3 and semiconductor chip 4 and bonding members 7c between the semiconductor chip 4 and bonding portion 5a are maintained approximately uniform. When the molten bonding members 7b and 7c solidify, the bonding members 7b and 7c bond the insulating circuit board 3, semiconductor chip 4, and bonding portion 5a of the lead frame 5, respectively. The bonding members 7b and 7c also have uniform thicknesses. Therefore, the semiconductor chip 4 and lead frame 5 are properly connected. A stable electrical connection is achieved between the semiconductor chip 4 and lead frame 5, preventing electrical defects. During this process, the locking portion 15b of the pressing jig 15 prevents excessive pressure on the semiconductor chip 4. Therefore, damage to the main electrodes of the semiconductor chip 4 is prevented.

[0049] 2, the pressing jig 15, the lead frame positioning jig 13, and the chip positioning jig 12 are removed in this order, and then the substrate fixing jig 11 is removed. As a result, the semiconductor unit 2 is obtained.

[0050] Here, as a reference example, a bonding process that does not use pressing jig 15 will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing a semiconductor unit manufacturing process in a semiconductor device manufacturing method of the reference example. Fig. 11 shows a case where pressing jig 15 is removed from Fig. 10.

[0051] In this case, when heating is performed in the same manner as in step S11e, the bonding members 7b and 7c melt. As described above, the semiconductor chip 4 warps due to the difference in thermal expansion coefficient with the insulating circuit board 3. When the melted bonding members 7b and 7c solidify in this state, the thickness of the bonding members 7b and 7c becomes uneven according to the warpage of the semiconductor chip 4, as shown in FIG. 11. A stable electrical connection cannot be achieved between the semiconductor chip 4 and lead frame 5 bonded in this manner, and electrical defects may occur.

[0052] In the first embodiment, the semiconductor chip 4 is pressed by the pressing jig 15 via the bonding portion 5a, and the thickness of the bonding member 7b between the insulating circuit board 3 and the semiconductor chip 4 and the bonding member 7c between the semiconductor chip 4 and the bonding portion 5a are maintained approximately uniform. In this state, the bonding members 7b and 7c are solidified, and the semiconductor chip 4 and the lead frame 5 are properly connected mechanically and electrically.

[0053] Next, the bonding step of step S12 in the flowchart of Fig. 2 will be described with reference to Fig. 12. Fig. 12 is a flowchart of the bonding step included in the method for manufacturing the semiconductor device according to the first embodiment.

[0054] First, a setting step is performed in which the heat sink 6 is set on the base jig 21 (step S12a). Step S12a will be described with reference to FIGS. 13 and 14. FIG. 13 is a cross-sectional view showing the heat sink setting step included in the bonding step of the method for manufacturing a semiconductor device according to the first embodiment, and FIG. 14 is a plan view showing the heat sink setting step included in the bonding step of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view taken along the dashed-dotted line YY in FIG. 14. In addition, in FIG. 14, the position of the fixing member 21b is indicated by a dashed line.

[0055] The base jig 21 is a jig for fixing the heat sink 6 arranged in a predetermined position. The base jig 21 is flat and configured to be larger than the area of ​​the heat sink 6 in a plan view. The base jig 21 may have a recess 21a formed on its front surface. The recess 21a is formed, for example, parallel to the short side of the base jig 21 without penetrating the base jig 21. A fixing groove 6a having a shape similar to the recess 21a is also formed on the back surface of the heat sink 6 at a position opposite the recess 21a. A fixing member 21b is fitted into the recess 21a of the base jig 21, and the fixing groove 6a of the heat sink 6 is positioned in the fixing member 21b. The fixing member 21b has a shape corresponding to the recess 21a. This fixes the heat sink 6 to the base jig 21, preventing misalignment in the X and Y directions.

[0056] Next, a fixing step of fixing the heat sink 6 is performed (step S12b). Step S12b will be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a cross-sectional view showing the heat sink fixing step included in the bonding step of the method for manufacturing a semiconductor device according to the first embodiment, and Fig. 16 is a plan view showing the heat sink fixing step included in the bonding step of the method for manufacturing a semiconductor device according to the first embodiment.

[0057] As shown in FIGS. 15 and 16 , a fixing jig 22 is set on the base jig 21, surrounding the heat sink 6. The fixing jig 22 includes a first frame portion 22a and a first protrusion portion 22b. The first frame portion 22a has a frame shape in a plan view. The first frame portion 22a includes a first inner wall portion 22a1 that surrounds the entire periphery of the heat sink 6. The first inner wall portion 22a1 has flat surfaces on four sides that abut the entire periphery of the heat sink 6. The first protrusion portion 22b protrudes perpendicularly from the first inner wall portion 22a1 and forms a continuous ring shape along the first inner wall portion 22a1. The first protrusion portion 22b is formed at a position corresponding to the thickness of the heat sink 6 from the underside of the first frame portion 22a. 15 and 16, when such a fixing jig 22 is attached to the heat sink 6 of the base jig 21, the first frame portion 22a of the fixing jig 22 fits onto the side surface of the heat sink 6, and the front surface of the outer periphery of the heat sink 6 is abutted by the first protruding portion 22b. This prevents the heat sink 6 from shifting in position in the Z direction on the base jig 21. At this time, the first opening region 22c is surrounded by the first protruding inner wall portion 22b1 inside the first protruding portion 22b.

[0058] Next, a positioning step of the semiconductor unit 2 is performed (step S12c). Step S12c will be described with reference to FIGS. 17 to 20. FIGS. 17 and 19 are cross-sectional views showing the positioning step of the semiconductor unit included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment, and FIGS. 18 and 20 are plan views showing the positioning step of the semiconductor unit included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment. FIGS. 17 and 19 are cross-sectional views taken along the dashed dotted line YY in FIGS. 18 and 20.

[0059] As shown in Figures 17 and 18, the unit positioning jig 23 is placed on the heat sink 6 in the first opening region 22c of the fixing jig 22. The unit positioning jig 23 includes a second frame portion 23a and a second protrusion portion 23b. The second frame portion 23a has a frame shape in a plan view. The second frame portion 23a includes a second inner wall portion 23a1. The second inner wall portion 23a1 surrounds the second opening region 23c on all four sides. The height of the second frame portion 23a is determined by the length from the front surface of the heat sink 6 to the front surface of the first frame portion 22a of the fixing jig 22. correspondence is doing.

[0060] The second protrusion 23b is provided on the second frame portion 23a so as to close the gap between the second frame portion 23a and the first frame portion 22a when the fixing jig 22 is placed on the heat sink 6. The second protrusion 23b is provided on the second frame portion 23a so as to be flush with the front surfaces of the second frame portion 23a and the first frame portion 22a when the fixing jig 22 is placed on the heat sink 6. The thickness of the second protrusion 23b is at most the height from the front surface of the first protrusion 22b to the front surface of the first frame portion 22a.

[0061] Then, using the unit positioning jig 23 thus arranged, the semiconductor unit 2 is placed on the heat sink 6 via the bonding members 7a, as shown in Figures 19 and 20. At this time, the front surface of the insulating circuit board 3 on the bonding members 7a is flush with the second frame portion 23a and the first frame portion 22a.

[0062] Next, a setting step is performed in which the spacer jig 24 is set on the unit positioning jig 23 and the insulating circuit board 3 (step S12d). Step S12d will be described with reference to FIGS. 21 and 22. FIG. 21 shows the setting step of the spacer jig, which is included in the bonding step of the manufacturing method of the semiconductor device according to the first embodiment. cross section FIG. 22 shows a step of setting a spacer jig included in the bonding step of the method for manufacturing a semiconductor device according to the first embodiment. plane 21 is a cross-sectional view taken along the dashed dotted line YY in FIG.

[0063] The spacer jig 24 includes a third frame portion 24a including a spacer opening 24d, a positioning and fixing portion 24b, and a guide portion 24c. The third frame portion 24a is flat. The third frame portion 24a includes a third inner wall portion 24a1 that surrounds the circuit pattern 3b of the insulating circuit board 3 when the spacer jig 24 is placed on the unit positioning jig 23. In other words, the third inner wall portion 24a1 surrounds the spacer opening 24d on all four sides. The spacer opening 24d includes components above the circuit pattern 3b of the semiconductor unit 2.

[0064] The positioning and fixing portion 24b is formed on the back surface of the third frame portion 24a. The positioning and fixing portion 24b is formed to be flush with the third inner wall portion 24a1 of the third frame portion 24a. The positioning and fixing portion 24b is formed to have a convex cross section so as to fit into the gap between the second frame portion 23a of the unit positioning jig 23 and the circuit pattern 3b when the spacer jig 24 is placed relative to the unit positioning jig 23. The positioning and fixing portion 24b is formed to be flush with the outside of the circuit pattern 3b of the insulating circuit board 3 and the second frame portion 23a. gap The positioning fixing portion 24b is formed continuously in a ring shape on the rear surface of the third frame portion 24a so as to fit into the insulating circuit board 3. Therefore, the width (±X direction and ±Y direction) of the positioning fixing portion 24b corresponds to the width of the insulating plate 3a of the insulating circuit board 3 that protrudes from the circuit pattern 3b.

[0065] The guide portion 24c is formed by a guide inner wall portion 24c1 protruding from a part of the third inner wall portion 24a1 of the third frame portion 24a. When the spacer jig 24 is mounted on the unit positioning jig 23 and the insulating circuit board 3, the guide inner wall portion 24c1 of the guide portion 24c extends to the side of the lead frame 5, as shown in Figures 21 and 22.

[0066] Next, a setting step of setting a weight is performed (step S12e). Step S12e will be described with reference to FIGS. 23 and 24. FIG. 23 is a cross-sectional view showing the weight setting step included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment, and FIG. 24 is a plan view showing the weight setting step included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment. Note that FIG. 23 is a cross-sectional view taken along the dashed dotted line YY in FIG. 24.

[0067] The weight 25 is placed on the spacer jig 24. The weight 25 includes a main body 25a and a guide hole 25b. The main body 25a is cubic. The main body 25a is made of, for example, stainless steel. The weight 25 only needs to have a predetermined weight. The weight 25 only needs to be taller than the lead frame 5 protruding from the front surface of the spacer jig 24. The guide hole 25b is formed in the main body 25a to correspond to the lead frame 5 (joint portion 5a) when the weight 25 is placed on the spacer jig 24. The shape of the guide hole 25b in a plan view corresponds to the shape of the pressing jig 15 in a plan view. The shape of the guide hole 25b in a plan view is, for example, rectangular or circular. It may also be triangular. In this example, the guide hole 25b is rectangular and surrounded on all four sides by guide inner wall portions 25b1.

[0068] 23 and 24, when such a weight 25 is placed on the spacer jig 24, the main body 25a of the weight 25 is supported by the spacer jig 24, and the lead frame 5 is positioned in the guide hole 25b. As a result, the semiconductor unit 2 is pressed toward the heat sink 6 by the weight 25 via the spacer jig 24.

[0069] Next, a setting step of setting a pressing jig is performed (step S12f). Step S12f will be described with reference to FIGS. 25 and 26. FIG. 25 is a cross-sectional view showing the setting step of a pressing jig included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment, and FIG. 26 is a plan view showing the setting step of a pressing jig included in the bonding step of the manufacturing method for a semiconductor device according to the first embodiment. Note that FIG. 25 is a cross-sectional view taken along the dashed dotted line YY in FIG. 26.

[0070] As explained in Fig. 10, pressing jig 15 includes pressing body 15a having pressing surface 15a1 at its tip as a pressing portion, and locking portion 15b. As shown in Figs. 25 and 26, pressing jig 15 is inserted into guide hole 25b of weight 25 and set. In this case, pressing surface 15a1 abuts against the front surface of joint 5a of lead frame 5. Pressing jig 15 presses joint 5a toward insulating circuit board 3 with pressing surface 15a1 due to its own weight. However, locking portion 15b prevents pressing jig 15 from applying excessive pressure to joint 5a.

[0071] In this manner, a joining jig set 20 is configured, including the base jig 21, the fixing jig 22, the unit positioning jig 23, the spacer jig 24, the weight 25, and the pressing jig 15. The base jig 21, the fixing jig 22, the unit positioning jig 23, and the spacer jig 24 of the joining jig set 20 may be configured from a material with excellent heat resistance. Such a material is, for example, carbon.

[0072] Next, the bonding process is carried out (step S12g). The bonding portion 5a of the lead frame 5 is heated while pressed against the insulating circuit board 3 by the pressing jig 15. This melts the bonding member 7a. The bonding members 7b and 7c also re-melt. At this time, the semiconductor chip 4, which warps due to the difference in thermal expansion coefficient with the insulating circuit board 3, is pressed against the insulating circuit board 3 by the pressing jig 15. This corrects the warpage of the semiconductor chip 4, as explained in the case of FIG. 10.

[0073] At this time, the circuit pattern 3b and the semiconductor chip 4 lead frame Since the joint portions 5a of the semiconductor unit 2 and the heat sink 6 are substantially parallel to each other, the thicknesses of the joint members 7a and 7b, 7c between the semiconductor unit 2 and the heat sink 6 are maintained substantially uniform. heat sink 6, The insulating circuit board 3, the semiconductor chip 4, and the joint 5a of the lead frame 5 are joint members. 7a,The insulating circuit board 3 is then bonded to the semiconductor chip 4 by bonding members 7b and 7c. At this time, the bonding members 7b and 7c also have a uniform thickness. Therefore, the semiconductor unit 2 is obtained in which the insulating circuit board 3, the semiconductor chip 4, and the lead frame 5 are bonded again. Furthermore, the heat sink 6 is bonded to the semiconductor unit 2. Because the heat sink 6 is pressed by the insulating circuit board 3, the thickness of the bonding member 7a is maintained thin and uniform.

[0074] After the joining process of step S12 in the flowchart of Figure 2 is performed, the weight 25, spacer jig 24, unit positioning jig 23, and fixing jig 22 are removed in that order, and then the base jig 21 is removed, thereby obtaining the semiconductor device 1 shown in Figure 1.

[0075] The method for manufacturing semiconductor device 1 described above includes preparing an insulating circuit board 3, a semiconductor chip 4 arranged on circuit pattern 3b of insulating circuit board 3 via bonding member 7b, and a lead frame 5 having bonding portion 5a arranged on semiconductor chip 4 via bonding member 7c, the lead frame including bonding portion 5a. Next, lead frame positioning jig 13 having lead frame opening 13c therethrough is placed opposite insulating circuit board 3 so that lead frame opening 13c corresponds to bonding portion 5a of lead frame 5 in plan view. Next, columnar pressing jig 15 having pressing surface 15a1 at its tip is inserted into lead frame opening 13c, and pressing surface 15a1 presses bonding portion 5a of lead frame 5 toward insulating circuit board 3.

[0076] In this way, the semiconductor chip 4 is pressed by the pressing jig 15 via the bonding portion 5a of the lead frame 5. Even if the semiconductor chip 4 warps due to the difference in thermal expansion coefficient with the insulating circuit board 3 when heated to bond the bonding members 7b and 7c, the semiconductor chip 4 is pressed by the pressing jig 15 and the warpage is corrected. As a result, the thickness of the bonding members 7b and 7c is made uniform, and the semiconductor chip 4 and the lead frame 5 are properly connected. A stable electrical connection is achieved between the semiconductor chip 4 and the lead frame 5, and the occurrence of electrical defects is suppressed. The same applies when bonding the semiconductor unit 2 and the heat sink 6.

[0077] [Second embodiment] In the second embodiment, a case where a pressing jig different from that in the first embodiment is used will be described with reference to Figs. 27 to 29. Fig. 27 is a cross-sectional view showing a weight setting step included in the bonding step of the method for manufacturing a semiconductor device according to the second embodiment. Fig. 28 is a cross-sectional view showing a pressing jig setting step included in the bonding step of the method for manufacturing a semiconductor device according to the second embodiment, and Fig. 29 is a plan view showing a pressing jig setting step included in the bonding step of the method for manufacturing a semiconductor device according to the second embodiment. Fig. 28 is a cross-sectional view taken along the dashed dotted line YY in Fig. 29.

[0078] The semiconductor unit 2 of the second embodiment has the same configuration as that of the first embodiment. However, in this case, two lead frames 5 are provided. The second embodiment is also manufactured according to the flowchart of FIG. 2. Furthermore, a pressing jig is also used in steps S11 and S12. Here, the case where a pressing jig is used in step S12 will be described.

[0079] In step S11, a semiconductor unit 2 is manufactured in which two lead frames 5 are bonded together. In step S12, a setting step (step S12a) of setting the heat sink 6 on the base jig 21, a fixing step (step S12b) of the heat sink 6, a positioning step (step S12c) of the semiconductor unit 2, and a setting step (step S12d) of the spacer jig 24 are performed in this order, following the flowchart of FIG.

[0080] Next, a setting step of setting the weight is performed (step S12e). As shown in FIG. 27, the weight 25, which has one guide hole 25b formed therein and faces the area including the two lead frames 5, is placed on the spacer jig 24. The weight 25 also includes a main body 25a and a guide hole 25b. The main body 25a is cubic. The main body 25a is made of, for example, stainless steel. The weight 25 only needs to have a predetermined weight. The weight 25 only needs to be taller than the lead frames 5 protruding from the front surface of the spacer jig 24. The guide hole 25b is formed in the main body 25a so as to correspond to the area including the two lead frames 5 (bonding portions 5a) when the weight 25 is placed on the spacer jig 24. Here, the guide hole 25b has a rectangular shape in a plan view. The weight 25 is supported by the spacer jig 24, and the lead frames 5 are positioned in the guide hole 25b. As a result, the semiconductor unit 2 is pressed against the heat sink 6 by the weight 25 via the spacer jig 24 .

[0081] Next, a setting step of setting the pressing jig is performed (step S12f). As shown in FIGS. 28 and 29, the pressing jig 15 is inserted into the guide hole 25b of the weight 25 and set. As in the first embodiment, the pressing jig 15 includes a pressing main body 15a with a pressing surface 15a1 at its tip and a locking portion 15b. However, the pressing main body 15a (pressing surface 15a1) used here corresponds to the shape of the guide hole 25b. Furthermore, covering portions 15c are formed on the pressing surface 15a1 of the pressing main body 15a so as to correspond to the bonding portions 5a of the lead frame 5. The covering portions 15c are formed in a concave shape relative to the pressing surface 15a1. The shape of the covering portions 15c in a plan view corresponds to the bonding portions 5a, and their depth may be approximately the thickness of the bonding portions 5a.

[0082] When the pressing jig 15 is inserted into the guide hole 25b and set, the bonding portions 5a of the lead frame 5 are each covered with the covering portion 15c. At this time, it is sufficient that the bonding portions 5a are entirely covered with the covering portion 15c. Therefore, it does not matter whether the front surface of the bonding portions 5a is in contact with the bottom surface of the covering portion 15c. The pressing surface 15a1 abuts against the front surface of the semiconductor chip 4. Also in this case, the locking portion 15b of the pressing jig 15 prevents excessive pressure on the bonding portions 5a and the semiconductor chip 4.

[0083] Next, a bonding step is performed (step S12g). and semiconductor chip 4 is heated while pressed against the insulating circuit board 3. As in the first embodiment, the warpage of the semiconductor chip 4 is corrected. The same effects as in the first embodiment are obtained. Furthermore, at this time, since the bonding portion 5a is covered with the covering portion 15c, the bonding material 7c below the bonding portion 5a is prevented from scattering onto the front surface of the semiconductor chip 4.

[0084] In the second embodiment, the weight 25 is positioned facing the area including the plurality of lead frames 5. do The explanation is given taking the guide hole 25b as an example. However, this is not limited to this case, and a plurality of guide holes 25b may be provided for the weight 25 for each of a plurality of lead frames 5 (see, for example, FIGS. 32 and 33). In this case, a covering portion 15c is formed for each pressing jig 15 set in each guide hole 25b.

[0085] [Third embodiment] In the third embodiment, a method for manufacturing a semiconductor device different from that of the first embodiment will be described with reference to Figures 30 and 31. Note that in the semiconductor device 30, components similar to those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and their description may be omitted (or simplified). Figure 30 is a plan view of the semiconductor device of the third embodiment, and Figure 31 is a perspective view of a semiconductor unit included in the semiconductor device of the third embodiment.

[0086] As shown in Fig. 30, the semiconductor device 30 includes a semiconductor unit 2 and a case 40 that houses the semiconductor unit 2. The inside of the case 40 may be sealed with a sealing member (not shown). The semiconductor unit 2 is disposed on a heat sink 6 (see Fig. 32) that is provided on the back surface of the case 40. The semiconductor unit 2 will be described in detail later.

[0087] The case 40 has a substantially rectangular shape in a plan view and includes a frame 41 including a pair of short frame sides 41a, 41b and a pair of long frame sides 41c, 41d. The case 40 includes a storage section 42 surrounded on all four sides by the pair of short frame sides 41a, 41b and the pair of long frame sides 41c, 41d. The storage section 42 has a substantially rectangular shape in a plan view. The semiconductor unit 2 is stored in the storage section 42. When sealing with a sealing member, the inside of the storage section 42 is sealed.

[0088] The sealing member in this case may be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Epoxy resin is preferable. Furthermore, the sealing portion Material A filler may be added to the sealing member. The filler is a ceramic material that is insulating and has high thermal conductivity. Examples of such fillers include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride. The filler content is 10% by volume or more and 70% by volume or less of the entire sealing member.

[0089] Case 40 also has input terminals arranged on frame short sides 41a. The input terminals are specifically P terminals 43 and N terminals 44 provided along frame short sides 41a. Case 40 also has output terminals arranged on frame short sides 41b, which are opposite to the input terminals on the front surface of case 40. The output terminal is specifically M terminal 45 provided on frame short side 41b.

[0090] The P terminal 43, the N terminal 44, and the M terminal 45 are provided on either side of the storage section 42. Furthermore, the case 40 is provided with control terminals 46a and 46b on both sides of the M terminal 45 in the storage section 42. The other ends of these terminals are electrically connected to the semiconductor chips of the semiconductor unit 2 stored in the storage section 42. For example, the other ends of the control terminals 46a and 46b are electrically connected to control electrodes, which are the gate electrodes of the semiconductor chips 4a1 and 4b1, via wires 58. The other ends of the P terminal 43, the N terminal 44, and the M terminal 45 are electrically connected to main electrodes, such as the emitter electrode (or source electrode) and the collector electrode (or drain electrode), of the semiconductor chips 4a2 and 4b2, respectively.

[0091] Furthermore, a cooling unit (not shown) can be attached to the back surface of the case 40 to which the heat sink 6 is attached. In this case, the cooling unit is made of, for example, a metal with excellent thermal conductivity. The metal may be aluminum, iron, silver, copper, or an alloy containing at least one of these. The cooling unit may be a heat sink or a water-cooled jacket equipped with one or more fins. The heat sink may also be integrated with such a cooling unit.

[0092] 31, semiconductor unit 2 includes insulating circuit board 3, semiconductor chips 4a1, 4a2, 4b1, and 4b2, and lead frames 50a and 50b. As in the first embodiment, insulating circuit board 3 includes insulating plate 3a, multiple circuit patterns 3b formed on insulating plate 3a, and metal plate 3c formed on the back surface of insulating plate 3a. Semiconductor chips 4a1 and 4b1 include the RC-IGBTs described in the first embodiment.

[0093] The lead frame 50a directly connects the semiconductor chips 4a1 and 4a2 to the circuit pattern 3b. The lead frame 50a includes a bonding portion 50a1 bonded to the main electrodes on the front surfaces of the semiconductor chips 4a1 and 4a2, a bonding portion 50a2 bonded to the circuit pattern 3b, and a wiring portion 50a3 connecting the bonding portions 50a1 and 50a2 (see, for example, FIG. 32). The lead frame 50b directly connects the semiconductor chips 4b1 and 4b2 to the circuit pattern 3b. The lead frame 50b includes a bonding portion 50b1 bonded to the main electrodes on the front surfaces of the semiconductor chips 4b1 and 4b2, a bonding portion 50b2 bonded to the circuit pattern 3b, and a wiring portion 50b3 connecting the bonding portions 50b1 and 50b2 (see, for example, FIG. 32).

[0094] The semiconductor unit 2 and the semiconductor device 30 including the semiconductor unit 2 according to the third embodiment are manufactured according to the flowchart of FIG. 2 for the first embodiment. Steps S11 and S12 included in this flowchart are performed, and a pressing jig 15 is used as in the first and second embodiments. Here, the case where the pressing jig 15 is used in the bonding step of step S12 will be described with reference to FIGS. 32 to 34. FIG. 32 is a cross-sectional view showing a weight setting step included in the bonding step of the semiconductor device manufacturing method according to the third embodiment, and FIG. 33 is a plan view showing a weight setting step included in the bonding step of the semiconductor device manufacturing method according to the third embodiment. FIG. 34 is a cross-sectional view showing a pressing jig setting step included in the bonding step of the semiconductor device manufacturing method according to the third embodiment. FIG. 32 is a cross-sectional view taken along the dashed dotted line YY in FIG. 33.

[0095] In step S11, the semiconductor unit 2 shown in Fig. 31 is manufactured. In step S12, a setting step (step S12a) of setting the heat sink 6 on the base jig 21, a fixing step (step S12b) of fixing the heat sink 6, a positioning step (step S12c) of the semiconductor unit 2, and a setting step (step S12d) of the spacer jig 24 are performed in accordance with the flowchart of Fig. 12. In the third embodiment, the height of the spacer jig 24 is higher than the height of the lead frames 50a, 50b of the semiconductor unit 2 from the front surface of the insulating circuit board 3.

[0096] Next, a setting step of setting the weight is performed (step S12e). As shown in FIGS. 32 and 33, the weight 25, which has four guide holes 25b formed therein and which face the bonding portions 50a1, 50a2, 50b1, and 50b2 of the lead frames 50a and 50b, is placed on the spacer jig 24 (FIG. 32 shows the guide holes 25b of the weight 25 facing the bonding portions 50a1 and 50b1). The weight 25 also includes a main body 25a and four guide holes 25b. The main body 25a is cubic. The main body 25a is made of, for example, stainless steel. The weight 25 only needs to have a predetermined weight. The guide holes 25b are formed in the main body 25a so as to correspond to the bonding portions 50a1, 50a2, 50b1, and 50b2 of the lead frames 50a and 50b when the weight 25 is placed on the spacer jig 24. Here, the guide hole 25b has a rectangular shape in a plan view. The weight 25 is supported by the spacer jig 24, and the joints 50a1, 50a2, 50b1, and 50b2 of the lead frames 50a and 50b are positioned in the guide hole 25b. As a result, the semiconductor unit 2 is pressed toward the heat sink 6 by the weight 25 via the spacer jig 24.

[0097] Next, a setting step of setting the pressing jigs is performed (step S12f). As shown in FIG. 34, the pressing jigs 15 are inserted into the guide holes 25b of the weights 25 and set. As in the first embodiment, the pressing jig 15 includes a pressing main body portion 15a having a pressing surface 15a1 at its tip and a locking portion 15b. However, the pressing main body portion 15a (pressing surface 15a1) used here corresponds to the shape of the guide holes 25b.

[0098] When pressing jig 15 is inserted into four guide holes 25b and set, pressing surface 15a1 comes into contact with bonding portions 50a1, 50a2, 50b1, and 50b2, respectively. Note that Fig. 34 illustrates bonding portions 50a1 and 50b1 that come into contact with pressing surface 15a1 of pressing jig 15. Also in this case, excessive pressing of pressing jig 15 against bonding portions 50a1, 50a2, 50b1, and 50b2 and semiconductor chip 4 is suppressed by locking portion 15b.

[0099] Next, a bonding process is performed (step S12g). Bonding portions 50a1, 50a2, 50b1, and 50b2 of lead frames 50a and 50b are heated while pressed against insulating circuit board 3 by pressing jig 15. As in the first embodiment, warpage of semiconductor chips 4a1, 4a2, 4b1, and 4b2 is corrected, and the same effects as in the first embodiment are obtained.

[0100] Note that, similarly to the second embodiment, a covering portion 15c may be formed on the pressing surface 15a1 of the pressing jig 15 of the third embodiment. In this case, too, the bonding portions 50a1, 50a2, 50b1, and 50b2 of the lead frames 50a and 50b are covered with the covering portion 15c, thereby preventing the bonding material that bonds the bonding portions 50a1, 50a2, 50b1, and 50b2 from scattering onto the front surfaces of the semiconductor chips 4a1, 4a2, 4b1, and 4b2. [Explanation of symbols]

[0101] 1,30 Semiconductor devices 2 Semiconductor Unit 3. Insulated circuit board 3a Insulating plate 3b Circuit pattern (conductive plate) 3c metal plate 4,4a1,4a2,4b1,4b2 Semiconductor chips 5,50a,50b Lead frame 5a,50a1,50a2,50b1,50b2 joint 5b,50a3,50b3 Wiring section 6 Heat sink 6a Fixed groove 7a,7b,7c Joining parts 10 Manufacturing jig set 11 Circuit board fixing jig 11a Frame 11b Fixed area 11c bottom 12 Chip positioning jig 12a Chip frame 12b Fixed part 12c Tip Opening 13 Lead frame positioning jig 13a Lead frame frame 13c Lead frame opening 13c1 Lead frame inner wall 15 Pressing jig 15a Pressing body 15a1 Pressing surface 15b Locking part 15c Covering part 20 Joining jig set 21 Base jig 21a Recess 21b Fixing member 22 Fixture 22a 1st frame part 22a1 1st inner wall part 22b 1st protrusion 22b1 Projecting inner wall part 22c 1st opening area 23 Unit positioning jig 23a 2nd frame part 23a1 2nd inner wall part 23b Second protrusion 23c 2nd opening area 24 Spacer jig 24a 3rd frame 24a1 3rd inner wall part 24b Positioning fixing part 24c Guide section 24c1 Guide inner wall 24d Spacer opening 25 weight 25a Main body 25b Guide hole 25b1 Guide inner wall 40 cases 41 Frame 41a, 41b Short side of frame 41c, 41d Frame length 42 Storage area 43 P terminal 44 N terminal 45M terminal 46a, 46b control terminals 58 Wire

Claims

1. a preparation step of preparing a conductive plate, a semiconductor chip disposed on the conductive plate via a first bonding material, and a connection terminal including a bonding portion further disposed on the semiconductor chip via a second bonding material; a first jig placement process of placing a first guide jig having a first guide hole passing therethrough, facing the conductive plate so that the first guide hole corresponds to the joint portion in a plan view; a first pressing step of inserting a columnar pressing jig having a pressing portion at a lower end thereof into the first guide hole and pressing the joint portion of the connection terminal toward the conductive plate with the pressing portion; and The pressing jig further includes a locking portion above the pressing portion, In the first pressing step, the locking portion of the pressing jig is locked to the first guide jig, and the pressing portion presses the joint portion. A method for manufacturing a semiconductor device.

2. The first pressing step includes pressing with the pressing portion of the pressing jig while heating. The method for manufacturing a semiconductor device according to claim 1 .

3. The conductive plate is included in an insulating circuit board together with an insulating plate having the conductive plate formed on its front surface and a metal plate formed on the back surface of the insulating plate.

3. The method for manufacturing a semiconductor device according to claim 1.

4. In the preparation step, a heat sink and the insulating circuit board are further prepared, After the first pressing step, the insulating circuit board, to which the semiconductor chip and the bonding portions of the connection terminals are bonded in order, is placed on the heat sink via a third bonding material; The method further includes a second pressing step of pressing the joint portion of the connection terminal with the first guide jig and the pressing jig. The method for manufacturing a semiconductor device according to claim 3 .

5. The second pressing step includes pressing with the pressing portion of the pressing jig while heating. The method for manufacturing a semiconductor device according to claim 4 .

6. In the second pressing step, a spacer jig having an opening corresponding to the semiconductor chip in a plan view is disposed in the opening so as to include the semiconductor chip and the bonding portion of the connection terminal; placing the first guide jig on the spacer jig; 6. The method for manufacturing a semiconductor device according to claim 4.

7. a height of the opening of the spacer jig being greater than a combined height of the semiconductor chip and the joint portion of the connection terminal disposed on the semiconductor chip; The method for manufacturing a semiconductor device according to claim 6 .

8. a guide portion extending to the joining portion is formed on the inner surface of the opening of the spacer jig; The method for manufacturing a semiconductor device according to claim 6 or 7.

9. In the first pressing step, The semiconductor chip is bonded to the conductive plate with the first bonding material, and the bonding portion of the connection terminal is bonded to the semiconductor chip with the second bonding material to form a semiconductor unit. The method for manufacturing a semiconductor device according to claim 1 .

10. The pressing portion of the pressing jig is flat, and a recessed accommodation portion is formed in the pressing portion to accommodate the joint portion of the connection terminal. The method for manufacturing a semiconductor device according to claim 1 .

11. a first guide jig disposed opposite the conductive plate to a bonding portion of a connection terminal disposed via a second bonding material on a semiconductor chip disposed on the conductive plate via a first bonding material, the first guide jig having a first guide hole passing therethrough that faces the bonding portion in a plan view; a pressing tool having a columnar shape and a pressing portion at a lower end thereof, the pressing tool being inserted into the first guide hole and configured to press the joint portion of the connection terminal toward the conductive plate with the pressing portion; Including, the pressing jig is inserted into the first guide hole and engaged with the first guide jig, and further includes an engaging portion above the pressing portion. Jig set.

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