Dry etching method for single crystal silicon wafer, manufacturing method for single crystal silicon wafer, and single crystal silicon wafer

Abstract

To provide a method for dry etching a silicon wafer, which is capable of forming a roughened surface on a silicon wafer, and a method for producing a silicon wafer, a roughened surface being formed only on one side of a silicon wafer.SOLUTION: A method for dry etching a single crystal silicon wafer is a dry etching method for forming a roughened surface on a single crystal silicon wafer. As the single crystal silicon wafer, a single crystal silicon wafer having a surface where a natural oxide film (SiO2) is present is used. The method includes a step in which the surface of the single crystal silicon wafer, on the surface the natural oxide film being present, is subjected to a dry etching process by means of a gas that contains at least fluorine. In addition, in the dry etching process, a roughened surface is formed on the single crystal silicon wafer by setting the etching selectivity of Si over SiO2 as calculated by (etching rate of Si / etching rate of SiO2) to 18 or more, and setting the etching amount of SiO2 to 2.5 nm or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a dry etching method for silicon wafers that can form a roughened surface on semiconductor silicon wafers, and a method for manufacturing silicon wafers in which a roughened surface is formed on only one side of the silicon wafer. [Background technology]

[0002] The manufacturing process for silicon wafers for semiconductor devices consists of a single crystal manufacturing process in which a single crystal ingot is grown using the Czochralski (CZ) method or other methods, and a wafer processing process in which this single crystal ingot is sliced ​​and processed to a mirror finish.To add further value, the process may also include an annealing process in which heat treatment is performed and an epitaxial growth process in which an epitaxial layer is formed.

[0003] Currently, to obtain highly flat wafers, the mirror-finish processing process employs the DSP (double-sided polishing) process, in which both sides are polished to a mirror finish, followed by the CMP (single-sided polishing) process. During these polishing processes, wafers are sometimes transported while stored underwater in a pit tank or similar, due to particle quality considerations. Furthermore, during the CMP process, wafers stored underwater must be chucked by a robot or similar device and transported to the CMP equipment. Similarly, after CMP polishing, wafers wet with abrasives or pure water must be chucked and transported to the cleaning process as necessary.

[0004] As described above, in the wafer processing process, it is essential to transport wafers in a wet environment, not a dry one. However, especially in such a wet environment, when a wafer held by a chuck is to be released, because the wafer is double-sided polished and has a high degree of flatness, it cannot be released even when the chuck is released, resulting in transport failure. The cause of this is thought to be the roughness of the wafer surface being chucked. If the surface roughness of the chucked wafer is too good, the contact area with the chuck increases, making it difficult for the wafer to be released from the chuck. Conversely, if the wafer surface roughness is poor, the contact area decreases, making it easier for the wafer to be released.

[0005] Generally, the chucked surface is prone to forming chucking marks, which can lead to a decrease in quality, and so the chucked surface is often the backside of the silicon wafer. Therefore, from the perspective of reducing transport defects, it is preferable that only the backside of the silicon wafer is rough, and a method for manufacturing such wafers is being sought.

[0006] It is generally known that the surface roughness of a silicon wafer is affected by the etching action that dissolves Si and SiO2. For example, when Si is immersed in a strong alkaline solution such as NaOH or KOH, the following reaction occurs: Si + 2H2O + 2OH - →SiO2(OH)2 2- When Si reacts with water and hydroxyl groups, as in +2H2, it dissolves as hydroxide, and the etching of Si progresses. Furthermore, it is known that the more this etching progresses, the worse the surface roughness becomes due to the anisotropy of Si.

[0007] There are two types of etching methods: wet etching, which uses chemical solutions, and dry etching, which uses plasma-activated gas. As semiconductor devices become increasingly miniaturized, dry etching has become more prevalent than wet etching in the semiconductor device manufacturing process. Dry etching is a method in which gas supplied to a reaction chamber is activated by plasma discharge and reacts with the silicon on the wafer surface, causing an etching reaction. Typical gases used are those containing fluorine (F) or chlorine (Cl). For example, if we consider CF4 as a fluorocarbon gas, the F activated by plasma discharge reacts with the silicon, forming volatile SiF4, which then etches the silicon.

[0008] Dry etching techniques such as this are often used in the manufacturing process of semiconductor devices to form patterned elements. Dry methods offer greater control and reproducibility of etching than wet methods.

[0009] Patent Document 1 discloses a technology for etching polycrystalline or amorphous silicon with high selectivity relative to silicon compounds by plasma etching using a gas consisting of 0.1 to 20 vol% of a halogen compound, water or a hydroxyl group-containing compound, and the remainder being oxygen. However, this technology is not for etching single-crystal silicon.

[0010] Patent Document 2 discloses a method for selectively etching silicon-based materials by adjusting the fluorine-based active species to be used depending on the silicon-based material to be etched. In particular, in the case of single-crystal Si, a method is disclosed in which only fluorine active species are used without adding water vapor, but there is no description of specific etching selectivity or etching rate.

[0011] Non-Patent Document 1 discloses a Si etching technique using a gas mixture of CF4 and O2. Specifically, it describes that the etching rate of Si changes when O2 is added to CF4.

[0012] On the other hand, dry etching technology is sometimes used in wafer manufacturing processes. Patent Document 3 discloses a technology for manufacturing silicon wafers by dry etching the entire surface of a raw material wafer that has a post-grinding damage layer to remove the damage layer, and then performing double-sided polishing. In this way, the main purpose of dry etching in the wafer manufacturing process is to remove the damage layer. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-356557 [Patent Document 2] Japanese Patent Application Laid-Open No. 2000-164559 [Patent Document 3] Patent No. 7028353 [Non-patent literature]

[0014] [Non-Patent Document 1] Dry Etching Technology for LSI Manufacturing (Metal Surface Technology 30(5),256-268,1979) Summary of the Invention [Problem to be solved by the invention]

[0015] As mentioned above, there is a need for chucked silicon wafers with rough backsides to reduce transport defects during processing.

[0016] The present invention has been made to solve the above problems, and an object of the present invention is to provide a silicon wafer dry etching method capable of forming a roughened surface on a silicon wafer, and a silicon wafer manufacturing method in which a roughened surface is formed on only one side of the silicon wafer. [Means for solving the problem]

[0017] In order to solve the above problems, the present invention provides: A dry etching method for forming a roughened surface on a single crystal silicon wafer, comprising: The method includes a step of using a single crystal silicon wafer having a native oxide film (SiO2) on its surface as the single crystal silicon wafer, and subjecting the surface of the single crystal silicon wafer having the native oxide film thereon to a dry etching treatment using a gas containing at least fluorine, and In the dry etching treatment, the etching selectivity ratio of Si to SiO calculated from (etching rate of Si / etching rate of SiO) is set to 18 or more, and the etching amount of SiO is set to 2.5 nm or more, thereby providing a dry etching method for a single crystal silicon wafer, which forms a roughened surface on the single crystal silicon wafer.

[0018] Such a dry etching method for a single crystal silicon wafer makes it possible to form a roughened surface by utilizing the effect that Si is preferentially etched.

[0019] It is also preferable that the etching rate of Si is a value calculated using a single crystal silicon wafer, and the etching rate of SiO2 is a value calculated using a single crystal silicon wafer with a thermal oxide film.

[0020] This method allows for highly accurate evaluation of the etching behavior of SiO2 and Si. In particular, polycrystalline silicon wafers are generally used to confirm the dry etching rate of Si, but from the perspective of more accurate evaluation, it is preferable to use single-crystal silicon wafers.

[0021] In the dry etching process, it is preferable that the amount of Si etched is 200 nm or less.

[0022] By controlling the amount of etching in this way, it is possible to form a suitable roughened surface.

[0023] In the dry etching process, it is preferable to use a fluorocarbon gas as the fluorine-containing gas.

[0024] By using a fluorocarbon gas in this way, a roughened surface can be suitably formed.

[0025] In the dry etching process, it is preferable to use CF4 as the fluorocarbon gas.

[0026] By using CF4 gas in this way, a suitable roughened surface can be formed.

[0027] In the dry etching process, it is preferable to add oxygen to the fluorine-containing gas to adjust the etching selectivity of Si to SiO2, the etching rate of Si, and the etching rate of SiO2.

[0028] By adding O2 in this way, the etching selectivity and etching rate can be easily controlled.

[0029] Furthermore, it is preferable that the native oxide film is formed by SC1 cleaning, SC2 cleaning, or O3 cleaning.

[0030] This method makes it possible to form a uniform native oxide film.

[0031] The present invention also provides a method for producing a single crystal silicon wafer, comprising: (1) A process of double-sided polishing a raw wafer from which the processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning to prepare a double-sided polished wafer with a native oxide film on the surface; (2) performing a dry etching process on one side of the double-side polished wafer using a single-wafer dry etching apparatus to form a rough surface by the above-mentioned dry etching method for single crystal silicon wafers; (3) performing single-side polishing on the side opposite to the side on which the roughened surface of the dry-etched double-side polished wafer is formed, thereby obtaining a single crystal silicon wafer having a roughened surface formed only on one side. The present invention provides a method for producing a single crystal silicon wafer, comprising:

[0032] This manufacturing method makes it possible to manufacture wafers with a roughened surface formed on only one side by dry etching using a single wafer process, thereby reducing transport defects.

[0033] The present invention also provides a method for producing a single crystal silicon wafer, comprising: (1) A process of double-sided polishing a raw wafer from which the processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning to prepare a double-sided polished wafer with a native oxide film on the surface; (2) performing a dry etching process on both sides of the double-side polished wafer using a batch-type dry etching apparatus to form rough surfaces by the above-mentioned dry etching method for single crystal silicon wafers; (3) performing single-side polishing on the dry-etched double-side polished wafer to obtain a single crystal silicon wafer having a roughened surface formed on only one side; The present invention provides a method for producing a single crystal silicon wafer, comprising:

[0034] This manufacturing method makes it possible to manufacture wafers with a roughened surface formed on only one side by dry etching in a batch process, thereby reducing transport defects.

[0035] Further, the present invention provides a single crystal silicon wafer, The present invention provides a single crystal silicon wafer having a three-dimensional calculated average height Sa as an index, with Sa on the front side being 0.2 nm or less and Sa on the back side being 0.5 nm or more.

[0036] Such single crystal silicon wafers can reduce transport defects.

[0037] Further, the present invention provides a single crystal silicon wafer, Using the three-dimensional calculated average height Sa as an index, a single crystal silicon wafer having (rear surface side Sa / front surface side Sa) of 5 or more is provided.

[0038] Such single crystal silicon wafers can reduce transport defects. [Effects of the Invention]

[0039] The dry etching method for a single crystal silicon wafer of the present invention can form a roughened surface on the single crystal silicon wafer. Furthermore, the manufacturing method for a single crystal silicon wafer of the present invention can produce a highly flat single crystal silicon wafer having a roughened surface formed on only one side. Furthermore, the silicon wafer of the present invention can reduce transport defects during processing. [Brief explanation of the drawings]

[0040] [Figure 1] 1 is a flowchart showing an example of a method for dry etching a single crystal silicon wafer according to the present invention. [Figure 2] 1 is a flowchart showing an example of a method for producing a single crystal silicon wafer according to the present invention. [Figure 3] 1 is a graph showing haze after dry etching is performed on a single crystal silicon wafer having a native oxide film by adding O2 to CF4 at various concentrations. [Figure 4] 1 is a graph showing the etching rates of single crystal Si and thermal oxide film SiO2 under various dry etching conditions. [Figure 5] 1 is a graph showing the etching selectivity of Si to SiO 2 under various dry etching conditions. [Figure 6] 1 is a graph showing the etching treatment time dependency of haze value under each dry etching condition. [Figure 7]1 is a graph showing the amount of SiO2 etched versus processing time under various dry etching conditions. [Figure 8] 1 is a graph showing the three-dimensional calculated average height Sa of the rough surface side of a single crystal silicon wafer having a rough surface formed thereon under various dry etching conditions and treatment times, as measured by AFM. [Figure 9] 1 is a schematic diagram showing an example of a single crystal silicon wafer of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0041] As described above, there has been a need for the development of a silicon wafer dry etching method capable of forming a roughened surface on a silicon wafer, and a silicon wafer manufacturing method for forming a roughened surface on only one side of the silicon wafer.

[0042] In order to achieve the above object, the present inventors have employed dry etching, which has better controllability and reproducibility than wet etching, for single crystal silicon wafers, and have conducted extensive research into whether a roughened surface can be formed by dry etching using a fluorine-containing gas to induce an etching action on the wafer surface. As a result, they have found that when single crystal silicon wafers, particularly those having a native oxide film, are etched under conditions where the etching selectivity ratio of Si to SiO2 is high, etching of Si progresses rapidly where Si is exposed during etching, forming a roughened surface, and that the formation of this roughened surface can be controlled by adjusting the etching selectivity and the amount of SiO2 etching, thereby completing the present invention.

[0043] That is, the present invention provides a dry etching method for forming a roughened surface on a single crystal silicon wafer, the method comprising the steps of: using a single crystal silicon wafer having a native oxide film (SiO) on its surface as the single crystal silicon wafer; and dry etching the surface of the single crystal silicon wafer on which the native oxide film is present, with a gas containing at least fluorine; and in the dry etching treatment, setting the etching selectivity of Si to SiO, calculated from (etching rate of Si / etching rate of SiO), to 18 or more and the etching amount of SiO to 2.5 nm or more, thereby forming a roughened surface on the single crystal silicon wafer.

[0044] The present invention will be described in detail below as an example of an embodiment with reference to the drawings, but the present invention is not limited to this.

[0045] It should be noted that the "surface" in the "single crystal silicon wafer having a native oxide film on its surface" does not mean only the front surface of the so-called front and back surfaces of the wafer, but refers to a part or all of the part of the wafer that is visible from the outside. Hereinafter, whether "surface" is used in any of the above senses or in another sense will be interpreted appropriately depending on the context in this specification.

[0046] [Dry etching method for single crystal silicon wafers] FIG. 1 is a flowchart showing an example of a method for dry etching a single crystal silicon wafer according to the present invention. First, as shown in FIG. 1, a single crystal silicon wafer on which a roughened surface is to be formed is prepared. There are no restrictions on the conductivity type or diameter of the wafer, but a native oxide film must be formed on the wafer surface. The native oxide film is preferably formed by SC1 cleaning, SC2 cleaning, or O3 cleaning.

[0047] Next, as shown in Figure 1, the surface of the prepared single crystal silicon wafer, where the native oxide film is present, is subjected to a dry etching process using a gas containing at least fluorine. The dry etching process may be performed on a portion of the wafer surface (the front or back surface of the wafer) or on the entire wafer surface (the entire surface), but is preferably performed on the entire wafer surface. In this dry etching process, a roughened surface is formed on the single crystal silicon wafer by setting the etching selectivity of Si to SiO2, calculated from (Si etching rate / SiO2 etching rate), to 18 or more and the etching amount of SiO2 to 2.5 nm or more. This dry etching process will be described in detail below.

[0048] In dry etching, a gas containing fluorine (F) is activated by plasma discharge on a single-crystal silicon wafer, and the activated species of F react with Si to generate volatile SiF4, which causes etching of the Si (Si + 4F → SiF4). Fluorine-containing gases that can be used include, but are not limited to, fluorocarbons such as CF4, C2F6, C3F8, and C4F8, and inorganic fluorine-based gases such as SF6 and NF3. Chlorine may also be included as long as fluorine is included.

[0049] Here, we will discuss in detail the formation of rough surfaces by dry etching using CF4 as a fluorine-containing gas, from the perspective of the presence or absence of a native oxide film on the wafer surface and the etching behavior of Si and SiO2.

[0050] As an example, Figure 3 shows the results of evaluating haze, an index of roughness, with a particle counter after etching a single crystal silicon wafer on which a native oxide film had been formed using SC1 cleaning, using CF4 alone or CF4 with various concentrations of O2 added. All other conditions except for the gas ratio were standard etching conditions.

[0051] The higher the haze value, the rougher the surface, i.e., the more a rough surface has been formed. Looking at the effect of the O2 ratio, at O2 ratios of 0 to 20 vol%, the haze value was higher than that of the Ref without dry etching treatment, and the lower the O2 ratio, the greater the roughness tended to be. On the other hand, the haze value at O2 ratios of 50 and 80 vol% was the same as the Ref, indicating that a rough surface had not been formed.

[0052] Furthermore, when the same process was performed on a bare wafer from which the native oxide film had been removed by hydrofluoric acid cleaning, the haze was the same as that of the Reference. This shows that the etching conditions and the presence of the native oxide film affect the progression of roughening.

[0053] As a consideration of this, the etching rates of Si and SiO2 are shown in Figure 4. Note that the specific etching rate calculation method for Si was to etch a single crystal silicon wafer for a specified time, and then subtract the wafer thickness after etching from the wafer thickness before etching. For SiO2, the etching rate was calculated by etching a single crystal silicon wafer with a thermal oxide film grown by thermal oxidation for a specified time, and then subtracting the thermal oxide film thickness after etching from the thermal oxide film thickness before etching.

[0054] According to Figure 4, the etching rates of Si and SiO2 increased when a small amount of O2 was added. However, when the O2 ratio was 50 vol% or more, the etching rate tended to decrease. This is probably because the addition of a small amount of O2 increases the number of active fluorine species, and if too much O2 is added, an oxide film is formed on the surface, inhibiting etching.

[0055] Next, the etching selectivity of Si to SiO2 was calculated from (Si etching rate / SiO2 etching rate), and the results are shown in Figure 5. The higher this etching selectivity ratio, the more preferentially Si is etched. This graph shows that the lower the O2 ratio, the higher this etching selectivity ratio.

[0056] Comparing the results with those in Figure 3, we can see that the haze value increases when the etching selectivity ratio is 18 or higher, i.e., a roughened surface is formed. Therefore, to form a roughened surface, an etching selectivity ratio of 18 or higher is necessary. There is no particular upper limit to this etching selectivity ratio, but it can be set to 28 or lower, for example. These results allow us to consider the roughening mechanism. If we consider the native oxide film to be SiO2, when SiO2, which is more etch-resistant than Si, is etched, Si is locally exposed on the surface, and if the environment is such that Si is preferentially etched, rapid etching of the Si proceeds. As a result, irregularities are formed on the wafer surface, i.e., a roughened surface is formed.

[0057] Next, the effect of processing time at O2 ratios of 0 to 10% is shown in graph 6. Also, Fig. 7 is a graph in which the SiO2 etching amount at each O2 ratio is calculated from the SiO2 etching rate in Fig. 4.

[0058] As can be seen from Figure 6, the haze values ​​for O2 ratios of 0% and 2.5% and a treatment time of 30 seconds were the same as for Ref, indicating that no roughened surface was formed. However, the haze value increased after 60 seconds of treatment, indicating that roughening had progressed after 60 seconds of treatment at O2 ratios of 0% and 2.5%. Next, the haze value increased from 30 seconds of treatment at O2 ratios of 5%, 7.5%, and 10%, indicating that roughening had progressed after 30 seconds of treatment at O2 ratios of 5%, 7.5%, and 10%.

[0059] This difference can be explained by the SiO2 etching amount shown in Figure 7. As mentioned above, to promote roughening, it is necessary to locally etch the native oxide film on the top surface and expose the Si at the surface. The SiO2 etching amounts for 0% and 2.5% O2 ratios, which formed a rough surface after 60 seconds of treatment, were 14.1 Å and 14.6 Å, respectively, after 30 seconds of treatment, and 28.3 Å and 29.2 Å, respectively, after 60 seconds of treatment. The SiO2 etching amounts for 5%, 7.5%, and 10% O2 ratios, which formed a rough surface after 30 seconds of treatment, were 30.9 Å, 44.9 Å, and 54.3 Å, respectively, after 30 seconds of treatment. Therefore, a rough surface can be formed by etching 25 Å (2.5 nm) or more of SiO2 with a Si / SiO2 selectivity of 18 or more. There is no upper limit to the SiO2 etching amount, but it can be set to, for example, 300 Å (30 nm) or less.

[0060] Furthermore, the processing time dependence of Figure 6 shows that the haze value reaches a maximum at a certain processing time and then gradually decreases. As shown, excessive etching can reduce the roughness of the formed roughened surface. Therefore, shortening the etching time is desirable from the perspective of throughput and cost. Figure 6 shows that the processing times at which haze reaches its maximum are 120 s, 120 s, 60 s, 30 s, and 30 s for O2 ratios of 0%, 2.5%, 5%, 7.5%, and 10%, respectively. The silicon etching depths at these times were calculated to be 1600 Å, 1400 Å, 1400 Å, 1000 Å, and 1000 Å, respectively, based on Figure 4. Therefore, a silicon etching depth of 2000 Å (200 nm) or less can efficiently form a roughened surface. While there is no particular lower limit for the silicon etching depth, it can be set to, for example, 700 Å (70 nm) or more. Furthermore, with these etching depths, a roughened surface can be formed without compromising the flatness achieved by the double-side polishing process.

[0061] Figure 8 shows the results of evaluating the surface roughness of a roughened single-crystal silicon wafer using an atomic force microscope (AFM). The sample was a single-crystal silicon wafer after SC1 cleaning, etched for 20 and 30 seconds using the aforementioned O2 ratios of 7.5% and 10%. Note that the SiO2 etching volume at 20 seconds for the 7.5% and 10% O2 ratios was 29.9 Å (2.99 nm) and 36.2 Å (3.62 nm), respectively, confirming that it was greater than 25 Å (2.5 nm). The roughness index was the 3D calculated average height Sa. Compared to the reference, the Sa value increased at 20 and 30 seconds for both the 7.5% and 10% O2 ratios, indicating the formation of a rough surface. In particular, the Sa value was very high at 10% O2 ratio and 30 seconds for the 30-second treatment, at 0.94 nm, demonstrating the formation of a rough surface even when the Sa value is used as an index. Performing the dry etching process described above successfully produced a rough surface.

[0062] [Manufacturing method for single crystal silicon wafers] The present invention also provides a method for producing a single crystal silicon wafer using the above-mentioned method for dry etching a single crystal silicon wafer of the present invention.

[0063] A first aspect of the method for producing a single crystal silicon wafer of the present invention comprises: (1) A process of double-sided polishing a raw wafer from which the processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning to prepare a double-sided polished wafer with a native oxide film on the surface; (2) performing a dry etching process on one side of the double-side polished wafer using a single-wafer dry etching apparatus to form a rough surface by the dry etching method for single crystal silicon wafers of the present invention; (3) performing single-side polishing on the side opposite to the side on which the roughened surface of the dry-etched double-side polished wafer is formed, thereby obtaining a single crystal silicon wafer having a roughened surface formed only on one side. The present invention relates to a method for producing a single crystal silicon wafer, comprising the steps of:

[0064] A second aspect of the method for producing a single crystal silicon wafer of the present invention is to (1) A process of double-sided polishing a raw wafer from which the processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning to prepare a double-sided polished wafer with a native oxide film on the surface; (2) performing a dry etching process on both sides of the double-side polished wafer using a batch-type dry etching apparatus by the dry etching method for single crystal silicon wafers of the present invention to form rough surfaces; (3) performing single-side polishing on the dry-etched double-side polished wafer to obtain a single crystal silicon wafer having a roughened surface formed on only one side; The present invention relates to a method for producing a single crystal silicon wafer, comprising the steps of:

[0065] The first and second embodiments differ in that in step (2), the treatment by the dry etching method of the present invention is performed on one side or both sides of the double-side polished wafer. As will be described below, in either embodiment, a single crystal silicon wafer having a roughened surface formed on only one side can be obtained.

[0066] Fig. 2 is a flowchart showing an example of a method for producing a single crystal silicon wafer including the dry etching method of the present invention. Hereinafter, the method for producing a single crystal silicon wafer of the present invention will be described with reference to Fig. 2, but the present invention is not limited thereto.

[0067] (Process (1)) In step (1), a double-side polished wafer having a native oxide film on its surface is prepared.

[0068] In the example shown in Figure 2, a silicon ingot is subjected to a slicing process, a chamfering process, a lapping or grinding process, an etching process, a double-sided polishing process, and a cleaning process to prepare a silicon single crystal wafer (double-sided polished wafer) on which a native oxide film is formed. However, step (1) is not limited to this. Each step will be described below.

[0069] Slicing process The slicing process is a process in which, for example, a silicon ingot is cut into disk-shaped silicon wafers using a wire saw.

[0070] Chamfering process The chamfering process is a process in which the outer periphery of the wafer is chamfered using, for example, a grinding wheel with electrodeposited diamond abrasive grains in order to prevent chipping or cracking of the edge portion of the silicon wafer obtained in the slicing process.

[0071] Lapping or grinding process The lapping or grinding process is a process aimed at removing and flattening the strain layer formed on the front and back surfaces of the silicon wafer during the slicing process. In the lapping process, a lapping liquid, for example, a mixture of alumina or zirconia abrasive grains, water, and a surfactant, is poured between a lapping plate and a silicon wafer held by a carrier, and the silicon wafer surface is mechanically lapped by rotating and rubbing under pressure. In the grinding process, for example, the silicon wafer is ground using a grinding wheel with electroplated diamond. Grinding can be performed on one side at a time or on both sides simultaneously, but either method is acceptable.

[0072] Etching process The etching process removes the damage layers on the front and back surfaces of the wafer that were introduced during the lapping and grinding processes. For example, the damage layers can be removed by alkaline etching using an aqueous solution of NaOH or KOH, or by acid etching using a mixture of hydrofluoric acid and nitric acid.

[0073] Double-sided polishing process In the double-side polishing process, the front and back surfaces of a single crystal silicon wafer are polished to improve flatness. For example, both sides of a single crystal silicon wafer from which the post-etching damage layer has been removed are polished simultaneously using a polishing cloth and polishing slurry.

[0074] Cleaning process The cleaning process removes slurry residues such as silica that adhered during the double-sided polishing process. For example, silica can be efficiently removed by performing SC1 cleaning, which uses a chemical solution consisting of ammonia water, hydrogen peroxide, and water, or O3 cleaning, which uses O3 water. SC2 cleaning can also be performed using a chemical solution consisting of hydrochloric acid, hydrogen peroxide, and water.

[0075] Here, the surface of a single crystal silicon wafer immediately after double-side polishing is a bare surface, with the silicon surface exposed. By subjecting this bare surface to SC1 cleaning, SC2 cleaning, or O3 cleaning, which have an oxidizing effect, the silicon surface is oxidized and a native oxide film is formed on the surface. Therefore, the above-mentioned cleaning processes combine silica removal and native oxide film formation, making it easy to prepare single crystal silicon wafers (double-side polished wafers) with a native oxide film.

[0076] The cleaning conditions are not particularly limited as long as they are conditions that achieve silica removal and formation of a native oxide film. For example, SC1, SC2, and O3 cleaning can be performed using a conventional method as an oxidizing cleaning.

[0077] (Process (2)) Dry etching process (roughening surface formation) Next, the single crystal silicon wafer thus obtained, having a native oxide film on its surface, is subjected to a dry etching treatment by the dry etching method shown in FIG. 1, that is, the above-described dry etching method of the present invention, thereby forming a roughened surface.

[0078] The dry etching method may be either a single-wafer method for processing one wafer or a batch method for processing multiple wafers at once. Furthermore, the processing surface may be either a single-sided processing or a double-sided processing. The dry etching conditions for at least the surface on which a rough surface is to be formed are set to the dry etching conditions of the present invention. Thereafter, for example, if it is desired to form a rough surface only on the back surface side, only the back surface on one side can be processed by a single-wafer method according to the first aspect of the present invention. Even if double-sided processing is performed by a batch method according to the second aspect of the present invention, a single crystal silicon wafer can be produced in which one side has a normally polished surface by polishing the front surface side in the single-side polishing step described below.

[0079] (Step (3)) Subsequently, in step (3), a single crystal silicon wafer having a rough surface formed on only one side is obtained. In this step, as shown in Fig. 2, a mirror chamfering step, a single-side polishing step, and a final cleaning step can be performed. However, step (3) is not limited to these.

[0080] Mirror chamfering process In the mirror chamfering process, the chamfered portion of the single crystal silicon wafer that has been processed by dry etching is subjected to mirror finishing using an abrasive cloth and abrasive slurry to obtain a mirror finish.

[0081] Single side polishing process The single-side polishing process is a process in which a final wafer surface is created on one side of a silicon wafer using an abrasive cloth and abrasive slurry. In this case, if a rough surface is formed on only one side in the dry etching process (first embodiment), a single crystal silicon wafer having a rough surface on only one side can be produced by polishing the surface opposite to the rough surface. Normally, the rough surface is preferably on the back side, so the polished surface is the front surface of the silicon wafer. Also, even if rough surfaces are formed on both sides in the dry etching process (second embodiment), a single crystal silicon wafer having a rough surface formed on only one side can be produced by polishing the front surface side of the silicon wafer.

[0082] Final cleaning process In the final cleaning process, particles and metal impurities adhering to the silicon wafer are removed.

[0083] By using such a manufacturing process, it is possible to manufacture a silicon wafer having a three-dimensional calculated average height Sa of 0.2 nm or less on the front side and 0.5 nm or more on the back side.

[0084] The Sa values ​​of the front and back surfaces of silicon wafers fabricated according to the flow shown in Figure 2 were evaluated. The dry etching conditions were an O2 ratio of 10% and processing times of 20 and 30 seconds. After a processing time of 20 seconds, Sa was 0.068 nm on the front surface and 0.51 nm on the back surface, resulting in a (back surface Sa / front surface Sa) of 7.5. After a processing time of 30 seconds, Sa was 0.071 nm on the front surface and 0.92 nm on the back surface, resulting in a (back surface Sa / front surface Sa) of 13.0. Without the dry etching step, Sa was 0.069 nm on the front surface and 0.21 nm on the back surface, resulting in a (back surface Sa / front surface Sa) of 3.04. Therefore, a silicon wafer having a roughened surface formed only on the back surface can be fabricated by the method for fabricating a single crystal silicon wafer using the dry etching process of the present invention.

[0085] Furthermore, if such a silicon wafer has a rough surface formed only on the back side, chucking failure will not occur even in a wet environment, and stable manufacturing will be possible.

[0086] [Single crystal silicon wafer] The present invention also provides a single crystal silicon wafer in which, using a three-dimensional calculated average height Sa as an index, the Sa on the front side is 0.2 nm or less and the Sa on the back side is 0.5 nm or more. Figure 9 shows an example of a single crystal silicon wafer of the present invention. A single crystal silicon wafer 10 of the present invention has a front side 1 and a back side 2, and the back side 2 is a rough surface. Here, Sa on the front side 1 is 0.2 nm or less and Sa on the back side 2 is 0.5 nm or more.

[0087] The present invention further provides a single crystal silicon wafer in which, using a three-dimensional calculated average height Sa as an index, (Sa on the back surface side / Sa on the front surface side) is 5 or more. The single crystal silicon wafer of the present invention will be explained again with reference to FIG. 9. The single crystal silicon wafer 10 of the present invention has a front surface 1 and a back surface 2, and the back surface 2 is a rough surface. Here, (Sa on the back surface 2 side / Sa on the front surface 1 side) is 5 or more.

[0088] The single crystal silicon wafer of the present invention can be manufactured by the above-mentioned method for manufacturing a single crystal silicon wafer of the present invention. With such a single crystal silicon wafer, transportation defects can be reduced. [Example]

[0089] The present invention will be further described below with reference to examples, but these examples are given for illustrative purposes and should not be construed as limiting.

[0090] (Example) In this example, 50 P-type silicon single crystal wafers with a diameter of 300 mm and having a roughened surface formed only on the back surface side were manufactured according to the flowchart shown in Figure 2. The method for manufacturing the single crystal silicon wafer according to this example will be described below.

[0091] In the slicing process, the silicon single crystal ingot was cut into disc-shaped silicon wafers using a wire saw. The surfaces of the cut silicon wafers had undulations and layers of processing strain caused by the cutting process.

[0092] In the chamfering process, the rough edges of the silicon wafers were chamfered with a 3000-grit grinding wheel with diamond electrodeposited on it, forming the chamfered shape while preventing chipping and cracking during the wafer manufacturing process.

[0093] In the lapping process, in order to remove the surface distortion layer formed in the slicing process and to flatten the surface, a lapping liquid was poured between the lapping plate and the silicon wafer held by the carrier, and the silicon wafer surface was mechanically lapped by rotating and rubbing under pressure.

[0094] In the etching process, the wafer was immersed in an aqueous NaOH solution to remove the strain layer on the front and back surfaces of the wafer introduced by lapping, thereby obtaining silicon wafers from which the strain layer had been removed.

[0095] In the double-side polishing process, the etched silicon wafer was polished simultaneously with a polishing cloth and a polishing slurry. Both sides of the silicon wafer were polished and flattened at the same time.

[0096] In the cleaning process, SC1 cleaning was performed using a chemical solution consisting of ammonia water, hydrogen peroxide water, and water to remove silica remaining in the double-sided polishing process and form a natural oxide film on the surface.

[0097] In the dry etching process, a single-wafer dry etching system was used to form a roughened surface only on the backside of silicon wafers with a native oxide film. Fluorine active species were generated by high-frequency excitation in a gas mixture of 90 vol% CF4 and 10 vol% O2, and these fluorine active species were then supplied to the wafer surface for etching. The total gas flow rate was 420 sccm, the chamber pressure was 40 Pa, and the wafer support stage temperature was 70°C. Under these conditions, the Si etching rate calculated using a single-crystal silicon wafer was 2000 Å / min, and the SiO2 etching rate calculated using a single-crystal silicon wafer with a thermal oxide film was 109 Å / min, resulting in an etching selectivity of Si to SiO2 of 18.4. The processing time was set to 30 seconds (SiO2 etching depth: 54.5 Å) to ensure that the SiO2 etching depth was at least 25 Å (2.5 nm). This resulted in a roughened surface on the backside.

[0098] In the mirror-chamfering process, the chamfered portion of the silicon wafer after dry etching was mirror-finished using an abrasive cloth and abrasive slurry, resulting in a mirror-finished chamfer without any damage caused by machining.

[0099] In the single-side polishing process, the front side of the silicon wafer, opposite to the rough surface, was polished using a polishing cloth and polishing slurry, resulting in a well-polished surface on the front side.

[0100] In the final cleaning process, particles and metal impurities adhering to the silicon wafers were removed. Here, a batch-type cleaning machine was used, cleaning with chemicals SC1 and SC2.

[0101] One of the resulting silicon wafers was sampled, and the roughness of the front and back sides was evaluated using an AFM with an observation field of 2 μm. The three-dimensional calculated average height Sa was 0.065 nm on the front side and 0.94 nm on the back side. (Back side Sa / front side Sa) was 14.5, confirming that a rough surface was formed only on the back side. A transfer test was then performed 200 times in which the back side of the wafer stored underwater was chucked and the wafer was unchucked onto the stage of a polishing machine. All 200 transfers were successful without any defects.

[0102] (Comparative Example) In the comparative example, 50 P-type silicon single crystal wafers having a diameter of 300 mm were manufactured using the same procedures as in the example, except that only the dry etching step in the example was not performed.

[0103] One silicon wafer was sampled and the roughness of the front and back sides was evaluated using an AFM with an observation field of 2 μm. The three-dimensional calculated average height Sa was 0.067 nm on the front side and 0.22 nm on the back side. (Back side Sa / front side Sa) was 3.28, which was significantly smaller than the Sa value on the back side compared to the example. A transfer test was then conducted 200 times in which the back side of the wafer stored underwater was chucked and the wafer was unchucked onto the stage of a polishing machine. In four of the 200 tests, the wafer failed to detach from the chuck.

[0104] From the above results, it was found that by using the dry etching method of the present invention, it was possible to manufacture single crystal silicon wafers having a rough surface formed only on the back surface side, and transport defects could be reduced. In particular, it was possible to control the surface roughness to an arbitrary (targeted) level, and the back surface roughness (back surface Sa / front surface Sa) was well controlled and reproducible, allowing the manufacture of single crystal silicon wafers of stable quality.

[0105] This specification includes the following inventions.

[0106] [1]: A dry etching method for forming a roughened surface on a single crystal silicon wafer, comprising: a step of using a single crystal silicon wafer having a native oxide film (SiO2) on its surface as the single crystal silicon wafer; and dry etching the surface of the single crystal silicon wafer having the native oxide film with a gas containing at least fluorine; and wherein, in the dry etching, an etching selectivity of Si to SiO2 calculated from (Si etching rate / SiO2 etching rate) is set to 18 or more, and an etching amount of SiO2 is set to 2.5 nm or more, thereby forming a roughened surface on the single crystal silicon wafer.

[0107] [2]: The method for dry etching a single crystal silicon wafer according to the above [1], wherein the etching rate of Si is a value calculated using a single crystal silicon wafer, and the etching rate of SiO is a value calculated using a single crystal silicon wafer with a thermal oxide film.

[0108] [3]: The method for dry etching a single crystal silicon wafer according to [1] or [2] above, wherein the amount of Si etched in the dry etching treatment is 200 nm or less.

[0109] [4]: The method for dry etching a single crystal silicon wafer according to [1], [2], or [3] above, wherein a fluorocarbon gas is used as the fluorine-containing gas in the dry etching treatment.

[0110] [5]: The method for dry etching a single crystal silicon wafer according to the above [4], wherein CF4 is used as the fluorocarbon gas in the dry etching treatment.

[0111] [6]: The method for dry etching a single crystal silicon wafer according to [1], [2], [3], [4], or [5] above, wherein oxygen is added to the fluorine-containing gas in the dry etching treatment to adjust the etching selectivity of Si to SiO2, the etching rate of Si, and the etching rate of SiO2.

[0112] [7]: The method for dry etching a single crystal silicon wafer according to [1], [2], [3], [4], [5], or [6] above, wherein the native oxide film is formed by SC1 cleaning, SC2 cleaning, or O3 cleaning.

[0113] [8]: A method for producing a single crystal silicon wafer, comprising the steps of: (1) double-side polishing a raw material wafer from which a processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning, to prepare a double-side polished wafer having a native oxide film on its surface; (2) performing a dry etching process on one side of the double-side polished wafer using a single-wafer dry etching apparatus to form a roughened surface by the dry etching method for single crystal silicon wafers described in [1], [2], [3], [4], [5], [6], or [7]; and (3) performing single-side polishing on a side of the double-side polished wafer opposite to the side on which the roughened surface has been formed, to obtain a single crystal silicon wafer having a roughened surface formed on only one side.

[0114] [9]: A method for producing a single crystal silicon wafer, comprising the steps of: (1) double-side polishing a raw material wafer from which a processing strain layer has been removed, and then forming a native oxide film by SC1 cleaning, SC2 cleaning, or O3 cleaning, to prepare a double-side polished wafer having a native oxide film on its surface; (2) performing a dry etching process on both sides of the double-side polished wafer using a batch-type dry etching apparatus to form rough surfaces by the dry etching method for single crystal silicon wafers described in [1], [2], [3], [4], [5], [6], or [7]; and (3) performing single-side polishing on the double-side polished wafer that has been dry-etched, to obtain a single crystal silicon wafer having a rough surface formed on only one side.

[0115]

[10] : A single crystal silicon wafer, characterized in that, using a three-dimensional calculated average height Sa as an index, Sa on the front side is 0.2 nm or less and Sa on the back side is 0.5 nm or more.

[0116]

[11] : A single crystal silicon wafer, characterized in that, using a three-dimensional calculated average height Sa as an index, (Sa on the back surface side / Sa on the front surface side) is 5 or more.

[0117] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0118] 1...front surface, 2...back surface, 10...single crystal silicon wafer.

Claims

1. A dry etching method for forming a roughened surface on a single crystal silicon wafer, comprising: The single crystal silicon wafer has a natural oxide film (SiO ２ using a single crystal silicon wafer having a native oxide film thereon, and subjecting the surface of the single crystal silicon wafer having the native oxide film thereon to a dry etching treatment using a gas containing at least fluorine; and In the dry etching process, (Si etching rate / SiO ２ SiO calculated from the etching rate ２ The etching selectivity of Si to SiO is 18 or more. ２ a roughened surface is formed on the single crystal silicon wafer by setting the etching amount to 2.5 nm or more.

2. The etching rate of Si is set to a value calculated using a single crystal silicon wafer, and the SiO ２ 2. The method for dry etching a single crystal silicon wafer according to claim 1, wherein the etching rate is a value calculated using a single crystal silicon wafer with a thermal oxide film.

3. 2. The method for dry etching a single crystal silicon wafer according to claim 1, wherein the amount of Si etched in the dry etching process is set to 200 nm or less.

4. 2. The method for dry etching a single crystal silicon wafer according to claim 1, wherein a fluorocarbon gas is used as the fluorine-containing gas in the dry etching process.

5. In the dry etching process, the fluorocarbon gas is CF ４ 5. The method for dry etching a single crystal silicon wafer according to claim 4, wherein the etching is carried out by using a method for dry etching a single crystal silicon wafer.

6. In the dry etching process, oxygen is added to the fluorine-containing gas, thereby ２ the etching selectivity of Si to the SiO ２ 2. The method for dry etching a single crystal silicon wafer according to claim 1, wherein the etching rate is adjusted.

7. The native oxide film is cleaned by SC1 cleaning, SC2 cleaning, or O ３ 2. The method for dry etching a single crystal silicon wafer according to claim 1, wherein the surface is formed by cleaning.

8. A method for manufacturing a single crystal silicon wafer, comprising: (1) After double-side polishing of the raw material wafer from which the processing strain layer has been removed, the wafer is cleaned by SC1 cleaning, SC2 cleaning, or O ３ preparing a double-side polished wafer having a native oxide film on its surface by forming a native oxide film by cleaning; (2) performing a dry etching process on one side of the double-side polished wafer by the dry etching method for single crystal silicon wafers according to any one of claims 1 to 7 using a single-wafer dry etching apparatus to form a rough surface; (3) performing single-side polishing on the surface opposite to the surface on which the roughened surface of the dry-etched double-side polished wafer is formed, thereby obtaining a single crystal silicon wafer having a roughened surface formed only on one side; 2. A method for producing a single crystal silicon wafer, comprising:

9. A method for manufacturing a single crystal silicon wafer, comprising: (1) After double-side polishing of the raw material wafer from which the processing strain layer has been removed, the wafer is cleaned by SC1 cleaning, SC2 cleaning, or O ３ preparing a double-side polished wafer having a native oxide film on its surface by forming a native oxide film by cleaning; (2) performing a dry etching process on both sides of the double-side polished wafer by the dry etching method for single crystal silicon wafers according to any one of claims 1 to 7 using a batch-type dry etching apparatus to form rough surfaces; (3) performing single-side polishing on the dry-etched double-side polished wafer to obtain a single crystal silicon wafer having a roughened surface formed on only one side; 2. A method for producing a single crystal silicon wafer, comprising:

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