Semiconductor memory device and method for initializing the same

Abstract

A semiconductor memory device and an initialization method thereof are provided that refresh initial data in memory cells during initialization and stabilize the charge amount of the memory cells. [Solution] A semiconductor memory device 100 includes a memory array, a refresh controller, and an initialization controller. The memory array has a plurality of equalization circuits and N memory cells. The plurality of equalization circuits are respectively connected to the N memory cells via a plurality of bit line pairs. The refresh controller sequentially refreshes initial data in the N memory cells in accordance with an auto-refresh command. The initialization controller performs an initialization operation in accordance with an initialization start command. During the initialization operation, the initialization controller enables the equalization circuit and periodically generates auto-refresh commands.

Description

[Technical Field]

[0001] The present invention relates to a memory operating method, and more particularly to a semiconductor memory device and an initialization method thereof. [Background technology]

[0002] When a dynamic random access memory (DRAM) is initialized at power-on, no turn-on voltage is applied to the word line, so the access transistors in the memory cells remain off. The charge stored in each memory cell may be unstable due to contact, static electricity, or other effects. This can slow the bit line voltage during sensing of the memory cell, resulting in slower sensing speeds, higher power consumption, and even potential sensing failures. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a semiconductor memory device and an initialization method thereof that can stabilize the charge amount (voltage) of a memory cell during initialization of the semiconductor memory device. [Means for solving the problem]

[0004] The semiconductor memory device of the present invention includes a memory array, a refresh controller, and an initialization controller. The memory array has a plurality of equalization circuits and N memory cells. The plurality of equalization circuits are respectively connected to the N memory cells via a plurality of bit line pairs, where N is a positive integer greater than 1. The refresh controller is connected to the memory array and configured to sequentially refresh initial data in the N memory cells in accordance with an auto-refresh command. The initialization controller is connected to the memory array and the refresh controller and configured to perform an initialization operation in accordance with an initialization start command. During the initialization operation, the initialization controller enables the equalization circuit and periodically generates auto-refresh commands.

[0005] A semiconductor memory device initialization method of the present invention is applied to a semiconductor memory device including the memory array described above, and includes the steps of: performing an initialization operation in accordance with an initialization start command; enabling an equalization circuit during the initialization operation and periodically generating an auto-refresh command; and refreshing initial data in N memory cells in accordance with the auto-refresh command. [Effects of the Invention]

[0006] The semiconductor memory device and the initialization method thereof according to the present invention can refresh initial data in memory cells during initialization, thereby stabilizing the charge of the memory cells, and can quickly stabilize the voltage of the bit line when a specified operation is subsequently performed, thereby improving sensing speed, reducing power consumption, and effectively avoiding sensing failures. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a schematic block diagram of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] 1 shows a schematic circuit diagram of a memory array according to one embodiment of the present invention; [Figure 3] FIG. 2 shows a schematic block diagram of an initialization controller according to an embodiment of the present invention. [Figure 4] 2 shows a flowchart of an initialization method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] 1, a semiconductor memory device 100 of the present invention includes a memory array 110, a refresh controller 120, and an initialization controller 130. The memory array 110 is an array configured of, for example, dynamic random access memories. As shown in FIG. 2, the memory array 110 includes equalization circuits 112_1 and 112_2, sense amplifier circuits 114_1 and 114_2, selection circuits 116_1 and 116_2, and N memory cells 118, where N is a positive integer greater than 1.

[0009] The equalization circuits 112_1 and 112_2 are connected to N memory cells 118 via bit line pairs BLP1 and BLP2, respectively. In particular, in FIG. 2, the bit line pair BLP1 is connected to a first bit line BLb <0> and the second bit line BLt <0> The bit line pair BLP2 includes the first bit line BLb <1> and the second bit line BLt <1> The equalization circuit 112_1 includes transistors M1_1 to M3_1. A first terminal of the transistor M1_1 is connected to the first bit line BLb <0> , a second terminal of the transistor M1_1 receives the equalization voltage VBLEQ, and a control terminal of the transistor M1_1 receives the equalization signal EQL. A first terminal of the transistor M2_1 is connected to the second terminal of the transistor M1_1, and a second terminal of the transistor M2_1 is connected to the second bit line BLt. <0> The control terminal of the transistor M2_1 receives the equalization signal EQL. The first terminal of the transistor M3_1 is connected to the first bit line BLb. <0> , and the second end of the transistor M3_1 is connected to the second bit line BLt <0> , and a control terminal of the transistor M3_1 receives an equalization signal EQL. The equalization circuit 112_2 includes transistors M1_2 to M3_2, the connection of which is similar to that of the transistors M1_1 to M3_1 of the equalization circuit 112_1. The transistors M1_1 to M3_1 and M1_2 to M3_2 may be realized by, for example, N-type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOSFETs).

[0010] Each of the equalization circuits 112_1 and 112_2 can receive an equalization signal EQL from the initialization controller 130. When the equalization signal EQL is converted to an enable level (e.g., a high logic level), the transistors M1_1 to M3_1 in the equalization circuit 112_1 and the transistors M1_2 to M3_2 in the equalization circuit 112_2 are turned on. In this way, the equalization circuit 112_1 uses the equalization voltage VBLEQ to turn on the first bit line BLb <0> The voltage of the second bit line BLt <0> The equalization circuit 112_2 can control the voltage of the first bit line BLb using the equalization voltage VBLEQ. <1> The voltage of the second bit line BLt <1> The voltage can be controlled to match that of the

[0011] Similarly, the sense amplifier circuits 114_1 and 114_2 are connected to N memory cells 118 via bit line pairs BLP1 and BLP2, respectively. The sense amplifier circuit 114_1 includes transistors M4_1 to M7_1. A first terminal of the transistor M4_1 receives a first sensing control voltage NCS, and a second terminal of the transistor M4_1 is connected to a first bit line BLb. <0> , and the control terminal of the transistor M4_1 is connected to the second bit line BLt <0> The first terminal of the transistor M5_1 is connected to the first bit line BLb. <0> , and the second terminal of the transistor M5_1 receives a second sensing control voltage PCS, and the control terminal of the transistor M5_1 is connected to the second bit line BLt <0> A first terminal of the transistor M6_1 receives the first sensing control voltage NCS, and a second terminal of the transistor M6_1 is connected to the second bit line BLt. <0> , and the control terminal of the transistor M6_1 is connected to the first bit line BLb <0> The first terminal of the transistor M7_1 is connected to the second bit line BLt <0> , and the second end of the transistor M7_1 receives the second sensing control voltage PCS, and the control terminal of the transistor M7_1 is connected to the first bit line BLb <0> The sense amplifier circuit 114_2 includes transistors M4_2 to M7_2, and the connection method thereof is similar to that of the transistors M4_1 to M7_1 of the sense amplifier circuit 114_1. The transistors M4_1, M6_1, M4_2, and M6_2 may be realized, for example, by N-type metal-oxide-semiconductor field-effect transistors, and the transistors M5_1, M7_1, M5_2, and M7_2 may be realized, for example, by P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs).

[0012] When the sense amplifier circuits 114_1 and 14_2 sense N memory cells 118, the first sensing control voltage NCS is set to a voltage of logic 0 (e.g., low logic level), and the second sensing control voltage PCS is set to a voltage of logic 1. In this manner, the sense amplifier circuits 114_1 and 14_2 can use the first sensing control voltage NCS and the second sensing control voltage PCS to stabilize the voltages of the bit line pairs BLP1 and BLP2, respectively.

[0013] The selection circuit 116_1 is connected between the bit line pair BLP1 and the data line pair DLP1. Specifically, the data line pair DLP1 is connected to the first data line DQb <0> and the second data line DQt <0> The selection circuit 116_1 includes transistors M8_1 and M9_1. A first terminal of the transistor M8_1 is connected to the first bit line BLb <0> , and the second end of the transistor M8_1 is connected to the first data line DQb <0> The control terminal of the transistor M8_1 receives the row selection signal CSL. The first terminal of the transistor M9_1 is connected to the second bit line BLt. <0> , and the second end of the transistor M9_1 is connected to the second data line DQt <0> , and the control terminal of the transistor M9_1 receives a row selection signal CSL. When the memory cell 118 connected to the bit line pair BLP1 is selected to perform a specified operation (e.g., a write operation or a read operation), the row selection signal CSL turns on the transistors M8_1 and M9_1 to make the transmission path between the bit line pair BLP1 and the data line pair DLP1 conductive. The transistors M8_1 and M9_1 may be realized, for example, by N-type metal oxide semiconductor field effect transistors.

[0014] The selection circuit 116_2 is connected between the bit line pair BLP2 and the data line pair DLP2. The data line pair DLP2 is connected to the first data line DQb <1> and the second data line DQt <1> The selection circuit 116_2 includes transistors M8_2 and M9_2. A first terminal of the transistor M8_2 is connected to the first bit line BLb <1> , and the second end of the transistor M8_2 is connected to the first data line DQb <1> The control terminal of the transistor M8_2 receives the row selection signal CSL. The first terminal of the transistor M9_2 is connected to the second bit line BLt <1> , and the second end of the transistor M9_2 is connected to the second data line DQt <1> , and the control terminal of the transistor M9_2 receives a row selection signal CSL. When the memory cell 118 connected to the bit line pair BLP2 is selected to perform a specified operation, the row selection signal CSL turns on the transistors M8_2 and M9_2, making the transmission path between the bit line pair BLP2 and the data line pair DLP2 conductive. The transistors M8_2 and M9_2 may be realized, for example, by N-type metal oxide semiconductor field effect transistors.

[0015] Returning to FIG. 1 , the refresh controller 120 is connected to the memory array 110. The refresh controller 120 is configured to sequentially refresh the initial data IData of N memory cells 118 in the memory array 110 in accordance with an auto-refresh command IC_AR. The initialization controller 130 is connected to the memory array 110 and the refresh controller 120. The initialization controller 130 is configured to output an initialization signal STM to the memory array 110 to start an initialization operation in accordance with an initialization start command Init_on. The initialization start command Init_on is a command output by the memory controller, for example, when the semiconductor memory device 100 is started, indicating that initialization is to be performed. The initial data IData is, for example, data indicating a logic 0, and the voltage of the memory cell 118 storing the initial data IData is, for example, a ground voltage (e.g., 0 volts). An advantage of this configuration is that when a memory cell 118 is subsequently selected and a specified operation is performed, the turn-on voltage Von applied to the corresponding word line WL does not need to be very high (theoretically, it only needs to be greater than the threshold voltage of the access transistor MA), thereby improving operational convenience.

[0016] During the initialization operation, the initialization controller 130 enables the equalization circuits 112_1, 112_2 in the memory array 110 and disables the sense amplifier circuits 114_1, 114_2 in the memory array 110, while periodically generating a refresh command IC_AR.

[0017] The initialization signal STM output by the initialization controller 130 includes at least an equalization signal EQL and an equalization voltage VBLEQ used by each equalization circuit 112_1, 112_2, a first sensing control voltage NCS and a second sensing control voltage PCS used by each sense amplifier circuit 114_1, 114_2, and a turn-on voltage Von for turning on the access transistor MA in the memory cell 118. During the initialization operation, the initialization controller 130 maintains the equalization signal EQL at an enable level and sets the equalization voltage VBLEQ to be equal to the ground voltage, thereby enabling the equalization circuits 112_1, 112_2.

[0018] During the initialization operation, the initialization controller 130 also sets the first sensing control voltage NCS and the second sensing control voltage PCS to be equal to the ground voltage, thereby disabling the sense amplifier circuits 114_1 and 114_2 and avoiding leakage current.

[0019] During the initialization operation, the initialization controller 130 sets an initial value of K to 1. Every time the initialization controller 130 generates an auto-refresh command IC_AR, the initialization controller 130 simultaneously turns on multiple access transistors MA in the Kth to K+Jth memory cells among the N memory cells 118, and then increases K by J+1 (K=K+J+1) until K becomes greater than N or the initialization controller 130 receives an initialization end command Init_done. J is a positive integer greater than or equal to 1. Furthermore, the refresh controller 120 may operate in cooperation with the initialization controller 130. Every time the refresh controller 120 receives an auto-refresh command IC_AR generated by the initialization controller 130, the refresh controller 120 can refresh the initial data IData from the Kth to K+Jth memory cells among the N memory cells 118.

[0020] Assuming J is equal to 3, when the auto-refresh command IC_AR is generated for the first time (K is equal to 1), the initialization controller 130 provides a turn-on voltage Von to the word lines WL corresponding to the first to fourth memory cells 118 to be refreshed, thereby simultaneously turning on the access transistors MA in the first to fourth memory cells 118, and then increases K to 5. Furthermore, upon receiving the auto-refresh command IC_AR this time, the refresh controller 120 can simultaneously refresh the initial data IData to the first to fourth memory cells 118. When the auto-refresh command IC_AR is generated for the second time (K is equal to 5), the initialization controller 130 provides a turn-on voltage Von to the word lines WL corresponding to the fifth to eighth memory cells 118 to be refreshed, thereby simultaneously turning on the access transistors MA in the fifth to eighth memory cells 118, and then increases K to 9. Furthermore, the refresh controller 120, which has now received the auto-refresh command IC_AR, can simultaneously refresh the initial data IData in the fifth through eighth memory cells 118. This process continues until K accumulates to a value greater than N (indicating that all access transistors MA in the memory cells 118 have been turned on) or until the initialization controller 130 receives an initialization end command Init_done. The initialization end command Init_done is, for example, a command output by the memory controller indicating the end of initialization.

[0021] In this embodiment, the value of J may correspond to the number of memory cells 118 that are simultaneously refreshed. Those skilled in the art can appropriately adjust the value of J according to actual needs and with reference to the teachings of this embodiment.

[0022] Through the above operations, when the semiconductor memory device is initialized, the charge amounts of all memory cells can be stabilized as much as possible. In this way, even when the memory cells are sensed for the first time after the initialization is completed, unstable factors due to connection, static electricity, or other effects can be eliminated, and the voltage of the bit line can be quickly stabilized, improving the sensing speed, reducing power consumption, and effectively preventing sensing failures.

[0023] The internal structure of the initialization controller 130 will be described below as an example. Referring to Fig. 3, the initialization controller 130 includes a voltage dividing and oscillating circuit 132, a counting and controlling circuit 134, a signal generating circuit 136, and a refresh counter circuit 138. The voltage dividing and oscillating circuit 132 is configured to receive an initialization start command Init_on, and is activated in response to the initialization start command Init_on to generate a clock signal CLK. Upon receiving the initialization start command Init_on, the voltage dividing and oscillating circuit 132 starts generating the clock signal CLK at a predetermined cycle.

[0024] The counting and control circuit 134 is connected to the voltage dividing and oscillation circuit 132. The counting and control circuit 134 is configured to receive an initialization start command Init_on and a clock signal CLK. The counting and control circuit 134 can output a refresh start command IC_on in response to the initialization start command Init_on. Upon receiving the initialization start command Init_on, the counting and control circuit 134 outputs the refresh start command IC_on to the signal generating circuit 136.

[0025] The counter and control circuit 134 may count the clock signal CLK to accumulate a first count value. Each time the first count value accumulates to a first predetermined number of times, the counter and control circuit 134 may reset the first count value to zero and output an auto-refresh command IC_AR to the refresh controller 120 and the signal generation circuit 136. The magnitude of the first predetermined number of times may be determined by a delay time required for the refresh controller 120 to refresh the initial data IData from the Kth memory cell to the (K+J)th memory cell among the N memory cells 118.

[0026] The signal generation circuit 136 is connected to the counting and control circuit 134. The signal generation circuit 136 is configured to receive a refresh start command IC_on and an auto-refresh command IC_AR. The signal generation circuit 136 can provide an initialization signal STM to the memory array 110 in accordance with the refresh start command IC_on and the auto-refresh command IC_AR. Specifically, upon receiving the refresh start command IC_on, the signal generation circuit 136 can provide an enable level equalization signal EQL and an equalization voltage VBLEQ set to be equal to the ground voltage to the equalization circuits 112_1 and 112_2 in the memory array 110, and can provide a first sensing control voltage NCS and a second sensing control voltage PCS set to be equal to the ground voltage to the sense amplifier circuits 114_1 and 114_2 in the memory array 110. Furthermore, whenever the auto-refresh command IC_AR is received, the signal generation circuit 136 can provide a turn-on voltage Von to the word line WL corresponding to the memory cell 118 to be refreshed.

[0027] The refresh counter circuit 138 is connected to the voltage divider and oscillator circuit 132 and the counting and control circuit 134. The refresh counter circuit 138 is configured to receive a clock signal CLK. The refresh counter circuit 138 counts the clock signal CLK to accumulate a second count value. When the second count value has accumulated to a second predetermined number of times, it indicates that all memory cells 118 in the display memory array 110 have been refreshed. At this time, the refresh counter circuit 138 can output a refresh end command IC_done to the counting and control circuit 134. The magnitude of the second predetermined number of times can be determined by the delay time required to refresh all memory cells 118 in the memory array 110.

[0028] When the counting and control circuit 134 receives the refresh end command IC_done, the counting and control circuit 134 can stop outputting the auto-refresh command IC_AR in response to the refresh end command IC_done. In this way, the refresh controller 120 stops refreshing the initial data IData to the memory cells 118 in the memory array 110, and ends the initialization operation.

[0029] When the refresh counter circuit 138 receives the initialization end command Init_done, it outputs a refresh end command IC_done to the counting and control circuit 134. In this way, even if there are memory cells 118 in the memory array 110 that have not been refreshed, the initialization operation can be immediately ended depending on the situation, and any disruption to the startup process of the semiconductor memory device 100 can be avoided.

[0030] The refresh controller 120 and the initialization controller 130 may be realized by digital circuits, and the related hardware architecture is not particularly limited and can be generated by digital circuit design methods known to those skilled in the art.

[0031] 4, the initialization method for a semiconductor memory device includes the following steps: 1. Perform an initialization operation in accordance with an initialization start command (step S400). 2. During the initialization operation, enable an equalization circuit and periodically generate an auto-refresh command (step S402). 3. Sequentially refresh the initial data in N memory cells in accordance with the auto-refresh command (step S404). 4. Details of the implementation of steps S400 to S404 can be explained with reference to the embodiments of FIGS. 1 to 3, and will not be described in detail here.

[0032] In summary, during the initialization operation, the equalization voltage used by the equalization circuit and the sensing control voltage used by the sense amplifier circuit are adjusted to refresh the initial data in the memory cells, thereby stabilizing the charge amount of the memory cells. When a specified operation is subsequently performed, unstable factors caused by contact, static electricity, or other effects can be eliminated, and the voltage of the bit line can be quickly stabilized, thereby improving the sensing speed, reducing power consumption, and effectively avoiding sensing failures. [Industrial Applicability]

[0033] The semiconductor memory device and the initialization method thereof according to the present invention can be applied to perform initialization operations of a memory. [Explanation of symbols]

[0034] 100: Semiconductor memory device 110: Memory array 112_1, 112_2: Equalization circuit 114_1, 114_2: Sense amplifier circuit 116_1, 116_2: Selection circuit 118: Memory cell 120: Refresh controller 130: Initialization controller 132: Voltage divider and oscillator circuit 134: Counting and control circuit 136: Signal generation circuit 138: Refresh counter circuit BLP1, BLP2: bit line pair BLb <0> , BLb <1> : 1st bit line BLt <0> , BLt <1> : Second bit line CLK: Clock signal CSL: Row selection signal DLP1, DLP2: Data line pair DQb <0> , DQb <1> : First data line DQt <0> , DQt <1> : Second data line EQL: Equalization signal IC_AR: Automatic refresh command IC_done, IC_on: Refresh end command, refresh start command IData: Initial data Init_done, Init_on: Initialization end command, initialization start command M1_1 to M9_1, M1_2 to M9_2: transistors MA: Access transistor NCS, PCS: 1st sensing control voltage, 2nd sensing control voltage STM: Initialization signal VBLEQ: Equalization voltage Von: Turn-on voltage WL: Word line Process: S400~S404

Claims

1. a memory array having a plurality of equalization circuits and N memory cells, wherein the plurality of equalization circuits are respectively connected to the N memory cells via a plurality of bit line pairs, where N is a positive integer greater than 1; a refresh controller connected to the memory array for sequentially refreshing initial data in the N memory cells in accordance with an automatic refresh command; an initialization controller connected to the memory array and the refresh controller, configured to perform an initialization operation according to an initialization start command; Equipped with During the initialization operation, the initialization controller enables the plurality of equalization circuits and periodically generates the auto-refresh command; the memory array further comprises a plurality of sense amplifier circuits, each of which is connected to the N memory cells via the plurality of bit line pairs; When the plurality of sense amplifier circuits sense the N memory cells, each of the plurality of sense amplifier circuits uses a first sensing control voltage and a second sensing control voltage to stabilize the voltage of the corresponding bit line pair; During the initialization operation, the initialization controller sets the first sensing control voltage and the second sensing control voltage to be equal to a ground voltage. Semiconductor memory device.

2. During the initialization operation, the initialization controller sets an initial value of K to 1, and each time the automatic refresh command is generated, the initialization controller simultaneously turns on multiple access transistors in the Kth memory cell to the K+Jth memory cell among the N memory cells, and then increases K by J+1, where J is a positive integer greater than or equal to 1, until K is greater than N or the initialization controller receives an initialization end command.

2. The semiconductor memory device according to claim 1.

3. Each time the automatic refresh command is received, the refresh controller refreshes the initial data from the Kth memory cell to the K+Jth memory cell among the N memory cells.

3. The semiconductor memory device according to claim 2.

4. each of the plurality of bit line pairs includes a first bit line and a second bit line, and each of the plurality of equalization circuits receives an equalization signal from the initialization controller, and when the equalization signal is converted to an enable level, each of the plurality of equalization circuits controls a voltage of the corresponding first bit line and a voltage of the corresponding second bit line using an equalization voltage; 2. The semiconductor memory device according to claim 1.

5. The method of claim 1, wherein the initialization controller disables the plurality of sense amplifier circuits during the initialization operation.

2. The semiconductor memory device according to claim 1.

6. The initialization controller: a voltage divider and oscillator circuit configured to receive the initialization start command, activate in response to the initialization start command, and generate a clock signal; a counting and control circuit connected to the voltage dividing and oscillating circuit, configured to receive the initialization start command and the clock signal, to output a refresh start command in response to the initialization start command, to count the clock signal to accumulate a first count value, to reset the first count value to zero each time the first count accumulates to a first predetermined number of times, and to output the auto-refresh command; a signal generating circuit connected to the counter and control circuit, configured to receive the refresh start command and the auto-refresh command, provide an equalization signal and an equalization voltage used by each of the plurality of equalization circuits and the first sensing control voltage and the second sensing control voltage used by each of the plurality of sense amplifier circuits during the initialization operation period in accordance with the refresh start command, and provide turn-on voltages to a plurality of word lines corresponding to the plurality of memory cells to be refreshed in accordance with the auto-refresh command; 6. The semiconductor memory device according to claim 5, comprising:

7. The initialization controller: a refresh counter circuit connected to the voltage dividing and oscillating circuit and the counting and control circuit, configured to receive the clock signal, count the clock signal to accumulate a second count value, and output a refresh end command to the counting and control circuit when the second count value reaches a second predetermined number of times; further comprising the counting and control circuit stops outputting the automatic refresh command in response to the refresh end command; 7. The semiconductor memory device according to claim 6.

8. 1. A method for initializing a semiconductor memory device including a memory array having a plurality of equalization circuits, N memory cells, and a plurality of sense amplifier circuits, wherein N is a positive integer greater than 1, performing an initialization operation in accordance with an initialization start command; during the initialization operation, enabling the plurality of equalization circuits and periodically generating an auto-refresh command; sequentially refreshing the initial data in the N memory cells according to an automatic refresh command; Including, The plurality of sense amplifier circuits are respectively connected to the N memory cells via a plurality of bit line pairs, and when the plurality of sense amplifier circuits sense the N memory cells, each of the plurality of sense amplifier circuits uses a first sensing control voltage and a second sensing control voltage to stabilize the voltage of the corresponding bit line pair; The initialization method includes: During the initialization operation, setting the first sensing control voltage and the second sensing control voltage to be equal to a ground voltage; The method for initializing a semiconductor memory device further includes:

9. During the initialization operation, setting an initial value of K to 1; Each time the automatic refresh command is generated, simultaneously turn on a plurality of access transistors in a Kth memory cell to a K+Jth memory cell among the N memory cells, and then increase K by J+1 until K is greater than N or an initialization end command is received, where J is a positive integer greater than or equal to 1; The initialization method of claim 8 further comprising:

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