Indication device

Abstract

SOLUTION: A display device includes: a substrate including a display region, an optical region including a through hole and arranged within the display region, and a non-display region surrounding the display region; a plurality of insulator layers arranged on a substrate; at least one dam arranged on the plurality of insulator layers; and at least one connection prevention part arranged on at least one insulator layer and closer to the through hole than at least one dam. A first trench is arranged in a part of the plurality of insulator layers which overlap at least one connection prevention part in the optical region.EFFECT: It is possible to prevent propagation of a crack generated by external interference in an optical region.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device that can block crack propagation paths in an area where a camera or sensor is placed. [Background technology]

[0002] With the advent of the information age, the field of display devices that visually display electrical information signals has been developing rapidly, and research is ongoing to develop various display devices with improved performance, such as thinner, lighter, and lower power consumption.

[0003] Representative display devices include liquid crystal displays (LCDs), field emission displays (FEDs), electro-wetting displays (EWDs), and organic light emitting displays (OLEDs).

[0004] Electroluminescent displays (ELDs), typified by organic light-emitting displays (OLEDs), are self-emitting displays that, unlike LCDs, do not require a separate light source and can be manufactured in a lightweight and thin form. Furthermore, ELDs are advantageous in terms of power consumption due to their low voltage operation, and also have excellent color realization, response speed, viewing angle, and contrast ratio (CR), making them expected to be used in a variety of fields. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can prevent cracks generated by external interference from propagating in an area where a camera or sensor is disposed.

[0006] Another object of the present invention is to provide a display device that can ensure product yield and reliability.

[0007] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment of the present specification includes a substrate including a display area, an optical area disposed within the display area and including a through hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and closer to the through hole than the at least one dam, and a first trench is disposed in a portion of the plurality of insulating layers overlapping with the at least one connection prevention portion in the optical area.

[0009] Further details of the embodiments are included in the detailed description and drawings.

[0010] A display device according to an embodiment of the present disclosure may prevent moisture and oxygen from penetrating through the through-holes by forming a plurality of connection prevention portions around the through-holes. The prevention portions may cut off connections between organic common layers, i.e., light-emitting layers, of light-emitting elements disposed on the front surface of the display panel, thereby blocking the movement of moisture and oxygen.

[0011] In an embodiment of the present disclosure, a display device may include a plurality of dams disposed near a plurality of connection prevention portions to prevent an organic insulating layer of the encapsulation layer from overflowing into the camera hole, and the dams may prevent contamination of the camera hole area and interference with a camera disposed in the through hole, which may occur when the organic insulating layer overflows into the camera hole.

[0012] In one embodiment of the present specification, a display device has a trench formed by etching a portion of a plurality of inorganic insulating layers that overlap a plurality of connection prevention portions, so that even if a crack occurs in a through hole, the path along which the crack propagates is blocked, thereby preventing the crack from propagating.

[0013] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present specification. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 3] FIG. 2 is an enlarged plan view of region A in FIG. [Figure 4] FIG. 4 is an enlarged plan view of region B in FIG. 3. [Figure 5] FIG. 5 is a cross-sectional view taken along the line VV′ of FIG. 4. [Figure 6a] FIG. 6 is an enlarged cross-sectional view of region C in FIG. 5 according to one embodiment of the present specification. [Figure 6b] FIG. 10 is a cross-sectional view of a display device according to another embodiment of the present specification. [Figure 6c] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 6d] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 6e] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 7a] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 7b] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 7c] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 7d] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. DETAILED DESCRIPTION OF THE INVENTION

[0015] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The present embodiment is provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the embodiments of the present invention to those skilled in the art.

[0016] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are merely illustrative and should not be construed as limiting the scope of the embodiments of this specification. The same reference symbols refer to the same elements throughout the specification. Furthermore, when describing an embodiment of this specification, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of the embodiment of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0017] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0018] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0019] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0020] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0021] Like reference numbers refer to like elements throughout the specification.

[0022] The area and thickness of each structure shown in the drawings are shown for convenience of explanation, and an embodiment of this specification is not necessarily limited to the area and thickness of the structure shown.

[0023] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0024] An embodiment of the present specification will be described below with reference to the drawings.

[0025] FIG. 1 is a block diagram of a display device according to an embodiment of the present specification.

[0026] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include an image processor 151, a timing controller 152, a data driver 153, a gate driver 154, and a display panel DP.

[0027] At this time, the image processor 151 can output an externally supplied data signal DATA, a data enable signal DE, etc. In addition to the data enable signal DE, the image processor 151 can output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0028] The timing controller 152 receives a data signal DATA together with a data enable signal DE or drive signals including a vertical sync signal, a horizontal sync signal, a clock signal, etc. from the image processor 151. The timing controller 152 can output a gate timing control signal GDC for controlling the operation timing of the gate driver 154 and a data timing control signal DDC for controlling the operation timing of the data driver 153 based on the drive signals.

[0029] In addition, the data driver 153 can sample and latch the data signal DATA supplied from the timing controller 152 in response to the data timing control signal DDC supplied from the timing controller 152, convert it into a gamma reference voltage, and output it. The data driver 153 can output the data signal DATA through the data lines DL1 to DLn.

[0030] Furthermore, the gate driver 154 can output gate signals while shifting the level of the gate voltage in response to a gate timing control signal GDC supplied from the timing controller 152. The gate driver 154 can output gate signals through the gate lines GL1 to GLm.

[0031] The display panel DP can display an image by causing the pixels P to emit light in response to the data signal DATA and the gate signal supplied from the data driver 153 and the gate driver 154. The detailed structure of the pixel P will be described in detail with reference to FIG.

[0032] The display panel DP can include a display area DA, an optical area OA disposed within the display area DA and including through-holes TH, and a non-display area NDA surrounding the display area DA.

[0033] The display area DA is an area where an image is displayed on the display panel DP.

[0034] A number of pixels P and circuits for driving the pixels P may be arranged in the display area DA. The pixels P are the smallest units constituting the display area DA, and a display element may be arranged in each of the pixels P. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode may be arranged in each of the pixels P, but this is not limited thereto. In addition, the circuit for driving the pixels P may include driving elements and wiring, etc. For example, the circuit may include, but is not limited to, a thin film transistor, a storage capacitor, a gate wiring, a data wiring, etc.

[0035] The optical area OA is disposed within the display area DA and is an area where the through-holes TH are disposed. The display panel DP has the through-holes TH disposed within the display area DA, which can reduce the bezel area, which is the non-display area (NDA), and maximize the display area DA. Products designed to maximize the display area DA can maximize the user's immersive experience and be more aesthetically pleasing.

[0036] The through-holes TH may be formed to correspond to optical electronic devices such as cameras or optical sensors.

[0037] 1, the number of through-holes TH may be two, but is not limited thereto and may be variously arranged. For example, one or two holes may be arranged within the display area DA, with a camera arranged in the first hole and a distance sensor or a face recognition sensor and a wide-angle camera arranged in the second hole.

[0038] The non-display area NDA is an area where no video is displayed.

[0039] The non-display area NDA may be bent so that it cannot be seen from the front or may be hidden by a case (not shown), and is also called a bezel area.

[0040] 1, the non-display area NDA is shown surrounding the rectangular display area DA, but the shapes and arrangements of the display area DA and the non-display area NDA are not limited to the example shown in Fig. 1. That is, the display area DA and the non-display area NDA may have shapes suitable for the design of an electronic device incorporating the display device 100. For example, exemplary shapes of the display area DA may be pentagonal, hexagonal, circular, elliptical, etc.

[0041] Various wirings and circuits for driving the organic light emitting elements in the display area DA may be arranged in the non-display area NDA, such as link wirings for transmitting signals to a number of sub-pixels and circuits in the display area DA, GIP (Gate-In-Panel) wirings, or driving ICs such as the gate driver 154 and the data driver 153, but are not limited thereto.

[0042] The display device 100 may further include various additional components for generating various signals or driving pixels in the display area DA. Additional components for driving pixels may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, etc. The display device 100 may also include additional components associated with functions other than driving pixels. For example, the display device 100 may further include additional components providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, etc. The aforementioned additional components may be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0043] In the following, reference will be made to FIG. 2 for a more detailed description of the cross-sectional structure of the display area DA of the display device 100.

[0044] FIG. 2 is a cross-sectional view showing the cross-sectional structure of one pixel arranged in a display region according to an embodiment of the present specification.

[0045] The display device 100 according to an embodiment of the present specification may include a substrate 110, a first buffer layer 111, a first thin film transistor TR1, a second thin film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connecting electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, a spacer 116b, an anode 121, a light-emitting layer 122, a cathode 123, an encapsulation layer 117, and a touch sensing unit.

[0046] The substrate 110 serves to support and protect the components of the flexible display device disposed thereon.

[0047] The substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. By configuring the substrate 110 with the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c in this manner, moisture penetration can be prevented. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may be a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0048] A light blocking layer 125 may be disposed on the substrate 110 .

[0049] A first buffer layer 111 may be disposed on the substrate 110, covering the light-shielding layer 125. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110, covering the light-shielding layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0050] The multi-buffer layer 111a can delay the diffusion of moisture or oxygen that has penetrated into the substrate 110, and can include at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0051] The active buffer layer 111b can protect the first active layer A1 and block various types of defects from entering from the substrate 110. For example, the active buffer layer 111b can include at least one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0052] The first thin film transistor TR1 may be disposed on the first buffer layer 111. The first thin film transistor TR1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Here, according to the design of the pixel circuit, the first source electrode S1 may be the first drain electrode, and the first drain electrode D1 may be the first source electrode.

[0053] The first active layer A1 may be disposed on the first buffer layer 111 so as to overlap the light-shielding layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low-temperature polysilicon (LTPS). For example, polysilicon material has high mobility (100 cm 2 / Vs or more), low energy consumption, and excellent reliability, the thin film transistor (TR1) may be applied to a gate driver and / or a multiplexer (MUX) for a driving element that drives a thin film transistor for a display element, and may be applied to the first active layer A1 of the driving thin film transistor in the display device 100 according to an embodiment of the present disclosure, but is not limited thereto. For example, the thin film transistor (TR1) may also be applied to the second active layer A2 of the switching thin film transistor depending on the characteristics of the display device 100. The first active layer A1 may be formed by depositing an amorphous silicon (a-Si) material on the first buffer layer 111 and performing a dehydrogenation process and a crystallization process to form polysilicon, and then patterning the polysilicon. Here, the first active layer A1 may include a first channel region in which a channel is formed when the first thin film transistor TR1 is operated, and first source and drain regions on both sides of the first channel region. The first source region refers to a portion of the first active layer A1 connected to the first source electrode S1, and the first drain region refers to a portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region may be formed by ion doping (impurity doping) the first active layer A1. The first source region and the first drain region may be formed by ion doping a polysilicon material, and the first channel region may refer to the remaining portion of the polysilicon material that is not ion doped.

[0054] A first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. Contact holes may be formed in the first gate insulating layer 112a to connect the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 to the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1, respectively.

[0055] A first gate electrode G1 of the first thin film transistor TR1 and a first capacitor electrode C1 of the storage capacitor Cst may be disposed on the first gate insulating layer 112a.

[0056] In this case, the first gate electrode G1 and the first capacitor electrode C1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode G1 may be formed on the first gate insulating layer 112a to overlap with the first channel region of the first active layer A1 of the first thin film transistor TR1.

[0057] The first capacitor electrode C1 may be omitted depending on the driving characteristics of the display device 100 and the structure and type of the thin film transistor. The first gate electrode G1 and the first capacitor electrode C1 may be formed by the same process. The first gate electrode G1 and the first capacitor electrode C1 may be formed of the same material and on the same layer.

[0058] A first interlayer insulating layer 113a may be disposed on the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the first interlayer insulating layer 113a to expose a first source region and a first drain region of the first active layer A1 of the first thin film transistor TR1.

[0059] A second capacitor electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 may be formed on the first interlayer insulating layer 113a to overlap the first capacitor electrode C1. The second capacitor electrode C2 may be formed of the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted depending on the driving characteristics of the display device 100 and the structure and type of the thin film transistor.

[0060] A second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. Contact holes may be formed in the second buffer layer 114 to expose the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1. In addition, a contact hole may be formed in the second buffer layer 114 to expose the second capacitor electrode C2 of the storage capacitor Cst.

[0061] The second buffer layer 114 may be formed as a multi-layer structure, but is not limited thereto.

[0062] A second active layer A2 of a second thin film transistor TR2 may be disposed on the second buffer layer 114. Here, the second thin film transistor TR2 may include the second active layer A2, a second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. Here, according to the design of the pixel circuit, the second source electrode S2 may be the drain electrode, and the second drain electrode D2 may be the source electrode.

[0063] The second active layer A2 may include a second channel region where a channel is formed when the second thin film transistor TR2 is driven, and a second source region and a second drain region on both sides of the second channel region. The second source region may refer to a portion of the second active layer A2 connected to the second source electrode S2, and the second drain region may refer to a portion of the second active layer A2 connected to the second drain electrode D2.

[0064] The second active layer A2 may be made of an oxide semiconductor. Oxide semiconductor materials have a larger bandgap than silicon materials, preventing electrons from crossing the bandgap in the off state, resulting in a low off-current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor may be suitable for, but not limited to, a switching thin film transistor, which maintains a short on-time and a long off-time. Depending on the characteristics of the display device 100, it may also be used as a driving thin film transistor. Furthermore, since the off-current is small, the storage capacitance can be reduced, making it suitable for high-resolution display devices. For example, the second active layer A2 may be made of a metal oxide, such as indium-gallium-zinc-oxide (IGZO). Here, the second active layer A2 of the second thin film transistor TR2 has been described assuming that it is made of IGZO among various metal oxides, but is not limited thereto and may be made of other metal oxides such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide).

[0065] The second active layer A2 may be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0066] The second gate insulating layer 112b may be disposed over the entire substrate 110, including the second active layer A2. For example, the second gate insulating layer 112b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof.

[0067] A second gate electrode G2 may be disposed on the second gate insulating layer 112b.

[0068] The second gate electrode G2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0069] For example, a metal material may be formed on the second gate insulating layer 112b, a photoresist pattern may be formed on the metal material, and the metal material may be wet-etched using the photoresist pattern as a mask to form the second gate electrode G2. The wet etching solution for etching the metal material may be a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or alloys thereof, but does not etch insulating materials.

[0070] A second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate electrode G2. Contact holes may be formed in the second interlayer insulating layer 113b to expose the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2. For example, contact holes may be formed in the second interlayer insulating layer 113b to expose the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1. Contact holes may be formed in the second interlayer insulating layer 113b to expose the second source region and the second drain region of the second active layer A2 of the second thin film transistor TR2.

[0071] The second interlayer insulating layer 113b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of these.

[0072] A connecting electrode CE, a first source electrode S1 and a first drain electrode D1 of the first thin film transistor TR1, and a second source electrode S2 and a second drain electrode D2 of the second thin film transistor TR2 may be disposed on the second interlayer insulating layer 113b.

[0073] The connecting electrode CE may be electrically connected to the second drain electrode D2 of the second thin film transistor TR2. The connecting electrode CE may also be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through a contact hole formed in the second buffer layer 114 and the second interlayer insulating layer 113b. That is, the connecting electrode CE may serve to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin film transistor TR2.

[0074] Here, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 can be connected to the first active layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0075] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be connected to the second active layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0076] The connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be formed using the same material by the same process.

[0077] For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin film transistor TR2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin film transistor TR2 may be formed as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0078] The connecting electrode CE may be integrally formed with the second drain electrode D2 of the second thin film transistor TR2, but is not limited thereto.

[0079] A first planarization layer 115a may be disposed on the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0080] The first planarization layer 115a may be an organic layer for planarizing and protecting the tops of the first thin film transistor TR1 and the second thin film transistor TR2, and may be formed of, for example, an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0081] An auxiliary electrode 145 may be disposed on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin film transistor TR2 through a contact hole in the first planarization layer 115a. The auxiliary electrode 145 may serve to electrically connect the second thin film transistor TR2 to the anode 121. The auxiliary electrode 145 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode 145 may be formed of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0082] The second planarization layer 115b may be disposed on the auxiliary electrode 145 and the first planarization layer 115a. For example, the second planarization layer 115b may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0083] The light emitting element 120 may be disposed on the second planarization layer 115b.

[0084] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 through a contact hole provided in the second planarization layer 115b. The anode 121 may be formed of a metallic material.

[0085] When the display device 100 is a top emission type in which light emitted from the light emitting element 120 is emitted above the substrate 110 on which the light emitting element 120 is disposed, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0086] A bank 116a may be disposed to cover the anode 121. A portion of the bank 116a corresponding to a light-emitting region of a sub-pixel may be open. A portion of the anode 121 may be exposed in the open portion of the bank 116a (hereinafter referred to as the open region). In this case, the bank 116a may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene-based resin, an acrylic-based resin, or an imide-based resin, but is not limited thereto. A spacer 116b may be further disposed on the bank 116a.

[0087] The light-emitting layer 122 can be disposed in and around the open areas of the bank 116a, thereby disposing the light-emitting layer 122 on the anode 121 exposed through the open areas of the bank 116a.

[0088] A cathode 123 may be disposed on the light-emitting layer 122 .

[0089] The anode 121, the light-emitting layer 122, and the cathode 123 may form a light-emitting element 120. The light-emitting layer 122 may include multiple organic films.

[0090] An encapsulation layer 117 may be positioned over the light emitting element 120 described above.

[0091] The sealing layer 117 may have a single-layer structure or a multi-layer structure. For example, the sealing layer 117 may include a first sealing layer 117a, a second sealing layer 117b, and a third sealing layer 117c.

[0092] In this case, the first encapsulating layer 117a and the third encapsulating layer 117c may be made of an inorganic film, and the second encapsulating layer 117b may be made of an organic film. Among the first encapsulating layer 117a, the second encapsulating layer 117b, and the third encapsulating layer 117c, the second encapsulating layer 117b is the thickest and can serve as a planarizing layer.

[0093] The first encapsulating layer 117a may be disposed on the cathode 123 and may be disposed closest to the light emitting element 120. The first encapsulating layer 117a may be formed of an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulating layer 117a may be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Because the first encapsulating layer 117a is deposited in a low-temperature atmosphere, it is possible to prevent damage to the light emitting layer 122, which includes organic materials that are vulnerable to high-temperature atmospheres, during the deposition process.

[0094] The second encapsulation layer 117b may be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer to relieve stress between layers due to warping of the flexible display device and to enhance planarization performance.

[0095] For example, the second sealing layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbonate (SiOC), etc. For example, the second sealing layer 117b may be formed using an inkjet method, but is not limited thereto.

[0096] The third encapsulation layer 117c may be formed on the substrate 110 on which the second encapsulation layer 117b is formed, to cover the top and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. In this case, the third encapsulation layer 117c may minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0097] A touch sensitive layer may be disposed on the encapsulation layer 117.

[0098] For example, the touch buffer layer 118a may be disposed on the third sealing layer 117c, and the touch electrode TE may be disposed on the touch buffer layer 118a.

[0099] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM located in different layers, and an inter-touch insulating layer 118b may be disposed between the touch sensor metal TS and the bridge metal BM.

[0100] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be disposed to eliminate a step at the point where the touch electrode TE is disposed and to ensure good electrical insulation.

[0101] Meanwhile, although not shown, a polarizing layer may be disposed on the touch sensing layer.

[0102] The polarizing layer suppresses reflection of external light on the display area DA of the substrate 110. When the display device 100 is used outdoors, external natural light enters and may be reflected by the reflective layer included in the anode 121 of the light emitting element 120 or by the electrode made of metal disposed under the light emitting element 120. Such reflected light may make it difficult to view images on the display device 100. The polarizing layer polarizes the external light in a specific direction and prevents the reflected light from being emitted outside the display device 100.

[0103] Although not shown, a cover glass may be attached to the polarizing layer by an adhesive layer. The adhesive layer may serve to bond the components of the display device 100 together, and may be formed using an optically transparent adhesive for displays, such as, but not limited to, a pressure-sensitive adhesive, an optically clear adhesive (OCR), or an optically clear resin (OCR).

[0104] The cover glass protects the components of the display device 100 from external impacts and can prevent damage such as scratches.

[0105] FIG. 3 is an enlarged plan view of area A, which corresponds to the optical area in FIG.

[0106] Referring to FIG. 3, the optical area OA has a through hole TH at its center for disposing an optical electronic device, where a camera module or a sensor may be disposed. The optical area OA may include a circular or elliptical through hole TH and an area in which a dam structure 300, a connection prevention portion 200, etc. are disposed nearby. The through hole TH may be removed by a laser during the panel completion process. The non-display area NDA may be located between the through hole TH and the display area DA, and a high-potential power wiring PL, a gate wiring SL, etc. may be disposed therein. The connection prevention portion 200 and the dam structure 300 may be disposed around the through hole TH. Referring to FIG. 3, the connection prevention portion 200 may be composed of a first prevention portion 210 and a second prevention portion 220, and the dam structure 300 may be composed of a first dam 301 and a second dam 302. The first prevention portion 210, the first dam 301, the second prevention portion 220, and the second dam 302 may be sequentially disposed around the through hole TH. In general, the dam structure may prevent the second encapsulation layer 117b, a part of the encapsulation layer 117, from sliding down to the edge of the outer periphery of the display panel DP, thereby maintaining the adhesive strength between the upper and lower substrates constituting the display panel DP. The dam structure 300 in the optical region OA may also be formed with multiple structures, such as a first dam 301 and a second dam 302, to prevent the second encapsulation layer 117b of the encapsulation layer 117, which protects the light emitting element 120, from penetrating or leaking into the optical region OA. The connection prevention member 200 may be formed to cut off the connection between the light emitting layer 122 and prevent the penetration of moisture or oxygen. While this specification proposes two dams, this is not limiting, and additional dams may be arranged depending on the spatial arrangement. Referring to FIG. 3, a first prevention member 210 may be arranged near the through-hole TH, followed by a first dam 301, a second prevention member 220, and a second dam 302, in sequence. The first and second protection members 210 and 220 may be disposed to protect the light emitting elements 120 in the display area from moisture or oxygen that may enter through the through holes TH. The light emitting layer 122 of the light emitting element 120 may be deposited on the front surface of the display panel DP, but may also be uniformly deposited in the optical area OA. The light emitting layer 122 is an organic material that has high reactivity and propagating properties to moisture and oxygen, and may transfer moisture and oxygen to the light emitting elements 120 in the display area DA.To prevent this, the first and second prevention portions 210 and 220 may partially cut off the light emitting layer 122. Although two prevention portions are shown in this specification, the present invention is not limited to this.

[0107] Although the light emitting elements 120 and pixel circuits in the optical area OA are removed due to the arrangement of the optical area OA, the light emitting elements 120 and pixel circuits arranged above, below, left and right of the optical area OA must be electrically connected. To this end, the high-potential power supply wiring PL and the gate wiring SL may be arranged in the non-display area NDA adjacent to the optical area OA so as to bypass the through-holes TH and be connected above, below, left and right.

[0108] FIG. 4 is an enlarged plan view of region B in FIG.

[0109] 4, a first prevention unit 210 may be disposed near the through hole TH, a first dam 301 may be disposed between the first prevention unit 210 and the second prevention unit 220, and a second dam 302 may be disposed to the right of the second prevention unit 220. The first prevention unit 210 may include a first structure 211, a second structure 212, a third structure 213, and a fourth structure 214, and the second prevention unit 220 may include a fifth structure 221, a sixth structure 222, a seventh structure 223, and an eighth structure 224. Referring to FIGS. 3 and 4, it can be seen that the first prevention unit 210, the first dam 301, the second prevention unit 220, and the second dam 302 are arranged in a closed loop shape centered on the through hole TH. The first prevention member 210, the first dam 301, the second prevention member 220, and the second dam 302 are arranged in a closed loop because even a single opening could allow moisture and oxygen to penetrate into the display area DA from the outside, or conversely, allow the second encapsulation layer 117b to flood into the optical area OA and through-holes TH from the inside. Referring to Figure 4, the first prevention member 210 and the second prevention member 220 may each be composed of four structures, but are not limited to this. For example, the number of structures may be three or less or five or more, but are not limited to this.

[0110] FIG. 5 is a cross-sectional view of the optical region of FIG. 4 taken along line VV'.

[0111] The first and second prevention portions 210 and 220 may be arranged in a closed loop around the through hole TH, a first dam 301 may be arranged between the first and second prevention portions 210 and 220, and a second dam 302 may be arranged in a closed loop on the other side of the second prevention portion 220. Referring to FIG. 5 , the through hole TH may be arranged close to the first prevention portion 210.

[0112] As described with reference to FIG. 4 , the first prevention member 210 may include first structures 211 to 214. The first structures 211 to 214 may be formed as a two-tiered structure, with upper and lower structures, to separate the light-emitting layer 122, which may serve as a moisture transmission path from the region where the through-holes TH are disposed. An undercut structure may be formed on the side of the upper structure. Specifically, the upper portions of the first structures 211 to 214 may be arranged to have a trapezoidal cross section with a positive taper, and the lower portions may be arranged to have a rectangular cross section with a reverse taper or a constant height that is nearly vertical. This may result in a difference in width between the lower surface of the upper portion and the upper surface of the lower portion, where the upper and lower portions meet. The upper surfaces of the lower portions may be narrower than the lower surfaces of the upper portions, forming an undercut structure in which a portion of the lower surface of the upper portion is exposed. As a result, the light-emitting layer 122 deposited on the front surface of the display panel DP may be separated by the undercut structure on the side surfaces of the upper portions of the first structures 211 to 214 described above.

[0113] The first to fourth structures 211, 212, 213, and 214 constituting the first prevention unit 210 may be made of organic and inorganic materials. For example, the upper portions of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the first planarization layer 115a and the second planarization layer 115b, but are not limited to this. Also, the lower portions of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the second interlayer insulating layer 113b, but are not limited to this.

[0114] The second prevention unit 220 may include fifth structures 221 to eighth structures 224. The fifth structures 221 to eighth structures 224 constituting the second prevention unit 220 may be formed in a two-tiered structure, with an upper and lower layer, like the first structures 211 to 214. The second sealing layer 117b disposed on the second prevention unit 220 makes it difficult for moisture or oxygen to permeate the upper portion, and an undercut structure may be formed on the side of the upper portion, similar to the first prevention unit 210, to block the permeation path, mainly through the through-hole TH and the side where the first prevention unit 210 is disposed. The arrangement of the first prevention unit 210 and the second prevention unit 220 may prevent moisture or oxygen from permeating through the light-emitting layer 122 to the light-emitting elements 120 in the display area DA in the optical area OA.

[0115] The fifth to eighth structures 221, 222, 223, and 224 constituting the second prevention unit 220 may also be made of organic and inorganic materials. For example, the upper portions of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the first planarization layer 115a and the second planarization layer 115b, but are not limited to this. The lower portions of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the second interlayer insulating layer 113b, but are not limited to this.

[0116] As shown in FIG. 5, the first dam 301 and the second dam 302 may be formed by stacking the second planarization layer 115b, the bank 116a, and the spacer 116b, but are not limited thereto and may further include the first planarization layer 115a or other layers.

[0117] Referring to FIG. 3, the optical region OA may vary depending on the size of the camera applied to the product. While the corresponding region is shown as an empty space, an insulating film or wiring structure may be disposed in some areas. However, since this is a dummy region that will not remain in the finished product when the through-hole TH is removed with a laser, a separate designation is omitted. The laser may be irradiated in a circular or elliptical shape according to the shape of the optical region OA, and the entire upper region of the substrate, including the substrate 110, may be removed through the laser irradiation. The actual optical region OA and the laser irradiation region may differ. For example, the laser irradiation region of the optical region OA may be a region about 100 μm inward. Such a difference between the laser irradiation region and the optical region OA prevents damage to the insulating layer of the optical region OA during laser irradiation. The laser may be, but is not limited to, a picosecond laser or a femtosecond laser. Lasers utilize stimulated emission of light generated by applying energy to a specific material. They have radio-like properties and are monochromatic and directional. Lasers are used in communications, medical care, and industry. Lasers can easily form patterns or remove specific areas. Lasers use energy to form or remove patterns. When a laser irradiates a target, the thermal energy melts the target, forming a pattern. The longer the laser is irradiated, the more likely a thermal effect will occur, which spreads to the surrounding area of ​​the patterned area. This thermal effect occurs when heat accumulates around the laser irradiated area of ​​the target, potentially burning or deforming surrounding areas larger than the intended pattern. Due to these laser characteristics, if the laser irradiated area overlaps or is adjacent to an insulating film, the laser's thermal energy can also deform the insulating film. Deformation of the insulating film can cause cracks, which can propagate through the insulating film, resulting in peeling or allowing moisture and oxygen to penetrate.For example, in order to prevent deformation or peeling of insulating films such as the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, all of the insulating films may be removed at a distance of approximately 100 μm from the laser irradiation position.

[0118] Cracks that occur when cutting the substrate 110 using a laser can propagate through the inorganic insulating layer. While moisture or oxygen is characterized by its propagation through reaction with the light-emitting layer 122 of the light-emitting element 120, cracks can propagate through the rigid inorganic insulating layer, which is not flexible. Alternatively, cracks can occur in the through-holes TH formed by the laser due to interference during assembly of a camera or sensor. These cracks can also propagate through the inorganic insulating layer. If a crack that occurs in the through-holes TH propagates through the inorganic insulating layer, line defects or growing dark spots (GDS) can occur.

[0119] Therefore, in a display device 100 according to one embodiment of this specification, a first trench T1 is arranged in a portion of the insulating layers arranged in the optical area OA, thereby forming a step structure in the insulating layers and blocking the crack propagation path.

[0120] FIG. 6a is an enlarged cross-sectional view of area C of FIG. 5 according to one embodiment of the present specification.

[0121] 5 and 6a, according to an embodiment of the present specification, the optical region OA may include a first trench T1 disposed in a portion of a plurality of insulating layers overlapping at least one anti-connection portion 200. For example, the plurality of insulating layers may be at least one of a first buffer layer 111, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b disposed on a substrate 110, and the first trench T1 may be disposed in a portion of the insulating layers disposed at the top of the plurality of insulating layers.

[0122] Specifically, referring to both Figures 3 and 6a, a first trench T1 may be included in which at least a portion of a plurality of insulating layers overlapping at least one anti-connection portion 200 disposed in the optical region OA, i.e., the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, are etched.

[0123] The first trench T1 can form a step structure in multiple insulating layers, so that even if a crack occurs in the through hole TH, the inorganic insulating layer through which the crack propagates has been removed in the area where the first trench T1 is formed, preventing the crack from propagating.

[0124] Also, according to an embodiment of the present specification, at least one of the first planarization layer 115a and the second planarization layer 115b may be disposed in the first trench T1 to fill the first trench T1.

[0125] According to one embodiment of the present specification, a first trench T1 is formed by removing a portion of the inorganic insulating layers through which cracks propagate, and the first trench T1 is filled with an organic material, so that if a crack occurs in the through hole TH, the crack will not propagate further within the first trench T1.

[0126] Although the first trenches are shown in the optical area OA in FIGS. 5 and 6a, the first trenches in the optical area OA according to an embodiment of the present specification are not limited thereto.

[0127] Figure 6b is a cross-sectional view of a display device according to another embodiment of the present specification. Figure 6c is a cross-sectional view of a display device according to yet another embodiment of the present specification. Figure 6d is a cross-sectional view of a display device according to yet another embodiment of the present specification. Figure 6e is a cross-sectional view of a display device according to yet another embodiment of the present specification.

[0128] A display device 1000 according to another embodiment of the present specification may further include, as shown in FIG. 6b, a first trench T1 overlapping at least one connection prevention portion 200 arranged in the optical region OA, as well as a second trench T2 arranged in a portion of a plurality of insulating layers overlapping a dam structure 300 arranged in the optical region OA.

[0129] Specifically, as shown in FIG. 6b, the optical region OA may include a first trench T1 in which at least a portion of the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b overlapping at least one anti-connection portion 200 is etched, and a second trench T2 in which at least a portion of the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b overlapping the dam structure 300 is etched.

[0130] Therefore, in a display device 1000 according to another embodiment of this specification, by arranging a first trench T1 and a second trench T2 in the optical region OA, even if a crack occurs during the formation of the through hole TH in the optical region OA or during the assembly of the optical electronic device in the through hole TH, the first trench T1 and the second trench T2 block the propagation path of the crack, thereby preventing defects due to crack propagation.

[0131] For example, after forming a plurality of insulating layers, the depths of the first trench T1 and the second trench T2 disposed in some of the insulating layers can be adjusted using a mask process, and in this case, the first trench T1 and the second trench T2 can be formed using the same mask process.

[0132] The depths of the first trench T1 and the second trench T2 can be adjusted by changing the conditions of the mask process as needed.

[0133] FIG. 6c is a cross-sectional view of a display device according to still another embodiment of the present disclosure.

[0134] As shown in FIG. 6c, in a display device 1100 according to another embodiment of the present specification, the first trench T1 and the second trench T2 overlap with at least one anti-connection portion 200 and dam structure 300, respectively, and can be disposed in at least a portion of the gate metal GM, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b, which are disposed in the same layer as the gate electrode G1 of the first thin film transistor.

[0135] 6d and 6e are cross-sectional views of a display device according to still another embodiment of the present specification.

[0136] As shown in FIG. 6d, in a display device 1200 according to another embodiment of the present specification, the first trench T1 and the second trench T2 overlap with at least one anti-connection portion 200 and dam structure 300, respectively, and can be disposed in at least a portion of the light-shielding layer 125, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0137] FIG. 6e is a cross-sectional view of a display device according to yet another embodiment of the present disclosure.

[0138] As shown in FIG. 6e, in a display device 1300 according to another embodiment of the present specification, the first trench T1 and the second trench T2 overlap with at least one anti-connection portion 200 and dam structure 300, respectively, and can be disposed in at least a portion of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0139] According to another embodiment of the present specification, by arranging the first trench T1 and the second trench T2 in the optical region OA, even if a crack occurs during the formation of the through hole TH in the optical region OA or during the assembly of the optical electronic device in the through hole TH, the first trench T1 and the second trench T2 block the propagation path of the crack, thereby preventing defects due to crack propagation.

[0140] In addition, according to another embodiment of the present specification, the first trench T1 and the second trench T2 are arranged to overlap with at least one connection prevention portion 200 and dam structure 300 in the optical area OA, respectively, so that no additional space is required to prevent crack propagation, and therefore the non-display area NDA adjacent to the optical area OA can be minimized.

[0141] Hereinafter, reference will be made to FIG. 7 for a more detailed description of the optical area OA of a display device according to another embodiment of the present specification.

[0142] FIG. 7a is a cross-sectional view of a display device according to yet another embodiment of the present specification. FIG. 7b is a cross-sectional view of a display device according to yet another embodiment of the present specification. FIG. 7c is a cross-sectional view of a display device according to yet another embodiment of the present specification. FIG. 7d is a cross-sectional view of a display device according to yet another embodiment of the present specification. The cross-sectional views of FIGS. 7a to 7d are substantially the same as the cross-sectional views of FIGS. 6a to 6e in other configurations except for the first and second metal layers. Therefore, for convenience of explanation, redundant explanations except for the first and second metal layers will be omitted.

[0143] In another embodiment of the present specification, the display device 1400 may further include a first metal layer 410 disposed along the surface of some of the insulating layers in each of the first trench T1 and the second trench T2.

[0144] For example, the first metal layer 410 may be disposed in contact with the surfaces of the insulating layers in each of the first trench T1 and the second trench T2.

[0145] 7a, a first metal layer 410 may be disposed in the first trench T1 and the second trench T2 so as to contact the surfaces of the insulating layers. For example, the first metal layer 410 may be made of the same material as the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1.

[0146] In a display device 1400 according to another embodiment of the present specification, the crack propagation path is blocked by the step structure of the multiple insulating layers formed by the first trench T1 and the second trench T2, and the crack propagation is further blocked by the first metal layer 410 arranged inside the first trench T1 and the second trench T2 so as to contact the surfaces of the multiple insulating layers. Therefore, even if a crack occurs during the formation of the through hole TH in the optical region OA or during the assembly of the optical electronic device in the through hole TH, the crack propagation path is completely blocked by the first trench T1, the second trench T2 and the first metal layer 410, thereby preventing defects due to crack propagation.

[0147] FIG. 7a shows the structure of a first metal layer 410 arranged along the surface of some of the insulating layers in each of the first trench T1 and second trench T2 of the optical region OA, but the structure of the optical region OA according to one embodiment of this specification is not limited to this.

[0148] FIG. 7b is a cross-sectional view of a display device according to still another embodiment of the present disclosure.

[0149] A display device 1500 according to another embodiment of the present disclosure may further include a second metal layer 520 disposed under each of the first trench T1 and the second trench T2 in the optical area OA.

[0150] 7b, the first metal layer 510 may contact side surfaces of some of the insulating layers in each of the first trench T1 and the second trench T2, and the first metal layer 510 and the second metal layer 520 may contact each other. For example, the first metal layer 510 may be disposed in the same layer as the first source electrode S1 and the first drain electrode D1 and may be made of the same material, and the second metal layer 520 may be disposed in the same layer as the first gate electrode G1 and may be made of the same material.

[0151] In a display device 1500 according to another embodiment of the present specification, the crack propagation path is blocked by the step structure of multiple insulating layers formed by the first trench T1 and the second trench T2, and the crack propagation path is further blocked by the first metal layer 510 and the second metal layer 520 disposed inside and below the first trench T1 and the second trench T2, respectively. Even if a crack occurs during the formation of the through hole TH in the optical region OA or during the assembly of the optical electronic device in the through hole TH, the crack propagation path is completely blocked by the first trench T1, the second trench T2, the first metal layer 510, and the second metal layer 520, and defects due to crack propagation can be prevented.

[0152] According to another embodiment of the present specification, the depths of the first trench T1 and the second trench T2 disposed in some of the insulating layers can be adjusted, and in this case, the materials forming the first metal layer 510 and the second metal layer 520 can be different depending on the depths of the first trench T1 and the second trench T2.

[0153] 7c is a cross-sectional view of a display device according to another embodiment of the present disclosure. As shown in FIG. 7c, in a display device 1600 according to another embodiment of the present disclosure, the first metal layer 610 may be made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 620 may be made of the same material as the light-shielding layer 125.

[0154] 7d is a cross-sectional view of a display device according to another embodiment of the present disclosure. As shown in FIG. 7d, in a display device 1700 according to another embodiment of the present disclosure, a second metal layer 720 may be disposed in contact with the surfaces of the insulating layers in each of the first trench T1 and the second trench T2, and a first metal layer 710 may be disposed in contact with the surfaces of the second metal layer 720 in each of the first trench T1 and the second trench T2. For example, the first metal layer 710 may be disposed in the same layer as the second source electrode S2 and the second drain electrode D2 and may be made of the same material, and the second metal layer 720 may be disposed in the same layer as the first source electrode S1 and the first drain electrode D1 and may be made of the same material.

[0155] According to another embodiment of the present specification, by arranging the first trench T1 and the second trench T2 in the optical region OA, even if a crack occurs during the formation of the through hole TH in the optical region OA or during the assembly of the optical electronic device in the through hole TH, the first trench T1 and the second trench T2 block the crack propagation path, thereby preventing defects due to the crack propagation. Furthermore, by arranging the first trench T1 and the second trench T2 to overlap at least one connection prevention part 200 and at least one dam structure 300 in the optical region OA, respectively, no additional space is required to prevent crack propagation, thereby minimizing the non-display area NDA near the optical region OA.

[0156] Furthermore, according to another embodiment of the present specification, by disposing first metal layers 410, 510, 610, 710 in the first trench T1 and the second trench T2 and disposing second metal layers 420, 520, 620, 720 so as to be in contact with the first metal layers 410, 510, 610, 710, the propagation of cracks is further blocked. Even if cracks occur during the formation of the through holes TH in the optical region OA or during the assembly of the optical electronic device in the through holes TH, the propagation path of the cracks is completely blocked by the first trench T1, the second trench T2, the first metal layers 410, 510, 610, 710 and the second metal layers 420, 520, 620, 720, and this makes it possible to prevent defects due to crack propagation.

[0157] An embodiment of the present invention can also be described as follows.

[0158] According to an aspect of the present invention, a display device includes a substrate including a display region, an optical region disposed in the display region and including a through hole, and a non-display region surrounding the display region, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and closer to the through hole than the at least one dam, wherein a first trench is disposed in a portion of the plurality of insulating layers overlapping with the at least one connection prevention portion in the optical region. According to another feature of the present specification, the plurality of insulating layers may include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate, and the first trench may be disposed in an upper portion of the plurality of insulating layers.

[0159] According to another feature of the present disclosure, the semiconductor device may further include a second trench disposed in a portion of the plurality of insulating layers overlapping the at least one dam in the optical region.

[0160] According to another feature of the present specification, the semiconductor device may further include a first metal layer disposed along a surface of some of the insulating layers in each of the first trench and the second trench.

[0161] According to another feature herein, a first metal layer may be disposed in contact with a surface of the plurality of insulating layers in each of the first trench and the second trench.

[0162] According to another feature of the present specification, the pixel may further include a first thin film transistor disposed on a substrate in the display region and including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; and a second thin film transistor disposed on the insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

[0163] According to another feature herein, the first metal layer may be composed of the same material as the first source electrode and the first drain electrode.

[0164] According to another feature of the present disclosure, the semiconductor device may further include a second metal layer disposed below each of the first trench and the second trench.

[0165] According to another feature of the present specification, the first metal layer may contact a side surface of some of the insulating layers in each of the first trench and the second trench, and the first metal layer and the second metal layer may contact each other.

[0166] According to another feature of the present specification, the first metal layer may be disposed in the same layer as the first source electrode and the first drain electrode and may be composed of the same material, and the second metal layer may be disposed in the same layer as the first gate electrode and may be composed of the same material.

[0167] According to another feature of the present specification, the semiconductor device may further include a light-shielding layer disposed below the first active layer to overlap with the first gate electrode, wherein the first metal layer is composed of the same material as the first source electrode and the first drain electrode, and the second metal layer is composed of the same material as the light-shielding layer.

[0168] According to another feature of the present specification, a second metal layer may be disposed in contact with a surface of the plurality of insulating layers at each of the first trench and the second trench, and the first metal layer may be disposed in contact with a surface of the second metal layer at each of the first trench and the second trench.

[0169] According to another feature of the present specification, the first metal layer may be disposed in the same layer as the second source electrode and the second drain electrode and may be composed of the same material, and the second metal layer may be disposed in the same layer as the first source electrode and the first drain electrode and may be composed of the same material.

[0170] According to another feature herein, the optical device may further include an optical-electronic device disposed overlapping the optical region.

[0171] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. All technical concepts within the scope of the claims of the present specification should be construed as being within the scope of the present specification.

Claims

1. a substrate including a display area, an optical area disposed within the display area and including through holes, and a non-display area surrounding the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulating layers; At least one anti-coupling portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam; and first metal layer Including, a first trench is disposed in a portion of the insulating layers overlapping the at least one connection prevention portion in the optical region; The display device, wherein the first metal layer is disposed in the first trench and along surfaces of some of the plurality of insulating layers.

2. the plurality of insulating layers include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate; The display device according to claim 1 , wherein the first trench is disposed in an upper part of the insulating layers.

3. The display device of claim 1 , further comprising a second trench disposed in a portion of the plurality of insulating layers overlapping the at least one dam in the optical region.

4. A display device, a substrate including a display area, an optical area disposed within the display area and including through holes, and a non-display area surrounding the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulating layers; and at least one anti-coupling portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam; Including, a first trench is disposed in a portion of the insulating layers overlapping the at least one connection prevention portion in the optical region; the plurality of insulating layers include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate; the first trench is disposed in an upper part of the insulating layers, The display device includes: a first thin film transistor disposed on the substrate in the display region, the first thin film transistor including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; a first planarization layer disposed on the first source electrode and the first drain electrode of the first thin film transistor; and further comprising a second planarization layer disposed on the first planarization layer; At least one of the first planarization layer and the second planarization layer is disposed within the first trench to fill the first trench.

5. A display device as described in claim 3, further comprising another first metal layer arranged along the surface of some of the plurality of insulating layers in the second trench.

6. The display device according to claim 5 , wherein the first metal layer is disposed in the first trench, and the other first metal layer is disposed in the second trench so as to contact surfaces of the plurality of insulating layers.

7. a first thin film transistor disposed on the substrate in the display region, the first thin film transistor including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; and The display device of claim 6 , further comprising a second thin film transistor disposed on the at least one insulating layer, the second thin film transistor including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

8. The display device according to claim 7 , wherein the first metal layer and the another first metal layer are made of the same material as the first source electrode and the first drain electrode.

9. The display device of claim 7 , further comprising a second metal layer disposed below each of the first trench and the second trench.

10. the first metal layer is disposed in the first trench, and the other first metal layer is disposed in the second trench so as to contact a side surface of a part of the insulating layers among the plurality of insulating layers; The display device of claim 9 , wherein the first metal layer and the second metal layer are in contact with each other.

11. the first metal layer and the another first metal layer are disposed in the same layer as the first source electrode and the first drain electrode and are made of the same material; The display device according to claim 10 , wherein the second metal layer is disposed in the same layer as the first gate electrode and is made of the same material as the first gate electrode.

12. a light-shielding layer disposed under the first active layer so as to overlap the first gate electrode; the first metal layer and the another first metal layer are made of the same material as the first source electrode and the first drain electrode; The display device according to claim 10 , wherein the second metal layer is made of the same material as the light-shielding layer.

13. the second metal layer is disposed so as to contact surfaces of the plurality of insulating layers in each of the first trench and the second trench; The display device according to claim 10 , wherein the first metal layer is disposed in the first trench, and the other first metal layer is disposed so as to contact a surface of the second metal layer in each of the second trenches.

14. the first metal layer and the another first metal layer are disposed in the same layer as the second source electrode and the second drain electrode and are made of the same material; The display device according to claim 13 , wherein the second metal layer is disposed in the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode.

15. The display device of claim 1 further comprising an optoelectronic device disposed overlying the optical region.

16. The display device according to claim 15 , wherein the through-hole is formed to correspond to the optical-electronic device.

17. A display device as described in claim 4, further comprising a second thin film transistor disposed on the at least one insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

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