Input / output control method, input / output control program, and input / output control device

Abstract

To enable a RTL module having an internal state to be incorporated into a pipeline of an OpenCL even when the number of input cycles and the number of output cycles are different from each other and input / output is intermittent.SOLUTION: An OpenCL kernel 20 calls a RTL module 30 as a library in each predetermined cycle. A valid flag indicating that data is valid or an invalid flag indicating that data is invalid is input to the RTL module 30 together with input data. The RTL module 30 outputs the valid flag or the invalid flag to the OpenCL kernel 20 together with output data.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a data input / output control method, an input / output control program, and an input / output control device when designing an FPGA (Field-Programmable Gate Array) by mixing descriptions in a language designed in OpenCL (Open Computing Language) and Register Transfer Level (RTL). [Background technology]

[0002] In recent years, FPGAs have been attracting attention as devices that realize hardware acceleration for various applications. Unlike conventional ASIC (Application Specific Integrated Circuit) devices, FPGAs are rewritable circuits. One method of circuit design for FPGAs is RTL, which is written in a hardware description language such as VerilogHDL (Hardware Description Language), which is also used in the design of conventional ASIC devices. In addition, in recent years, a design method called "high-level synthesis" has been developed as a method of circuit design for FPGAs, which generates RTL from source code written in a high-level programming language based on C or C++, such as OpenCL.

[0003] Design using high-level synthesis is also called high-level design in contrast to RTL design (hereinafter referred to as "RTL design"), which describes behavior closer to the hardware level. Design using high-level synthesis can be written in a programming style based on C or C++, which are commonly used in software development, so it can be designed at a lower cost than traditional RTL design. However, high-level synthesis has not yet completely replaced RTL design because it can sometimes result in lower performance and higher resource usage within FPGAs compared to RTL-designed circuits.

[0004] Therefore, FPGA circuits may be designed by combining high-level design using OpenCL with traditional RTL design. Specifically, when you want to utilize existing RTL design assets, or when you want to use RTL design for circuit blocks where high performance is required, and when there is the possibility of flexible recombination of the design, or when high performance is not required, you may use OpenCL for circuit blocks. In this way, by combining high-level design using OpenCL with traditional RTL design, it is possible to achieve both low design costs and the required performance.

[0005] For example, Non-Patent Document 1 discloses a development kit for FPGAs used to incorporate a circuit designed using RTL (hereinafter referred to as an "RTL module") into a program using OpenCL. This development kit includes a "helper function method" and an "IO (Input / Output) channel method." The helper function method uses an RTL module as a library for an OpenCL program written in OpenCL. In an OpenCL program, this library RTL module is called and used as a kernel function of the OpenCL program (hereinafter referred to as an "OpenCL kernel function"). This OpenCL kernel function is called a helper function. On the other hand, the IO channel method is a method in which an RTL module is called and used in the same way as other external IP (Intellectual Property: circuit design data).

[0006] The helper function method calls an RTL module as an OpenCL kernel function, allowing it to be used in the same programming style as a regular OpenCL kernel function. Therefore, the helper function method offers advantages in terms of implementation cost, scalability, and portability. However, the helper function method has the disadvantages of being restricted to function calls for input / output and being unable to control external IO functions.

[0007] On the other hand, the IO channel method has the advantage of allowing flexible implementation, including the implementation of external IO functions. However, the IO channel method has the disadvantage that the BSP (Board Support Package) provided by the FPGA board manufacturer must be modified to connect to OpenCL kernel functions. Another disadvantage of the IO channel method is that every time you change FPGA boards, you must modify the BSP to match the BSP of that FPGA board.

[0008] Therefore, when there is no special need to control external IO functions, helper functions are used, which have advantages in terms of implementation cost, scalability, and portability. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] Intel Corporation, Intel(R) FPGA SDK for OpenCLTM Pro Edition: Programming Guide, April 1, 2019, URL: https: / / www.intel.co.jp / content / www / jp / ja / docs / programmable / 683846 / 19-1 / overview.html [Non-patent document 2] Norihisa Fujita, Yuma Ohata, Ryohei Kobayashi, Yoshiki Yamaguchi, and Tae-woo Park, "FPGA Programming Using Mixed Descriptions of OpenCL and Verilog HDL," Information Processing Society of Japan Technical Report Vol. 2017-HPC-158 No. 16, March 9, 2017, URL: https: / / ipsj.ixsq.nii.ac.jp / ej / ?action=repository_uri&item_id=177921&file_id=1&file_no=1 Summary of the Invention [Problem to be solved by the invention]

[0010] In a helper function implementation, the RTL module operates within the OpenCL pipeline. The frequency (initiation interval) at which the RTL module inputs data to the pipeline can be preset. However, even if the initiation interval is set, the RTL module does not necessarily receive data from the OpenCL kernel at every initiation interval. For example, if the processing in the OpenCL kernel is complex or if the RTL module is not ready to receive data, the RTL module will receive data intermittently rather than continuously. Furthermore, depending on the timing of the RTL module's processing and data output, the OpenCL kernel may intermittently receive data output from the RTL module.

[0011] Therefore, it is necessary to set latency, which is the amount of delay according to the number of cycles of processing within the RTL module, so that the OpenCL kernel can obtain output data when the processing in the RTL module is completed.Latency is set by specifying the number of cycles in a configuration file.However, there is an issue in that the number of cycles specified in this configuration file can only be set as a fixed value that represents a one-to-one relationship from input to output for that input.

[0012] For example, an RTL module that performs image processing may process multiple input data, such as multiple pixels, over a predetermined number of cycles and output multiple results. Such an RTL module requires multiple cycles to receive input data and executes the predetermined processing over multiple cycles while maintaining an internal state. Furthermore, such an RTL module may be designed to output results in a different number of cycles than the number of inputs. In other words, the number of input cycles and the number of output cycles for such an RTL module are different.

[0013] As described above, there is a problem that it is not possible to set an appropriate latency for an RTL module that has different input and output cycles, performs data input and output intermittently, and has an internal state. This causes problems such as the RTL module being unable to execute processing based on accurate input data, and the data output by the RTL module being unable to be accurately passed to the OpenCL kernel.

[0014] The disclosed technology has been made in consideration of the above points, and aims to provide an input / output control method, an input / output control program, and an input / output control device that can incorporate an RTL module with an internal state into an OpenCL pipeline, even if the number of input cycles and the number of output cycles are different and input / output is intermittent. [Means for solving the problem]

[0015] A first aspect of the present disclosure is an input / output control method, the method comprising: an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language) calls an RTL circuit designed at the register transfer level as a library at predetermined cycles; inputting a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; and the RTL circuit outputting the valid flag or the invalid flag to the OpenCL kernel together with output data.

[0016] A second aspect of the present disclosure is an input / output control program for causing a computer to function as an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), wherein the OpenCL kernel calls an RTL module designed at the register transfer level as a library at predetermined cycles, inputs a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL module along with input data, and the RTL module outputs the valid flag or the invalid flag to the OpenCL kernel along with output data.

[0017] A third aspect of the present disclosure is an input / output control device including an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), wherein the OpenCL kernel calls an RTL circuit designed at the register transfer level as a library at predetermined cycles, inputs a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL circuit along with input data, and the RTL circuit outputs the valid flag or the invalid flag to the OpenCL kernel along with output data. [Effects of the Invention]

[0018] According to the disclosed technology, even if the number of input cycles and the number of output cycles are different and input and output are intermittent, an RTL module having an internal state can be incorporated into an OpenCL pipeline. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 2 is a schematic diagram illustrating an example of a hardware configuration of an input / output control device according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating an example of a configuration of an OpenCL kernel according to the first embodiment. [Figure 3]FIG. 2 is a block diagram showing an example of a functional configuration of an OpenCL kernel according to the first embodiment. [Figure 4] 10 is a flowchart illustrating an example of input / output control processing in an OpenCL kernel according to the first embodiment. [Figure 5] FIG. 2 is a schematic diagram for explaining the effect of the input / output control device according to the first embodiment. [Figure 6] FIG. 10 is a schematic diagram illustrating an example of a configuration of an OpenCL kernel according to a second embodiment. [Figure 7] FIG. 10 is a block diagram showing an example of a functional configuration of an OpenCL kernel according to a second embodiment. [Figure 8] 10 is a flowchart illustrating an example of input / output control processing in an OpenCL kernel according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] An example of an embodiment of the disclosed technology will be described below with reference to the drawings. Note that the same or equivalent components and parts in each drawing are given the same reference numerals. Also, the dimensional proportions in the drawings are exaggerated for the convenience of explanation and may differ from the actual proportions.

[0021] [First embodiment] 1, an input / output control device 10 according to this embodiment includes an FPGA 11, a DRAM (Dynamic Random Access Memory) 12, and an SRAM (Static Random Access Memory) 13. Each component is connected to each other via a bus 19 so as to be able to communicate with each other.

[0022] The FPGA 11 is designed to implement each function of an OpenCL kernel 20, which will be described later. Specifically, the FPGA 11 is designed to execute a kernel program 100 as an input / output control program.

[0023] The DRAM 12 is an external memory of the FPGA 11. The SRAM 12 is an internal memory inside the FPGA 11.

[0024] Next, the configuration of the OpenCL kernel 20 according to this embodiment will be described with reference to FIG.

[0025] As shown in FIG. 2, an OpenCL kernel 20 incorporates an RTL module 30 .

[0026] The OpenCL kernel 20 is called from a host program in an OpenCL program or from an OpenCL kernel other than the OpenCL kernel 20. When a predetermined process is completed, the OpenCL kernel 20 returns to the host program or other OpenCL kernel that is the caller.

[0027] The RTL module 30, which is an RTL circuit, executes processing based on multiple input data and outputs multiple output data. The OpenCL kernel 20 controls the continuous cycle operation of the RTL module 30 by continuously calling the RTL module 30 as a library at predetermined cycles using a loop construct such as a for statement or a while statement. The RTL module 30 is included in a wrapper module 40.

[0028] The wrapper module 40 has input ports for receiving datain_0 and datain_1 from the OpenCL kernel 20. The RTL module 30 also has an input port for receiving datain_0 from the wrapper module 40 and an input port for receiving valid_flag_in stored in datain_1.

[0029] The RTL module 30 also has output ports for outputting dataout_0, write_addr, req_ready, req_addr, valid_flag_out, and finish_flag. The wrapper module 40 multiplexes (MUXes) the multiple output ports of the RTL module 30 into one output port and adjusts the output data to the bit width of the variable provided by the OpenCL kernel 20. This allows the RTL module 30 to simultaneously output the values ​​of the output ports to the OpenCL kernel 20 even if it has multiple output ports.

[0030] Note that the conventional RTL module is not included in the wrapper module 40, and only has an input port for receiving datain_0 from the OpenCL kernel 20. Therefore, the RTL module 30 according to this embodiment differs from the conventional RTL module in that it further has an input port for receiving datain_1.

[0031] Furthermore, while conventional RTL modules only have output ports for outputting dataout_0 and write_addr, the RTL module 30 according to this embodiment differs from conventional RTL modules in that it further has output ports for outputting req_ready, req_addr, valid_flag_out, and finish_flag.

[0032] The flags output by the RTL module 30 are flags for data processing and do not have a significant effect on the actual processing inside the RTL module 30. Details of datain_0, datain_1, valid_flag_in, dataout_0, write_addr, req_ready, req_addr, valid_flag_out, and finish_flag will be described later.

[0033] Next, the functional configuration of the OpenCL kernel 20 according to this embodiment will be described with reference to Fig. 3. The OpenCL kernel 20 has functions as an input RAM 201, a preparation unit 202, a determination unit 203, a function unit 204, a parsing unit 205, a termination determination unit 206, and an output RAM 207.

[0034] The input RAM 201 is a storage area that stores a group of input data to be input to the RTL module 30. The input RAM 201 is realized by the DRAM 12 and the SRAM 13.

[0035] The preparation unit 202 executes initialization processing. Specifically, the preparation unit 202 copies input data from the DRAM 12 and stores the copied input data in the SRAM 13. The array variable used by the preparation unit 202 to access the DRAM 12 is designated dram_in[i], and the array variable used by the preparation unit 202 to access the SRAM 13 is designated sram_in[i]. i indicates an index for array access. The input / output control device 10 transfers data in advance from the DRAM used within the host program in the OpenCL program to the DRAM 12 and sets an index variable for accessing the desired DRAM 12, thereby enabling reference to data stored in the DRAM 12. However, since the latency from the request to access the DRAM 12 to the actual return of a value is relatively long, in this embodiment, the input data copied in advance from the DRAM 12 by the preparation unit 202 is stored in the SRAM 13.

[0036] The preparation unit 202 also stores 0 in datain_0, which is a register variable used when transferring input data to the RTL module 30, and in write_addr, which indicates a write address when output data output by the RTL module 30 is written to the DRAM 12 or SRAM 13. The preparation unit 202 also sets False to datain_1, which is a flag variable indicating whether the input data is valid or invalid, and to req_ready, which indicates an input request flag by which the RTL module 30 requests valid input data. The preparation unit 202 also sets False to req_addr, which indicates an address for accessing a RAM area where valid input data is stored, and to valid_flag_out, which indicates whether the output data output by the RTL module 30 is valid or invalid. The preparation unit 202 also sets False to finish_flag, which indicates that all processing in the RTL module 30 has ended.

[0037] Furthermore, when the RTL module 30 requests valid input data from the OpenCL kernel 20, the preparation unit 202 acquires the valid input data from the input RAM 201 based on the address information indicated by req_addr. Then, the preparation unit 202 stores the valid input data in datain_0.

[0038] When the RTL module 30 requests valid input data, the determination unit 203 determines to input to the RTL module 30 the valid input data acquired by the preparation unit 202 from the input RAM 201, along with a valid flag indicating that the data is valid. On the other hand, when the RTL module 30 does not request valid input data, the determination unit 203 determines to input to the RTL module 30 any invalid input data (e.g., 0) along with an invalid flag indicating that the data is invalid. Note that the any invalid input data may be any value other than 0, for example, a value that never appears in processing. Then, the determination unit 203 sets True as a valid flag or False as an invalid flag to datain_1. Then, the determination unit 203 passes datain_0 and datain_1 to the wrapper module 40. Details of the function of the function unit 204 of the RTL module 30 and the wrapper module 40 will be described later.

[0039] The parsing unit 205 parses dataout output from the function unit 204 using a predetermined bit mask and stores the resulting data in predetermined variables. dataout is a return value that combines the values ​​of dataout_0, req_addr, req_ready, write_addr, valid_flag_out, and finish_flag. Specifically, the parsing unit 205 performs a given bit masking process represented by A on dataout, and stores the resulting value obtained by bit-shifting it to the right by a bits in dataout_0. The parsing unit 205 also performs a given bit masking process represented by B on dataout, and stores the resulting value obtained by bit-shifting it to the right by b bits in req_addr. The parsing unit 205 also performs a given bit masking process represented by C on dataout, and stores the resulting value obtained by bit-shifting it to the right by c bits in req_ready. The parsing unit 205 also performs a given bit masking process represented by D on dataout, and stores the value obtained by bit-shifting it to the right by d bits in write_addr. The parsing unit 205 also performs a given bit masking process represented by E on dataout, and stores the value obtained by bit-shifting it to the right by e bits in valid_flag_out. The parsing unit 205 also performs a given bit masking process represented by F on dataout, and stores the value obtained by bit-shifting it to the right by f bits in finish_flag. The parsing unit 205 then passes finish_flag to the termination determination unit 206. Note that A to F and a to f are values ​​defined in advance depending on the design contents.

[0040] Furthermore, when a valid flag is output from the RTL module 30, the parsing unit 205 stores the valid output data output together with the valid flag in the output RAM 207. Specifically, when valid_flag_out is set to True, the parsing unit 205 stores dataout_0 in an area specified by write_addr in the output RAM 207. On the other hand, when an invalid flag is output from the RTL module 30 (i.e., when valid_flag_out is set to False), the parsing unit 205 does not store the invalid output data output together with the invalid flag.

[0041] The termination determination unit 206 determines whether or not True is set in finish_flag acquired from the parsing unit 205. In other words, the termination determination unit 206 determines whether or not a setting indicating that all processing in the RTL module 30 has been completed is set in finish_flag. If False is set in finish_flag, the termination determination unit 206 causes the preparation unit 202 to execute processing. On the other hand, if True is set in finish_flag, the termination determination unit 206 terminates processing.

[0042] The output RAM 207 is a storage area that stores valid output data among the output data output from the parser 205 for each predetermined cycle. The output RAM 207 is realized by the DRAM 12 and the SRAM 13.

[0043] Next, the function of the function unit 204 will be described in detail with reference to FIG.

[0044] The OpenCL kernel 20 inputs datain_0, in which valid input data or invalid input data is stored, and datain_1, in which a valid flag or invalid flag is stored, to the wrapper module 40. The wrapper module 40 inputs datain_0 to the RTL module 30 and inputs datain_1 to the RTL module 30 as valid_flag_in.

[0045] When valid_flag_in is set to False, i.e., when an invalid flag is input, the RTL module 30 does not take in the invalid input data stored in datain_0 and does not execute processing. On the other hand, when valid_flag_in is set to True, i.e., when a valid flag is input, the RTL module 30 takes in the valid input data stored in datain_0 and executes processing.

[0046] The RTL module 30 then outputs output data at predetermined cycles. Specifically, the RTL module 30 outputs dataout_0, which stores invalid output data other than valid output data obtained by execution based on input data from the OpenCL kernel 20, and an invalid flag, valid_flag_out, to which False is set. The RTL module 30 also outputs dataout_0, which stores valid output data obtained by execution based on input data from the OpenCL kernel 20, a valid flag, valid_flag_out, to which True is set, and write_addr.

[0047] Furthermore, if the RTL module 30 requests valid input data in the next cycle, it outputs req_ready with True set and req_addr with an address for accessing the RAM area where the valid input data is stored. On the other hand, if the RTL module 30 does not request valid input data in the next cycle, it outputs req_ready with False set. Furthermore, if all processing has been completed, the RTL module 30 outputs finish_flag with True set, and if all processing has not been completed, it outputs finish_flag with False set.

[0048] The wrapper module 40 multiplexes (MUXes) the data output by the RTL module 30 into one port, adjusts the data to the bit width of the variables provided by the OpenCL kernel 20, and outputs the data to the OpenCL kernel 20. The OpenCL kernel 20 then stores the multiplexed data in dataout.

[0049] Next, the operation of the OpenCL kernel 20 according to this embodiment will be described.

[0050] FIG. 4 is a flowchart showing the flow of input / output control processing by the OpenCL kernel 20.

[0051] In step S100, the preparation unit 202 copies input data from the DRAM 12 and stores the copied input data in the SRAM 13. Specifically, the preparation unit 202 sets sram_in[i] to dram_in[i]. Then, the processing of the preparation unit 202 proceeds to step S101.

[0052] In step S101, the preparation unit 202 executes initialization processing. Specifically, the preparation unit 202 stores 0 in datain_0 and write_addr. The preparation unit 202 also sets False to datain_1, req_ready, req_addr, valid_flag_out, and finish_flag. Then, the processing of the preparation unit 202 proceeds to step S102.

[0053] In step S102, the determination unit 203 determines whether the RTL module 30 is requesting valid input data from the OpenCL kernel 20. In other words, the determination unit 203 determines whether req_ready is set to True. If req_ready is set to True (step S102: YES), the determination unit 203 proceeds to step S103. On the other hand, if req_ready is set to False (step S102: NO), the determination unit 203 proceeds to step S105.

[0054] In step S103, the preparation unit 202 stores valid input data acquired from sram_in in datain_0 based on the address information indicated by req_addr. Then, the processing of the preparation unit 202 proceeds to step S104.

[0055] In step S104, the decision unit 203 sets datain_1 to indicate that the data is valid. That is, the decision unit 203 sets datain_1 to True. Then, the process of the decision unit 203 proceeds to step S107.

[0056] In step S105, the determination unit 203 stores the invalid input data in datain_0. Then, the process of the determination unit 203 proceeds to step S106.

[0057] In step S106, the decision unit 203 sets datain_1 to indicate that the data is invalid. That is, the decision unit 203 sets datain_1 to False. Then, the process of the decision unit 203 proceeds to step S107.

[0058] In step S107, the function unit 204 executes processing using datain_0 and datain_1 as arguments and stores the return value in dataout. Specifically, the function unit 204 calls and executes the helper function RTL_module of the RTL module 30 using datain_0 and datain_1 as arguments. Based on datain_0 and datain_1 input via the helper function RTL_module, if datain_1 is set to True, the RTL module 30 determines that valid input data has been input and performs processing using datain_0. Then, the RTL module 30 outputs something every predetermined cycle, and if the output is valid output data after processing in the RTL module 30, it outputs valid_flag_out set to True, dataout_0 storing the valid output data, and write_addr. Furthermore, if the RTL module 30 requests valid input data in the next cycle as well, it outputs req_ready and req_addr set to True. Then, the wrapper module 40 multiplexes (MUXes) these into one port, and then stores the value that appears as a return value from the helper function in dataout of the OpenCL kernel 20. Then, the processing of the function unit 204 proceeds to step S108.

[0059] In step S108, the parser 205 stores the values ​​obtained by parsing dataout with a predetermined bit mask in dataout_0, req_addr, req_ready, write_addr, valid_flag_out, and finish_flag. Then, the process of the parser 205 proceeds to step S109.

[0060] In step S109, the parsing unit 205 determines whether or not valid_flag_out is set to indicate that the output data output by the RTL module 30 is valid. Specifically, the parsing unit 205 determines whether or not True is stored in valid_flag_out obtained in step S108. If True is set in valid_flag_out (step S109: YES), the parsing unit 205 proceeds to step S110. On the other hand, if False is set in valid_flag_out (step S109: NO), the parsing unit 205 returns to step S102. In other words, the parsing unit 205 repeats the processes from step S102 to step S109 until True is set in valid_flag_out.

[0061] In step S110, the parser 205 stores dataout_0 in sram_out[i], which is an area specified by write_addr in the SRAM 13 of the output RAM 207. Then, the processing of the parser 205 proceeds to step S111.

[0062] In step S111, the termination determination unit 206 determines whether or not finish_flag is set to indicate that all processing in the RTL module 30 has been completed. Specifically, the termination determination unit 206 determines whether or not True is set in finish_flag. If True is set in finish_flag (step S111: YES), the termination determination unit 206 proceeds to step S112.

[0063] In step S112, the parser 205 stores the value stored in sram_out[i] in step S110 in dram_out[i], which is an area specified by i in the DRAM 12 of the output RAM 207, and ends this input / output control process.

[0064] On the other hand, if finish_flag is set to False (step S111: NO), the termination determination unit 206 returns to step S102. In other words, the termination determination unit 206 repeats the processes from step S102 to step S111 until finish_flag is set to True.

[0065] Here, req_ready and req_addr in the iterative process from step S102 to step S111 are output from the RTL module 30 in the previous iterative process (i.e., the previous cycle). Specifically, when the OpenCL kernel 20 calls the RTL module 30 as a library at predetermined cycles, the RTL module 30 outputs req_ready and req_addr with True set to them to the OpenCL kernel 20 in the cycle before the timing at which the OpenCL kernel 20 inputs valid input data. Then, in the cycle next to the timing at which req_ready and req_addr with True set are output, the OpenCL kernel 20 acquires valid input data from the input RAM 201. Then, the OpenCL kernel 20 inputs a valid flag to the RTL module 30 along with the valid input data. This allows the OpenCL kernel 20 to input valid input data to the RTL module 30 at appropriate timing. Furthermore, the OpenCL kernel 20 can receive output data from the RTL module 30 at appropriate timing. If it takes a predetermined number of n cycles for the preparation unit 202 to prepare the data requested by the RTL module 30, the RTL module 30 can output req_ready set to True n cycles before the cycle in which the data is required.

[0066] Next, the effects of the input / output control device 10 according to this embodiment will be described.

[0067] For example, as shown in the upper diagram of Figure 5, the number of input and output cycles for an RTL module is assumed to be the same, and data input and output is assumed to be continuous. Therefore, latency can only be set to a fixed value that represents a one-to-one relationship from input to output for that input. In the example shown in Figure 5, the cycles required for the entire processing of the RTL module are assumed to be 1000 clk (clocks). However, as shown in the lower diagram of Figure 5, the number of input and output cycles for an actual RTL module differ, and data input and output is performed intermittently, and the module has internal states. Therefore, because it is not possible to set an appropriate latency, there are issues such as the RTL module being unable to execute processing based on accurate input data and the data output by the RTL module being unable to be accurately passed to the OpenCL kernel.

[0068] To address this issue, in the input / output control method according to this embodiment, the OpenCL kernel 20 calls the RTL module 30 as a library at predetermined cycles, and inputs a valid flag or invalid flag together with the input data to the RTL module 30. The RTL module 30 then outputs the valid flag or invalid flag together with the output data to the OpenCL kernel 20. This makes it possible to incorporate the RTL module 30, which has an internal state, into the pipeline of the OpenCL 20, even if the number of input cycles and the number of output cycles are different and input / output is intermittent.

[0069] [Second embodiment] The second embodiment differs from the first embodiment in that an error is notified when the difference between the number of times the OpenCL kernel 20 has called the RTL module 30 and the number of times the OpenCL kernel 20 last called the RTL module 30 is not a predetermined number of cycles. The second embodiment also differs from the first embodiment in that an error is notified when the difference between the number of cycles since the RTL module 30 was started and the number of cycles since the previous RTL module 30 was started is not a predetermined number of cycles. The differences from the first embodiment will be described below.

[0070] First, the configuration of the OpenCL kernel 20 according to this embodiment will be described with reference to FIG.

[0071] As shown in FIG. 6, the wrapper module 40 according to this embodiment differs from the first embodiment in that it further includes a processing circuit (timing_judge) 50.

[0072] The processing circuit 50 is an RTL circuit connected to the RTL module 30, but is a different RTL circuit from the RTL module 30. In this way, by including an additional RTL circuit in the wrapper module 40, even when adding a function that cannot be realized by a single RTL circuit alone, this becomes possible by having the wrapper module 40 match the input / output interface with the OpenCL kernel 20. The processing circuit 50 has two input ports for inputting count_opencl and count_rtl, which will be described later, and one output port for outputting timing_err_flag. Note that the processing circuit 50 may be integrated with the RTL module 30.

[0073] Next, the functional configuration of the OpenCL kernel 20 according to this embodiment will be described with reference to Fig. 7. The OpenCL kernel 20 according to this embodiment differs from the first embodiment in that it has an input timing determination unit 208 and an output timing determination unit 209. Note that the input RAM 201, preparation unit 202, function unit 204, termination determination unit 206, and output RAM 207 are the same as those in the first embodiment, and therefore description thereof will be omitted here.

[0074] The determination unit 203 passes count_opencl to the input timing determination unit 208. count_opencl is information that is incremented by 1 each time the RTL module 30 (i.e., the helper function RTL_module) is called, i.e., the number of times the RTL module 30 has been called. Specifically, count_opencl is a loop counter used when the OpenCL kernel 20 repeatedly calls the RTL module 30, or a counter variable defined to count the number of times the RTL module 30 has been repeatedly called. When count_opencl is a loop counter and the repeated calling process is performed using a for statement inside the OpenCL kernel 20, count_opencl may be a loop index of the for statement.

[0075] The function of the input timing determination unit 208 will be described in detail later.

[0076] The parsing unit 205 parses dataout output from the function unit 204 and obtains the necessary output data and flags. Then, the parsing unit 205 passes timing_err_flag and count_rtl to the output timing determination unit 209. count_rtl is a value obtained by counting the number of cycles by one from immediately after the RTL module 30 is started.

[0077] If timing_err_flag is set to True, the output timing determination unit 209 determines that the communication between the OpenCL kernel 20 and the RTL module 30 is not operating as desired, and issues an error notification. If timing_err_flag is set to False, the output timing determination unit 209 calculates the difference between count_rtl, which is the internal counter information of the RTL module 30, and pre_count_rtl, which is the internal counter information of the RTL module 30 at the time of the previous call. If the difference is not a predetermined number of cycles, the output timing determination unit 209 determines that the RTL module 30 is not outputting output data at predetermined cycles, and issues an error notification.

[0078] On the other hand, if the difference is equal to the predetermined cycle, the output timing determination unit 209 notifies the parsing unit 205 that the difference is equal to the predetermined cycle. Upon receiving the notification, the parsing unit 205 stores the valid output data output together with the valid flag in the output RAM 207 when a valid flag is output from the RTL module 30.

[0079] Next, the function of the input timing determination unit 208 will be described in detail with reference to FIG.

[0080] The OpenCL kernel 20 inputs datain_2 in addition to datain_0 and datain_1 to the wrapper module 40. The wrapper module 40 inputs count_opencl stored in datain_2 to the processing circuit 50. In addition, the RTL module 30 inputs count_rtl to the processing circuit 50.

[0081] The processing circuit 50, which functions as the input timing determination unit 208, determines whether the RTL module 30 receives data from the OpenCL kernel 20 at a predetermined timing. Specifically, the processing circuit 50 determines whether the difference between count_opencl in the current cycle and pre_count_opencl stored at the time of the previous call is a predetermined number of cycles. The processing circuit 50 also determines whether the difference between count_rtl in the current cycle and pre_count_rtl stored at the time of the previous call is a predetermined number of cycles. The processing circuit 50 sets timing_err_flag to True and outputs it when at least one of the difference between the values ​​of count_opencl and pre_count_opencl and the difference between the values ​​of count_rtl and pre_count_rtl is not the predetermined number of cycles. On the other hand, the processing circuit 50 sets timing_err_flag to False and outputs it when both the difference between the values ​​of count_opencl and pre_count_opencl and the difference between the values ​​of count_rtl and pre_count_rtl are the predetermined number of cycles.

[0082] For example, if the RTL module 30 is configured to receive data from the OpenCL kernel 20 every cycle, the difference between the values ​​of count_opencl and pre_count_opencl and the difference between the values ​​of count_rtl and pre_count_rtl will both be 1. However, if the RTL module 30 is not called every cycle, the difference between the values ​​of count_opencl and pre_count_opencl will be 1, but the difference between the values ​​of count_rtl and pre_count_rtl will be greater than 1. In this way, if at least one of the difference between the values ​​of count_opencl and pre_count_opencl and the difference between the values ​​of count_rtl and pre_count_rtl is not 1, the processing circuit 50 sets timing_err_flag to True and outputs it. On the other hand, if the difference between the values ​​of count_opencl and pre_count_opencl and the difference between the values ​​of count_rtl and pre_count_rtl are both 1, the processing circuit 50 sets timing_err_flag to False and outputs it.

[0083] Next, the operation of the OpenCL kernel 20 according to this embodiment will be described.

[0084] FIG. 8 is a flowchart showing the flow of input / output control processing by the OpenCL kernel 20.

[0085] In step S200 of Fig. 8, the preparation unit 202 executes the same process as in step S100 of Fig. 4. Then, the process of the preparation unit 202 proceeds to step S201.

[0086] In step S201, the preparation unit 202 executes initialization processing. Specifically, the preparation unit 202 stores 0 in count_opencl, count_rtl, and pre_count_rtl in addition to datain_0 and write_addr. The preparation unit 202 also sets False to datain_1, req_ready, req_addr, valid_flag_out, and finish_flag. Then, the processing of the preparation unit 202 proceeds to step S202.

[0087] In step S202, the determination unit 203 increments count_opencl.

[0088] The processing from step S203 to step S207 is the same as the processing from step S102 to step S106 in FIG. 4, and therefore a description thereof will be omitted.

[0089] In step S208, count_opencl is stored in datain_2, and the process of the determination unit 203 then proceeds to step S209.

[0090] In step S209, the function unit 204 and the input timing determination unit 208 store in dataout the return values ​​from the RTL module 30 and the processing circuit 50 that have been executed using datain_0, datain_1, and datain_2 as arguments. Then, the processing of the function unit 204 and the input timing determination unit 208 proceeds to step S210.

[0091] In step S210, the parsing unit 205 stores the values ​​obtained by parsing dataout using a predetermined bit mask in dataout_0, req_addr, req_ready, write_addr, valid_flag_out, and finish_flag. Furthermore, the parsing unit 205 stores the values ​​obtained by parsing dataout using a predetermined bit mask in count_rtl and timing_err_flag. Then, the processing of the parsing unit 205 proceeds to step S211.

[0092] In step S211, the output timing determination unit 209 determines whether the RTL module 30 has not received input data from the OpenCL kernel 20 at a predetermined timing. In other words, the output timing determination unit 209 determines whether True is stored in timing_err_flag obtained in step S210. If True is set in timing_err_flag (step S211: YES), the output timing determination unit 209 proceeds to step S214. On the other hand, if False is set in timing_err_flag (step S211: NO), the output timing determination unit 209 proceeds to step S212.

[0093] In step S212, the output timing determination unit 209 determines whether the difference between count_rtl and pre_count_rtl is a predetermined cycle (1 in the example shown in FIG. 8). If the difference between count_rtl and pre_count_rtl is a predetermined cycle (1 in the example shown in FIG. 8) (step S212: YES), the output timing determination unit 209 proceeds to step S213. On the other hand, if the difference between count_rtl and pre_count_rtl is not a predetermined cycle (1 in the example shown in FIG. 8) (step S212: NO), the output timing determination unit 209 proceeds to step S214.

[0094] In step S213, the input timing determination unit 208 stores the value stored in count_rtl in pre_count_rtl. Then, the processing of the input timing determination unit 208 proceeds to step S215.

[0095] In step S214, the output timing determination unit 209 issues an error notification indicating that the RTL module 30 has not received input data at the predetermined cycles or has not output output data at the predetermined cycles. Then, the output timing determination unit 209 ends this input / output control process.

[0096] The processing from step S215 to step S218 is the same as the processing from step S109 to step S112 in FIG. 4, and therefore a description thereof will be omitted.

[0097] Next, the effects of the input / output control device 10 according to this embodiment will be described.

[0098] The RTL module is expected to be called by the OpenCL kernel at predetermined cycles and receive input data. However, even if the OpenCL kernel intends to input input data at predetermined cycles, there are cases where the RTL module does not receive the input data at the predetermined cycles due to delays in reading the input data from the OpenCL kernel, for example. Delays in reading input data can occur when the input data input by the OpenCL kernel is stored in DRAM, which has a longer access latency than SRAM, or when memory access conflicts occur due to other accesses. Furthermore, even if the RTL module intends to output output data at predetermined cycles, the OpenCL kernel may not receive the output data at the predetermined cycles. In this case, a pipeline stall may occur, preventing the desired results from being obtained. However, because the generated hardware program appears to operate without errors, identifying the cause of the problem was difficult.

[0099] To address this issue, the OpenCL kernel 20 according to this embodiment notifies an error if at least one of the difference between the number of times the OpenCL kernel 20 has called the RTL module 30 and the number of times the OpenCL kernel 20 last called the RTL module 30, and the difference between the number of cycles since the RTL module 30 was started and the number of cycles since the previous RTL module 30 was started, is not a predetermined number of cycles. This makes it possible to know if the RTL module 30 is not receiving input data at predetermined cycles or if the RTL module 30 is not outputting output data at predetermined cycles.

[0100] [Variations] The present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the spirit and scope of the present invention.

[0101] For example, the various processes executed by the FPGA in each of the above embodiments may be executed by various processors other than the FPGA. In this case, an example of the processor is a GPU (Graphics Processing Unit). Furthermore, the input / output control process may be executed by one of these various processors, or may be executed by a combination of two or more processors of the same or different types (for example, multiple FPGAs, or a combination of a GPU and an FPGA, etc.). [Explanation of symbols]

[0102] 10 Input / Output Control Unit 11 FPGA 12 DRAM 13 SRAM 19 Bus 20 OpenCL Kernels 30 RTL modules 40 Wrapper Modules 50 Processing circuit 201 Input RAM 202 Preparation Department 203 Decision Section 204 Function section 205 Perth Department 206 End Judgment Section 207 Output RAM 208 Input timing determination unit 209 Output timing determination unit

Claims

1. An OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language) calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; When the RTL circuit outputs the output data from a plurality of output ports, a wrapper module including the RTL circuit multiplexes the plurality of output ports into one output port and adjusts the output data to a bit width of a variable provided by the OpenCL kernel. Input / output control method.

2. An OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language) calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the RTL circuit outputs an input request flag to the OpenCL kernel requesting valid input data a predetermined number of cycles before the cycle in which the OpenCL kernel inputs valid input data; the OpenCL kernel inputs the valid input data to the RTL circuit in the predetermined number of cycles after the input request flag is output; Input / output control method.

3. An OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language) calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the OpenCL kernel notifies an error if at least one of a difference between the number of times the OpenCL kernel has called the RTL circuit and the number of times the OpenCL kernel called the RTL circuit last time, and a difference between the number of cycles since the RTL circuit was started and the number of cycles since the RTL circuit was last started is not equal to the predetermined number of cycles. Input / output control method.

4. An input / output control program for causing a computer to function as an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL module designed at the register transfer level as a library at every predetermined cycle, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL module together with the input data; the RTL module outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data if the RTL module requests valid input data, and inputs the invalid flag together with the invalid input data if the RTL module does not request valid input data; when the valid flag is output from the RTL module, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL module, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL module takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL module outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; When the RTL module outputs the output data from a plurality of output ports, a wrapper module including the RTL module multiplexes the plurality of output ports into one output port and adjusts the output data to a bit width of a variable provided by the OpenCL kernel. Input / output control program.

5. An input / output control program for causing a computer to function as an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL module designed at the register transfer level as a library at every predetermined cycle, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL module together with the input data; the RTL module outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data if the RTL module requests valid input data, and inputs the invalid flag together with the invalid input data if the RTL module does not request valid input data; when the valid flag is output from the RTL module, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL module, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL module takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL module outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the RTL module outputs an input request flag to the OpenCL kernel requesting valid input data a predetermined number of cycles before the cycle in which the OpenCL kernel inputs valid input data; the OpenCL kernel inputs the valid input data to the RTL module in the predetermined number of cycles after the input request flag is output; Input / output control program.

6. An input / output control program for causing a computer to function as an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL module designed at the register transfer level as a library at every predetermined cycle, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL module together with the input data; the RTL module outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data if the RTL module requests valid input data, and inputs the invalid flag together with the invalid input data if the RTL module does not request valid input data; when the valid flag is output from the RTL module, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL module, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL module takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL module outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the OpenCL kernel notifies an error if at least one of a difference between the number of times the OpenCL kernel has called the RTL module and the number of times the OpenCL kernel called the RTL module last time, and a difference between the number of cycles since the RTL module was started and the number of cycles since the RTL module was last started is not equal to the predetermined number of cycles. Input / output control program.

7. An input / output control device including an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; When the RTL circuit outputs the output data from a plurality of output ports, a wrapper module including the RTL circuit multiplexes the plurality of output ports into one output port and adjusts the output data to a bit width of a variable provided by the OpenCL kernel. Input / output control unit.

8. An input / output control device including an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the RTL circuit outputs an input request flag to the OpenCL kernel requesting valid input data a predetermined number of cycles before the cycle in which the OpenCL kernel inputs valid input data; the OpenCL kernel inputs the valid input data to the RTL circuit in the predetermined number of cycles after the input request flag is output; Input / output control unit.

9. An input / output control device including an OpenCL kernel in an OpenCL program written in OpenCL (Open Computing Language), The OpenCL kernel calls an RTL circuit designed by the register transfer level as a library at predetermined cycles, and inputs a valid flag indicating that the data is valid or an invalid flag indicating that the data is invalid to the RTL circuit together with input data; the RTL circuit outputs the valid flag or the invalid flag together with output data to the OpenCL kernel; the OpenCL kernel inputs the valid flag together with the valid input data when the RTL circuit requests valid input data, and inputs the invalid flag together with the invalid input data when the RTL circuit does not request valid input data; when the valid flag is output from the RTL circuit, the OpenCL kernel stores the valid output data output together with the valid flag, and when the invalid flag is output from the RTL circuit, the OpenCL kernel does not store the invalid output data output together with the invalid flag. when the valid flag is input from the OpenCL kernel, the RTL circuit takes in the valid input data input together with the valid flag, and when the invalid flag is input from the OpenCL kernel, does not take in the invalid input data input together with the invalid flag; the RTL circuit outputs the valid flag together with the valid output data when the output data is valid, and outputs the invalid flag together with the invalid output data when the output data is invalid; the OpenCL kernel notifies an error if at least one of a difference between the number of times the OpenCL kernel has called the RTL circuit and the number of times the OpenCL kernel called the RTL circuit last time, and a difference between the number of cycles since the RTL circuit was started and the number of cycles since the RTL circuit was last started is not equal to the predetermined number of cycles. Input / output control unit.

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