Control program, information processing device, and control method

Abstract

To avoid the peaks of the power consumption of CPUs from synchronizing with one another and equalize the power consumption while keeping the performance.SOLUTION: The processors of an information processor 10 calculate the delay time of a self-processor so that the processors will have different delay times from each other when the synchronization of the power consumptions of the processors is detected, disclose the data of the power consumption of a point of time in the past to the delay times to other processors as data of current power consumptions, and perform load dispersion by using the data of the power consumption disclosed to other processor and the data of power consumption disclosed by other processors.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a control program and the like that has an architecture that improves the efficiency of data transfer. [Background technology]

[0002] When a single central processing unit (CPU) repeatedly accesses system resources, peaks and valleys alternate in power consumption. For example, this applies when the same processing is performed repeatedly using a loop, such as storage input / output (IO) processing or routine batch processing of a database.

[0003] In a distributed processing system consisting of multiple CPUs, dynamic load balancing is not performed when the load on any of the CPUs is low. Without dynamic load balancing, the allocation of CPU processing is uneven, so the peak and bottom of the power consumption of each CPU do not align, and the power consumption of the entire system does not exceed the total power consumption amount determined at the time of design. Figure 11 is a reference diagram showing the transition of power consumption when dynamic load balancing is not performed. As shown in Figure 11, without dynamic load balancing, the peak and bottom of the power consumption of each CPU do not align. And the power consumption of the entire system does not exceed the total power consumption amount.

[0004] On the other hand, if the load on any CPU is high or low, dynamic load balancing between CPUs is performed at an appropriate time. When dynamic load balancing is performed, the allocation of processing to a CPU is performed by checking the status of other CPUs at runtime, and feedback is applied to even out the allocation of processing. As a result, the peaks and valleys of power consumption of each CPU gradually become aligned. This phenomenon is called the synchronization phenomenon. Figure 12 is a reference diagram showing the transition of power consumption when dynamic load balancing is performed. As shown in the upper diagram of Figure 12, when dynamic load balancing is performed, the peaks and valleys of power consumption of each CPU become aligned, and the synchronization phenomenon occurs.

[0005] When a synchronization phenomenon occurs, the peak and bottom of the power consumption of each CPU are aligned, and the power consumption of the entire system at peak times may reach the total power consumption amount determined at the time of design. In such a case, the power consumption of the entire system cannot exceed the total power consumption amount determined at the time of design, so the system temporarily lowers the CPU clock to reduce performance (this is called power capping). As shown in the lower diagram of Figure 12, when a synchronization phenomenon occurs, the power consumption of the entire system reaches the total power consumption amount at the peak, but cannot exceed it, so the total power consumption is capped. This reduces CPU performance.

[0006] One way to avoid power capping is to shift the timing (phase) of the peak and bottom of one cycle of CPU power consumption. For example, a system could avoid power capping by slowing down the CPU clock on a per-CPU basis or by inserting a short sleep period within a process to shift the phase. However, slowing down the CPU clock on a per-CPU basis or inserting a short sleep period within a process will still result in a decrease in CPU performance.

[0007] Furthermore, a technology has been disclosed that can change the phase of tasks in a task queue and tasks to be newly added to a task queue by selecting and adding a task queue to store tasks with the same period to the same queue, so that the processing volume of tasks that can be estimated from the processing volume period is distributed among task queues (see, for example, Patent Document 1).

[0008] Furthermore, a technique has been disclosed in which the performance of a processor is controlled by changing the power mode during program execution (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-227708 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-225263 Summary of the Invention [Problem to be solved by the invention]

[0010] However, in a distributed processing system consisting of multiple CPUs, dynamic load balancing equalizes the utilization rate of each CPU, but the peak power consumption of each CPU is synchronized, making it impossible to equalize power consumption while maintaining performance.

[0011] For example, techniques such as slowing down the CPU clock on a per-CPU basis or inserting short periods of sleep within processing can avoid synchronizing the peak power consumption of each CPU, but this results in a decrease in performance.

[0012] Furthermore, with the technology of varying task phases, if the amount of processing for each task can be estimated in advance, the task phases can be varied, making it possible to avoid the synchronization of peak power consumption for each CPU. However, if the amount of processing for each task cannot be estimated in advance, it is difficult to avoid the synchronization of peak power consumption for each CPU. As a result, the peak power consumption for each CPU is synchronized, making it impossible to level out power consumption while maintaining performance.

[0013] Furthermore, the technology for changing power modes is not a technology for dynamic load balancing between CPUs in the first place.

[0014] One aspect is to avoid the peak power consumption of each CPU from being synchronized, and to level out power consumption while maintaining performance. [Means for solving the problem]

[0015] In the first proposal, the control program is a control program for each control unit in an information processing device consisting of multiple control units, and when synchronization of the power consumption of each control unit is detected, the control program calculates the delay time of its own control unit so that the delay time is different for each control unit, discloses power consumption data at a past point in time relative to the delay time to other control units as current power consumption data, and causes a computer to execute a process of load balancing using the power consumption data disclosed to the other control units and the power consumption data disclosed by the other control units. [Effects of the Invention]

[0016] According to one embodiment, it is possible to prevent peak power consumption of each CPU from occurring simultaneously, and to equalize power consumption while maintaining performance. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a hardware configuration diagram of a computer system. [Figure 2] FIG. 2 is a diagram illustrating an example of a configuration of a processor. [Figure 3] FIG. 3 is a diagram illustrating an example of a functional configuration of the information processing device according to the embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of virtual power consumption information. [Figure 5] FIG. 5 is a diagram illustrating an example of a flow of monitoring control according to the embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of a flowchart of the synchronization relaxation control process according to the embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of a flowchart of the phase movement control process. [Figure 8] FIG. 8 is a diagram illustrating another example of a flowchart of the phase movement control process. [Figure 9] FIG. 9 is a diagram illustrating an example of a flowchart of the load distribution process. [Figure 10] FIG. 10 is a diagram illustrating the effect of the control process according to the embodiment. [Figure 11]FIG. 11 is a reference diagram showing the transition of power consumption when dynamic load balancing is not performed. [Figure 12] FIG. 12 is a reference diagram showing the transition of power consumption when dynamic load balancing is performed. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the control program, information processing device, and control method according to the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. Furthermore, the embodiments can be combined as appropriate within a consistent range.

[0019] 1 is a hardware configuration diagram of a computer system 1. The computer system 1 includes an information processing device 10, a drive device 20, and a display device 30.

[0020] The information processing device 10 includes processors 11 and 12, a memory 13, a network device 14, a storage device 15, an SSD (Solid State Drive) 16, and an HDD (Hard Disk Drive) 17. The processors 11 and 12, the memory 13, the network device 14, the storage device 15, the drive device 20, and the display device 30 are interconnected by a bus 40.

[0021] Each of the processors 11 and 12 has multiple cores. The processors 11 and 12 load and execute a program on the memory 13. When executing the program, the cores of the processors 11 and 12 each execute a thread included in the program.

[0022] The processors 11 and 12 run programs to operate applications. By running the applications, the processors 11 and 12 cause the network device 14 to communicate with the outside via the network switch 2. By running the applications, the processors 11 and 12 also perform data transfers, reading and writing data from and to the SSD 16 and HDD 17, via the storage device 15. Control of data transfer processes using the network device 14 or the storage device 15 by the processors 11 and 12 in this embodiment will be described in detail later. Here, while two processors 11 and 12 are shown in FIG. 1, there is no particular limitation on the number of processors as long as it is not limited to one.

[0023] The network device 14 is a high-speed IO device such as InfiniBand. The network device 14 is connected to the network switch 2. Upon receiving an instruction from the processor 11 or 12, the network device 14 transmits and receives data to and from an external device via the network switch 2.

[0024] The SSD 16 and the HDD 17 are large-capacity auxiliary storage devices that store various programs and data.

[0025] The storage device 15 is a high-speed IO device such as NVMe. The storage device 15 is connected to an SSD 16 and an HDD 17. The storage device 15 receives instructions from the processor 11 or 12 and executes reading and writing of data from and to the SSD 16 and the HDD 17.

[0026] The drive device 20 has a removable portable storage medium, such as a magnetic disk or optical disk, inserted therein, and writes and reads data to and from the inserted portable storage medium.

[0027] The display device 30 displays the images transmitted from the processors 11 and 12. The user can receive the information by checking the display device 30.

[0028] An example of the configuration of the processors 11 and 12 will now be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the processors. As shown in Fig. 2, two processors 11a and 11b are mounted in one CPU socket #1. Also, two processors 12a and 12b are mounted in one CPU socket #2. In other words, multi-socket and multi-core are realized.

[0029] FIG. 3 is a diagram illustrating an example of the functional configuration of an information processing device according to an embodiment. The information processing device 10 according to the embodiment performs control to mitigate a synchronization phenomenon that occurs during load balancing in a multiprocessor. Specifically, when load balancing is performed, the peaks and troughs of the power consumption of each processor (CPU) become aligned, resulting in a synchronization phenomenon. When a synchronization phenomenon occurs, the peaks and troughs of the power consumption of each CPU become aligned, and the power consumption of the entire system may reach the total power consumption amount determined at the time of design at the peak. In such a case, the power consumption of the entire system cannot exceed the total power consumption amount determined at the time of design, so the information processing device 10 performs power capping, which temporarily reduces the CPU clock speed to reduce performance. Therefore, the information processing device 10 performs control to shift the phase of the power consumption of each CPU to mitigate the synchronization of the power consumption of each CPU without performing power capping.

[0030] Here, we explain the synchronization phenomenon that occurs during load balancing. When a large number of oscillators are interconnected and their oscillation speeds influence each other, synchronization of oscillators occurs, a phenomenon widely observed in nature. The Kuramoto model is a well-known mathematical model that explains synchronization. References on the Kuramoto model include [Y.Kuramoto 75] Y.Kuramoto.; In International Symposium on Mathematical Problems in Theoretical Physics, volume 39 of Lecture Notes in Physics, page 420. Springer, New York, (1975). [Y.Kuramoto 84] Y.Kuramoto.: Chemical Oscillations, Waves, and Turbulence. Springer, Berlin, (1984). Also, [Nagasaki 2016] Nagasaki et al., Analysis of Explosive Synchronization Transition on Complete Bipartite Graph Structures, 2016 National Conference of the Japanese Society for Artificial Intelligence.

[0031] In the embodiment, by applying the CPU power fluctuations to the Kuramoto model as an oscillator, each processor 11, 12 monitors the synchronization status and detects a synchronization phenomenon. When each processor 11, 12 detects a synchronization phenomenon, it discloses to the other processors power consumption data from a past point in time corresponding to a delay time calculated based on a predetermined calculation as current power consumption data. Each processor 11, 12 then performs dynamic load balancing using the disclosed power consumption data of each processor. As a result, the information processing device 10 can perform dynamic load balancing using intentionally shifted power consumption data to be referenced, thereby shifting power consumption peaks and leveling power consumption while maintaining performance.

[0032] The information processing device 10 has control units 11-1 and 11-2 and storage units 13-1 and 13-2. The control units 11-1 and 11-2 correspond to the processors 11 and 12 shown in Fig. 1, respectively. The storage units 13-1 and 13-2 correspond to the memory 13 shown in Fig. 1.

[0033] Control unit 11-1 is a processing unit that controls the entire information processing device 10, and includes a monitoring control unit 111, a synchronization relaxation control unit 112, and a load distribution unit 113. Storage unit 13-1 includes a FIFO (First In First Out) buffer 131 and virtual power consumption information 132. Note that control unit 11-2 has the same functions as control unit 11-1, and therefore its description will be omitted. Note that storage unit 13-2 has the same functions as storage unit 13-1, and therefore its description will be omitted.

[0034] The FIFO buffer 131 is a cyclic buffer that stores the power consumption value of the processor 11 (CPU) at each point in time. The points in time for storage may be, for example, every 30 minutes or every hour, as long as they are determined in advance.

[0035] The virtual power consumption information 132 is information on power consumption to be disclosed as the current power consumption. The virtual power consumption information 132 is set by the monitoring control unit 111.

[0036] An example of the virtual power consumption information 132 will now be described with reference to FIG. 4. FIG. 4 is a diagram showing an example of the virtual power consumption information. As shown in FIG. 4, the virtual power consumption information 132 stores a current power consumption value, a virtual frequency, and a virtual phase in association with each other. The current power consumption value is a virtual current value that is disclosed to other processors as the current power consumption value. The current power consumption value is a power consumption value at a past point in time relative to a delay time calculated by the own processor based on a predetermined calculation. The predetermined calculation is performed by the synchronization relaxation control unit 112. The virtual frequency is the frequency of the power consumption at the time when the current power consumption value is calculated. The virtual phase is the phase of the power consumption at the time when the current power consumption value is calculated.

[0037] Returning to FIG. 3 , the monitoring control unit 111 monitors the power consumption data of each processor. For example, the monitoring control unit 111 stores the power consumption values ​​of its own processor (CPU) in the FIFO buffer 131 at predetermined time intervals. The monitoring control unit 111 then passes the power consumption values ​​stored in the FIFO buffer 131 through a low-pass filter. The low-pass filter is used to calculate a moving average. The moving average is used to avoid the impact of a single abnormal value. That is, when the delay time is 0, which indicates the initial value, the monitoring control unit 111 calculates a moving average of the power consumption values ​​stored in the FIFO buffer 131 from the most recent power consumption value to the most recent period. Furthermore, when a delay time is set by the synchronization relaxation control unit 112 (described later), the monitoring control unit 111 calculates a moving average of the power consumption values ​​from the power consumption value at a past point corresponding to the delay time to the most recent period. The monitoring control unit 111 then stores the calculated moving average as the current power consumption value in the virtual power consumption information 132. The monitoring control unit 111 then discloses the current power consumption values ​​stored in the virtual power consumption information 132 to the other processors at predetermined time intervals or in response to a request from the other processors.

[0038] The monitoring control unit 111 also has a trigonometric function approximation mechanism and performs a Fourier transform to calculate the frequency and phase of the power consumption at the time when the current power consumption value is calculated.The monitoring control unit 111 then stores the frequency and phase of the power consumption as the virtual frequency and virtual phase in the virtual power consumption information 132.

[0039] When the synchronization mitigation control unit 112 detects that the power consumption of each processor is synchronized, it calculates a delay time calculated based on a predetermined calculation. In other words, the synchronization mitigation control unit 112 calculates the delay time of its own processor so that each processor has a different delay time. For example, the synchronization mitigation control unit 112 collects the frequency and phase of the power consumption of each processor when the power fluctuations of each processor are considered as oscillators. The frequency and phase of the power consumption of each processor are calculated asynchronously by the monitoring control unit 111 of each processor. The synchronization mitigation control unit 112 then calculates an order parameter η from the frequency and phase of the power consumption of each processor. The order parameter η here represents the degree of synchronization and corresponds to the order parameter η in the Kuramoto model. The order parameter η is a point within a unit circle with a radius of "1" on a complex plane, and the order parameter distance |η| is the distance from the origin 0. The closer the order parameter distance |η| is to 1, the stronger the synchronization, and the closer it is to 0, the more disordered it is. The synchronization relaxation control unit 112 determines whether or not synchronization is occurring by comparing the order variable distance |η| with a predetermined synchronization threshold p that identifies whether or not synchronization is occurring.

[0040] And when it is determined that synchronization is in progress, the phase shift control unit 112 performs phase shift control. Phase shift control is control that assumes that the power consumption of its own processor and other processors is at the same phase (situation), and moves the phase in order to avoid becoming the same phase as other processors. That is, phase shift control uses the current power consumption value in its own processor as the phase difference past value. As an example, phase shift control evenly divides 360 degrees representing one cycle by the number of processors, and selects a divided section (phase) with a random number. As another example, phase shift control evenly divides 360 degrees representing one cycle by the number of processors, and selects the section (phase) corresponding to the number of its own processor among the divided sections (phases). Then, phase shift control converts the phase difference of the selected section (phase) into time to calculate the past time difference (delay time) δ. Then, phase shift control sets the calculated delay time δ to the monitoring control unit 111. After this, the monitoring control unit 111 discloses the moving average of the power consumption value in the most recent period from the power consumption value at the time point δ in the past set to other processors as the current power consumption value.

[0041] Here, the basic Kuramoto model will be described. In the Kuramoto model, it is premised on a fully connected graph in which all oscillators are connected to each other, and the motion of each oscillator i is given by the following equation (1). Note that K in Equation (1) is the coupling strength, N is the number, and ω is the natural frequency.

Number

[0042] And the order parameter η and the distance r are determined by the following equation (2).

Number

[0043] When N is sufficiently large, there is a threshold value Kc for the coupling strength. When K ≥ Kc, a synchronization phenomenon always occurs, and when k < Kc, synchronization does not occur. Kc mentioned here is determined by the following equation (3).

Number

[0044] Note that the synchronization relaxation control unit 112 may calculate the order variable η by applying the natural frequency and phase of the power consumption of its own processor to ωi and θi respectively, applying the phase of the power consumption of other processors to θj. The natural frequency is the frequency of its own processor i when there is no influence from other oscillators (other processors). However, in reality, since they affect each other, the natural frequency of its own processor i becomes the frequency at a certain point in time. In the Kubamoto model, when the order variable η is close to 1, the relationship K≧Kc holds (Kubamoto transfer occurs), and when the order variable η is close to 0, the relationship K<Kc holds. Therefore, the synchronization relaxation control unit 112 determines that it is in a synchronous state if the order variable distance |η| is greater than or equal to the synchronization threshold p for identifying whether it is a predetermined synchronization, and determines that it is in an asynchronous state if the order variable distance |η| is less than the synchronization threshold p.

[0045] The load distribution unit 113 performs dynamic load distribution according to each current power consumption value in the virtual power consumption information 132 stored in each processor. For example, as a method of dynamic load distribution, the load distribution unit 113 may apply a method of equalizing the load (task) size between two processors determined by a random algorithm. Such methods include the work stealing method, the work sharing method, etc., but any method other than static load distribution that performs pre-planned load distribution may be used. As an example, Japanese Unexamined Patent Application Publication No. 2020-144737, which improves load distribution among multiple processors, can be cited.

[0046] FIG. 5 is a diagram showing an example of the flow of monitoring control according to an embodiment. As shown in FIG. 5, the monitoring control unit 111 reads the power consumption value from the power consumption monitoring device 111a every predetermined time and stores it in the FIFO buffer 131 (S10 ). Note that the power consumption monitoring device 111a is not limited to hardware and may be software. The FIFO buffer 131 accumulates data of time and power consumption values in the FIFO order.

[0047] The monitoring control unit 111 passes the power consumption values ​​from the read index to the most recent period, which are stored in the FIFO buffer 131, through the low-pass filter 111b to calculate a moving average. For example, when the delay time setting value δ is 0, which indicates the initial value, the read index of the FIFO buffer 131 indicates the most recent position, so the low-pass filter 111b calculates a moving average of the power consumption values ​​from the most recent power consumption value indicated by the read index to the most recent period (S110). Furthermore, when the delay time setting value δ is set, the monitoring control unit 111 resets the read index corresponding to the delay time setting value δ (S111). Then, the low-pass filter 111b calculates a moving average of the power consumption values ​​from the reset read index to the most recent period (S110). That is, the monitoring control unit 111 calculates a moving average of the power consumption values ​​for the most recent period, moving backward from the power consumption value at a past point corresponding to the delay time.

[0048] Then, at predetermined time intervals or in response to a request from another processor, the monitoring control unit 111 writes the moving average corresponding to the read index into the current power consumption value of the virtual power consumption information 132 (S120). The monitoring control unit 111 also uses the trigonometric function approximation mechanism 111c to calculate the frequency and phase of the power consumption at the time when the current power consumption value was calculated, and stores them as a virtual frequency and virtual phase in the virtual power consumption information 132 (S130). The monitoring control unit 111 then discloses the current power consumption value stored in the virtual power consumption information 132 to the other processors (S140).

[0049] As a result, the load distribution unit 113 executes dynamic load distribution in accordance with the current power consumption values ​​disclosed by each processor, thereby shifting the phase of the power consumption of each processor. In other words, the monitoring control unit 111 exchanges data on power consumption at a certain point in the past based on the delay time that differs for each processor, thereby enabling the information processing device 10 to avoid the peak power consumption of each processor being synchronized due to load distribution.

[0050] 6 is a diagram illustrating an example of a flowchart of the synchronization relaxation control process according to the embodiment. The synchronization relaxation control unit 112 requests the latest power consumption information from its own processor and other processors at a predetermined timing. As shown in FIG. 6, the synchronization relaxation control unit 112 collects the latest power consumption information (phase, frequency) from all processors (step S11).

[0051] Then, the synchronization relaxation control unit 112 calculates the order parameter η using the collected power consumption information (phase, frequency) from all the processors (step S12). For example, the synchronization relaxation control unit 112 calculates the order parameter η by applying the power consumption information (phase, frequency) of all the processors to equations (1) and (2).

[0052] Then, the synchronization relaxation control unit 112 determines whether the order variable distance |η| is equal to or greater than the synchronization threshold p (step S13). If it is determined that the order variable distance |η| is equal to or greater than the synchronization threshold p (step S13; Yes), the synchronization relaxation control unit 112 determines that a synchronized state exists, and executes a phase shift control process (step S14). A flowchart of the phase shift control process will be described later. Then, the synchronization relaxation control unit 112 proceeds to step S15.

[0053] On the other hand, if it is determined that the order parameter distance |η| is not equal to or greater than the synchronization threshold p (step S13; No), the synchronization relaxation control unit 112 determines that the state is asynchronous, and proceeds to step S15.

[0054] In step S15, the synchronization relaxation control unit 112 determines whether to terminate the synchronization relaxation control (step S15). For example, the synchronization relaxation control unit 112 determines to terminate the synchronization relaxation control when an operation to terminate the execution of the synchronization relaxation control is performed or when an interrupt to terminate the control is received. When it is determined not to terminate the synchronization relaxation control (step S15; No), the synchronization relaxation control unit 112 proceeds to step S11.

[0055] On the other hand, if it is determined that the synchronization relaxation control is to be ended (step S15; Yes), the synchronization relaxation control unit 112 ends the synchronization relaxation control process.

[0056] 7 is a diagram showing an example of a flowchart of the phase shift control process. As shown in FIG. 7, the phase shift control process sets a virtual frequency of its own power consumption to f (step S21). For example, the phase shift control process copies the virtual frequency stored in its own virtual power consumption information 132 to f.

[0057] Then, the phase shift control process calculates the delay time δ by substituting the virtual frequency f into the following equation (step S22). That is, the phase shift control process equally divides 360 degrees, which represents one cycle, by the total number of processors (CPUs), N, and selects the divided sections (phases) using random numbers. Note that N in the following equation is the total number of processors (CPUs). Furthermore, rand(0,N) is a function that calculates uniform random numbers between the lower limit "0" and the upper limit "N". δ=(1 / f)×(rand(0,N) / N)

[0058] Then, the phase movement control process sets the calculated delay time δ as its own delay time setting value (step S23). For example, the phase movement control process copies the delay time δ to its own delay time setting value. After this, the phase movement control process sets the delay time setting value δ in the monitoring control unit 111.

[0059] 8 is a diagram showing another example of a flowchart of the phase shift control process. As shown in FIG. 8, the phase shift control process sets the virtual frequency of its own power consumption to f (step S31). For example, the phase shift control process copies the virtual frequency stored in its own virtual power consumption information 132 to f.

[0060] Then, the phase shift control process calculates the delay time δ by substituting the virtual frequency f into the following equation (step S32). That is, the phase shift control equally divides 360 degrees, which represents one cycle, by the total number of CPUs N, and selects a partition (phase) from the divided partitions (phases) that corresponds to the ID (CPU ID) corresponding to the own processor. Note that N in the following equation is the total number of processors (CPUs). δ=(1 / f)×(CPUID / N)

[0061] Then, the phase movement control process sets the calculated delay time δ as its own delay time setting value (step S33). For example, the phase movement control process copies the delay time δ to its own delay time setting value. After this, the phase movement control process sets the delay time setting value δ in the monitoring control unit 111.

[0062] Thereafter, the phase movement control process sets the delay time setting value δ in the monitoring control unit 111. Then, the monitoring control unit 111 discloses data on power consumption at a certain point in the past (current power consumption value) based on the delay time setting value δ of its own processor, which is a different delay time setting value for each processor.

[0063] 9 is a diagram illustrating an example of a flowchart of the load balancing process according to the embodiment. The load balancing unit 113 executes the load balancing process, for example, when its own current power consumption value is disclosed. As shown in FIG. 9, the load balancing unit 113 collects the latest power consumption information (current power consumption value) from all processors (step S41). Then, the load balancing unit 113 executes dynamic load balancing according to the collected current power consumption values ​​of all processors (step S42).

[0064] As a result, the load distribution unit 113 can shift the phase of the power consumption of each processor by performing dynamic load distribution according to the current power consumption values ​​disclosed by each processor. In other words, the monitoring control unit 111 exchanges data on power consumption at a certain point in the past based on delay times that differ for each processor, so that the information processing device 10 can avoid the peak power consumption of each processor being synchronized due to load distribution.

[0065] FIG. 10 is a diagram illustrating the effect of control processing by an information processing device according to an embodiment. In FIG. 10, the information processing device 10 includes three CPUs (processors). As shown in the upper diagram of FIG. 10, when each CPU detects synchronization of the power consumption of the three CPUs, it publishes the current power consumption value to the other CPUs as a power consumption value at a past point in time based on a delay time that differs for each CPU. Therefore, each CPU can dynamically distribute loads according to the published power consumption value, thereby shifting overlapping peak phases so that they do not overlap. Here, the power consumption peaks of the three CPUs are slightly different from each other.

[0066] As a result, the information processing device 10 can autonomously and asynchronously shift the phase without changing the load balancing process or temporarily slowing down the CPU clock to reduce performance (power capping) as a system. As a result, the information processing device 10 can avoid the peak power consumption of each CPU from being synchronized, and can level out the power consumption while maintaining performance. As shown in the lower diagram of Figure 10, the information processing device 10 can level out the power consumption while maintaining performance because the phase shift in the power consumption of each CPU prevents the overall power consumption from reaching the total power consumption amount.

[0067] [Effects of the Example] According to the above embodiment, the information processing device 10 includes multiple control units 11-1 and 11-2. When the control unit 11-1 detects synchronization of the power consumption of each of the control units 11-1 and 11-2, it calculates the delay time of its own control unit 11-1 so that the delay time is different for each of the control units 11-1 and 11-2. The control unit 11-1 discloses data on power consumption at past times relative to the delay time to the other control units 11-2 as data on current power consumption. The control unit 11-1 performs load balancing using the power consumption data disclosed to the other control units 11-2 and the power consumption data disclosed by the other control units 11-2. In this way, the information processing device 10 can avoid synchronization of peak power consumption of each of the control units 11-1 and 11-2 by load balancing using power consumption data at different times relative to different delay times, thereby leveling out power consumption.

[0068] Furthermore, according to the above embodiment, the control unit 11-1 equally divides one cycle of the power consumption period by the number of the control units 11-1 and 11-2, selects a partition for its own control unit 11-1 from the divided partitions based on a random number, and calculates the delay time corresponding to the selected partition. This allows the information processing device 10 to reliably calculate a different delay time for each of the control units 11-1 and 11-2.

[0069] Furthermore, according to the above embodiment, control unit 11-1 equally divides one cycle of the power consumption period by the number of control units 11-1 and 11-2, selects a partition for its own control unit 11-1 from the divided partitions based on the identification number assigned to each control unit 11-1 and 11-2, and calculates the delay time corresponding to the selected partition. This allows information processing device 10 to reliably calculate a different delay time for each control unit 11-1 and 11-2.

[0070] Furthermore, according to the above embodiment, the control unit 11-1 discloses to the other control unit 11-2 a moving average of power consumption data from past power consumption data to the most recent period with respect to the delay time as current power consumption data. This allows the control unit 11-1 to avoid the influence of one piece of power consumption data being abnormal data, and to disclose normal data to the other control unit 11-2.

[0071] Furthermore, according to the above embodiment, the control unit 11-1 inputs data related to the power consumption of each of the control units 11-1 and 11-2 into the Kuramoto model, outputs an order variable, and detects the synchronization of the power consumption of each of the control units 11-1 and 11-2 using the order variable. In this way, the control unit 11-1 can detect the synchronization of the power consumption using the Kuramoto model.

[0072] [others] The information including the processing procedures, control procedures, specific names, various data and parameters shown in the above documents and drawings can be changed as desired unless otherwise specified.

[0073] Furthermore, the components of each device shown in the figure are conceptual functional components and do not necessarily have to be physically configured as shown. In other words, the specific form of distribution and integration of each device is not limited to that shown. In other words, all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0074] Furthermore, all or any part of the processing functions performed by each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware using wired logic. [Explanation of symbols]

[0075] 1. Computer Systems 2. Network Switch 10. Information processing equipment 11,12 Processor 11a, 11b, 12a, 12b processors 11-1, 11-2 Control section 13-1,13-2 Storage section 13. Memory 14 Network Devices 15. Storage Devices 16 SSD 17 HDD 20 Drive device 30 Display device 40 Bus 111 Monitoring and control unit 112 Synchronization mitigation control section 113 Load distribution section 131 FIFO buffers 132 Virtual Power Consumption Information

Claims

1. A control program for each control unit in an information processing device including a plurality of control units, When the synchronization of the power consumption of each control unit is detected, the delay time of the control unit itself is calculated so that the delay time is different for each control unit, Disclose data of power consumption at a past point in time with respect to the delay time to another control unit as data of current power consumption; Distributing loads among the plurality of control units using data on power consumption disclosed to other control units and data on power consumption disclosed by other control units A control program that causes a computer to execute a process.

2. The process of calculating the delay time includes equally dividing one cycle of the power consumption period by the number of the plurality of control units, selecting a partition of the control unit itself from among the divided partitions based on a random number, and calculating the delay time corresponding to the selected partition.

2. The control program according to claim 1.

3. The process of calculating the delay time includes equally dividing one cycle of the power consumption period by the number of the plurality of control units, selecting a partition of the control unit itself from among the divided partitions based on an identification number assigned to each control unit, and calculating the delay time corresponding to the selected partition.

2. The control program according to claim 1.

4. The process of disclosing to the other control unit discloses to the other control unit a moving average of power consumption data from a past point in time to a most recent period with respect to the delay time as current power consumption data.

2. The control program according to claim 1.

5. Data relating to the power consumption of each control unit is input to the Kuramoto model, and an order variable is output, and the synchronization of the power consumption of each control unit is detected using the order variable.

2. The control program according to claim 1.

6. An information processing device comprising a plurality of control units, Each control unit: a calculation unit that calculates a delay time of its own control unit when detecting synchronization of the power consumption of each control unit so that the delay time differs for each control unit; a disclosure unit that discloses data of power consumption at a past point in time relative to the delay time to another control unit as data of current power consumption; a load distribution unit that distributes loads among the plurality of control units using data of power consumption disclosed to other control units and data of power consumption disclosed by other control units; An information processing device comprising:

7. A control method for each control unit in an information processing device including a plurality of control units, When the synchronization of the power consumption of each control unit is detected, the delay time of the control unit itself is calculated so that the delay time is different for each control unit, Disclose data of power consumption at a past point in time with respect to the delay time to another control unit as data of current power consumption; Distributing loads among the plurality of control units using data on power consumption disclosed to other control units and data on power consumption disclosed by other control units A control method characterized in that processing is executed by a computer.

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