Processing device and processing method

Abstract

To improve the processing performance of an arithmetic processing unit when data to be computed has a small number of parallels.SOLUTION: An arithmetic processing unit has: an instruction decoder that decodes an instruction; a computing unit that executes the instruction decoded by the instruction decoder and is operable as a plurality of sub computing units according to the bit width of data to be computed; and an observation unit that observes the operating state of the computing unit. When the observation unit observes that the instruction is not executed in part of the plurality of sub computing units, the instruction decoder outputs, to the computing unit, an instruction obtained by parallelizing the decoded instruction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processing device and a processing method. [Background technology]

[0002] In recent years, the number of elements that can be simultaneously executed with a SIMD (Single Instruction Multiple Data) instruction has been increasing in order to improve the processing performance of processors. In some applications or programs, this type of processor may not be able to increase the number of parallel data operations, resulting in insufficient improvement in performance. Furthermore, when a SIMD instruction is executed, parallel-arranged processors operate regardless of the number of parallel data operations, resulting in unnecessary power consumption.

[0003] Therefore, a method has been proposed to reduce power consumption by stopping the operation of arithmetic units not used in an operation when the number of parallel data to be operated is small (see, for example, Patent Document 1).Also, a method has been proposed to reduce power consumption by changing the number of SIMD operation units to be used depending on the arithmetic type of the arithmetic operation (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-47872 [Patent Document 2] US Patent Application Publication No. 2009 / 0144523 Summary of the Invention [Problem to be solved by the invention]

[0005] The technique of halting the operation of unused arithmetic units when the number of parallel data operations is small reduces power consumption but does not improve the processing performance of the processing unit, regardless of whether the architecture is one that improves data transfer efficiency.

[0006] In one aspect, the present invention aims to improve the processing performance of a processing device when the number of parallel operations on data to be processed is small. [Means for solving the problem]

[0007] According to one aspect, the processing device includes an instruction decoder that decodes an instruction, an arithmetic unit that executes the instruction decoded by the instruction decoder and is operable as a plurality of sub-arithmetic units according to the bit width of data to be operated on, Based on whether the data supplied to the plurality of sub-operation units is valid or invalid, and an observation unit that observes the operating state of the arithmetic unit, and when the observation unit observes that an instruction is not being executed in some of the plurality of sub-arithmetic units, the instruction decoder outputs an instruction that has parallelized the decoded instruction to the arithmetic unit. [Effects of the Invention]

[0008] When the number of parallel data operations to be performed is small, the processing performance of the processing unit can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processing unit according to an embodiment. [Figure 2] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. [Figure 3] FIG. 3 is a block diagram illustrating an example of an instruction decoder of FIG. 2. [Figure 4] 4 is an explanatory diagram showing an example of an instruction decoded by the instruction decoder of FIG. 3; FIG. [Figure 5] 3 is a flowchart showing an example of the operation of the arithmetic processing device of FIG. 2. [Figure 6] FIG. 6 is a flowchart showing an example of the operation of step S40 in FIG. 5. [Figure 7] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. [Figure 8]FIG. 8 is a block diagram showing an example of a computing unit and an observation unit in FIG. 7. [Figure 9] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] Fig. 1 shows an example of a processing device according to an embodiment. The processing device 100 shown in Fig. 1 is a processor such as a CPU having a function of executing multiple multiply-add operations in parallel based on, for example, a SIMD (Single Instruction Multiple Data) processing instruction.

[0012] The arithmetic processing device 100 has an instruction decoder 2, an arithmetic unit 4, and an observation unit 6. In addition to the elements shown in FIG. 1, the arithmetic processing device 100 may have an instruction buffer, a register file, etc. (not shown). A reservation station may be arranged between the instruction decoder 2 and the arithmetic unit 4.

[0013] The instruction decoder 2 decodes the operation instructions received in sequence and outputs the decoded operation instructions to the arithmetic unit 4. The arithmetic unit 4 can operate as multiple sub-arithmetic units 5. The arithmetic unit 4 executes an operation using at least one of the sub-arithmetic units 5 based on instruction information included in the operation instruction received from the instruction decoder 2. For example, the arithmetic unit 4 may be a SIMD arithmetic unit capable of executing multiple pieces of data in each of the sub-arithmetic units 5 in response to one operation instruction. Hereinafter, the operation instruction will also be simply referred to as an instruction.

[0014] In FIG. 1, the arithmetic unit 4 can be divided into two sub-arithmetic units 5, but the number of sub-arithmetic units 5 may be 2 n (n is an integer equal to or greater than 1), such as four or eight. For example, when the bit width of data received from the instruction decoder 2 is 128 bits, the arithmetic unit 4 executes a 128-bit operation, or executes two 64-bit operations as two sub-arithmetic units 5. In this way, the arithmetic unit 4 can operate as multiple sub-arithmetic units 5 depending on the bit width of the data to be operated on. In the following, it is assumed that the bit width of the data processed by the arithmetic unit 4 is 128 bits. However, the bit width of the data may be 256 bits, 512 bits, or the like.

[0015] The arithmetic unit 4 has a normal arithmetic function, a SIMD arithmetic unit function, and a function of executing different instructions using multiple sub-arithmetic units 5. Based on instruction information received from the instruction decoder 2 together with an instruction code, the arithmetic unit 4 executes a 128-bit operation, a 64-bit operation, a 64-bit SIMD operation, or a 64-bit operation of two instructions using two sub-arithmetic units 5. In this way, the arithmetic unit 4 has a function of causing multiple sub-arithmetic units 5 to execute in parallel an operation on multiple pieces of data corresponding to one instruction, and a function of causing multiple sub-arithmetic units 5 to each execute an operation on multiple pieces of data corresponding to multiple instructions.

[0016] The observation unit 6 observes the operating state of the arithmetic unit 4 and outputs the operating state obtained by the observation as observation information to the instruction decoder 2. For example, the observation unit 6 observes whether the arithmetic unit 4 is executing an operation using two sub-arithmetic units 5 or only one sub-arithmetic unit 5, and outputs the observation information to the instruction decoder 2.

[0017] The instruction decoder 2 determines whether to output the decoded instructions to the arithmetic unit 4 one at a time in the order in which they were decoded, or two at a time in the order in which they were decoded, based on the operation information from the observation unit 6. In states (1) and (2) shown in FIG. 1, the instruction decoder 2 decodes instructions A, B, C, D, E, F, G, and H in order. For example, each instruction AH is a 64-bit instruction. At the time when the instruction decoder 2 decodes instructions A, B, C, and D (before state (1)), the instruction decoder 2 receives observation information from the observation unit 6 that the arithmetic unit 4 is performing an operation using two sub-arithmetic units 5.

[0018] Based on the received observation information, the instruction decoder 2 determines that there is no free space in the sub-operational unit 5, and sequentially outputs the decoded 64-bit instructions A, B, C, and D to the operation unit 4. For example, the instruction decoder 2 outputs instruction information to the operation unit 4 that causes the sub-operational unit 5 on the higher bit side to execute an operation. In state (1), the codes A, B, C, and D on the higher side of the decoded instruction indicate 64-bit valid data to be executed by the sub-operational unit 5 on the higher bit side. The code X shown on the lower side of the decoded instruction indicates 64-bit invalid data to be executed by the sub-operational unit 5 on the lower bit side.

[0019] The computing unit 4 executes two 64-bit operations using two sub-computing units 5. The sub-computing unit 5 on the higher bit side sequentially outputs valid operation result data a, b, c, and d. The sub-computing unit 5 on the lower bit side sequentially outputs invalid operation result data x. In other words, the sub-computing unit 5 on the lower bit side does not execute an instruction.

[0020] The observation unit 6 observes the operating state of the arithmetic unit 4 based on the instruction information or data supplied to the arithmetic unit 4, for example, in the execution cycle of the instruction AD. Then, the observation unit 6 outputs observation information indicating that the sub-arithmetic unit 5 on the lower bit side is not executing a valid operation to the instruction decoder 2.

[0021] In state (2), the instruction decoder 2 determines, based on the observation information received from the observation unit 6, to have two sub-processing units 5 execute the following instructions E and F and instructions G and H, two instructions at a time, in parallel. The instruction decoder 2 then sequentially outputs to the processing unit 4 instruction information for causing the processing unit 4 to execute instructions E and F in parallel, and instruction information for causing the processing unit 4 to execute instructions G and H in parallel. The codes E and G on the upper side of the decoded instruction indicate 64-bit valid data to be executed by the sub-processing unit 5 on the upper bit side. The codes F and H on the lower side of the decoded instruction indicate 64-bit valid data to be executed by the sub-processing unit 5 on the lower bit side.

[0022] The arithmetic unit 4 executes an operation on two 64-bit valid data using two sub-arithmetic units 5. That is, the arithmetic unit 4 divides the operation function of the two sub-arithmetic units 5 and executes a pair of instructions E and F and a pair of instructions G and H, respectively. By dividing the operation function and having the two sub-arithmetic units 5 execute instructions independently, it is possible to improve the efficiency of instruction execution. The sub-processing unit 5 on the higher-order bit side sequentially outputs valid operation result data e, g. The sub-processing unit 5 on the lower-order bit side sequentially outputs valid operation result data f, h. As a result, in the example shown in FIG. 1, in state (2), the instruction processing efficiency can be doubled compared to state (1). For example, in states (1) and (2), the operation time that takes 8 cycles can be reduced to 6 cycles (75%). As a result, the processing performance of the arithmetic processing device 100 can be improved.

[0023] As described above, in this embodiment, when the instruction decoder 2 determines that some of the sub-operating units 5 are not executing instructions based on the operating states of the operating units 4 observed by the observation unit 6, it outputs the decoded instructions in parallel to the operating units 4. This makes it possible to make the sub-operating units 5 that are operating uselessly execute instructions. As a result, it is possible to improve the efficiency of instruction processing by the operating units 4 compared to a case where the observation unit 6 is not provided, and it is possible to improve the processing performance of the arithmetic processing device 100.

[0024] Fig. 2 shows an example of a processing device according to another embodiment. Detailed descriptions of elements similar to those in Fig. 1 will be omitted. The processing device 102 shown in Fig. 2 is a processor such as a CPU having the function of executing multiple multiply-add operations in parallel based on SIMD operation instructions, similar to the processing device 100 in Fig. 1.

[0025] The processing unit 102 includes an instruction cache 10, an instruction buffer 20, an instruction decoder 30, reservation stations 40 and 42, a computing unit 50, a register file 60, a data cache 70, and an observation unit 80.

[0026] The instruction cache 10 holds instructions to be executed by the arithmetic unit 50 and outputs the held instructions to the instruction buffer 20. If the instruction cache 10 does not hold an instruction corresponding to an address indicated by the program counter, it outputs an access request to a lower-level memory 200 connected to the arithmetic processing unit 100 and retrieves the instruction from the memory 200. For example, the instruction cache 10 is a primary instruction cache. The memory 200 is a secondary cache or a main memory.

[0027] The instruction buffer 20 sequentially holds instructions output from the instruction cache 10, and outputs a plurality of instructions (for example, four instructions) from among the held instructions to the instruction decoder 30 in order.

[0028] The instruction decoder 30 decodes each of the multiple instructions output from the instruction buffer 20, and outputs the multiple instructions including the instruction information obtained by decoding in order to the reservation station 40 or the reservation station 42. The instruction decoder 30 outputs an operation instruction for floating-point numbers to the reservation station 40, and outputs an operation instruction for fixed-point numbers to the reservation station 42. Hereinafter, when there is no need to distinguish between an operation instruction for floating-point numbers and an operation instruction for fixed-point numbers, they will simply be referred to as an operation instruction or an instruction.

[0029] For example, the instruction decoder 30 can decode up to four instructions in parallel and can output in parallel a plurality of instructions including a plurality of pieces of instruction information obtained by decoding. The instruction decoder 30 can output up to two instructions in parallel to each of the reservation stations 40, 42. Note that, as will be described later, the instruction decoder 30 decodes instructions one instruction at a time, two instructions at a time, or four instructions at a time based on observation information received from the observation unit 80, and supplies the decoded instructions to one entry ENT of the reservation station 40.

[0030] The reservation station 40 has a plurality of entries ENT that hold floating-point operation instructions in the order decoded by the instruction decoder 30. The reservation station 40 outputs the instructions held in the entries ENT to the arithmetic unit 50 in the order in which they can be executed (out of order).

[0031] When entry ENT holds one instruction, reservation station 40 outputs one instruction to arithmetic unit 50. When entry ENT holds two instructions, reservation station 40 outputs the two instructions in parallel to arithmetic unit 50. When entry ENT holds four instructions, reservation station 40 outputs the four instructions in parallel to arithmetic unit 50.

[0032] The reservation station 42 has a plurality of entries ENT that hold fixed-point operation instructions in the order decoded by the instruction decoder 30. The reservation station 42 outputs the instructions held in the entries ENT to an integer arithmetic unit (not shown) in the order in which they can be executed.

[0033] The arithmetic unit 50 executes an instruction based on instruction information included in an arithmetic instruction received from the instruction decoder 30. The arithmetic unit 50 is capable of executing, for example, a 256-bit floating-point number operation. The arithmetic unit 50 can also operate as four sub-arithmetic units 52 that respectively execute four 64-bit floating-point number operations. The arithmetic unit 50 has a normal arithmetic function, a SIMD arithmetic unit function, and a function of executing different instructions in the multiple sub-arithmetic units 52.

[0034] The arithmetic unit 50 executes a 256-bit operation, two 128-bit SIMD operations, or four 64-bit SIMD operations based on instruction information received together with an instruction code from the instruction decoder 30. The arithmetic unit 50 also executes two 128-bit operations corresponding to two instructions, or four 64-bit operations corresponding to four instructions. In this way, the arithmetic unit 50 has a function of causing multiple sub-arithmetic units 52 to execute in parallel an operation on multiple pieces of data corresponding to one instruction, and a function of causing multiple sub-arithmetic units 52 to each execute an operation on multiple pieces of data corresponding to multiple instructions.

[0035] The register file 60 has a plurality of registers that hold data (operands) used in operations and operation results. The operands held in the register file 60 are transferred from the data cache 70, and the operation results held in the register file 60 are transferred to the data cache 70.

[0036] The data cache 70 holds a portion of the data held by the memory 200 in cache line units. For example, the data cache 70 is a primary data cache. When the data cache 70 holds data to be operated on by the arithmetic unit 50 (cache hit), it transfers the held data to the register file 60. On the other hand, when the data cache 70 does not hold data to be operated on by the arithmetic unit 50 (cache miss), it reads data of a cache line including the data to be operated on from the memory 200. Then, the data cache 70 transfers the data contained in the cache line read from the memory 200 to the register file 60 and holds the data of the cache line.

[0037] The observation unit 80 observes the operating state (e.g., availability) of the arithmetic unit 50 based on the floating-point number arithmetic instructions transferred from the instruction buffer 20 to the instruction decoder 30. The observation unit 80 outputs the operating state obtained by the observation to the instruction decoder 30 as observation information. The observation unit 80 has a counter 82 that counts the number of consecutive 128-bit or 64-bit arithmetic instructions.

[0038] For example, the observation unit 80 updates the counter 82 for each operation instruction while 128-bit operation instructions are consecutive, and resets the counter 82 when an instruction that is not a 128-bit operation instruction appears. Similarly, the observation unit 80 updates the counter 82 for each operation instruction while 64-bit operation instructions are consecutive, and resets the counter 82 when an instruction that is not a 64-bit operation instruction appears. Then, the observation unit 80 outputs observation information to the instruction decoder 30 indicating that the number of consecutive operation instructions of the same type has reached a predetermined number.

[0039] For example, the observation unit 80 determines the number of bits of an operation instruction based on mask information included in the operand of the floating-point number operation instruction. In other words, the observation unit 80 observes how many sub-operation units 52 the operation unit 50 uses to execute the operation based on the mask information. The observation unit 80 then outputs to the instruction decoder 30 as observation information that a predetermined number of operations using one or two sub-operation units 52 are consecutive. The operations of the observation unit 80 and the instruction decoder 30 will be described with reference to FIG. 3 and subsequent figures.

[0040] The observation unit 80 may observe the operating state of the arithmetic unit 50 based on the fixed-point number arithmetic instruction transferred from the instruction buffer 20 to the instruction decoder 30. The observation unit 80 may then output to the instruction decoder 30, as observation information, that a predetermined number of operations using one or two sub-arithmetic units 52 have been performed consecutively.

[0041] 3 shows an example of the instruction decoder 30 of FIG. 2. The following shows an example in which the instruction decoder 30 decodes a floating-point arithmetic instruction. The instruction decoder 30 has four sub-decoders 32 that respectively decode four instructions received from the instruction buffer 20. The functions of each sub-decoder 32 are the same as each other. The sub-decoder 32 has a switch 34, a first decode unit 361, a second decode unit 362, and a third decode unit 363.

[0042] The switch 34 outputs the instruction received from the instruction decoder 30 to either the first decoding unit 361, the second decoding unit 362, or the third decoding unit 363, based on the observation information from the observation unit 80. The switch 34 outputs the instruction to the first decoding unit 361 when the observation information does not indicate either the continuation of execution of a 128-bit arithmetic instruction (2SIMD) using two sub-arithmetic units 52 or the continuation of execution of a 64-bit arithmetic instruction using one sub-arithmetic unit 52.

[0043] When the observation information indicates a predetermined number of consecutive executions of 128-bit operation instructions using two sub-operation units 52, the switch 34 outputs the instruction to the second decoding unit 362. When the observation information indicates a predetermined number of consecutive executions of 64-bit operation instructions using one sub-operation unit 52, the switch 34 outputs the instruction to the third decoding unit 363.

[0044] The first decoding unit 361 decodes the arithmetic instruction transferred via the switch 34, and outputs the decoded arithmetic instruction to the reservation station 40. For example, the first decoding unit 361 decodes a 256-bit arithmetic instruction (4SIMD), a 128-bit arithmetic instruction (2SIMD), or a 64-bit arithmetic instruction.

[0045] The second decoding unit 362 decodes the two 128-bit operation instructions transferred sequentially via the switch 34. Then, the second decoding unit 362 outputs the two decoded 128-bit operation instructions in parallel to one entry ENT of the reservation station 40. The two 128-bit operation instructions are executed in parallel in the arithmetic unit 50 using the two upper sub-arithmetic units 52 and the two lower sub-arithmetic units 52.

[0046] The third decoding unit 363 decodes the four 64-bit operation instructions transferred sequentially via the switch 34. Then, the third decoding unit 363 outputs the four decoded 64-bit operation instructions in parallel to one entry ENT of the reservation station 40. The four 64-bit operation instructions are executed in parallel in the arithmetic unit 50 using the four sub-arithmetic units 52.

[0047] The reservation station 40 stores each of the instructions received from the first decoding unit 361, the two instructions received in parallel from the second decoding unit 362, and the four instructions received in parallel from the third decoding unit 363 in one entry ENT in units of reception. Then, the reservation station 40 outputs the instructions held in the entry ENT to the arithmetic unit 50 in the order in which they can be executed.

[0048] When a fixed-point arithmetic instruction is received, the switch 34 may output an instruction to any one of the first decoding unit 361, the second decoding unit 362, or the third decoding unit 363 based on the observation information, just as when a floating-point arithmetic instruction is received. In this case, the first decoding unit 361 decodes the received arithmetic instruction and outputs it to the reservation station 42. The second decoding unit 362 decodes the two received 128-bit fixed-point arithmetic instructions (2SIMD) and outputs them to one entry ENT of the reservation station 42. The third decoding unit 363 outputs the four received 64-bit fixed-point arithmetic instructions to one entry ENT of the reservation station 42.

[0049] The operation of the reservation station 42 is similar to the operation of the reservation station 40. When the switch 34 receives a load instruction or a store instruction from the instruction buffer 20, it outputs the received instruction to the first decoding unit 361 regardless of the observation information.

[0050] Fig. 4 shows an example of an instruction decoded by the instruction decoder 30 of Fig. 3. In the example shown in Fig. 4, the instruction decoder 30 successively decodes multiply-add instructions (2SIMD) of 128-bit floating-point numbers. In this example, the instruction buffer 20 holds at least eight instructions A to H, and outputs them to the instruction decoder 30 in order starting with instruction A. Furthermore, since the eight instructions A to H have no data dependency with each other, the reservation station 40 can issue the instructions to the arithmetic unit 50 in this order.

[0051] A multiply-and-accumulate instruction includes, for example, an instruction code fmla, a first operand, mask information, a second operand, and a third operand. The second and third operands (source operands) indicate the register numbers that hold the data to be multiplied. The first operand (destination operand) indicates the register number to which the multiplication result is added.

[0052] The mask information includes four mask bits corresponding to the four sub-operation units 52 in Fig. 2. A mask bit with the code T indicates that the corresponding sub-operation unit 52 is to execute an operation. A mask bit with the code F indicates that the corresponding sub-operation unit 52 is not to execute an operation.

[0053] The observation unit 80 counts the number of 128-bit arithmetic instructions transferred from the instruction buffer 20 to the instruction decoder 30 using a counter 82. When the count value of the counter 82 reaches a predetermined number (="4") after counting the number of four instructions A to D, the observation unit 80 outputs observation information to the instruction decoder 30 indicating that the number of consecutive instructions has reached a predetermined number.

[0054] Before receiving the observation information, the instruction decoder 30 decodes the 128-bit instructions A to D and outputs the decoded instructions to the reservation station 40. For example, the instruction information of each of the instructions A to D includes an instruction to use the two sub-operation units 52 on the upper bit side. The symbols A1, A2, ..., D1, D2 of each of the instructions A to D indicate, for example, the data to be used by each sub-operation unit 52.

[0055] The code X corresponding to each of the instructions A to D indicates 64-bit invalid data to be executed by the sub-operation unit 52 on the lower bit side. The reservation station 40 holds the received instructions A to D together with the invalid data in the entry ENT, and inputs them to the operation unit 50 starting from the executable instruction. For example, the operation unit 50 executes the instructions A to D sequentially using a predetermined number of clock cycles.

[0056] Based on the received observation information, the instruction decoder 30 outputs two instructions, E and F, and two instructions, G and H, in parallel to the reservation station 40. The reservation station 40 holds the received pair of instructions E and F and the received pair of instructions G and H in one entry ENT, respectively, and inputs the executable instruction pairs to the arithmetic unit 50. For example, the arithmetic unit 50 sequentially executes the pair of instructions E and F and the pair of instructions G and H, using a predetermined number of clock cycles. This makes it possible to improve the efficiency of instruction processing and the processing performance of the arithmetic processing device 102, as in the above-described embodiment.

[0057] Fig. 5 shows an example of the operation of the arithmetic processing device 102 of Fig. 2. First, in step S10, the observation unit 80 observes the availability of the arithmetic unit 50. For example, the observation unit 80 observes the availability of the arithmetic unit 50 based on mask information included in each instruction transferred from the instruction buffer 20 to the instruction decoder 30.

[0058] For example, if all four mask information for each instruction are "T", the availability is 100%. If two of the four mask information for each instruction are "T" and the rest are "F", the availability is 50%. If one of the four mask information for each instruction is "T" and the rest are "F", the availability is 25%.

[0059] Next, in step S20, the observation unit 80 determines whether the utilization rate for a predetermined number of instructions is constant. Although not limited to this, in the example shown in FIG. 4, the predetermined number is "4." If the utilization rate for the predetermined number of instructions is constant, the observation unit 80 outputs observation information indicating the utilization rate to the instruction decoder 30. Thereafter, the operation of the arithmetic processing device 102 proceeds to step S30. If the utilization rate for the predetermined number of instructions is not constant, the observation unit 80 outputs observation information indicating that the utilization rate is not constant to the instruction decoder 30. Thereafter, the operation of the arithmetic processing device 102 proceeds to step S32. Note that a constant utilization rate means that the utilization rate is maintained at 100%, 50%, or 25%.

[0060] In step S30, the instruction decoder 30 determines the number of divisions of the arithmetic functions of the arithmetic unit 50 according to the operation rate indicated by the observation information received from the observation unit 80. For example, if the operation rate exceeds 50%, the instruction decoder 30 determines to execute each instruction without dividing the operation functions of the four sub-arithmetic units 52 (number of divisions="1"). An operation rate exceeding 50% includes a case where the execution of 256-bit operation instructions is dominant.

[0061] If the utilization rate is 50%, i.e., if 128-bit operation instructions are consecutive, the instruction decoder 30 divides the operation function into two upper sub-operation units 52 and two lower sub-operation units 52, and determines to execute two instructions in parallel (number of divisions="2"). If the utilization rate is 25%, i.e., if 64-bit operation instructions are consecutive, the instruction decoder 30 divides the operation function into four sub-operation units 52, and determines to execute four instructions in parallel (number of divisions="4"). After step S30, the operation of the arithmetic processing device 102 proceeds to step S40.

[0062] In step S32, the instruction decoder 30 determines to execute each instruction without dividing the operation functions of the four sub-operational units 52 (number of divisions="1"), because the observation information received from the observation unit 80 indicates that the operation rate is not constant. After step S32, the operation of the operation processing device 102 proceeds to step S40.

[0063] Next, in step S40, the instruction decoder 30 executes a decoding process according to the division number determined in step S30, and outputs the decoded instruction to the reservation station 40. An example of the operation of step S40 is shown in FIG.

[0064] Next, in step S50, the reservation station 40 inputs instructions to the arithmetic unit 50 in the order in which they can be executed. Next, in step S60, the arithmetic unit 50 executes the instructions input from the reservation station 40 and stores the operation results in the register file. After step S60, the arithmetic processing device 102 returns the operation to step S10.

[0065] The arithmetic processing unit 102 executes arithmetic processing by pipeline operation. Therefore, the steps shown in Fig. 5 are executed in a redundant manner. For example, steps S10 and S20 are executed repeatedly, and steps S30 and S40 or steps S32 and S40 are executed repeatedly. Step S50 is executed repeatedly, and step S60 is executed repeatedly.

[0066] Fig. 6 shows an example of the operation of step S40 in Fig. 5. First, in step S402, the instruction decoder 30 determines whether the division number determined in steps S30 and S32 in Fig. 5 is "1". If the division number is "1", the instruction decoder 30 executes step S404, and if the division number is not "1", the instruction decoder 30 executes step S408.

[0067] In step S404, the instruction decoder 30 decodes each of the instructions received from the instruction buffer 20 as one instruction using the first decoding unit 361. Next, in step S406, the instruction decoder 30 inputs the decoded instruction into one entry ENT of the reservation station 40, and ends the operation of step S40.

[0068] In step S408, the instruction decoder 30 determines whether the division number determined in steps S30 and S32 of FIG. 5 is "2". If the division number is "2", the instruction decoder 30 executes step S410. If the division number is not "2", the division number is "4", so the instruction decoder 30 executes step S414. In step S410, the instruction decoder 30 decodes the instructions received from the instruction buffer 20 two instructions at a time using the second decoding unit 362. Next, in step S412, the instruction decoder 30 inputs the two decoded instructions into one entry ENT of the reservation station 40, and ends the operation of step S40.

[0069] In step S414, the instruction decoder 30 decodes the instructions received from the instruction buffer 20, four instructions at a time, using the third decoding unit 363. Next, in step S416, the instruction decoder 30 inputs the four decoded instructions into one entry ENT of the reservation station 40, and ends the operation of step S40.

[0070] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, the instruction decoder 30 determines the number of divisions of the arithmetic function of the arithmetic unit 50 based on the operation rate of the arithmetic unit 50 observed by the observation unit 80, and decodes instructions to be executed in parallel by the arithmetic unit 50 according to the determined number of divisions. This makes it possible to improve the efficiency of instruction processing by the arithmetic unit 50 and the processing performance of the arithmetic processing device 102 compared to a case where the observation unit 80 is not provided.

[0071] Furthermore, in this embodiment, the observation unit 80 can calculate the availability of the arithmetic unit 50 based on mask information included in each instruction transferred from the instruction buffer 20 to the instruction decoder 30. Then, the instruction decoder 30 decodes one, two, or four instructions based on the availability calculated from the mask information, and stores them in one entry ENT of the reservation station 40. Therefore, it is possible to calculate the availability of the arithmetic unit 50 without directly detecting the operating state of the arithmetic unit 50, and to decode instructions that improve the processing efficiency of the arithmetic unit 50 based on the calculated availability.

[0072] Furthermore, the availability of the arithmetic unit 50 can be observed (predicted) before the instruction to be observed by the observation unit 80 is supplied to the arithmetic unit 50. In other words, the availability of the arithmetic unit 50 can be observed (predicted) before the instruction to be observed by the observation unit 80 is decoded by the instruction decoder 30. Because the availability can be predicted in advance, it is possible to execute the process of determining the number of divisions of the arithmetic unit 50 and the process of decoding the instruction based on the determined number of divisions without lowering the clock frequency. In other words, it is possible to absorb the increase in processing time due to an increase in the circuit size of the instruction decoder 30.

[0073] Fig. 7 shows an example of a processing device according to another embodiment. Elements similar to those in Fig. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted. The processing device 104 shown in Fig. 7 is a processor such as a CPU having the function of executing multiple multiply-add operations in parallel based on SIMD operation instructions, similar to the processing device 100 in Fig. 2.

[0074] The arithmetic processing device 104 shown in Fig. 7 has an observation unit 84 instead of the observation unit 80 in Fig. 2. The configuration and functions of the arithmetic processing device 104 other than the observation unit 84 are the same as the configuration and functions of the arithmetic processing device 102 in Fig. 2. The observation unit 84 observes the operating state of the arithmetic unit 50 based on data transferred from the register file 60 to the arithmetic unit 50. The observation unit 80 outputs the operating state obtained by observation to the instruction decoder 30 as observation information.

[0075] 8 shows an example of the arithmetic unit 50 and the observation unit 84 of FIG. 7. The arithmetic unit 50 has four ALUs (Arithmetic Logic Units) as the sub-arithmetic units 52 of FIG. 2. For example, each ALU has two inputs for receiving source operand data and one output for outputting destination operand data. For example, the arithmetic processing device 104 has an architecture that supplies source operand data of "0" to ALUs that do not perform operations.

[0076] The observation unit 84 observes the operating state of the arithmetic unit 50 based on the source operand data supplied to the two inputs of each ALU. In other words, the observation unit 84 observes the operating state of the arithmetic unit 50 based on the source operand data transferred from the register file 60 to each ALU.

[0077] The observation unit 84 determines that an ALU that receives source operand data of "0" at two inputs a predetermined number of times in succession is an inoperative ALU. Then, the observation unit 84 outputs observation information including information on the ALU determined to be inoperative to the instruction decoder 30. In this way, the observation unit 84 can observe the operation rate of the arithmetic unit 50 based on the source operand data.

[0078] Based on the observation information, the instruction decoder 30 outputs instructions to be executed by the operating ALUs as well as instructions to be executed by the inoperating ALUs to one entry ENT of the reservation station 40. For example, the operation of the instruction decoder 30 and the arithmetic unit 50 of the arithmetic processing device 104 of this embodiment can be shown by the operation of the arithmetic unit 50 in FIG.

[0079] In the arithmetic unit 50 in Figure 4, symbols A1, A2, ..., D1, D2, E1, E2, G1, G2 indicate instructions to be executed by two operating ALUs. Symbols F1, F2, H1, H2 indicate instructions to be executed by two ALUs that do not normally operate. For example, when the instruction decoder 30 decodes instruction D (D1, D2), it receives observation information from the observation unit 84 that includes information on the ALUs that have been determined not to operate.

[0080] Then, the instruction decoder 30 outputs the next instruction E (E1, E2) to one entry ENT of the reservation station 40, followed by instructions E and F (F1, F2). This allows the arithmetic processing device 104 to improve its processing performance, similar to the arithmetic processing device 102. An example of the operation of the arithmetic processing device 104 is similar to the operation flow of the arithmetic processing device 102 shown in FIGS. 5 and 6.

[0081] As described above, this embodiment can also achieve the same effects as the above-described embodiments. Furthermore, in this embodiment, the observation unit 80 can directly observe the operation rate of the arithmetic unit 50 based on the source operand data supplied to the two inputs of each ALU. Then, the instruction decoder 30 can decode one, two, or four instructions based on the directly observed operation rate of the arithmetic unit 50, thereby decoding instructions that improve the processing efficiency of the arithmetic unit 50.

[0082] 9 shows an example of a processing device according to another embodiment. Elements similar to those in the above-described embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The processing device 106 shown in FIG. 9 has an instruction decoder 38 and an arithmetic unit 58 instead of the instruction decoder 30 and the arithmetic unit 50 in FIG. 2. The configuration and functions of the processing device 106 other than the instruction decoder 38 and the arithmetic unit 58 are similar to those of the processing device 102 in FIG. 2.

[0083] 3, the instruction decoder 38 has a circuit and a function for receiving mode information MD. The mode information MD indicates either the performance-first mode or the low-power mode of the arithmetic unit 50. The mode information MD may be generated inside the arithmetic processing device 106 or may be supplied from outside the arithmetic processing device 106.

[0084] When the instruction decoder 38 receives the mode information MD indicating the performance-first mode, it shifts the operation mode to the performance-first mode, executes the operation flows shown in FIGS.

[0085] When the instruction decoder 38 receives the mode information MD indicating the low power mode, it transitions the operation mode to the low power mode. Then, the instruction decoder 30 embeds stop information STP, which stops the operation of the sub-calculation unit 52 that does not execute the instruction, into the decoded instruction, and outputs the instruction with the embedded stop information STP to the reservation station 40.

[0086] The configuration and functions of the observation unit 80 are similar to those of the observation unit 80 shown in Figures 2 and 3. The configuration and functions of the reservation station 40 are similar to those of the reservation station 40 shown in Figure 2.

[0087] 2 and 4, the calculator 58 has a function of stopping the operation of the sub-calculator 52 corresponding to the stop information STP. For example, the operation of the sub-calculator 52 is executed by stopping the clock supplied to the sub-calculator 52.

[0088] 9 shows an example of the operation of the sub-operational unit 52 in low power mode. The symbol X in the operation unit 58 indicates a sub-operational unit 52 that does not execute an instruction. However, since the sub-operational unit 52 that does not execute an instruction performs an operation on meaningless invalid data (e.g., "0") supplied to the input of the sub-operational unit 52, the sub-operational unit 52 indicated by the symbol X consumes unnecessary power.

[0089] When the instruction received from the reservation station 40 includes the stop information STP, the calculator 58 stops the operation of the sub-calculator 52 corresponding to the stop information STP. By stopping the operation of the sub-calculator 52 that does not execute the instruction, the power consumption of the calculator 58 can be reduced.

[0090] As described above, this embodiment can also achieve the same effects as the above-described embodiment. Furthermore, this embodiment can improve the processing performance of the arithmetic unit 58 during the performance-first mode, and can reduce the power consumption of the arithmetic unit 58 during the low-power mode, thereby reducing the power consumption of the arithmetic processing device 106.

[0091] The following additional notes are further disclosed regarding the embodiment shown in FIGS. 1 to 9. (Appendix 1) an instruction decoder for decoding an instruction; a computing unit that executes the instruction decoded by the instruction decoder and can operate as a plurality of sub-computing units according to the bit width of data to be computed; an observation unit that observes the operating state of the computing unit, When the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the instruction decoder outputs an instruction obtained by parallelizing the decoded instruction to the operation unit. Processing unit. (Appendix 2) The observation unit observes the operating state of the sub-operating unit based on mask information for masking the operation of the sub-operating unit, the mask information being included in the instruction decoded by the instruction decoder. 2. The processing device of claim 1. (Appendix 3) The observation unit observes the operation state of the sub-operating units based on whether data supplied to the sub-operating units is valid or invalid. 2. The processing device of claim 1. (Appendix 4) a register for storing data used by the arithmetic unit; The observation unit observes the operating state of the computing unit based on data transferred from the register to the plurality of sub-computing units. 2. The processing device of claim 1. (Appendix 5) The instruction decoder parallelizes instructions when the observation unit observes that a predetermined number of instructions have been executed consecutively in some of the plurality of sub-operational units. 5. The processing device according to claim 1, (Appendix 6) The instruction decoder receiving mode information indicating performance improvement or power reduction of the computing unit; When the mode information indicates performance improvement and the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the instruction is parallelized; When the mode information indicates power reduction and the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the operation of the sub-operational unit that is not executing an instruction is stopped. 6. The processing device according to claim 1, (Appendix 7) The computing unit is a SIMD computing unit. 10. The processing device according to claim 1, wherein the first and second inputs are input to the processor. (Appendix 8) A processing method for a processing device having a computing unit that can operate as a plurality of sub-computing units according to the bit width of data to be operated, comprising: an observation unit included in the arithmetic processing device observes an operating state of the arithmetic unit; An instruction decoder included in the arithmetic processing device decodes an instruction, and when the observation unit observes that an instruction is not being executed in some of the plurality of sub-arithmetic units, the decoded instruction is parallelized and output to the arithmetic unit. Arithmetic processing method.

[0092] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0093] 2 Instruction Decoder 4 Arithmetic unit 5 Sub-operator 6 Observation Section 10 Instruction Cache 20 Instruction Buffer 30 Instruction Decoder 32 Sub-Decoder 34 Switch 38 Instruction Decoder 40, 42 Reservation Station 50, 58 Arithmetic unit 60 Register File 70 Data Cache 80, 84 Observation Section 82 counters 100, 102, 104, 106 Processing unit 200 memory 361 First Decoding Section 362 Second Decoding Section 363 Third Decoding Section

Claims

1. an instruction decoder for decoding an instruction; a computing unit that executes the instruction decoded by the instruction decoder and can operate as a plurality of sub-computing units according to the bit width of data to be computed; an observation unit that observes the operation state of the sub-operating units based on whether data supplied to the sub-operating units is valid or invalid, When the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the instruction decoder outputs an instruction obtained by parallelizing the decoded instruction to the operation unit. Processing unit.

2. an instruction decoder for decoding an instruction; a computing unit that executes the instruction decoded by the instruction decoder and can operate as a plurality of sub-computing units according to the bit width of data to be computed; a register for storing data used by the arithmetic unit; an observation unit that observes the operation state of the arithmetic unit based on data transferred from the register to the plurality of sub-arithmetic units, When the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the instruction decoder outputs an instruction obtained by parallelizing the decoded instruction to the operation unit. Processing unit.

3. The instruction decoder parallelizes instructions when the observation unit observes that a predetermined number of instructions have been executed consecutively in some of the plurality of sub-operational units. The processing unit according to claim 1 or 2.

4. The instruction decoder receiving mode information indicating performance improvement or power reduction of the computing unit; When the mode information indicates performance improvement and the observation unit observes that an instruction is not being executed in some of the plurality of sub-operational units, the instruction is parallelized; When the mode information indicates power reduction, if the observation unit observes that an instruction is not being executed in some of the plurality of sub-operation units, the operation of the sub-operation unit that is not executing an instruction is stopped. The processor according to any one of claims 1 to 3.

5. The computing unit is a SIMD computing unit. The processor according to any one of claims 1 to 4.

6. A processing method for a processing device having a computing unit that can operate as a plurality of sub-computing units according to the bit width of data to be operated, comprising: an observation unit included in the arithmetic processing device observes the operation states of the arithmetic units based on whether data supplied to the plurality of sub-arithmetic units is valid or invalid; An instruction decoder included in the arithmetic processing device decodes an instruction, and when the observation unit observes that the instruction is not being executed in some of the plurality of sub-arithmetic units, the decoded instruction is parallelized and output to the arithmetic unit. Arithmetic processing method.

7. 1. A processing method for a processing device having a computing unit operable as a plurality of sub-computing units according to the bit width of data to be operated on, and a register for holding data used by the computing unit, comprising: an observation unit included in the arithmetic processing device observes an operating state of the arithmetic unit based on data transferred from the register to the plurality of sub-arithmetic units; An instruction decoder included in the arithmetic processing device decodes an instruction, and when the observation unit observes that the instruction is not being executed in some of the plurality of sub-arithmetic units, the decoded instruction is parallelized and output to the arithmetic unit. Arithmetic processing method.

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