RECOVERY OF SPECULATIVE HISTORY USED TO MAKE SPECULATIVE PREDICTIONS FOR INSTRUCTIONS PROCESSED IN A PROCESSOR EMPLOYING CONTROL INDEPENDENCE TECHNIQUES - Patent application

Abstract

Recovering speculative history used to make speculative predictions for instructions processed by a processor. The processor may be configured to speculatively predict the outcome of a condition or predicate of a conditional control instruction before that condition is fully evaluated during execution. The prediction is made by the processor based on history, updated based on the outcomes of past predictions. If the conditional control instruction is mispredicted during execution, the processor may perform misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline back to the mispredicted conditional control instruction, and then refetching instructions in the correct instruction flow path for execution. The processor may be configured to recover speculative history entries associated with younger control-independent (CI) conditional control instructions, such that younger fetched instructions following the CI instruction that are not refetched in misprediction recovery use the more accurate speculative history.

Description

[Technical Field]

[0001] The techniques of this disclosure relate generally to speculative prediction of control flow computer instructions (“instructions”) in a processor's instruction pipeline, and more particularly to misprediction recovery after a speculative prediction of a control flow instruction at runtime is resolved as a misprediction. [Background technology]

[0002] Instruction pipelining is a processing technique in which the throughput of computer instructions being executed by a processor can be increased by dividing the processing of each instruction into a series of steps. These steps are performed in an execution pipeline consisting of multiple stages. Optimal processor performance can be achieved when all stages in the execution pipeline can process instructions simultaneously and sequentially as the instructions are ordered in the instruction pipeline(s). However, structural hazards can occur in an instruction pipeline that is unable to execute the next instruction without producing an incorrect computational result. For example, a control hazard can occur as a result of executing a control flow instruction that causes a precise interrupt in the processor. One example of a control flow instruction that can cause a control hazard is a conditional branch instruction. A conditional control instruction, such as a conditional branch instruction, can redirect the flow path of instruction execution based on a condition that is evaluated when the condition of the control branch instruction is executed. As a result, the processor must stall fetching additional instructions until the conditional control instruction is executed, resulting in reduced processor performance and power consumption.

[0003] One approach to maximizing processor performance involves utilizing prediction circuitry to speculatively predict the outcome of conditions that control the instruction execution flow path. For example, a prediction of whether a conditional branch instruction will be executed can be based on the branch prediction history of previous conditional branch instructions. When the control flow instruction eventually reaches the execute stage of the instruction pipeline and is executed, the resulting target address of the control flow instruction is verified by comparing it with the target address previously predicted when the control flow instruction was fetched. If the predicted and actual target addresses match, this indicates a correct prediction and no delay occurs in instruction execution because the subsequent instruction at the target address was correctly fetched and is already present in the instruction pipeline when the conditional branch instruction reached the execute stage of the instruction pipeline. However, if the predicted and actual target addresses do not match, a mispredicted branch hazard occurs in the instruction pipeline, causing a precise interrupt. As a result, the instruction pipeline is flushed and the instruction pipeline fetch unit is redirected to fetch new instructions starting from the target address, resulting in delays and performance degradation. Also, stages in the execution pipeline may remain dormant until a newly fetched instruction advances through the instruction pipeline to the execution stage, thereby reducing performance. Mispredictions in the processing of instructions in a processor are costly in terms of resulting delays and performance degradation.

[0004] One way to reduce misprediction penalties is to utilize control independence techniques. Control independence (CI) refers to a region of instructions that execute regardless of the instruction control flow path direction. In other words, CI instructions are independent of branch control decisions. This is illustrated by the example instruction stream 100 of FIG. 1, which is shown in the form of a flowchart 102. Instruction stream 100 includes a conditional branch instruction 104. The instruction execution flow path takes either flow path 106(1) or flow path 106(2), depending on the resolution of a condition (i.e., a predicate) in conditional branch instruction 104. The processor can speculatively predict the outcome of the predicate before conditional branch instruction 104 reaches the execute stage in the instruction pipeline, and then go ahead and insert instructions in the predicted flow path into the instruction pipeline to be executed, avoiding processing delays. Instructions 108(1), 108(2) that reside in one of two respective instruction control flow paths 106(1), 106(2) in respective control dependence (CD) regions 110(1), 110(2) of instruction stream 100 are CD instructions 108(1), 108(2). CD instructions are instructions that execute only depending on which flow path 106(1), 106(2) is taken based on the resolution of a predicate in conditional branch instruction 104. Other instructions 112 reside in CI region 114 within instruction stream 100, which are inserted into the instruction pipeline and executed regardless of which instruction control flow path 106(1), 106(2) is taken as a result from conditional branch instruction 104. These instructions 112 are also known as CI instructions 112. CI instructions 112 may be further classified based on their data dependencies on CD instructions 108(1) or 108(2) in the flow paths 106(1), 160(2) taken in the respective CD regions 110(1) or 110(2).If a CI instruction 112 (e.g., a load instruction) depends on data generated by a CD instruction 108(1) or 108(2) (e.g., a store instruction) in a CD region 110(1) or 110(2) of instruction stream 100, then the CI instruction 112 is a CI, data-dependent (DD) (CIDD) instruction 112D; otherwise, it is a CI, data-independent (DI) (CIDI) instruction 112I.

[0005] 1 identifies CIDD instruction 112D among CI instructions 112 in CI region 114 of instruction stream 100. The control independence technique includes CIDD instruction 112D being re-executed as part of misprediction recovery to ensure functional correctness. This is because CIDD instruction 112D within CI instruction 112 is inserted into the instruction pipeline executed by the processor regardless of the flow path 106(1), 106(2) taken, while CD instruction 108(1) or 108(2) executed based on the speculative prediction of conditional branch instruction 104 is not executed in misprediction recovery. Instead, CD instruction 108(1) or 108(2) that was not previously executed based on the speculative prediction of conditional branch instruction 104 is executed in misprediction recovery. This means that data generated by CD instructions 108(1), 108(2) previously executed based on a speculative misprediction and consumed by CIDD instruction 112D may not be accurate. Misprediction recovery effectively adds CD-generated data from CD instruction 108(1) or 108(2) executed during misprediction recovery. Thus, misprediction recovery effectively “removes” CD instruction 108(1) or 108(2) that executed based on a speculative misprediction, thereby effectively removing their CD-generated data. Thus, any load-based CIDD instruction 112D executed based on a speculative misprediction may rely on saved CD data that was removed and / or added other saved CD data prior to misprediction recovery. A load-based instruction is any instruction that performs a load operation to retrieve data from memory into a register.

[0006] To address the issue of CIDD instructions 112D that have been executed based on CD data that is later removed during misprediction recovery, the processor can mark all load-based CI instructions 112 to be re-executed during misprediction recovery. In this way, any additional saved CD data that affects the load-based CIDD instructions 112D will be used in re-executing the load-based CIDD instructions 112D during misprediction recovery. Summary of the Invention

[0007] Exemplary aspects disclosed herein include recovering a speculative history used to make speculative predictions for instructions processed within a processor. The processor is configured to speculatively predict a value associated with an operation. For example, the processor may be configured to speculatively predict the outcome of a condition or predicate of a conditional control instruction (e.g., a conditional branch instruction) before that condition is fully evaluated during execution. The prediction is made by speculative prediction circuitry within the processor based on a prediction history that is updated based on the results of past predictions. For example, if the outcome of a condition of a conditional control instruction is speculatively predicted and then subsequently determined to have been previously mispredicted during execution, the processor may perform misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline to the mispredicted conditional control instruction, and then refetching instructions in the correct instruction flow path for execution. The processor is configured to recover the speculative portion of the prediction history ("speculative history") back to the mispredicted conditional control instruction in misprediction recovery and correct the misprediction in the speculative history for the mispredicted conditional control instruction. Speculative prediction of a fetched younger conditional control instruction in the correct instruction flow path following the mispredicted conditional control instruction re-updates the speculative history. Recovery of the speculative history is performed to ensure that future conditional control instructions (or other speculations made based on the speculative history) have the correct historical context to provide accurate predictions. More accurate speculative predictions can result in fewer misprediction recoveries, thus reducing flush events, overhead, and pipeline stalls associated with misprediction recovery.

[0008] To improve recovery time in misprediction recovery, a processor can use control-independence techniques to avoid the need to flush all younger control-independent (CI) instructions following a mispredicted conditional control instruction. For example, the control-independence technique can include identifying and replaying younger CI, data-independent (DI) (CIDI) instructions in misprediction recovery, without the need to refetch such CIDI instructions. This is because the younger CIDI instructions are neither control-dependent nor data-dependent on instructions that may have been fetched and processed from the incorrect instruction flow path following the older conditional control instruction. However, even with a processor that uses control-independence techniques to avoid flushing younger CIDI instructions, the speculative history used to make the speculative prediction of the younger CIDI conditional control instruction may have been updated based on previously processed younger control-dependent (CD) conditional control instructions in the incorrect instruction flow path before misprediction recovery. This means that even with misprediction recovery, a younger CIID conditional control instruction following a CD conditional control instruction in the incorrect instruction flow path may have been predicted using the incorrect speculative history. Thus, if the speculative history is simply recovered, the speculative history contains information about predictions previously made for CIDI instructions before misprediction recovery when the incorrect instruction flow path is processed, because the CIDI instructions are not flushed.

[0009] Thus, in example aspects disclosed herein, in addition to recovering the speculative history in the misprediction recovery back to the mispredicted conditional control instruction, the processor may also be configured to recover speculative history entries associated with the younger CI conditional control instruction. Because not all CI conditional control instructions may be refetched and processed in accordance with the control independence technique performed by the processor, the speculative history entries associated with the younger CI conditional control instruction may not be updated again. Thus, if the recovered entries of the speculative history associated with the younger CI conditional control instruction are not recovered, those entries of the speculative history associated with the younger CI conditional control instruction may remain unupdated (e.g., treated as all taken or not taken). Thus, in this instance, the speculative history entries related to the younger CI conditional control instruction are not recovered as part of the recovered speculative history. This may cause a younger fetched conditional control instruction after misprediction recovery that follows a non-refetched CI conditional control instruction in misprediction recovery to use a less accurate speculative history that includes speculative history information that was not recovered for the older, non-refetched CI conditional control instruction. This may result in a reduction in the accuracy of speculative predictions. By recovering the speculative history entries associated with the younger CI conditional control instruction, a younger fetched conditional control instruction that follows a non-refetched CI instruction in misprediction recovery uses a more accurate speculative history that includes speculative history information that was recovered for the older, non-refetched CI conditional control instruction.

[0010] In other exemplary aspects, in addition to recovering the speculative history of the mispredicted conditional control instruction and the younger CI instruction, the processor may also be configured to correct entries in the speculative history associated with the younger CI conditional control instruction. The recovered entries in the speculative history associated with the younger CI conditional control instruction may be inaccurate because they may have been based on previous updates of the speculative history from older CD instructions in the erroneous instruction flow path and / or older CI, data dependent (DD) (CIDD) instructions that are refetched and reprocessed in misprediction recovery. Thus, if the recovered entries in the speculative history associated with the younger CI conditional control instruction are not corrected in addition to being recovered, speculative predictions for younger fetched conditional control instructions that follow the non-refetched CI conditional control instruction in misprediction recovery may use a speculative history that includes uncorrected speculative history entries for the older non-refetched CI conditional control instruction. This may result in reduced accuracy of speculative prediction. By correcting the speculative history entry associated with the younger CI conditional control instruction, the younger fetched conditional control instruction that follows the non-refetched CI instruction in misprediction recovery uses the correct speculative history, including corrected speculative history information for the older non-refetched CI conditional control instruction.

[0011] In this regard, in one exemplary aspect, a processor is provided. The processor includes an instruction processing circuit having one or more instruction pipelines. The processor also includes a speculative prediction history indicator. The instruction processing circuit is configured to speculatively predict a condition within a conditional control instruction in an instruction stream in the instruction pipeline based on the speculative prediction history indicator. The instruction processing circuit is also configured to speculatively predict a condition of one or more CD conditional control instructions in a first CD instruction region following the conditional control instruction in the instruction stream. The instruction processing circuit is also configured to speculatively predict a condition of one or more CI conditional control instructions in a CI instruction region following the first CD instruction region in the instruction stream. The instruction processing circuit is also configured to update one or more CI prediction entries of the speculative prediction history indicator based on the speculative prediction of each of the one or more CI conditional control instructions in the CI instruction region. The instruction processing circuit is also configured to execute the conditional control instruction to resolve the condition of the conditional control instruction. In response to the speculative prediction not matching a resolved condition in the execution of the conditional control instruction, the instruction processing circuitry is also configured to save one or more CI prediction entries in the speculative prediction history indicator, fetch one or more CD instructions in a second CD instruction region of the conditional control instruction based on the resolved condition of the conditional control instruction, speculatively predict conditions of the one or more CD conditional control instructions in the second CD instruction region, and restore the saved one or more CI prediction entries in the speculative prediction history indicator.

[0012] In another exemplary aspect, a method for recovering speculative history used to make speculative predictions for conditional control instructions in a processor is provided. The method includes speculatively predicting a condition within a conditional control instruction within an instruction stream in an instruction pipeline based on a speculative prediction history indicator. The method also includes speculatively predicting the condition of one or more CD conditional control instructions in a first CD instruction region following the conditional control instruction in the instruction stream. The method also includes speculatively predicting the condition of one or more CI conditional control instructions in a CI instruction region following the first CD instruction region in the instruction stream. The method also includes updating one or more CI prediction entries of the speculative prediction history indicator based on the speculative prediction of each of the one or more CI conditional control instructions in the CI instruction region. The method also includes executing the conditional control instruction to resolve the condition of the conditional control instruction. In response to the speculative prediction not matching a resolved condition in the execution of the conditional control instruction, the method also includes saving one or more CI prediction entries in the speculative prediction history indicator; fetching one or more CD instructions in a second CD instruction region of the conditional control instruction based on the resolved condition of the conditional control instruction; speculatively predicting conditions of the one or more CD conditional control instructions in the second CD instruction region; and restoring the saved one or more CI prediction entries in the speculative prediction history indicator.

[0013] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects according to the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1]FIG. 1 is an instruction stream in flowchart form illustrating a conditional branch instruction, control dependent (CD) instructions whose execution depends on the instruction control flow path taken from the prediction or resolution of the predicate of the conditional branch instruction, and control independent (CI) instructions whose execution is independent of the instruction control flow path taken from the conditional branch instruction. [Figure 2] 2 is a diagram of an example processor including example instruction processing circuitry including speculative prediction circuitry configured to make speculative predictions based on speculative history, where the processor is configured to recover speculative history entries associated with younger CI-conditional control instructions upon misprediction recovery. [Figure 3A] FIG. 3A is a diagram of an exemplary predicted branch recovery trace recording illustrating conditional control instructions in the order in which they are fetched into the instruction pipeline as an instruction stream by the instruction processing circuitry of FIG. 2, and the speculative prediction of the condition of each conditional control instruction by the speculative prediction circuitry for each conditional control instruction. [Figure 3B] FIG. 3B is a diagram of an exemplary actual branch recovery trace recording illustrating the conditional control instructions in the order in which they are fetched into the instruction pipeline as an instruction stream by the instruction processing circuitry of FIG. 2, and the actual resolved conditions of the conditional control instructions during execution. [Figure 3C] FIG. 3C is a diagram of an exemplary non-speculative history used by the speculative prediction circuitry of FIG. 2 to make speculative predictions. [Figure 3D] Figure 3D is a diagram of an exemplary speculative history based on the speculative prediction of the conditional control instruction of Figures 3A and 3B prior to the misprediction recovery used by the speculative prediction circuitry within the conditional control instruction of Figure 2 to perform the speculative prediction, and the recovered speculative history resulting from the misprediction recovery. [Figure 4]FIG. 4 is a flow chart illustrating an exemplary process of the instruction processing circuit of FIG. 2 recovering a speculative history entry associated with a younger CI conditional control instruction in a misprediction recovery. [Figure 5] FIG. 5 is a diagram of an exemplary branch reorder buffer (BRB) circuit in the processor of FIG. 2 before misprediction recovery, showing the instruction stream and information captured for the conditional control instructions in the order fetched by the instruction processing circuit of FIG. 2, as well as speculative predictions and the actual resolved condition of each conditional control instruction. [Figure 6] FIG. 6 is a diagram of the BRB circuitry in the processor of FIG. 2 after misprediction recovery, illustrating out-of-order conditional control instructions compared to the conditional control instructions fetched into the instruction pipeline within the instruction stream. [Figure 7A] FIG. 7A is a diagram of another example BRB circuit in the processor of FIG. 2 configured to be indexed to point to the next conditional control instruction in the instruction stream to be fetched in the instruction pipeline before and after a flush event and after reconvergence, respectively, to maintain proper ordering of conditional control instructions in the instruction stream as they are fetched into the instruction pipeline. [Figure 7B] FIG. 7B is a diagram of another example BRB circuit in the processor of FIG. 2 configured to be indexed to point to the next conditional control instruction in the instruction stream to be fetched in the instruction pipeline before and after a flush event and after reconvergence, respectively, to maintain proper ordering of conditional control instructions in the instruction stream as they are fetched into the instruction pipeline. [Figure 7C]FIG. 7C is a diagram of another example BRB circuit in the processor of FIG. 2 configured to be indexed to point to the next conditional control instruction in the instruction stream to be fetched in the instruction pipeline before and after a flush event and after reconvergence, respectively, to maintain proper ordering of conditional control instructions in the instruction stream as they are fetched into the instruction pipeline. [Figure 8A] FIG. 8A is a diagram of the predicted branch recovery trace of FIG. 3A. [Figure 8B] FIG. 8B is an illustration of the actual branch recovery trace of FIG. 3B. [Figure 8C] FIG. 8C is a diagram of the non-speculative history of FIG. 3C. [Figure 8D] Figure 8D is a diagram of an exemplary speculative history based on the speculative prediction of the conditional control instruction of Figures 8A and 8B prior to the misprediction recovery used by the speculative prediction circuitry within the conditional control instruction of Figure 2 to perform the speculative prediction, and the recovered and correct speculative history resulting from the misprediction recovery. [Figure 9] 9 is a block diagram of an exemplary processor-based system including a processor and instruction processing circuitry having one or more instruction pipelines for processing computer instructions for execution, where the processor is configured to recover speculative history entries associated with younger CI-conditional control instructions upon misprediction recovery, including but not limited to the processor of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] Exemplary aspects disclosed herein include recovering a speculative history used to make speculative predictions for instructions processed within a processor. The processor is configured to speculatively predict a value associated with an operation. For example, the processor may be configured to speculatively predict the outcome of a condition or predicate of a conditional control instruction (e.g., a conditional branch instruction) before that condition is fully evaluated during execution. The prediction is made by speculative prediction circuitry within the processor based on a prediction history that is updated based on the results of past predictions. For example, if the outcome of a condition of a conditional control instruction is speculatively predicted and then determined to be mispredicted previously during execution, the processor may perform misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline to the mispredicted conditional control instruction, and then refetching instructions in the correct instruction flow path for execution. In exemplary aspects disclosed herein, the processor may be configured to recover a speculative history entry associated with the younger control-independent (CI) conditional control instruction. By recovering the speculative history entry associated with the younger CI conditional control instruction, the younger fetched instruction that follows the non-refetched CI instruction in the misprediction recovery uses a more accurate speculative history, including recovered speculative history information for the older non-refetched CI instruction.

[0016] Before describing an example of recovering speculative history used to make speculative predictions for instructions processed within a processor beginning with FIG. 3A, an exemplary processor 200 in a processor-based system 202 is first described below with respect to FIG. 2.

[0017] In this regard, Figure 2 is a diagram of an exemplary processor 200 that is part of a processor-based system 202. The processor 200 may be, by way of non-limiting example, an in-order or out-of-order processor (OoP). The processor 200 includes instruction processing circuitry 204, including instruction fetch circuitry 206 configured to fetch instructions 208 from an instruction memory 210. The instruction memory 210 may, by way of example, be provided within or as part of a system memory in the processor-based system 202. The instruction fetch circuitry 206 in this example is configured to provide instructions 208 as fetched instructions 208F to the instruction pipeline IP in the instruction processing circuitry 204 as an instruction stream 212, where they are decoded in decode circuitry 214 and processed as decoded instructions 208D before being executed in execution circuitry 216. The values ​​generated by execution circuitry 216 from executing decoded instruction 208D are committed (i.e., written back) to a storage location indicated by the destination of decoded instruction 208D, which may be, for example, memory 218 in processor-based system 202 or physical registers P0-P1 in physical register file (PRF) 220. X It could be.

[0018] 2, once fetched instruction 208F is decoded into decoded instruction 208D, the decoded instruction 208D is provided to rename / allocate circuitry 222 in instruction processing circuitry 204. Rename / allocate circuitry 222 is configured to determine whether any register names in decoded instruction 208D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. Rename / allocate circuitry 222 also renames logical source register operands and / or assigns destination register operands of decoded instruction 208D to available physical registers P0-P1 in PRF 220. XThe RMT 224 is configured to access a register map table (RMT) 224 to write to each of the logical registers R0-R1. P The mapping entries are mapped to (i.e., associated with) physical registers P0-P1 in the PRF 220. X The PRF 220 is configured to store information in the form of address pointers pointing to the physical registers P0-P X includes data entries 226(0)-226(X) configured to store data for source and / or destination register operands of the decoded instruction 208D.

[0019] Processor 200 also includes speculative prediction circuitry 228 configured to speculatively predict values ​​associated with operations in processor 200. For example, speculative prediction circuitry 228 may be configured to predict the condition of a conditional control instruction 208, such as a conditional branch instruction, that governs which instruction flow path the next instruction 208 is fetched for processing by instruction fetch circuitry 206. For example, if conditional control instruction 208 is a conditional branch instruction, speculative prediction circuitry 228 may predict whether the condition of conditional branch instruction 208 will later resolve as “taken” or “not taken” in execution circuitry 216. In this example, speculative prediction circuitry 228 is configured to consult prediction history indicator 230 to make the speculative prediction. In one example, prediction history indicator 230 includes a global history of previous predictions. The prediction history indicator 230 is hashed with the program counter (PC) of the current conditional control instruction 208 to be predicted in this example to generate a prediction index into a prediction table circuit 232. The prediction table circuit 232 contains a prediction value (e.g., a counter value) mappable to the conditional control instruction 208 based on the prediction index assigned to the conditional control instruction 208. As described in more detail below, the prediction index of the conditional control instruction 208 may be stored in a branch reorder buffer (BRB) circuit 234. The indexed prediction value in the prediction table circuit 232 is used to generate a current speculative prediction for the conditional control instruction 208. In this manner, the prediction of the newly fetched conditional control instruction 208F is based on recent and past resolutions of the conditional control instruction in the instruction processing circuit 204. The prediction value is used by the instruction fetch circuitry 206 to determine whether to fetch the next instruction 208 that follows (ie, is younger than) the conditional branch instruction 208 in the taken or not-taken instruction flow path.

[0020] If the condition outcome of the decoded speculatively predicted conditional control instruction 208D is determined to be mispredicted during execution, the instruction processing circuitry 204 may perform misprediction recovery. In this regard, in this example, the execution circuitry 216 issues a flush event 236 to the commit / flush circuitry 238. The commit / flush circuitry 238 is configured to stall the instruction pipeline IP and flush instructions 208F, 208D in the instruction pipeline IP within the instruction processing circuitry 204 that are younger than the mispredicted conditional control instruction 208. In this regard, the commit / flush circuitry 238 is configured to reference a reorder buffer circuitry 240, which saves and maintains the order of the fetched instructions 208F into the instruction pipeline IP. The rename / allocate circuit 222 is configured to insert the decoded instruction 208D into an entry in the reorder buffer circuit 240 as part of the in-order section of the instruction processing circuit 204 before the decoded instruction 208D is scheduled for execution by the scheduler circuit 242. The scheduler circuit 242 can schedule the decoded instructions 208D for out-of-order execution based on their dependencies and when their source data is available. In this manner, the reorder buffer circuit 240 can be used by the commit / flush circuit 238 to identify instructions 208 that are younger than the mispredicted conditional control instruction 208 for flushing. The commit / flush circuit 238 can then instruct the instruction fetch circuit 206 to fetch the instruction 208 in the instruction pipeline IP from the correct instruction flow path for the conditional control instruction 208 based on the resolved condition.

[0021] When a mispredicted conditional control instruction 208 is resolved and a flush event 236 is generated, the instruction processing circuit 204 is also configured to update the prediction history indicator 230 and the BRB circuit 234 as part of prediction training. This is so that previous updates of the prediction history indicator 230 and the BRB circuit 234 based on the mispredicted conditional control instruction 208 can essentially be reversed so as not to affect future predictions of the conditional control instruction 208 that include the correct instruction flow path from the mispredicted conditional control instruction 208 after flushing. In this regard, the prediction history indicator 230 is updated in response to the flush event 236 so that future predictions are based on the resolved condition of the conditional control instruction 208 to improve prediction accuracy. The BRB circuit 234 is also updated in response to the flush event 236 so that the prediction value at the prediction index in the prediction table circuit 232 that was previously indexed and accessed to predict the mispredicted conditional control instruction 208 is updated (i.e., trained) to record the misprediction. For example, the predicted value at a prediction index in the prediction table circuit 232 may be decremented to indicate a misprediction. The predicted value at a prediction index in the prediction table circuit 232 may be incremented to indicate a correct prediction. In this manner, the predicted value at a prediction index in the prediction table circuit 232 may be used to indicate a prediction (e.g., taken or not taken) as well as the confidence or strength of such prediction relative to future predictions that access the predicted value at the same prediction index in the prediction table circuit 232.

[0022] 3A-3D are provided to further illustrate misprediction recovery for a speculatively mispredicted conditional control instruction 208 by the speculative prediction circuitry 228 of FIG. 2. FIG. 3A is a diagram of an example predicted branch recovery trace record 300 for a fetched conditional control instruction 208F predicted in the instruction processing circuitry 204 of FIG. 2. As shown therein, a first conditional control instruction 208(1) fetched by the instruction processing circuitry 204 of FIG. 2 is shown as being from a branch PC (BRPC) of 0x1015. The speculative prediction circuitry 228 predicted the condition of this conditional control instruction 208(1) as not taken (NT). In this regard, the speculative prediction circuitry 228 uses the prediction history indicator 230 to generate a prediction index into the prediction table circuitry 232 of FIG. 2 as described above, and makes an NT prediction for the conditional control instruction 208(1) at BRPC 0x1015. 3C , in this example, the prediction history indicator 230 is composed of a non-speculative prediction history indicator 230NS and a speculative prediction history indicator 230S. The non-speculative prediction history indicator 230NS has resolved entries 304 (e.g., bits) that can each store a record of resolved conditions of conditional control instructions 208 previously executed in the instruction processing circuit 204. For example, a “0” bit stored in the resolved entry 304 can indicate an NT resolution, and a “1” bit stored in the resolved entry 304 can indicate a taken (T) resolution. The speculative prediction history indicator 230S is also an indicator that has unresolved prediction entries 306 (e.g., bits) that can each store a record of unresolved predictions made for predicted conditional control instructions 208 in the instruction processing circuit 204 that have not yet been executed. Again, as an example, a "0" bit stored in prediction entry 306 indicates an NT prediction, and a "1" bit stored in prediction entry 306 indicates a T prediction.3C , in speculative prediction history indicator 230S, the recorded bits of “010110” in unresolved prediction entry 306 indicate a sequential prediction history of NT, T, NT, T, T, NT (the leftmost bit being the oldest and the rightmost bit being the youngest). A recorded bit of “0” in leftmost prediction entry 306(1) in speculative prediction history indicator 230S represents an NT prediction for conditional control instruction 208(1). Speculative prediction history indicator 230S is appended to non-speculative prediction history indicator 230NS to form prediction history indicator 230 used by speculative prediction circuit 228 to make predictions for conditional control instruction 208. In this way, prediction history indicator 230 reflects a history of predictions, including both resolved and unresolved predictions.

[0023] Continuing with reference to FIG. 3A, as a result of the NT prediction of conditional control instruction 208(1), instruction fetch circuitry 206 fetches the next, younger instruction 208 in the NT instruction flow path for conditional control instruction 208(1). As shown in predicted branch recovery trace record 300, conditional control instruction 208(2) at BRPC 0x1022 is the next encountered conditional control instruction in the NT instruction flow path for conditional control instruction 208(1). As shown in FIG. 3A, the condition of conditional control instruction 208(2) is predicted by speculative prediction circuitry 228 as T based on speculative prediction history indicator 230. Speculative prediction history indicator 230S has a “0” recorded in prediction entry 306(1) for the NT prediction for conditional control instruction 208(1), as shown in FIG. 3C. Speculative prediction circuit 228 then records the T prediction as a “1” bit for conditional control instruction 208(2) in speculative prediction history indicator 230S of prediction history indicators 230, as shown in FIG. 3C. This is so that future predictions will be based on updated speculative prediction history indicator 230S, which includes the predictions recorded for conditional control instruction 208(1) and conditional control instruction 208(2). Predicted branch recovery trace recording 300 in FIG. 3A shows subsequent younger conditional control instructions 208(3)-208(6) processed by instruction processing circuit 204 of FIG. 2 and their predictions made by speculative prediction circuit 228.

[0024] Figure 3B shows an actual branch recovery trace record 302 that shows the resolved conditions of conditional control instructions 208(1)-208(6) based on their execution. As shown in Figure 3B, the NT prediction for conditional control instruction 208(1) resolved as correct, but the T prediction for conditional control instruction 208(2) resolved as incorrect. The correct resolution of the condition for conditional control instruction 208(2) was NT, and the NT prediction for conditional control instruction 208(2) by speculative prediction circuitry 228 was incorrect. This means that the younger conditional control instructions 208(3) and 208(4), shown in predicted branch recovery trace record 300 of Figure 3A, were incorrectly fetched. This is because conditional control instructions 208(3) and 208(4) are control dependent (CD) on the mispredicted conditional control instruction 208(2). Conditional control instructions 208(5) and 208(6) are instructions located at the merge point of conditional control instruction 208(2). Thus, conditional control instructions 208(5) and 208(6) are CI instructions that exist on both the taken T instruction flow path and the not-taken NT instruction flow path from conditional control instruction 208(2), as shown in predicted branch recovery trace record 300 and actual branch recovery trace record 302 in Figures 3A and 3B, respectively.

[0025] In response to detecting the misprediction of conditional control instruction 208(2), execution circuitry 216 of FIG. 2 issues flush event 236 to flush conditional control instructions 208(3), 208(4) and fetch instructions 208 in the correct, NT instruction flow path from conditional control instruction 208(2) in a misprediction recovery. Fetched instructions 208F in the correct, NT instruction flow path from conditional control instruction 208(2) are shown in actual branch recovery trace record 302 as conditional control instructions 208(7)-208(9), 208(5), and 208(6). As described above, the prediction of newly fetched conditional control instruction 208F is made based on prediction history indicators 230, including speculative prediction history indicator 230S. Thus, in this example, because speculative prediction history indicator 230S was updated based on the misprediction of conditional control instruction 208(2), if speculative prediction history indicator 230S were not also updated in response to flush event 236 in misprediction recovery, speculative prediction history indicator 230S would not accurately reflect prediction history. This is because the prediction of conditional control instruction 208(2), as well as the flushed younger conditional control instructions 208(3), 208(4), would otherwise still be present in speculative prediction history indicator 230S. Prediction entry 306(2) for conditional control instruction 208(2) in speculative prediction history indicator 230S would be T (e.g., a “1” bit) instead of NT (e.g., a “0” bit) if speculative prediction history indicator 230S were not updated in response to flush event 236 in misprediction recovery. Also, the prediction for conditional control instructions 208(3), 208(4) in speculative prediction history indicator 230S may be inaccurate because conditional control instructions 208(3), 208(4) were only fetched due to a misprediction of conditional control instruction 208(2) and were flushed in instruction pipeline IP upon misprediction recovery.

[0026] 3D , instruction processing circuit 204 may be configured to update speculative prediction history indicator 230S of prediction history indicators 230 as updated speculative prediction history indicators 230S-U in response to flush event 236 in misprediction recovery. Figure 3D shows updated speculative prediction history indicators 230S-U recording bits “0000010” (i.e., NT, NT, NT, NT, NT, T, NT) in prediction entries 306(1)-306(7) to reflect updated predictions for conditional control instructions 208(1)-208(2), 208(7)-208(9), and 208(5)-208(6), respectively, according to actual branch recovery trace recording 302 of FIG. Note that updated prediction entry 306(2) in updated speculative prediction history indicators 230S-U for conditional control instruction 208(2) is now “0,” signifying NT. Newly fetched conditional control instructions 208(7)-208(9) are predicted based on the more accurate, updated speculative prediction history indicators 230S-U instead of the previous speculative prediction history indicators 230S, which included a misprediction for conditional control instruction 208(2) and predictions for conditional control instructions 208(3), 208(4) fetched in the incorrect instruction flow path for conditional control instruction 208(2).

[0027] The instruction processing circuit 204 in the processor 200 of Figure 2 may also be configured to employ a control independence technique to avoid flushing all CI instructions upon misprediction recovery. For example, the control independence technique may include the instruction processing circuit 204 of Figure 2 identifying whether a CI instruction 208 is a CI, data independent (DI) (CIDI) instruction 208 or a CI, data dependent (DD) (CIDD) instruction 208 in the CI region of the instruction stream 212 upon misprediction recovery. For example, conditional control instructions 208(5) and 208(6) are in the CI instruction region 308 for the conditional control instruction 208(2) of Figure 3A. Conditional control instructions 208(3) and 208(4) are in the CD instruction region 310 for the conditional control instruction 208(2) of Figure 3A. 2 can refetch and reprocess the CIDD instruction 208 that follows the mispredicted conditional control instruction 208, so that its data dependency is correctly resolved based on the instruction 208F fetched in the correct instruction flow path. However, the CIDI instruction 208 can simply be processed (i.e., processed in the instruction pipeline IP) following the fetch and processing of the older instruction 208 in the correct instruction flow path in misprediction recovery without having to refetch such CIDI instruction. This is because the CIDI instruction 208 is neither control nor data dependent on the CD instruction 208, which was fetched from the misinstruction flow path and processed following the mispredicted conditional control instruction 208.

[0028] 3C , which is used to speculatively predict a younger CIDI conditional control instruction 208, may have a record of an incorrect prediction. As described above, the prediction history indicator 230 records a prediction from a younger CD conditional control instruction 208 in the incorrect instruction flow path that was predicted before misprediction recovery. This means that even with misprediction recovery, a younger CIID conditional control instruction 208 that follows a CD conditional control instruction 208 in the incorrect instruction flow path may be predicted using the incorrect prediction history indicator 230.

[0029] Thus, in the exemplary aspects disclosed herein, the instruction processing circuit 204 is configured to restore the speculative prediction history indicator 230S so that it is accurate despite not refetching and re-predicting the conditions of the younger, CIID-conditional control instructions 208 during their replay in misprediction recovery. In this regard, the instruction processing circuit 204 of FIG. 2 may be configured to restore the prediction entry 306 in the speculative prediction history indicator 230S that was recorded based on the speculative prediction of the younger, CIID-conditional control instruction 208. This is so that the previous prediction made for the younger, CIID-conditional control instruction 208 is recorded in the prediction entry 306 in the updated speculative prediction history indicator 230S-U, as shown in FIG. 3D . In this way, the younger conditional control instruction following such younger CI-conditional control instruction 208 is further predicted based on the accurate prediction history indicator 230 without the need to refetch and re-predict such younger CI-conditional control instruction 208. In this example, as younger CIDD conditional control instructions 208 are refetched and re-predicted in misprediction recovery, the re-predictions made for these younger CIDD conditional control instructions 208 are recorded in the updated speculative prediction history indicators 230S-U without recovery, as shown in Figure 3D. These example techniques are illustrated by the examples of Figures 3A-3D and described below in an example process 400 in Figure 4.

[0030] In this regard, in this example, instruction fetch circuitry 206 of instruction processing circuitry 204 is configured to fetch conditional control instruction 208 in instruction stream 212 in instruction pipeline IP of Figure 2. Instruction processing circuitry 204 is then configured to speculatively predict a condition in conditional control instruction 208 in instruction stream 212 in instruction pipeline IP of Figure 2 based on speculative prediction history indicator 230S (block 402 of Figure 4). One example of this is conditional control instruction 208(2) fetched at BRPC 0x1022 of Figure 3A, where the condition of conditional control instruction 208(2) is speculatively predicted as T by speculative prediction circuitry 228 of Figure 2. Speculative prediction circuitry 228 is configured to update prediction entry 306(2) in speculative prediction history indicator 230S based on the speculative prediction of the condition of conditional control instruction 208(2).

[0031] The instruction fetch circuitry 206 is then configured to fetch a CD instruction 208 for the conditional control instruction 208 in the first CD instruction region 310 of the conditional control instruction 208 based on the speculative prediction of the conditional control instruction 208. One example of this is shown in Figure 3A, where the CD instruction 208F fetched for the conditional control instruction 208(2) is the conditional control CD instructions 208(3), 208(4) in the CD instruction region 310 of the conditional control instruction 208(2). The speculative prediction circuitry 228 of the instruction processing circuitry 204 is configured to speculatively predict the condition of the fetched CD conditional control instruction 208F in the first CD instruction region 310 that follows the conditional control instruction 208 in the instruction stream 212 (block 404 of Figure 4). An example of this is shown in Figure 3A, where the conditions of CD-conditional control instructions 208(3) and 208(4) are speculatively predicted as NT and T, respectively, by speculative prediction circuitry 228 of Figure 2. Speculative prediction circuitry 228 is then configured to update prediction entries 306 in the speculative prediction history based on the speculative prediction of each of the CD-conditional control instructions 208 in first CD instruction region 310. An example of this is shown in Figure 3C, where prediction entries 306(3) and 306(4) in speculative prediction history indicator 230S of prediction history indicator 230 are recorded as NT and T, respectively, by speculative prediction circuitry 228 of Figure 2, along with predictions of CD-conditional control instructions 208(3) and 208(4). Prediction entries 306(3) and 306(4) in speculative prediction history indicator 230S of Figure 3C are referred to as CD prediction entries. This is because prediction entries 306(3) and 306(4) record predictions for CD conditional control instructions 208(3) and 208(4).

[0032] The instruction fetch circuitry 206 is configured to fetch one or more CI instructions 208 in the CI instruction region 308 of the conditional control instruction 208. An example of this is shown in Figure 3A, where the fetched CI instructions 208F for the conditional control instruction 208(2) are conditional control CI instructions 208(5), 208(6) in the CI instruction region 308 of the conditional control instruction 208(2). The speculative prediction circuitry 228 is then configured to speculatively predict the conditions of one or more CI conditional control instructions 208 in the CI instruction region 308 that follows the first CD instruction region 310 in the instruction stream 212 (block 406 of Figure 4). An example of this is shown in Figure 3A, where the conditions of the CI conditional control instructions 208(5), 208(6) are speculatively predicted as T and NT, respectively, by the speculative prediction circuitry 228 of Figure 2. Speculative prediction circuitry 228 is then configured to update CI prediction entries 306 of speculative prediction history indicator 230S based on the speculative prediction of each CI conditional control instruction 208 in CI instruction region 308 (block 408 of FIG. 4). One example of this is shown in FIG. 3C, where prediction entries 306(5), 306(6) in speculative prediction history indicator 230S are recorded by speculative prediction circuitry 228 of FIG. 2 as T and NT, respectively, along with predictions of CI conditional control instructions 208(5), 208(6). Prediction entries 306(5), 306(6) in prediction history indicator 230 of FIG. 3C are referred to as CI prediction entries because prediction entries 306(5), 306(6) record predictions of CI conditional control instructions 208(5), 208(6).

[0033] In this example, execution circuitry 216 in instruction processing circuitry 204 is configured to execute conditional control instruction 208(2) to resolve the condition of conditional control instruction 208(2) (block 410 of FIG. 4). Execution circuitry 216 resolves the condition of conditional control instruction 208(2). In this example, the resolved condition of conditional control instruction 208(2) is NT, as shown in FIG. 3B, but was previously predicted as T by speculative prediction circuitry 228. Thus, prediction entry 306(2) in speculative prediction history indicator 230S is recorded with a prediction of T, indicated by a “1” bit.

[0034] In response to the speculative prediction of conditional control instruction 208(2) not matching the resolved condition of the executing conditional control instruction 208(2) (block 412 of FIG. 4), instruction fetch circuitry 206 is configured to stall the fetching of new instructions 208 to the instruction pipeline IP. Speculative prediction circuitry 228 is configured to store predicted values ​​in prediction entries 306 associated with CI instruction 208 in speculative prediction history indicator 230S so that these predicted values ​​can be recovered after misprediction recovery (block 414 of FIG. 4). One example of this is shown in FIG. 3D, where predicted values ​​“10” in prediction entries 306(5) and 306(6) in speculative prediction history indicator 230S are stored so that these predicted values ​​can be recovered after misprediction recovery. Instruction processing circuitry 204 then removes CD prediction entry 306 in speculative prediction history indicator 230S (block 414 of FIG. 4). 3D, where speculative prediction history indicator 230S is right-shifted by four bits to remove all prediction values ​​for prediction entries 306(3)-306(6) for predictions made after the recorded prediction value in prediction entry 306(2) for mispredicted conditional control instruction 208(2) in speculative prediction history indicator 230S.

[0035] Instruction fetch circuitry 206 then unstalls and fetches one or more CD instructions 208 in second CD instruction region 312 in the correct instruction flow path of conditional control instruction 208(2) based on the resolved condition of conditional control instruction 208(2) (block 416 of FIG. 4). This is illustrated by the example of FIG. 3B, where CD conditional control instructions 208(7)-208(9) in second CD instruction region 312 in the correct instruction flow path of conditional control instruction 208(2) are fetched. Speculative prediction circuitry 228 then speculatively predicts the conditions of the one or more CD conditional control instructions 208 in second CD instruction region 312 (block 418 of FIG. 4). 3B , where speculative prediction circuitry 228 speculatively predicts the conditions of CD-conditional control instructions 208(7)-208(9) in second CD instruction region 312 as NT, NT, and NT, respectively. Speculative prediction circuitry 228 then updates prediction entries 306(3)-306(5) for CD-conditional control instructions 208(7)-208(9) in speculative prediction history indicator 230S, as indicated by updated speculative prediction history indicator 230S-U. This is illustrated by the example of FIG. 3D , where prediction entries 306(3)-306(5) are updated with a “0” bit to record an NT prediction for CD-conditional control instructions 208(7)-208(9). The speculative prediction circuit 228 is then configured to add the saved CI prediction entry 306 to the speculative prediction history indicator 230S to restore the saved CI prediction entry 306 to the speculative prediction history indicator 230S, such that the prediction of the CI conditional control instruction 208 associated with the saved CI prediction entry 306 is restored and an accurate prediction history indicator 230 is provided for the future, younger predicted conditional control instruction 208 (block 420 of FIG. 4). This is illustrated by the example of FIG. 3D, where the saved CI prediction entries 306(5), 306(6) are added to the updated speculative prediction history indicator 230S-U as CI prediction entries 306(6), 306(7).As mentioned above, in this example, it is desirable not to refetch and repredict the CIDI conditional control instruction 208 after misprediction recovery in order to reduce recovery time.

[0036] 2 is configured to replay CI condition control instructions 208 that are younger than the mispredicted condition control instruction 208 after misprediction recovery without having to refetch these CI condition control instructions 208. The CI conditional control instructions 208 may be reprocessed and executed in the instruction pipeline IP following the CD instructions 208 fetched in the correct instruction flow path of the mispredicted conditional control instruction 208. For example, the instruction processing circuit 204 may be configured to replay CIDI conditional constituent instructions 208 without having to replay those instructions 208 that follow the mispredicted conditional control instruction 208 in misprediction recovery. The instruction processing circuit 204 may also be configured to refetch and speculatively refetch the conditions of CIDD conditional constituent instructions 208 that follow the mispredicted conditional control instruction 208 in misprediction recovery due to their data dependency on the CD conditional control instruction 208 in the misinstruction flow path. The instruction processing circuit 204 may also fetch and speculatively predict additional younger CI conditional control instructions 208 based on the recovered speculative prediction history indicator 230S, and update the CI prediction entries of the speculative prediction history indicator 230S based on the speculative prediction of the younger CI conditional control instructions 208.

[0037] 5 and 6 are provided to provide further exemplary details regarding misprediction recovery in the instruction processing circuit 204 of FIG. 2. FIGS. 5 and 6 illustrate the state of the exemplary BRB circuit 234 of FIG. 2 before and after misprediction recovery, respectively, according to the predicted branch recovery trace record 300 and the actual branch recovery trace record 302 of FIGS. 3A and 3B. As shown in FIG. 5, the BRB circuit 234 includes multiple BRB entries 500(1)-500(X), each configured to store information regarding a conditional control instruction 208 fetched and processed in the instruction pipeline IP. As described above, the information in the BRB circuit 234 is maintained by the speculative prediction circuit 228. Each BRB entry 500(1)-500(X) includes a respective conditional control instruction identifier 502(1)-502(X) to identify the inserted conditional control instruction 208, which may be the BRPC of the conditional control instruction 208. Each BRB entry 500(1)-500(X) also includes a respective hit table indicator 504(1)-504(X), set number indicator 506(1)-506(X), and entry tag 508(1)-508(X), which collectively provide a prediction address pointer that provides a prediction index into the prediction table circuit 232 of FIG. 2 to obtain a prediction for the respective conditional control instruction 208 of the BRB entry 500(1)-500(X). As described above, the hit table indicator 504(1)-504(X), set number indicator 506(1)-506(X), and entry tag 508(1)-508(X) may be determined by the speculative prediction circuit 228 for a given conditional control instruction 208 based on the prediction history indicator 230 and a hash of the PC of the conditional control instruction 208. Separate hit table indicators 504(1)-504(X), set number indicators 506(1)-506(X), and entry tags 508(1)-508(X) are provided in this example within BRB entries 500(1)-500(X) because prediction table circuit 232 may include multiple prediction table circuits, each with different sets and entries within each set.Thus, in this example, hit table indicators 504(1)-504(X), set number indicators 506(1)-506(X), and entry tags 508(1)-508(X) can be used to identify a particular prediction table circuit 232, a set within that particular prediction table circuit 232, and an entry within that set.

[0038] 5, each BRB entry 500(1)-500(X) also includes a respective prediction entry 510(1)-510(X) and an actual entry 512(1)-512(X) for storing the speculative prediction of the condition for each conditional control instruction 208 and for storing the actual resolution of the condition for each conditional control instruction 208. This information is used by the speculative prediction circuitry 228 to handle misprediction recovery in response to a mispredicted conditional control instruction 208. Each BRB entry 500(1)-500(X) also includes a respective valid indicator 514(1)-514(X) that indicates whether the respective BRB entry 500(1)-500(X) is valid. For example, when a conditional control instruction 208 stored in a BRB entry 500(1)-500(X) is resolved, the BRB entry 500(1)-500(X) may be reused for another processed conditional control instruction 208. The validity indicator 514(1)-514(X) may be set to an invalid state when the respective BRB entry 500(1)-500(X) is not valid at a given time.

[0039] As shown in FIG. 5, BRB entries 500(1)-500(6) are filled using information about conditional control instructions 208(1)-208(6) from FIG. 3A that was fetched by instruction processing circuitry 204. A speculative prediction of either T or NT is entered into respective prediction entries 510(1)-510(6) within BRB entries 500(1)-500(6), as shown in FIG. 3A. Also as shown in FIG. 5, when the actual resolved condition for conditional control instruction 208(2) in BRB entry 500(2) is determined to be NT by execution circuitry 216 of FIG. 2, actual entry 512(2) in BRB circuitry 234 is updated to NT, which differs from the predicted condition of T stored in prediction entry 510(2). This means that conditional control instruction 208(2) was mispredicted by speculative prediction circuitry 228. 6, speculative prediction circuitry 228 is configured to flush BRB entries 500(3), 500(4) for CD conditional control instructions 208(3), 208(4) that follow mispredicted conditional control instruction 208(2) in BRB circuitry 234. The conditional control instructions 208 fetched in the correct instruction flow path are CD conditional control instructions 208(7)-208(9), as shown in BRB circuitry 234 and previously described in the example of FIG. 3B. As shown in FIG. 3B, the flushing of BRB entries 500(3), 500(4) leaves room for only two BRB entries 500 to store new conditional control instructions 208 fetched from the correct instruction flow path of conditional control instruction 208(2) in misprediction recovery. However, in this example, three new CD-conditional control instructions 208(7)-208(9) are fetched in the misprediction recovery. BRB entry 500(7) is available to store CD-conditional control instruction 208(9), but out of order, as shown in Figure 6. CD-conditional control instruction 208(9) is older than CI-conditional control instructions 208(5) and 208(6).Conditional control instructions 208 need to be stored in order in BRB circuit 234 so that speculative prediction history indicator 230S can be properly restored upon misprediction recovery. Speculative prediction circuit 228 is configured to update speculative prediction history indicator 230S based on the order of conditional control instructions 208 in BRB circuit 234. To alleviate this problem, additional processing would need to be employed to reorder BRB entries 500(5)-500(7) in BRB circuit 234 in an undesirable manner.

[0040] To reduce the need to order BRB entries 500(1)-500(X) in BRB circuit 234, an alternative BRB circuit 700 is provided and is shown in FIG. 7A, which may be BRB circuit 234 as shown in the example of FIG. 6. As described below, BRB circuit 700 facilitates a linked list structure to allow BRB entries to be used and flushed without the need to reorder the BRB entries. Instruction processing circuit 204 is configured to use the functionality of BRB circuit 700 to avoid the need to reorder branch entries in BRB circuit 700. BRB circuit 700 is shown using the example conditional control instructions 208(1)-208(6) of FIG. 3A and before a flush event occurs due to a misprediction of conditional control instruction 208(2). In this regard, the BRB circuit 700 includes multiple BRB entries 702(1)-702(X) similar to the BRB entries 500(1)-500(X) in the BRB circuit 234 of Figures 5 and 6. However, the BRB entries 702(1)-702(X) in the BRB circuit 700 also include respective index indicators 704(1)-704(X) and index link indicators 706(1)-706(X). The BRB circuit 700 also includes a head index indicator 708. The head index indicator 708 is configured to store the index of the BRB entry 702(1)-702(X), which identifies the first, or head, and youngest, conditional control instruction 208 in the BRB circuit 700. In this example, the youngest conditional control instruction 208 is conditional control instruction 208(1) in BRB entry 702(1), which has an index of "0" in its index indicator 704(1). Thus, head index indicator 708 stores an index of "0" in this example. Index link indicators 706(1)-706(X) store an index that points to the next BRB entry 500(1)-500(X), which contains the next youngest conditional control instruction 208.Therefore, index link indicator 706(1) stores an index of "4" because conditional control instruction 208(2) is the next youngest conditional control instruction after conditional control instruction 208(1). This is because BRB entry 702(5), which has index "4," stores conditional control instruction 208(2). Index link indicator 706(5) stores an index of "6," which points to BRB entry 500(7), which contains the next youngest conditional control instruction 208(3), and so on. Free list 710 stores a list of indices pointing to BRB entries 702(1)-702(X) that are free to be used to store new conditional control instructions 208. A CI index indicator 712 is provided in the BRB circuit 700 to indicate the index of the BRB entry 702(1)-702(X) that stores the next conditional control instruction 208 following the merge or convergence point.

[0041] Figure 7B shows the BRB circuit 700 of Figure 7A after a flush event 236 occurs during misprediction recovery when CD conditional control instructions 208(3) and 208(4) are removed as being in the incorrect instruction flow path. As shown in Figure 7B, as a result of the misprediction of conditional control instruction 208(2), BRB entries 702(6) and 702(7), which stored information about the flushed CD conditional control instructions 208(3) and 208(4), are removed. Indexes "5" and "6," corresponding to BRB entries 702(6) and 702(7), are placed back into the free list 710, indicating that the BRB entries 702(6) and 702(7) at indexes "5" and "6" are free to store information about the newly fetched conditional control instruction 208F. The CI index in CI index indicator 712 is updated to a value of “2” to point to BRB entry 702(3), which in this example has an index of “2” for its index indicator 704(3), identifying the first conditional control instruction 208(5) following the merge or convergence point for mispredicted conditional control instruction 208(2).

[0042] Figure 7C then shows BRB circuit 700 in Figure 7A after reconvergence when CD conditional control instructions 208(7)-208(9) are fetched in the correct instruction flow path for conditional control instruction 208(2). As shown in Figure 7C, BRB entries 702(2), 702(4), 702(7) with indexes of "1," "3," and "6," as identified by free list 710 in Figure 7B, may be used to store information about CD conditional control instructions 208(7)-208(9) fetched from the correct instruction flow path for conditional control instruction 208(2). In this regard, index link indicator 706(5) for conditional control instruction 208(2) in BRB entry 702(6) has an index of “1” to point to BRB entry 702(2), which stores information regarding the next conditional control instruction 208(7) following conditional control instruction 208(2). Index link indicator 706(2) for conditional control instruction 208(7) in BRB entry 702(2) has an index of “3” to point to BRB entry 702(4), which stores information regarding the next conditional control instruction 208(8) following conditional control instruction 208(7). Index link indicator 706(4) for conditional control instruction 208(8) in BRB entry 702(4) has an index of “6” to point to BRB entry 702(7), which stores information regarding the next conditional control instruction 208(9) following conditional control instruction 208(8). Index link indicator 706(7) for conditional control instruction 208(9) in BRB entry 702(4) has an index of "2" to point to BRB entry 702(3), which stores information about the next conditional control instruction 208(5), which follows conditional control instruction 208(9), and so on.

[0043] 3C and 3D , the instruction processing circuit 204 and / or its speculative prediction circuit 228 may be configured to restore CI prediction entries 306 indicating speculative predictions for CI-conditional control instructions 208 in the speculative prediction history indicators 230S of the processor 200 during misprediction recovery. This is to allow younger conditional control instructions 208 to be predicted based on the more accurate prediction history indicators 230. However, these saved CI prediction entries 306 were previously determined and set based on the speculative prediction history indicators 230S that existed when the corresponding CI-conditional control instructions 208 were fetched and processed by the speculative prediction circuit 228. This means that any older CD-conditional control instructions 208 in the speculatively predicted predicted instruction flow path also affected the speculative prediction history indicators 230S used to make speculative predictions for younger CI-conditional control instructions 208. However, these older CD-conditional control instructions 208 may have been in an instruction flow path that was erroneously fetched from an older conditional control instruction 208 that was later determined to have been mispredicted in the execution circuitry 216. In this instance, the CI prediction entry 306 saved and recovered for the corresponding CI-conditional control instruction 208 was based on a prediction for the older CD-conditional control instruction 208 that would be flushed in the misprediction recovery. Thus, the recovered CI prediction entry 306 in the speculative prediction history indicator 230S may not indicate the same prediction as if the CI prediction entry 306 were based on a speculative prediction from a speculative prediction history indicator 230S that was affected by an older CD-conditional control instruction 208 in the correct instruction flow path.

[0044] Thus, in another exemplary aspect, in addition to recovering the speculative prediction history indicator 230S corresponding to the younger CI conditional control instruction 208, the instruction processing circuit 204 may also be configured to correct the prediction value in the prediction table circuit 232 associated with the younger CI conditional control instruction 208 in misprediction recovery. In misprediction recovery, the instruction processing circuit 204 may be configured to speculatively re-predict the condition of the younger CI conditional control instruction 208 that is not flushed based on the speculative prediction history indicator 230S, which is updated based on the CD conditional control instruction 208 fetched in the correct instruction flow path. In misprediction recovery, by correcting the prediction value in the prediction table circuit 232 associated with the younger CI conditional control instruction 208, more accurate predictions can be made for future instances of the CI conditional control instruction 208.

[0045] Thus, in another example, to provide a more accurate prediction history for the CI conditional control instructions 208, the instruction processing circuit 204 is also configured to update the predicted address pointers in the BRB circuit 234 defined by the respective hit table indicators 504(0)-504(X), set number indicators 506(0)-506(X), and entry tags 508(0)-508(X) during misprediction recovery. For example, the predicted address pointers in the BRB circuit 234 for the CI conditional control instructions 208(5), 208(6) of FIG. 6 may be updated during misprediction recovery. The predicted address pointers in the BRB circuit 234 are updated for the CI conditional control instructions 208(5), 208(6) based on the non-speculative prediction history indicators 230NS upon execution or commitment of the generated values ​​generated by execution of the CI conditional control instructions 208(5), 208(6) in the execution circuit 216 of FIG. 2 . This allows non-speculative prediction history indicator 230NS to be used to update the prediction address pointer in BRB circuit 234 for CI conditional control instructions 208(5), 208(6) because CI conditional control instructions 208(5), 208(6) have executed and committed, and as a result, the CI prediction entry 306 with that prediction is no longer in speculative prediction history indicator 230S.

[0046] Speculative prediction circuitry 228 is then configured to compare the predicted value in prediction table circuitry 232 at the updated predicted address pointer in BRB circuitry 234 for CI conditional control instructions 208(5), 208(6) set in CI prediction entries 306(5), 306(6) with the resolved condition of CI conditional control instructions 208(5), 208(6). If the predicted value in prediction table circuitry 232 at the updated predicted address pointer in BRB circuitry 234 matches the actual resolved condition of CI conditional control instructions 208(5), 208(6), the predicted value in prediction table circuit 232 at the updated predicted address pointer in BRB circuitry 234 for CI conditional control instructions 208(5), 208(6) remains unchanged. However, if the predicted value in prediction table circuit 232 at the updated predicted address pointer in BRB circuit 234 matches the actual resolved condition of CI conditional control instructions 208(5), 208(6), then the predicted value in prediction table circuit 232 at the updated predicted address pointer in BRB circuit 234 for CI conditional control instructions 208(5), 208(6) remains unchanged. This can provide a correction to the predicted value in prediction table circuit 232 even if CI prediction entries 306(5), 306(6) for CI conditional control instructions 208(5), 208(6) are inaccurate based on updates to speculative prediction history indicator 230S when the old CD conditional control instruction 208 is fetched and predicted after misprediction recovery.

[0047] In this regard, FIGS. 8A-8D are provided to illustrate one example of a correct CI prediction entry 306 associated with a younger CI conditional control instruction 208 in a misprediction recovery. FIG. 8A is a diagram of an example predicted branch recovery trace record 300 of a fetched conditional control instruction 208F predicted in the instruction processing circuit 204 of FIG. 3A. FIG. 8B is a diagram of an example actual branch recovery trace record 302 of a fetched conditional control instruction 208F predicted in the instruction processing circuit 204 of FIG. 3B. FIG. 8C illustrates prediction history indicators 230, including the non-speculative prediction history indicator 230NS and the speculative prediction history indicator 230S shown in FIG. 3C. The previous description of FIGS. 3A-3C above is applicable to FIGS. 8A-8C, and therefore, there is no need to describe FIGS. 8A-8C again.

[0048] 8D , instruction processing circuit 204 is configured to update speculative prediction history indicator 230S of prediction history indicator 230 in response to flush event 236 in misprediction recovery. Instead of saving and restoring the previous predictions of T and NT (i.e., “10”) in CI prediction entries 306(5), 306(6) in speculative prediction history indicator 230S associated with CI conditional control instructions 208(5), 208(6), instruction processing circuit 204 is configured to restore the corrected predictions associated with CI conditional control instructions 208(5), 208(6) in updated speculative prediction history indicator 230S-U based on the fetching and speculative prediction of conditional control instructions 208(7)-208(9) in the correct instruction flow path for conditional control instruction 208(2) after misprediction recovery. In this example, the speculative prediction of conditional control instructions 208(7)-208(9) as NT, NT, NT (i.e., "000") affected updated speculative prediction history indicators 230S-U. The speculative prediction of CI conditional control instructions 208(5), 208(6) resulted in respective predictions T, T (i.e., "11") based on updated speculative prediction history indicators 230S-U in response to predicting conditional control instructions 208(7)-208(9) in the correct instruction flow path. These corrected predictions are provided in corrected CI prediction entries 806(5), 806(6), which are added to the prediction entries in updated speculative prediction history indicators 230S-U, as shown in FIG. 3D .

[0049] In this example, speculative prediction circuitry 228 of Figure 2 is configured to speculatively predict the conditions of CI conditional control instructions 208(5), 208(6) in CI instruction domain 308 of Figures 8A and 8B during misprediction recovery. The predicted conditions form CI prediction entries 806(5), 806(6), as shown in Figure 8D. Speculative prediction circuitry 228 is then configured to update speculative prediction history indicator 230S in updated speculative prediction history indicator 230S-U with CI prediction entries 806(5), 806(6) to provide corrected CI prediction entries 306(6), 306(7) in updated speculative prediction history indicator 230S-U. 2 and / or its speculative prediction circuitry 228 are configured to provide corrected CI prediction entries 806(6), 806(7) in updated speculative prediction history indicators 230S-U by re-predicting the conditions of CI conditional control instructions 208(5), 208(6) after BRB circuit 234 is flushed and CD conditional control instructions 208(7)-208(9) are fetched in the correct instruction flow path. Thus, updated predictions for CI conditional control instructions 208(5), 208(6) are made based on updated speculative prediction history indicators 230S-U, including updated predictions in CD prediction entries 306(3)-306(5) of FIG. 8D for CD conditional control instructions 208(7)-208(9).

[0050] In one example, unresolved CI-conditional control instructions 208 are processed based on updated speculative prediction history indicators 230S-U to improve accuracy. Instruction processing circuit 204 is configured to determine whether a re-prediction for an unresolved CI-conditional control instruction 208 in CI prediction entries 306(5), 806(6) differs from its initial prediction in CI prediction entries 806(5)-306(6) in speculative prediction history indicator 230S of FIG. 8C. If a re-prediction for an unresolved CI-conditional control instruction 208 in CI prediction entries 306(5), 806(6) differs from its initial prediction in CI prediction entries 806(5), 306(6) in speculative prediction history indicator 230S, instruction processing circuit 204 is also configured to override maintenance of BRB circuit 234. Corresponding unresolved CI conditional control instructions 208 whose CI prediction entries 306 do not match the re-prediction are flushed from the BRB circuit 234, and the unresolved CI conditional control instructions 208 are refetched and processed. In this manner, the refetched unresolved CI conditional control instructions 208 are again predicted based on updated speculative prediction history indicators 230S-U, which include updated predictions in CD prediction entries 306(3)-306(5) of Figure 8D for CD conditional control instructions 208(7)-208(9). The updated predicted address pointers in the BRB circuit 234 are defined by the respective hit table indicators 504(0)-504(X), set number indicators 506(0)-506(X), and entry tags 508(0)-508(X), and the predicted values ​​in the prediction entries 510(1)-510(X) for each outstanding CI conditional control instruction 208 in the BRB circuit 234 are updated to prevent erroneous prediction value updates in the prediction table circuit 232 with previous predicted address pointers in the BRB circuit 234 for the outstanding CI conditional control instruction 208.

[0051] This technique of re-predicting all outstanding CI-conditional control instructions 208 may delay the fetching and processing of newer, younger instructions 208 by the instruction processing circuitry 204. However, the improved accuracy of the predictions and the processing time savings from reduced misprediction recovery may outweigh this additional delay.

[0052] In another example, instead of re-predicting all outstanding CI conditional control instructions 208 and delaying the fetching of newer, younger instructions 208, the instruction processing circuitry 204 may be configured to continue fetching newer, younger instructions 208. A separate circuit in the instruction processing circuitry 204, such as the speculative prediction circuitry 228, may determine, in a separate process, updated predicted address pointers in the BRB circuitry 234 defined by respective hit table indicators 504(0)-504(X), set number indicators 506(0)-506(X), and entry tags 508(0)-508(X), for the outstanding CI conditional control instructions 208, as described above. The instruction processing circuit 204 may then be configured to re-predict the outstanding CI-conditional control instruction 208 after misprediction recovery as described above to determine whether the re-prediction for the outstanding CI-conditional control instruction 208 in CI prediction entries 306(5), 306(6) differs from its initial prediction in CI prediction entries 806(5), 806(6) in the speculative prediction history indicator 230S of Figure 8C. If the re-prediction for the outstanding CI-conditional control instruction 208 in CI prediction entries 306(5), 806(6) differs from its initial prediction in CI prediction entries 806(5), 306(6) in the speculative prediction history indicator 230S, the instruction processing circuit 204 is also configured to override maintenance of the BRB circuit 234, as described above.

[0053] FIG. 9 is a block diagram of an exemplary processor-based system 900 including a processor 902 configured to recover speculative history during misprediction recovery associated with a younger CI conditional control instruction 208 to provide an accurate speculative history for making the speculative prediction while avoiding the need to re-fetch the younger CI conditional control instruction. For example, the processor 902 may be configured to employ a control-independence technique to avoid the need to re-fetch the CI / DI instruction during misprediction recovery. The processor 902 may recover a previous prediction made for the CI conditional control instruction 208 prior to the misprediction of the older conditional control instruction such that the speculative prediction history indicator 230S accurately reflects the prediction history of the CI conditional control instruction. The processor 902 may include, without limitation, the processor 200 of FIG. 2 and any of the functionality for recovering speculative history during misprediction recovery associated with a younger CI conditional control instruction to provide an accurate speculative history for making the speculative prediction described in FIGS. 2-8.

[0054] The processor-based system 900 may be one or more circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 900 includes a processor 902. The processor 902 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. The processor 902 is configured to execute processing logic in computer instructions to perform the operations and steps described herein. In this example, the processor 902 includes a speculative prediction circuit 904 for speculatively predicting fetched conditional control instructions. The speculative prediction circuit 904 may be the speculative prediction circuit 228 of FIG. 2. The processor 902 also includes an instruction cache 906 for temporary, fast-access memory storage of instructions, and an instruction processing circuit 908. Instructions fetched or prefetched from memory, such as from system memory 910 via system bus 912, are stored in instruction cache 906. Instruction processing circuitry 908 is configured to process instructions fetched into instruction cache 906 and process the instructions for execution. Instruction processing circuitry 908 is configured to insert the fetched instructions into one or more instruction pipelines, which are then processed for execution.

[0055] The processor 902 and the system memory 910 are coupled to a system bus 912, which may interconnect peripheral devices included in the processor-based system 900. As is well known, the processor 902 communicates with these other devices by exchanging address, control, and data information via the system bus 912. For example, the processor 902 may communicate bus transaction requests to a memory controller 914 in the system memory 910, as an example of a slave device. Although not shown in FIG. 9, multiple system buses 912 may be provided, with each system bus constituting a different fabric. In this example, the memory controller 914 is configured to provide memory access requests to a memory array 916 in the system memory 910. The memory array 916 is comprised of an array of storage bit cells for storing data. The system memory 910 may be, by way of non-limiting example, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), etc., and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0056] Other devices may be connected to the system bus 912. As shown in FIG. 9, these devices may include, by way of example, a system memory 910, one or more input devices 918, one or more output devices 920, a modem 922, and one or more display controllers 924. The input devices 918 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 920 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 922 may be any device configured to enable the exchange of data to and from a network 926. The network 926 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The modem 922 may be configured to support any type of desired communication protocol. The processor 902 may also be configured to access a display controller 924 via the system bus 912 to control information sent to one or more displays 928. The display 928 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0057] 9 may include a set of instructions 930, which may include conditional control instructions, causing such instructions to be either CI or CD instructions. The instructions 930 may be stored in the system memory 910, the processor 902, and / or the instruction cache 906, as examples of non-transitory computer-readable media 932. The instructions 930 may also reside, completely or at least partially, within the system memory 910 and / or the processor 902 during execution. The instructions 930 may also be transmitted or received over the network 926 via the modem 922, such that the network 926 includes the non-transitory computer-readable medium 932.

[0058] Although the non-transitory computer-readable medium 932 is shown as a single medium in one exemplary embodiment, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" should therefore be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0059] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0060] The embodiments disclosed herein may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. The instructions may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having the instructions stored thereon. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical string media, flash memory devices, etc.).

[0061] Unless otherwise indicated, and as is apparent from the foregoing description, descriptions utilizing terms such as "processing," "computing," "determining," "displaying," etc. throughout the description should be understood to refer to the operations and processes of a computer system or similar electronic computing device that manipulates and converts data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory, registers, or other such information storage, transmission, or display devices.

[0062] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0063] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0064] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0065] The embodiments disclosed herein may be embodied in hardware and in instructions stored on the hardware, which may reside in, for example, RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. One exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0066] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. Additionally, one or more operational steps described in an exemplary embodiment may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0067] Unless otherwise expressly stated, it is in no way intended that any method disclosed herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps should be followed, or unless it is otherwise specifically stated in the claim or description that the steps are to be limited to a particular order, no particular order is intended to be inferred.

[0068] It will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that are incorporated into the spirit and substance of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

Claims

1. 1. A processor, comprising: an instruction processing circuit comprising one or more instruction pipelines; a first speculative prediction history indicator; The instruction processing circuit speculatively predicting a condition at a first conditional control instruction in an instruction stream in a first instruction pipeline of the one or more instruction pipelines based on the first speculative prediction history indicator; speculatively predicting the conditions of one or more first control-dependent (CD) conditional control instructions in a first CD instruction region that follow a first conditional control instruction in the instruction stream; speculatively predicting the condition of one or more first control independent (CI) conditional control instructions in a CI instruction region following the first CD instruction region in the instruction stream; updating one or more first CI prediction entries of the first speculative prediction history indicator based on a speculative prediction of each of the one or more first CI conditional control instructions in the CI instruction domain; Executing the first conditional control instruction to resolve the condition of the first conditional control instruction; and in response to the speculative prediction of the first conditional control instruction not meeting the resolved condition in execution of the first conditional control instruction, storing the one or more first CI prediction entries of the first speculative prediction history indicator; fetching one or more second CD conditional control instructions in a second CD instruction domain based on the resolved condition of the first conditional control instruction; speculatively predicting conditions of the one or more second CD conditional control instructions in the second CD instruction domain; and retrieving the one or more saved first CI prediction entries in the first speculative prediction history indicator; It is configured as follows: Processor.

2. The instruction processing circuit further fetching a plurality of instructions from memory into the first instruction pipeline of the one or more instruction pipelines; updating a first prediction entry in the first speculative prediction history indicator based on the speculative prediction of the condition of the first conditional control instruction; fetching the one or more first CD conditional control instructions from the plurality of instructions in the first CD instruction field of the first conditional control instruction based on the speculative prediction of the first conditional control instruction; updating one or more CD prediction entries of the first speculative prediction history indicator based on a speculative prediction of each of the one or more first CD conditional control instructions in the first CD instruction domain; fetching one or more CI instructions in the CI instruction field of the first conditional control instruction; and in response to the speculative prediction of the first conditional control instruction not meeting the resolved condition of the first conditional control instruction upon execution of the first conditional control instruction, updating the first prediction entry in the first speculative prediction history indicator based on the resolved condition of the first conditional control instruction; removing the one or more CD prediction entries of the first speculative prediction history indicator; speculatively predicting the conditions of one or more second CD conditional control instructions in the second CD instruction domain; and updating the one or more CD prediction entries of the first speculative prediction history indicator based on the respective speculative predictions of the one or more second CD conditional control instructions in the second CD instruction domain; The processor of claim 1 configured to:

3. in response to the speculative prediction of the first conditional control instruction not meeting the resolved condition upon execution of the first conditional control instruction; The instruction processing circuit further stalling fetching of a next instruction into the first instruction pipeline until the one or more first CI prediction entries of the first speculative prediction history indicator are restored; The processor of claim 1 .

4. The instruction processing circuit further updating one or more CD prediction entries of the first speculative prediction history indicator based on the respective speculative predictions of the one or more first CD conditional control instructions in the first CD instruction domain; It is structured as follows: The instruction processing circuit recovering the saved one or more first CI prediction entries of the first speculative prediction history indicator after the one or more CD prediction entries of the first speculative prediction history indicator are updated based on the respective speculative predictions of the one or more second CD conditional control instructions in the second CD instruction region; It is configured as follows: The processor of claim 1.

5. The instruction processing circuit configured to shift the one or more CD prediction entries in the first speculative prediction history indicator by the number of the one or more CD prediction entries to shift out the one or more CD prediction entries in the first speculative prediction history indicator, whereby removing the one or more CD prediction entries of the first speculative prediction history indicator.

5. The processor of claim 4, configured to:

6. the instruction processing circuit is configured to append the stored one or more first CI prediction entries in the first speculative prediction history indicator, whereby retrieving the one or more first CI prediction entries stored in the first speculative prediction history indicator; The processor of claim 1 configured to:

7. In response to the retrieval of the one or more saved first CI prediction entries in the first speculative prediction history indicator, the instruction processing circuitry further comprises: speculatively predicting the condition of one or more younger CI conditional control instructions based on the first speculative prediction history indicator; and updating the one or more first CI prediction entries of the first speculative prediction history indicator based on the respective speculative predictions of the one or more CI-conditional control instructions based on the first speculative prediction history indicator; It is configured as follows: The processor of claim 1.

8. In response to the retrieval of the one or more saved first CI prediction entries in the first speculative prediction history indicator, the instruction processing circuitry further comprises: processing the one or more first CI conditional control instructions using the recovered one or more first CI prediction entries based on the first speculative prediction history indicator; It is configured as follows: The processor of claim 1.

9. the instruction processing circuit processes the one or more first CI conditional control instructions using the recovered one or more first CI prediction entries without having to re-fetch the one or more first CI conditional control instructions based on the first speculative prediction history indicator. It is configured as follows: The processor of claim 8 .

10. the instruction processing circuitry processes the one or more first CI conditional control instructions, including the one or more CI data-independent (DI) (CIDI) conditional control instructions that are not data-dependent on the one or more first CD conditional control instructions in the first CD instruction region, without refetching one or more CI DI conditional control instructions based on the first speculative prediction history indicator having the recovered one or more first CI prediction entries. It is configured as follows: The processor of claim 8 .

11. The instruction processing circuit further executing the one or more first CI conditional control instructions using the recovered one or more first CI prediction entries based on the first speculative prediction history indicator; It is configured as follows: The processor of claim 1 .

12. In response to the retrieval of the one or more saved first CI prediction entries of the first speculative prediction history indicator, the instruction processing circuitry further comprises: refetching the one or more first CI conditional control instructions, the one or more first CI conditional control instructions including one or more CI data dependent (DD) (CIDD) conditional control instructions; It is configured as follows: The processor of claim 1 .

13. The processor further comprises: A branch reorder buffer (BRB) circuit, a plurality of branch entries, each comprising: a conditional control instruction identifier prediction entry configured to store an identifier of a conditional control instruction; a prediction address pointer generated based on the first speculative prediction history indicator; and a prediction entry configured to store a prediction indicator for the conditional control instruction; BRB circuit, The instruction processing circuit storing a first conditional control instruction identifier for the first conditional control instruction in a first branch entry of the plurality of branch entries in the BRB circuit; speculatively predicting the condition in the first conditional control instruction in the instruction stream based on a prediction value in a prediction table circuit addressable by the prediction address pointer in the first branch entry; storing one or more second conditional control instruction identifiers in each of the prediction entries within one or more second branch entries of the plurality of branch entries in the BRB circuit, the one or more second conditional control instructions identifying respective one or more first CD conditional control instructions in the first CD instruction field; storing the speculative predictions of the one or more first CD conditional control instructions as respective prediction indicators in the prediction entries of the one or more second branch entries; storing one or more third conditional control instruction identifiers in the prediction entry within one or more third branch entries of the plurality of branch entries in the BRB circuit, the one or more third conditional control instruction identifiers identifying respective one or more first CI conditional control instructions in the CI instruction space; and storing the speculative predictions of the one or more first CI conditional control instructions as respective prediction indicators in the prediction entries of the one or more third branch entries; It is configured as follows: The processor of claim 1.

14. In response to the speculative prediction of the first conditional control instruction not matching the resolved condition upon execution of the first conditional control instruction, the instruction processing circuitry further removing the one or more second conditional control instruction identifiers in the prediction entries in the one or more second branch entries; and storing one or more fourth conditional control instruction identifiers in the prediction entry in one or more fourth branch entries of the plurality of branch entries in the BRB circuit; the one or more fourth conditional control instruction identifiers identify the respective one or more second CD conditional control instructions in the second CD instruction field. It is configured as follows: The processor of claim 13.

15. each branch entry of the plurality of branch entries in the BRB circuit further comprising an index link indicator configured to store an index link to a next branch entry of the plurality of branch entries; In response to the speculative prediction of the first conditional control instruction not matching the resolved condition upon execution of the first conditional control instruction, the instruction processing circuitry further storing an index link in the index link indicator for each branch entry among the plurality of branch entries in the BRB circuit; the index link identifies the respective one or more second CD conditional control instructions in the second CD instruction region to a next branch entry among the plurality of branch entries in the BRB circuit for a next CD conditional control instruction within the one or more second CD conditional control instructions in the second CD instruction region. The processor of claim 14.

16. In response to retrieving the one or more saved first CI prediction entries of the first speculative prediction history indicator, the instruction processing circuitry further: speculatively re-predicting conditions of the one or more first CI conditional control instructions in the CI instruction domain; and updating the one or more first CI prediction entries of the first speculative prediction history indicator based on the speculative re-prediction of each of the one or more first CI conditional control instructions. It is configured as follows: The processor of claim 1 .

17. the instruction processing circuitry is configured to speculatively predict the condition of each of the one or more first CI conditional control instructions based on a prediction value in a prediction table circuit at a prediction address pointer determined based on the first speculative prediction history indicator; The instruction processing circuit further updating the predicted address pointer for each of the one or more first CI conditional control instructions based on a first non-speculative prediction history indicator in response to execution of the one or more first CI conditional control instructions; generating an actual resolved condition for each of the one or more first CI conditional control instructions based on execution of the one or more first CI conditional control instructions; comparing the predicted value for each of the one or more first CI conditional control instructions in the prediction table circuit at the updated prediction address pointer for each of the one or more first CI conditional control instructions with the actual resolved condition for each of the one or more first CI conditional control instructions; updating the prediction value for each of the one or more first CI conditional control instructions in the prediction table circuit at the updated prediction address pointer for each of the one or more first CI conditional control instructions in response to the prediction value for each of the one or more first CI conditional control instructions not matching the actual resolved condition of each of the one or more first CI conditional control instructions at execution time; It is configured as follows:

17. The processor of claim 16.

18. The instruction processing circuit further after fetching the one or more second CD conditional control instructions in the second CD instruction field of the first conditional control instruction based on the resolved condition of the first conditional control instruction; speculatively re-predicting the conditions of the one or more first CI conditional control instructions in the CI instruction domain; and performing a second update for the one or more first CI prediction entries of the first speculative prediction history indicator based on the speculative re-prediction of each of the one or more first CI-conditional control instructions; It is configured as follows:

17. The processor of claim 16.

19. The instruction processing circuit further determining whether the speculatively re-predicted condition of the one or more first CI conditional control instructions in the CI instruction domain matches the speculatively predicted condition of the one or more first CI conditional control instructions in the CI instruction domain; and in response to the speculatively re-predicted condition of the one or more first CI conditional control instructions not matching the speculatively predicted condition of the one or more first CI conditional control instructions in the CI instruction domain, reprocessing the one or more first CI conditional control instructions based on the first speculative prediction history indicator using the second updated one or more first CI prediction entries; It is configured as follows:

20. The processor of claim 18.

20. The instruction processing circuit further fetching a plurality of instructions following the one or more first CI conditional control instructions; speculatively re-predicting conditions of the one or more first CI conditional control instructions in the CI instruction domain; and updating the one or more first CI prediction entries of the first speculative prediction history indicator based on the speculative re-prediction of each of the one or more first CI conditional control instructions. It is configured as follows:

20. The processor of claim 18.

21. 1. A method in a processor for recovering speculative history used to make one or more speculative predictions for a conditional control instruction, the method comprising: speculatively predicting a condition at a first conditional control instruction in an instruction stream in a first instruction pipeline based on a first speculative prediction history indicator; speculatively predicting the conditions of one or more first control-dependent (CD) conditional control instructions in a first CD instruction region that follow the first conditional control instruction in the instruction stream; speculatively predicting the conditions of one or more first control-independent (CI) conditional control instructions in a CI instruction region following the first CD instruction region in the instruction stream; updating one or more first CI prediction entries of the first speculative prediction history indicator based on speculative predictions of each of the one or more first CI conditional control instructions in the CI instruction domain; executing the first conditional control instruction so as to resolve the condition of the first conditional control instruction; by the processor in response to the speculative prediction of the first conditional control instruction not matching the resolved condition in execution of the first conditional control instruction: storing the one or more first CI prediction entries in the first speculative prediction history indicator; fetching one or more second CD conditional control instructions in a second CD instruction field of the first conditional control instruction based on the resolved condition of the first conditional control instruction; speculatively predicting conditions of the one or more second CD conditional control instructions in the second CD instruction domain; and retrieving, within the first speculative-prediction history indicator, the one or more saved first CI prediction entries of the first speculative-prediction history indicator; A method comprising:

22. The method further comprises, by the processor: updating one or more CD prediction entries of the first speculative prediction history indicator based on the speculative prediction of each of the one or more first CD conditional control instructions in the first CD instruction domain; recovering the saved one or more first CI prediction entries of the first speculative prediction history indicator after updating the one or more CD prediction entries of the first speculative prediction history indicator based on the speculative prediction of each of the one or more second CD conditional control instructions in the second CD instruction domain; 22. The method of claim 21, comprising:

23. In response to retrieving the saved one or more first CI prediction entries of the first speculative prediction history indicator, the method further includes, by the processor: processing the one or more first CI conditional control instructions using the recovered one or more first CI prediction entries based on the first speculative prediction history indicator; 22. The method of claim 21, comprising:

24. In response to retrieving the saved one or more first CI prediction entries of the first speculative prediction history indicator, the method further includes, by the processor: speculatively re-predicting the conditions of the one or more first CI conditional control instructions in the CI instruction domain; updating the one or more first CI prediction entries of a first speculative prediction history indicator based on the speculative re-prediction of each of the one or more first CI conditional control instructions; 22. The method of claim 21, comprising:

25. The method further comprises, by the processor: speculatively predicting the condition of each of the one or more first CI conditional control instructions in the CI instruction domain based on a prediction value in a prediction table circuit at a prediction address pointer determined based on the first speculative prediction history indicator; The method further comprises, by the processor: updating the predicted address pointer for each of the one or more first CI conditional control instructions based on a first non-speculative prediction history indicator in response to execution of the one or more first CI conditional control instructions; generating an actual resolved condition for each of the one or more first CI conditional control instructions based on execution of the one or more first CI conditional control instructions; for each of the one or more first CI conditional control instructions, comparing the predicted value for each of the one or more first CI conditional control instructions in the updated prediction table circuit at the updated prediction address pointer with the actual resolved condition for each of the one or more first CI conditional control instructions; updating the prediction value for each of the one or more first CI conditional control instructions in the prediction table circuit with the updated prediction address pointer for each of the one or more first CI conditional control instructions in response to the prediction value for each of the one or more first CI conditional control instructions not matching the actual resolved condition of each of the one or more first CI conditional control instructions at execution time; 25. The method of claim 24, comprising:

26. further comprising, after fetching the one or more second CD conditional control instructions in the second CD instruction field of the first conditional control instruction based on the resolved condition of the first conditional control instruction, speculatively re-predicting conditions of the one or more first CI conditional control instructions in the CI instruction domain; updating the one or more first CI prediction entries of the first speculative prediction history indicator based on the speculative re-prediction of each of the one or more first CI conditional control instructions; 25. The method of claim 24, comprising:

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