Semiconductor device manufacturing method

Abstract

To improve reliability of a semiconductor device.SOLUTION: A second plating film in a different type from a first plating film is formed in a second region R2 after forming the first plating film in a first region R1 in a frame material FM having the first region R1 and the second region R2 extending in the x direction in parallel to which other while being separated from each other. Then, by performing stamping processing to the frame material FM having the first region R1 in which the first plating film is formed and the second region R2 in which the second plating film is formed, a lead frame having a plurality of leads is formed. The lead frame includes a first lead group and a second lead group. The first plating film is formed but the second plating film is not formed in the first lead group. The second plating film is formed, but the first plating film is not formed in the second lead group.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a manufacturing technique for a semiconductor device, and relates to a technique that is effective when applied to the manufacturing technique for a semiconductor device that uses, for example, two types of plating films. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2014-93431 (Patent Document 1) describes a technique that uses a plating film whose main component is nickel and a plating film whose main component is gold. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-93431 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, there is a technology in which two semiconductor chips are packaged together to form a single semiconductor device. In this technology, one semiconductor chip (referred to as the "first semiconductor chip") is connected to a certain lead with a first bonding wire, and the other semiconductor chip (referred to as the "second semiconductor chip") is connected to another lead with a second bonding wire. In this case, the material constituting the bonding wire connecting to the first semiconductor chip and the material constituting the bonding wire connecting to the second semiconductor chip may be different from each other. In other words, a semiconductor device in which two semiconductor chips are packaged together may use bonding wires made of two different materials.

[0005] In order to ensure the reliability of the connection between the bonding wire and the lead, a plating film is formed on the surface of the lead. In this case, the type of plating film to be formed on the surface of the lead is selected depending on the material of the bonding wire. Therefore, in a semiconductor device using bonding wires made of two different materials, two different types of plating films are used.

[0006] According to the inventor's investigations, it has become clear that there is room for improvement in the technology for manufacturing semiconductor devices using two different types of plating films from the viewpoint of improving the reliability of the manufactured semiconductor devices. Therefore, in the technology for manufacturing semiconductor devices using two different types of plating films, there is a need for innovations to improve the reliability of semiconductor devices. [Means for solving the problem]

[0007] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: (a) preparing a frame material including a first region and a second region extending parallel to but spaced from each other in a first direction; (b) forming a first plating film in the first region; (c) forming a second plating film, the second plating film being a different type from the first plating film, in the second region; and (d) after steps (b) and (c), stamping the frame material to form a plurality of device regions each including a portion of the first region and a portion of the second region. Each of the device regions formed in step (d) includes a first die pad, a second die pad, a plurality of first leads aligned in the first direction, and a plurality of second leads aligned in the first direction. The first leads, the first die pad, the second die pad, and the second leads are aligned in a second direction intersecting the first direction. Each of the plurality of first leads includes a portion of the first region but not a portion of the second region, and each of the plurality of second leads includes the portion of the second region but not a portion of the first region. [Effects of the Invention]

[0008] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a semiconductor device including a power transistor and a control circuit that controls the power transistor. [Figure 2] FIG. 1 is a diagram conceptually explaining the "spot plating method." [Figure 3] A diagram showing an example of countermeasures against "plating leaks" [Figure 4] FIG. 10 is a diagram showing an example of a countermeasure against "plating leakage." [Figure 5] FIG. 1 is a diagram conceptually explaining the "stripe plating method." [Figure 6] FIG. 1 is a diagram showing a package structure according to a related art, and is a top view of the package structure seen through a sealing body. [Figure 7] FIG. 1 is a diagram illustrating room for improvement in the related art. [Figure 8] FIG. 1 is a diagram illustrating room for improvement in the related art. [Figure 9] FIG. 2 is a diagram showing a package structure according to an embodiment, and is a top view of the package structure seen through a sealing body. [Figure 10] FIG. 2 is a bottom view of the package structure. [Figure 11] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device. [Figure 12] 12A to 12C are diagrams showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] 13 is a diagram showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 14] 14A to 14C are diagrams showing the manufacturing process of the semiconductor device following FIG. 13. [Figure 15] 15A to 15C are diagrams showing the manufacturing process of the semiconductor device following FIG. 14. [Figure 16] 16 is a diagram showing the manufacturing process of the semiconductor device following FIG. 15. [Figure 17]17A to 17C are diagrams showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 18] FIG. 18 is an enlarged view of the device region in FIG. 17. [Figure 19] 19 is a diagram showing the manufacturing process of the semiconductor device following FIG. 18. [Figure 20] 19A to 19C are diagrams showing the manufacturing process of the semiconductor device following FIG. [Figure 21] 21 is a diagram showing the manufacturing process of the semiconductor device following FIG. 20. [Figure 22] 22 is a diagram showing the manufacturing process of the semiconductor device following FIG. 21. [Figure 23] FIG. 1 is a diagram illustrating a technology under consideration. [Figure 24] FIG. 1 is a diagram illustrating a technology under consideration. [Figure 25] FIG. 1 is a diagram illustrating a technology under consideration. DETAILED DESCRIPTION OF THE INVENTION

[0010] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0011] <Configuration of power transistor and control circuit> FIG. 1 is a diagram showing a circuit configuration of a semiconductor device SA1 including a power transistor and a control circuit that controls the power transistor.

[0012] In FIG. 1, the semiconductor device SA1 has a switching circuit 100 and a control circuit 200. The switching circuit 100 has a main transistor 10 made of a power transistor, a sense transistor 20, and a temperature sensor 30.

[0013] In the switching circuit 100 configured as described above, the main transistor 10 is provided between a lead LD4, which is a power supply terminal that supplies a power supply potential, and a lead LD1 (lead LD7), which is an output terminal, and functions as a switching element for turning on and off the current flowing between the power supply terminal and the output terminal. Meanwhile, the sense transistor 20 has a function of detecting the current value of the current flowing through the main transistor 10, and the temperature sensor 30 has a function of detecting the temperature of the switching circuit 100.

[0014] Next, the control circuit 200 has a function of controlling the switching circuit 100, and includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor 10 and the gate electrode of the sense transistor 20. In Fig. 1, the control circuit 200 is electrically connected to leads LD3 and LD6 that are input terminals of the semiconductor device SA1, a lead LD2 that is a ground terminal, and a lead LD5 that is an output terminal for outputting the output from the control circuit 200 to the outside of the semiconductor device SA1.

[0015] The control circuit 200 is configured to control the on / off of the main transistor 10 included in the switching circuit 100 based on a control signal input from the lead LD3. That is, the control circuit 200 controls the on / off of the main transistor 10 by switching the gate voltage applied to the gate electrode of the main transistor 10.

[0016] In this way, by controlling the on / off of the main transistor 10, a current can be supplied from the lead LD1, which is an output terminal electrically connected to the source of the main transistor 10, to a load connected outside the semiconductor device SA1.

[0017] The semiconductor device SA1 has a circuit configuration as described above.

[0018] <Consideration of improvements> The semiconductor device SA1 described above has a switching circuit 100 and a control circuit 200. Considering the package structure of the semiconductor device SA1, there is a technique for packaging a first semiconductor chip on which the switching circuit 100 is formed and a second semiconductor chip on which the control circuit 200 is formed into a single package. In this technique, a source pad and a first lead of the first semiconductor chip may be connected by a first bonding wire, while a pad and a second lead of the second semiconductor chip may be connected by a second bonding wire.

[0019] In this case, since a large current flows through the first semiconductor chip, a thick aluminum wire primarily composed of aluminum is often used as the first bonding wire connecting the source pad of the first semiconductor chip to the first lead.

[0020] On the other hand, the second semiconductor chip, unlike the first semiconductor chip, does not carry a large current, so a thin gold wire primarily made of gold is often used as the second bonding wire connecting the pad of the second semiconductor chip to the second lead.

[0021] For example, when connecting an aluminum wire to a first lead, a nickel plating film containing nickel as a main component is formed on the surface of the first lead to ensure the connection reliability of the aluminum wire. On the other hand, when connecting a gold wire to a second lead, a silver plating film containing silver as a main component is formed on the surface of the second lead to ensure the connection reliability of the gold wire. In this way, in a package structure in which a first semiconductor chip and a second semiconductor chip are packaged in one package, two different types of plating films are used to correspond to the use of bonding wires made of two different materials.

[0022] First, a technique for forming a plating film on the surface of a lead will be described below.

[0023] <<Spot plating method>> FIG. 2 is a diagram conceptually explaining the "spot plating method."

[0024] In FIG. 2, in the "spot plating method," a frame material FM is prepared, and then a lead LD is formed by stamping (punching) the frame material FM, and a plating film PF is formed on the surface of the lead LD using a mask.

[0025] Here, the "spot plating method" requires a clearance A to account for misalignment of the mask. However, if this clearance A is narrow, "plating leakage" may occur on the side of the lead LD, and in the worst case, the plating may leak outside the package structure. In particular, if the plating film PF is a silver plating film, there is a concern that if the silver plating film leaks outside the package structure, silver migration will occur and short circuits will occur between adjacent leads.

[0026] Therefore, in the "spot plating method," in order to suppress "plating leaks" caused by misalignment of the mask, it is conceivable to ensure the clearance A by, for example, widening the width of the lead LD as shown in Figure 3. This makes it possible to reduce the possibility of "plating leaks" even if misalignment of the mask occurs. However, since the size of the lead LD increases, the size of the semiconductor device (package structure) also increases.

[0027] It is also possible to create a lead structure that is not affected even if "plating leakage" occurs by bending the leads LD, as shown in Figure 4. However, in this case, a lead bending process is added, which increases the manufacturing cost of the lead frame.

[0028] Therefore, the "stripe plating method" described below is being considered as an alternative technique to the "spot plating method," and this "stripe plating method" will be described below.

[0029] <<Stripe plating method>> FIG. 5 is a diagram conceptually explaining the "stripe plating method."

[0030] In FIG. 5 , in the “stripe plating method,” a frame material FM is prepared, a plating film PF is formed in a line shape (stripe shape) on the frame material FM, and then the frame material FM with the plating film PF formed thereon is stamped to form leads LD. In this “stripe plating method,” stamping is performed after the plating film PF is formed, so there is no risk of “plating leakage.” Therefore, the “stripe plating method” does not require measures to prevent “plating leakage,” thereby reducing the manufacturing cost of lead frames. In other words, the “stripe plating method” does not require consideration of “plating leakage” on the side surfaces of the leads LD, so the lead width can be minimized, resulting in the advantage of miniaturizing semiconductor devices. Furthermore, the “stripe plating method” does not require lead bending, resulting in the advantage of reducing the manufacturing cost of lead frames (and therefore the manufacturing cost of semiconductor devices).

[0031] Therefore, the following describes a related technique that uses a "stripe plating method" that has advantages that cannot be obtained with the "spot plating method."

[0032] <<Description of Related Art>> The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have discovered, and is a prerequisite for the present invention.

[0033] FIG. 6 is a diagram showing a package structure PKG according to the related art, and is a top view of the package structure PKG seen through the sealing body MR.

[0034] As shown in Fig. 6, the package structure PKG has a die pad DP which is a chip mounting portion, and a semiconductor chip CHP1 is mounted on this die pad DP via a conductive adhesive 40 made from solder or silver paste. A power transistor is formed on this semiconductor chip CHP1. A semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via an insulating adhesive (not shown). A control circuit for controlling the power transistor is formed on this semiconductor chip CHP2.

[0035] Next, the surface of the semiconductor chip CHP1 has a first source pad formation region in which a source pad SP1 is formed, a second source pad formation region in which a source pad SP2 is formed, and a region sandwiched between the first source pad formation region and the second source pad formation region in a planar view, and the semiconductor chip CHP2 is mounted in this sandwiched region via an insulating adhesive material (not shown).

[0036] The source pad SP1 is connected to the lead LD1 via a thick wire W1. On the other hand, the source pad SP2 is connected to the lead LD7 via a thick wire W2. Furthermore, a plurality of pads PD3 are formed on the semiconductor chip CHP1, while a plurality of pads PD4 and a plurality of pads PD5 are formed on the semiconductor chip CHP2. At this time, each of the plurality of pads PD3 is connected to each of the plurality of pads PD4 via a wire W3, and each of the plurality of pads PD5 is connected to the lead LD2, the lead LD3, the lead LD5, or the lead LD6. Also, the die pad DP is connected to the lead LD4.

[0037] 6, the outer lead portions of the leads LD1 to LD7 protrude from the sealing body MR. In this manner, the package structure PKG in the related art is mounted and configured.

[0038] As shown in FIG. 6, a nickel plating film PF1 containing nickel as a main component and a silver plating film PF2 containing silver as a main component are formed on a partial region of the surface of the leads LD1 to LD3 and LD5 to LD7.

[0039] In this specification, the term "main component" refers to the component that is contained in the largest amount, and is used to indicate that it does not exclude the presence of other components. For example, "mainly composed of nickel" means that nickel is contained in the largest amount, and similarly, "mainly composed of silver" means that silver is contained in the largest amount.

[0040] A thick wire W1 is connected to the lead LD1 via a nickel plating film PF2, and a thick wire W2 is connected to the lead LD7 via a nickel plating film PF2, while a wire W4 is connected to the leads LD2, LD3, LD5, and LD6 via a silver plating film PF1.

[0041] At this time, the nickel plating film PF1 and the silver plating film PF2 are each formed using a "stripe plating method." Specifically, in the related technology, after preparing a frame material, a silver plating film is formed in a line shape (striped shape) on the frame material, and then a nickel plating film having a stripe width smaller than that of the silver plating film is formed in a line shape on the striped silver plating film. In this way, a striped silver plating film and a striped nickel plating film can be formed. Next, a stamping process is performed on the frame material on which the silver plating film and the nickel plating film are formed. This forms a lead frame including leads LD1 to LD3 and LD5 to LD7 having silver plating film and nickel plating film. Thereafter, this lead frame can be used to manufacture, for example, a package structure PKG in the related technology shown in FIG. 6.

[0042] <<Room for improvement>> The package structure PKG in the related art described above uses two types of plating films formed by the "stripe plating method." For example, as shown in the left diagram of FIG. 7, a stripe-shaped silver plating film PF1 and a stripe-shaped nickel plating film PF2 are formed on the lead LD3. In this regard, if the silver plating film PF1 formed on the lower layer is misaligned to the right, as shown in the upper right diagram of FIG. 7, the exposed area of ​​the silver plating film PF1 becomes narrower, making it difficult to connect the wire W4 to the silver plating film PF1, which may result in wire peeling. On the other hand, if the silver plating film PF1 formed on the lower layer is misaligned to the left, as shown in the lower right diagram of FIG. 7, the silver plating film PF1 is formed on the surface of the lead LD3 exposed from the sealing body MR, which may cause silver migration. Furthermore, if silver migration occurs on the lead LD3, it may cause a short circuit between the adjacent leads LD2 and LD3. Thus, misalignment of the silver plating film PF1 formed on the lower layer significantly adversely affects the reliability of the package structure PKG.

[0043] Similarly, for example, as shown in the upper right diagram of Fig. 8, if the nickel plating film PF2 formed on the upper layer is misaligned to the right, the exposed area of ​​the nickel plating film PF2 becomes narrower, making it difficult to connect to a thick wire (not shown), which may result in wire peeling. On the other hand, for example, as shown in the lower right diagram of Fig. 8, if the nickel plating film PF2 formed on the upper layer is misaligned to the left, the wire W4 will be connected to the nickel plating film PF2, which may increase the risk of wire peeling. In this way, misalignment of the nickel plating film PF2 formed on the upper layer also has a significant adverse effect on the reliability of the package structure PKG.

[0044] For the reasons described above, there is room for improvement in the related art from the viewpoint of ensuring the reliability of the packaging structure PKG. Therefore, in this embodiment, a device is provided to overcome the room for improvement that exists in the related art. The technical concept of this embodiment that provides this device will be described below.

[0045] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to use the "stripe plating method," and instead of forming two types of plating films, a nickel plating film and a silver plating film, on each of the multiple leads as in the related art described above, the idea is to divide the multiple leads into a first group of leads on which a nickel plating film is formed and a second group of leads on which a silver plating film is formed.

[0046] That is, the basic idea is to form only one of the plating films, either nickel plating film or silver plating film, on the leads using the "stripe plating method."

[0047] Specifically, the basic concept is to form a nickel plating film in a frame material having a first region and a second region that are spaced apart but extend parallel to each other in a first direction, using a "stripe plating method" to form a nickel plating film in the first region, and then using the "stripe plating method" to form a silver plating film in the second region. Then, the frame material having the first region with the nickel plating film and the second region with the silver plating film is stamped to form a lead frame having multiple leads. At this time, the lead frame includes a first lead group formed by stamping the first region and a second lead group formed by stamping the second region, and only the nickel plating film is formed on the first lead group, while only the silver plating film is formed on the second lead group.

[0048] As a result, according to the basic concept, only one of the nickel plating film or the silver plating film is formed on each of the multiple leads. Therefore, according to the basic concept, relative positional misalignment between the nickel plating film and the silver plating film is not a problem, unlike related technologies in which two types of plating film, nickel plating film and silver plating film, are formed on each of the multiple leads. Therefore, according to the basic concept, wire peeling and silver migration caused by relative positional misalignment between the nickel plating film and the silver plating film can be suppressed, thereby improving the reliability of the semiconductor device (package structure).

[0049] The following describes embodiments that embody the above-described basic concept.

[0050] <Configuration of package structure (semiconductor device)> FIG. 9 is a diagram showing the package structure PKG1 in this embodiment, and is a top view of the package structure PKG1 seen through the sealing body MR.

[0051] As shown in Fig. 9, the package structure PKG1 has a die pad DP1 and a die pad DP2. A semiconductor chip CHP1 having, for example, a power transistor formed thereon is mounted on the die pad DP1. A source pad SP and a plurality of pads PDA are formed on the surface of this semiconductor chip CHP1. Meanwhile, a semiconductor chip CHP2 having, for example, a control circuit for controlling the power transistor formed thereon is mounted on the die pad DP2. A plurality of pads PDB and a plurality of pads PDC are formed on the surface of this semiconductor chip CHP2.

[0052] Next, the package structure PKG1 has a plurality of leads LDA. These leads LDA are integrated with post portions PST. A nickel plating film PFA containing nickel as a main component is formed on the surface of the post portions PST. The leads LDA are arranged side by side in the x direction (first direction).

[0053] The package structure PKG1 also has a plurality of leads LDB. A silver-plated film PFB, mainly composed of silver, is formed on one end of each of the leads LDB. The leads LDB are also arranged side by side in the x direction.

[0054] Here, the leads LDA, the die pad DP1, the die pad DP2, and the leads LDB are arranged in this order in the y direction (second direction) that intersects with the x direction.

[0055] Next, as shown in FIG. 9, a source pad SP formed on the semiconductor chip CHP1 and a post portion PST integrated with a plurality of leads LDA are connected by a plurality of bonding wires BW1. Here, each of the plurality of bonding wires BW1 is made of a material whose main component is aluminum, and each has a diameter of approximately 300 μm. At this time, since a nickel plating film PFA is formed on the surface of the post portion PST, the bonding wire BW1 connected to the post portion PST comes into contact with the nickel plating film PFA. This improves the connection reliability between the bonding wire BW1 and the post portion PST. In other words, by connecting the bonding wire BW1 to the nickel plating film PFA, wire peeling can be suppressed.

[0056] On the other hand, each of the pads PDA formed on the surface of the semiconductor chip CHP1 is connected to each of the pads PDB formed on the surface of the semiconductor chip CHP2 by a bonding wire BW2. Here, the bonding wire BW2 is made of a material containing gold as its main component, and its diameter is about 25 μm.

[0057] Next, as shown in FIG. 9, each of the pads PDC formed on the semiconductor chip CHP2 is connected to each of the leads LDB by a bonding wire BW3. Each of the bonding wires BW3 is made of a material primarily composed of gold, and each has a diameter of approximately 25 μm. Since a silver-plated film PFB is formed on the surface of one end of the lead LDB, the bonding wire BW3 connected to the lead LDB comes into contact with the silver-plated film PFB. This improves the connection reliability between the bonding wire BW3 and the lead LDB. In other words, by connecting the bonding wire BW3 to the silver-plated film PFB, wire peeling can be suppressed.

[0058] The above-mentioned semiconductor chip CHP1, semiconductor chip CHP2, post portion PST, a portion of each of the plurality of leads LDA, a portion of each of the plurality of leads LDB including one end portion, and the plurality of bonding wires BW1 to BW3 are sealed with a sealing body MR.

[0059] 9, the sealing body MR has a rectangular planar shape and has a first side S1 extending in the x-direction and a second side S2 opposite to the first side S1. A plurality of leads LDA are arranged side by side along the first side S1 of the sealing body MR, with the remaining portions of each of the leads LDA exposed only from the first side S1. Similarly, a plurality of leads LDB are arranged side by side along the second side S2 of the sealing body MR, with the remaining portions of each of the leads LDB exposed only from the second side S2.

[0060] Next, Fig. 10 is a bottom view of the package structure PKG1. As shown in Fig. 10, the bottom surfaces of the die pads DP1 and DP2 are exposed from the back surface of the sealing body MR. The package structure PKG1 is configured as described above.

[0061] Here, the package structure PKG1 is explained using a "SON (Small Outline Non-leaded package) package" as an example, but the basic idea of ​​this embodiment can also be embodied as a "SOP (Small Outline Package) package."

[0062] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the package structure (semiconductor device) PKG1 will be described.

[0063] First, as shown in FIG. 11, a frame material FM is prepared, which includes a first region R1 and a second region R2 that extend in parallel to but are spaced apart from each other in the x direction (first direction).

[0064] Then, as shown in Fig. 12, a masking tape MSK1 is attached to the frame material FM so as to cover the area other than the first region R1. Thereafter, the frame material FM with the masking tape MSK1 attached is immersed in a first plating solution containing nickel. As a result, a nickel plating film PFA is formed in the first region R1 exposed from the masking tape MSK1, as shown in Fig. 13.

[0065] Next, after peeling the masking tape MSK1 from the frame material FM, a masking tape MSK2 is attached to the frame material FM so as to cover the area other than the second area R2, as shown in Fig. 14. Then, the frame material FM with the masking tape MSK2 attached is immersed in a second plating solution containing silver. As a result, a silver plating film PFB is formed in the second area R2 exposed from the masking tape MSK2, as shown in Fig. 15.

[0066] Thereafter, the masking tape MSK2 is peeled off from the frame material FM, thereby obtaining the frame material FM having the nickel plating film PFA formed in the first region R1 and the silver plating film PFB formed in the second region R2, as shown in FIG.

[0067] Next, the frame material FM is subjected to stamping (punching). As a result, a plurality of device regions DR, each including a part of the first region R1 and a part of the second region R2, are formed in the frame material FM, as shown in Fig. 17. As a result, a lead frame LF can be manufactured, which is the frame material FM on which a plurality of device regions DR are formed.

[0068] Considering the above description, the nickel plating film PFA is formed over multiple device regions in the process of forming the nickel plating film PFA shown in Fig. 13. Similarly, the silver plating film PFB is formed over multiple device regions in the process of forming the silver plating film PFB shown in Fig. 15.

[0069] Here, FIG. 18 is a schematic diagram showing an enlarged view of one device region DR among a plurality of device regions DR formed on a lead frame LF.

[0070] 18, one device region DR is formed with a die pad DP1, a die pad D2, a plurality of leads LDA aligned in the x direction, and a plurality of leads LDB aligned in the x direction. At this time, the plurality of leads LDA, the die pad DP1, the die pad DP2, and the plurality of leads LDB are aligned in this order in the y direction that intersects with the x direction.

[0071] The leads LDA are integrally formed with the post portions PST, which are made up of a part of the first region R1 on which the nickel plating film PFA is formed. In other words, the leads LDA are connected to one another via a part of the first region R1 of the frame material. Thus, each of the leads LDA includes a part of the first region R1 but does not include a part of the second region R2.

[0072] On the other hand, each of the leads LDB is formed to include, as one end thereof, a portion of the second region R2 on which the silver plating film PFB is formed. In this manner, each of the leads LDB includes a portion of the second region R2 but does not include a portion of the first region R1.

[0073] In the following, a process for manufacturing the package structure PKG1 using the lead frame LF in which the above-mentioned device regions DR are formed will be described, focusing on one device region DR.

[0074] First, as shown in Fig. 19, a semiconductor chip CHP1 on which a power transistor is formed is mounted on a die pad DP1. Specifically, a conductive adhesive CP1 made of silver paste, solder, or the like is applied to the die pad DP1, and then the semiconductor chip CHP1 is mounted on the die pad DP1 via this conductive adhesive CP1. Also, a semiconductor chip CHP2 on which a control circuit is formed is mounted on the die pad DP2. Specifically, a conductive adhesive CP2 made of silver paste, solder, or the like is applied to the die pad DP2, and then the semiconductor chip CHP2 is mounted on the die pad DP2 via this conductive adhesive CP2.

[0075] 20, the source pad SP formed on the surface of the semiconductor chip CHP1 and the post portion PST (part of the first region) on which the nickel plating film PFA is formed are connected by a plurality of bonding wires BW1. At this time, each of the plurality of bonding wires BW1 is made of a material containing aluminum as a main component.

[0076] 21, the pad PDA formed on the surface of the semiconductor chip CHP1 and the pad PDB formed on the surface of the semiconductor chip CHP2 are connected by a bonding wire BW2. Also, the pad PDC formed on the surface of the semiconductor chip CHP2 is connected by a bonding wire BW3 to one end of the lead LDB on which the silver-plated film PFB is formed. At this time, the bonding wires BW2 and BW3 are made of a material mainly composed of gold.

[0077] As described above, a power transistor is formed on the semiconductor chip CHP1, and a control circuit for the power transistor is formed on the semiconductor chip CHP2. The bonding wire BW1 is electrically connected to the source pad SP of the semiconductor chip CHP1, which is electrically connected to the source of the power transistor. At this time, the multiple leads LDA are connected to each other via a part of the first region R1 of the frame material, and the diameter of the bonding wire BW1 is larger than the diameters of the bonding wires BW2 and BW3. This reduces the on-resistance of the source, which serves as the output path.

[0078] 22, the sealing body MR is formed by sealing (molding) the device region DR with resin. Specifically, at least the semiconductor chip CHP1, the semiconductor chip CHP2, the post portion PST (part of the first region), a part of each of the plurality of leads LDA, a part of each of the plurality of leads LDB including one end (part of the second region), and the plurality of bonding wires BW1 to BW3 are sealed with the sealing body MR.

[0079] Then, a plating layer is formed as needed on the remaining portions of the leads LDA and LDB exposed from the sealing body MR. Next, outside the sealing body MR, the leads LDA and LDB are cut at predetermined positions. In addition, the suspension leads connected to the die pads DP1 and DP2 are also cut at predetermined positions.

[0080] In this manner, the package structure PKG1 can be manufactured.

[0081] <Features of the embodiment> Next, the features of this embodiment will be described.

[0082] First, as described above, the basic idea of ​​this embodiment is to divide multiple leads into a first group of leads on which a nickel plating film is formed and a second group of leads on which a silver plating film is formed, assuming that the "stripe plating method" is used.

[0083] Therefore, in order to realize this basic idea, in this embodiment, a so-called "SON (Small Outline Non-leaded package) package" or "SOP (Small Outline Package) package" is adopted as the package structure of the semiconductor device.

[0084] 9, in the present embodiment, a configuration is adopted in which a plurality of leads LDA are arranged along the first side S1 and a plurality of leads LDB are arranged along the second side S2 in a package structure PKG1 including a sealing body MR having a first side S1 extending in the x direction and a second side S2 facing the first side S1 and extending in the x direction. This configuration is realized by a "SON package" or an "SOP package."

[0085] This allows the formation of multiple leads LDA formed integrally with the post portion PST on which the nickel plating film PFA is formed, and multiple leads LDB having one end on which the silver plating film PFB is formed, separately, as shown in Fig. 9. This means that the relative positional deviation between the nickel plating film PFA and the silver plating film PFB does not pose a problem.

[0086] In this embodiment, the basic concept is embodied by realizing a semiconductor device manufacturing method using the following "stripe plating method," assuming that a "SON package" or "SOP package" is used as the package structure of the semiconductor device. Specifically, for example, in a frame material FM having a first region R1 and a second region R2 that are spaced apart but extend parallel to each other in the x direction, a nickel-plated film PFA is formed in the first region R1 using the "stripe plating method," and then a silver-plated film PFB is formed in the second region R2 using the "stripe plating method." Thereafter, a leadframe LF having leads LDA and LDB is formed by stamping the frame material FM having the first region R1 on which the nickel-plated film PFA is formed and the second region R2 on which the silver-plated film PFB is formed. At this time, the lead frame LF includes a first lead group (plurality of leads LDA) formed by stamping the first region R1, and a second lead group (plurality of leads LDB) formed by stamping the second region R2, and only a nickel plating film PFA is formed on the post portion PST integrated with the plurality of leads LDA, while only a silver plating film PFB is formed on each of the plurality of leads LDB (see Figures 11 to 18).

[0087] As described above, the feature of this embodiment is that, in order to realize the basic idea, a "SON package" or an "SOP package" is adopted as a package structure of a semiconductor device, and the method of manufacturing this package structure is adopted as a method of manufacturing a semiconductor device shown in FIGS. 11 to 18, which incorporates a "stripe plating method."

[0088] As a result, according to the characteristic feature of this embodiment, as shown in FIG. 9, a bonding wire BW1 mainly composed of aluminum can be connected to the post portion PST on which the nickel plating film PFA is formed. Meanwhile, a bonding wire BW3 mainly composed of gold can be connected to the lead LDB having one end on which the silver plating film PFB is formed. In this embodiment, the lead LDA integrated with the post portion PST on which the nickel plating film PFA is formed and the lead LDB having one end on which the silver plating film PFB is formed are separately arranged on the first side S1 and the second side S2 of the sealing body MR, which face each other. Therefore, the relative positional deviation between the nickel plating film PFA and the silver plating film PFB does not pose a problem. Therefore, according to this embodiment, wire peeling and silver migration caused by the relative positional deviation between the nickel plating film PFA and the silver plating film PFB can be suppressed, thereby improving the reliability of the semiconductor device (package structure).

[0089] That is, in the related art, for example, as shown in FIG. 6, a so-called "TO package" is adopted in which semiconductor chips CHP1 and CHP2 are stacked and leads LD1 to LD7 are arranged along only one side of the sealing body MR. For this reason, when the "stripe plating method" is adopted in the related art, it is necessary to form two types of plating films, a nickel plating film and a silver plating film, on each lead. As a result, when the "stripe plating method" that can reduce manufacturing costs is used in the related art, the relative positional misalignment between the nickel plating film and the silver plating film becomes apparent as a problem. This point is a novel finding discovered by the present inventor.

[0090] Then, the inventors conducted research focusing on this new finding, and realized that if the first lead group on which a nickel plating film is formed and the second lead group on which a silver plating film is formed are configured as separate lead groups, and the first lead group and the second lead group are arranged along separate sides of the sealing body that constitutes the package structure, then when using the "stripe plating method," the relative positional deviation between the nickel plating film and the silver plating film will not be a problem (basic idea). Subsequently, the inventors arrived at the characteristic point of this embodiment, in which the above-mentioned basic idea is embodied in a semiconductor device manufacturing method shown in Figures 11 to 18, which incorporates the "stripe plating method" in a "SON package" or an "SOP package."

[0091] Considering this, it can be said that the novel findings discovered by the inventors motivated the conceiving of the basic idea, and that this basic idea motivated the conceiving of the features of the present embodiment. Therefore, it can be said that the novel findings discovered by the inventors and the conception of the basic idea based on this finding are of great significance in conceiving the features of the present embodiment.

[0092] Furthermore, when coming up with the specific features of this embodiment from the basic concept, the inventors also considered adopting a so-called "QFN (Quad Flat Non-leaded Package) package" or "QFP (Quad Flat Package) package," but did not end up adopting them, and the reason for this will be explained below.

[0093] A "QFN package" or a "QFP package" is a package structure in which leads are arranged along the four sides of a sealing body. For example, FIG. 23 is a schematic diagram showing a lead frame LF2 for forming a "QFN package" or a "QFP package." In FIG. 23, the area surrounded by dashed lines indicates the formation area of ​​the sealing body MR. The sealing body MR has a first side S1 extending in the x direction, a second side S2 opposite to the first side S1, a third side S3 extending in the y direction, and a fourth side S4 opposite to the third side S3. In this case, as shown in FIG. 23, a lead LDA is arranged along the first side S1, and a lead LDB is arranged along the second side S2. Furthermore, a lead LDC is arranged along the third side S3, and a lead LDD is arranged along the fourth side S4.

[0094] Here, in the lead frame LF2 for forming a "QFN package" or a "QFP package," a nickel-plated film PFA is formed on the post portion PST integrated with the lead LDA, while a silver-plated film PFB is formed on the leads LDB to LDD.

[0095] At this time, when the "stripe plating method" is used, a nickel-plated film PFA and a silver-plated film PFB are formed on a frame material FM as shown in Fig. 24, and then stamping is performed to obtain the lead frame LF2 shown in Fig. 23. As a result, in the lead frame LF2 shown in Fig. 23, a nickel-plated film PFA is formed on the post portion PST integrated with the lead LDA, and a silver-plated film PFB is formed on one end of the lead LDB and on the entire leads LDC and LDD.

[0096] Thereafter, the package structure PKG2 shown in FIG. 25 is manufactured from the lead frame LF2 shown in FIG. 23. Here, since the silver plating film PFB is formed on the entire surfaces of the leads LDC and LDD, in the package structure PKG2 shown in FIG. 25, the silver plating film PFB is formed on the surfaces of the leads LDC and LDD exposed from the package structure PKG2. As a result, there is a concern that silver migration may occur. If silver migration occurs in the leads LDC and LDD, for example, a short circuit may occur between adjacent leads.

[0097] In this way, when the lead frame LF2 for forming a "QFN package" or a "QFP package" is manufactured by the "stripe plating method," the silver plating film PFB is formed on the entire surface of the leads LDC and LDD due to the presence of the leads LDC and LDD extending in the extension direction (x direction) of the silver plating film PFB. As a result, the silver plating film PFB is formed even on the surfaces of the leads LDC and LDD exposed from the package structure PKG2, increasing the risk of short circuit defects due to silver migration.

[0098] For the reasons stated above, a "QFN package" or a "QFP package" is not adopted as a package structure that embodies the basic concept. In contrast, the "SON package" or "SOP package" adopted in this embodiment does not have leads that extend in the direction in which the silver-plated film PFB extends (x-direction). As a result, unlike the "QFN package" or "QFP package," there are no leads on whose entire surface the silver-plated film PFB is formed. For this reason, the "SON package" or "SOP package" can reduce the possibility of short-circuit defects caused by silver migration. Therefore, this embodiment adopts a "SON package" or "SOP package" rather than a "QFN package" or "QFP package" as a package structure that embodies the basic concept.

[0099] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0100] In this embodiment, the package structure PKG1 is described in which the lower surfaces of the die pads DP1 and DP2 are exposed from the back surface of the sealing body MR, but the technical idea of ​​this embodiment is not limited to this and can be widely applied to package structures in which the lower surfaces of the die pads DP1 and DP2 are covered with the sealing body MR. Note that the "lower surface of the die pad" is defined as the surface opposite to the chip mounting surface (upper surface) on which the semiconductor chip is mounted.

[0101] In the above-described embodiment, the description has been given assuming that a power MOSFET is used as the power transistor formed on the semiconductor chip. However, the technical ideas of the above-described embodiment are not limited to this, and can be widely applied to, for example, semiconductor devices that use an IGBT (Insulated Gate Bipolar Transistor) as the power transistor.

[0102] The above embodiment includes the following aspects.

[0103] (Addendum) Semiconductor device, including: First die pad; Second die pad; a first semiconductor chip mounted on the first die pad; a second semiconductor chip mounted on the second die pad; a plurality of first leads integrated with post portions on which a first plating film is formed; a plurality of second leads each including one end on which a second plating film is formed; a first conductive member connecting the first semiconductor chip and the post portion; a second conductive member connecting the second semiconductor chip and the one end; and an encapsulant that encapsulates at least the first semiconductor chip, the second semiconductor chip, the post portion, a portion of each of the plurality of first leads, a portion of each of the plurality of second leads including the one end portion, the first conductive member, and the second conductive member; where: The sealing body is a first side extending in the first direction; a second side opposite to the first side; and the plurality of first leads are arranged only along the first side, the second leads are arranged only along the second side; The first leads, the first die pad, the second die pad, and the second leads are arranged in this order in a second direction intersecting the first direction. [Explanation of symbols]

[0104] 10 Main Transistor 20 Sense transistor 30 Temperature Sensor 40 Conductive adhesive 50 Insulating adhesive 100 Switching Circuit 200 Control circuit BW1 Bonding Wire BW2 Bonding Wire BW3 Bonding Wire CHP1 semiconductor chip CHP2 semiconductor chip CP1 conductive adhesive CP2 conductive adhesive DP die pad DP2 die pad DR Device Area FM frame material LD lead LDA Lead LDB Lead LDC Lead LDD lead LD1 lead LD2 Lead LD3 Lead LD4 Lead LD5 Lead LD6 Lead LD7 Lead LF lead frame LF2 lead frame MR sealed body MSK1 masking tape MSK2 masking tape PDA Pad PDB Pad PDC Pad PD3 Pad PD4 Pad PD5 Pad PF plating film PFA nickel plating film PFB silver plating film PF1 Silver plating film PF2 Nickel plating film PKG package structure PKG1 package structure PKG2 package structure PST Post Department R1 1st area R2 2nd area SA1 Semiconductor Device SP sauce pad SP1 Source Pad SP2 Sourcepad S1 First side S2 Second side S3 Third side S4 Fourth side W1 thick wire W2 thick wire W3 Wire W4 Wire

Claims

1. A method for manufacturing a SON or SOP type semiconductor device, comprising the steps of: (a) preparing a frame material including a first region and a second region extending parallel to but spaced apart from each other in a first direction; (b) forming a first plating film in the first region; (c) forming a second plating film, the second plating film being of a different type from the first plating film, in the second region; (d) after the steps (b) and (c), stamping the frame material to form a plurality of device regions each including a portion of the first region and a portion of the second region; (e) after the step (d), a step of mounting a first semiconductor chip on the first die pad; (f) after the step (d), a step of mounting a second semiconductor chip on the second die pad; (g) after the steps (e) and (f), electrically connecting the first semiconductor chip to a plurality of first leads via a plurality of first conductive members; (h) after the steps (e) and (f), electrically connecting the second semiconductor chip to a plurality of second leads via a plurality of second conductive members different in type from the plurality of first conductive members; and (i) sealing at least the first semiconductor chip, the second semiconductor chip, a portion of the first region, and a portion of the second region with a sealing body; Here, each of the plurality of device regions formed in the step (d) is the first die pad; the second die pad; the first leads aligned in the first direction; and the plurality of second leads arranged in the first direction; and the plurality of first leads, the first die pad, the second die pad, and the plurality of second leads are arranged side by side in a second direction intersecting the first direction such that the first die pad and the second die pad are located between the plurality of first leads and the plurality of second leads in a plan view; In the step (b), the first plating film is formed over the plurality of device regions; In the step (c), the second plating film is formed across the plurality of device regions; each of the plurality of first leads includes the portion of the first region but does not include the portion of the second region; Each of the plurality of second leads includes the portion of the second region but does not include the portion of the first region.

2. 2. The method for manufacturing a semiconductor device according to claim 1, the first plating film is a nickel plating film, the second plating film is a silver plating film, each of the plurality of first conductive members is a first bonding wire containing aluminum as a main component; each of the plurality of second conductive members is a second bonding wire containing gold as a main component; the step (g) is a step of electrically connecting the plurality of first conductive members to the plurality of first leads via the first plating film, The step (h) is a step of electrically connecting the second conductive members to the second leads via the second plating film.

3. 3. The method for manufacturing a semiconductor device according to claim 2, After the step (d), the first leads are connected to one another via the part of the first region of the frame material; The diameter of the first bonding wire is larger than the diameter of the second bonding wire.

4. 4. The method for manufacturing a semiconductor device according to claim 3, a power transistor is formed on the first semiconductor chip, a control circuit for the power transistor is formed on the second semiconductor chip, The first bonding wire is electrically connected to a source pad of the first semiconductor chip, which is electrically connected to the source of the power transistor.

5. 2. The method for manufacturing a semiconductor device according to claim 1, (j) after the step (e) and the step (f) and before the step (i), electrically connecting the first semiconductor chip to the second semiconductor chip via a plurality of third conductive members; The present invention further includes:

6. 2. The method for manufacturing a semiconductor device according to claim 1, After the step (i), the lower surface of the first die pad and the lower surface of the second die pad are exposed from the encapsulant.

7. 2. The method for manufacturing a semiconductor device according to claim 1, After the step (i), the lower surface of the first die pad and the lower surface of the second die pad are covered with the sealing body.

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