Processor

Abstract

To provide a processor for accelerating processing in a multi-core mode to satisfy both performance and functional safety requirements.SOLUTION: In a processor having a dual-core lockstep mechanism, a core fault diagnosis method has a dynamic switching mode for switching to perform the diagnosis in a dual-core lockstep mode and to perform functions other than the fault diagnosis in a multi-core mode. In the dynamic switching mode, switching between the dual-core lockstep mode and the multi-core mode is performed within a predetermined execution cycle.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a processor having multiple cores. [Background technology]

[0002] Conventionally, processor systems equipped with a fault detection mechanism (dual-core lockstep) have been known (Patent Document 1). In dual-core lockstep, two cores are made to execute the exact same calculation, and processor faults are detected by comparing the outputs, so the actual performance is equivalent to that of a single core.

[0003] For this reason, processors have been developed that can dynamically switch between dual-core lockstep mode and multi-core mode depending on the required level of functional safety. For example, such processors can be controlled to operate in dual-core lockstep mode when running applications with strict safety requirements such as Automotive Safety Integrity Level (ASIL) C or D, and in multi-core mode for safety requirements of ASIL B or lower. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 198184 Summary of the Invention [Problem to be solved by the invention]

[0005] To detect processor failures during multi-core mode operation, software diagnosis (which involves performing diagnostic calculations on the processor) must be performed on each processor, but this increases the time required to perform the diagnosis, making it difficult to obtain the benefits of multi-core mode.Furthermore, since expected value data for calculation results must be stored in ROM or RAM beforehand for diagnosis, this also creates the problem of straining memory resources.

[0006] Therefore, an object of the present invention is to provide a processor that speeds up processing in multi-core mode and satisfies both the requirements for performance and functional safety. [Means for solving the problem]

[0007] The present invention employs the following technical means to solve the above problems. The processor of the present invention is a processor equipped with a dual-core lockstep mechanism and has a dynamic switching mode that switches so that core fault diagnosis is performed in dual-core lockstep mode and functions other than fault diagnosis are performed in multi-core mode.

[0008] Another aspect of the processor of the present invention is a processor having multiple cores, and is equipped with a comparator that compares the calculation results of the multiple cores, and a control unit that diagnoses core faults by having the multiple cores execute the same calculation and compares the results, and that performs functions other than fault diagnosis by having the multiple cores execute different calculations in parallel. [Effects of the Invention]

[0009] The configuration of the present invention can reduce the time required for fault diagnosis of cores, thereby increasing the execution time in multi-core systems while ensuring safety. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a configuration of a processor according to an embodiment. [Figure 2]1A and 1B are schematic diagrams showing an example of an externally controlled processor and an example of a self-contained processor, respectively; [Figure 3] FIG. 2 is a diagram illustrating a specific example of a core. [Figure 4] FIG. 2 is a diagram illustrating execution modes of a processor according to an embodiment. [Figure 5] 10 is a flowchart showing a method for determining an execution mode of a processor according to the present embodiment. [Figure 6] 10 is a flowchart showing mode switching in a dynamic switching mode. [Figure 7] 1A is a diagram illustrating a conventional fault diagnosis process, and FIG. 1B is a diagram illustrating a fault diagnosis process according to the present embodiment. [Figure 8] 10 is a schematic diagram comparing the processing time for fault diagnosis between the conventional technique and the present embodiment; [Figure 9] FIG. 1 is a diagram illustrating an example of a processor equipped with an FPU having a homogeneous multi-core configuration. [Figure 10] FIG. 1 is a diagram illustrating an example of a processor having two AD conversion units. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a processor according to an embodiment of the present invention will be described with reference to the drawings. 1 is a diagram showing the configuration of a processor according to an embodiment. The processor includes a first core 1 and a second core 2 as arithmetic units, a comparator 3 that compares the outputs of the first core 1 and the second core 2, a multiplexer MUX 4 for changing the processor's execution mode, a gate 5, and a control unit 6 that controls mode switching. The first core 1 and the second core 2 have the same configuration, and output the same arithmetic result when the same data is input. The processor has a dual-core lockstep mechanism that detects faults by comparing the arithmetic results of the first core 1 and the second core 2.

[0012] The processor has a first line L1 for inputting data to the first core 1 and a second line L2 for inputting data to the second core 2. The first line L1 branches, one end connected to the first core 1 and the other end connected to a multiplexer 4. The second line L2 is connected to the multiplexer 4. The processor also has a third line L3 for inputting a mode switching signal. The third line L3 is connected to the control unit 6.

[0013] The control unit 6 switches whether the processor operates in dual-core lockstep (hereinafter referred to as "DCLS") mode or multi-core mode based on the mode switching signal. The control unit 6 controls the first core 1, the second core 2, the comparator 3, the multiplexer 4, and the gate 5 based on the mode switching signal. Specifically, the control unit 6 performs synchronization control for the first core 1 and the second core 2 when switching modes. The control unit 6 also controls the comparator 3 to be enabled when in DCLS mode.

[0014] The control unit 6 controls the multiplexer 4 to switch the input data to the second core 2. In DCLS mode, the multiplexer 4 controls the data input from the first line L1 to be input to the second core 2. As a result, the same data is input to the first core 1 and the second core 2, and the first core 1 and the second core 2 perform the same calculation. The comparator 3 then compares the outputs of the first core 1 and the second core 2. If the outputs match, it determines that there is no abnormality, and if the outputs do not match, it determines that there is an abnormality and outputs an error. In addition, in DCLS mode, the control unit 6 controls the gate 5 to stop the output from the second core 2.

[0015] If the mode switching signal is a signal specifying the multi-core mode, the control unit 6 controls the multiplexer 4 to input the data input from the second line L2 to the second core 2. As a result, different data is input to the first core 1 and the second core 2, and the first core 1 and the second core 2 perform calculations independently. In this case, the comparator 3 disables its comparison operation and stops outputting an error. Furthermore, if the signal specifies the multi-core mode, the control unit 6 controls the gate 5 to output the output from the second core 2 to the outside.

[0016] When the mode switching signal is a signal specifying the dynamic switching mode, the control unit 6 switches so that core fault diagnosis is performed in the DCLS mode and main functions other than the fault diagnosis are performed in the multi-core mode. This operation will be described later with reference to FIG.

[0017] As described above, in DCLS mode, the second core 2 performs the same calculations as the first core 1 for comparison purposes, so the first core 1 is sometimes called the "master" and the second core 2 is sometimes called the "checker."

[0018] The explanation so far has been about an "externally controlled" type of processor in which the control unit 6 switches the processor mode in response to a mode switching signal from the outside. However, the control unit 6 may also switch modes independently. FIG. 2(a) is a schematic diagram showing an example of an externally controlled processor, and FIG. 2(b) is a schematic diagram showing an example of a self-contained processor. In the externally controlled type, the processor's operating mode is switched by receiving a mode switching signal from an external host or an external CPU 7. In contrast, in the self-contained type, the control unit 6 switches between DCLS mode and multi-core mode in response to instructions from the master core (first core 1). The self-contained switching mechanism is suitable for dynamic switching between DCLS mode and multi-core mode within a specified execution cycle.

[0019] Next, the configuration of the first core 1 and the second core 2 will be described. FIG. 3 is a diagram showing a specific example of the cores 1 and 2. As shown in FIG. 3, the cores 1 and 2 may be any of a CPU (Central Processing Unit) having a control register, a status register, a GPR (General Purpose Register), and a PC (Program Counter), an ALU (Arithmetic and Logic Unit), an FPU (Floating Point Unit), a DSP (Digital Signal Processor), a VPU (Vector Processing Unit), a GPU (Graphics Processing Unit), an AI processor, or a combination of these. Note that the configuration shown in FIG. 3 is an example, and the cores 1 and 2 can be implemented in various forms depending on the application. As such, the cores 1 and 2 are not limited to CPUs, but may be arithmetic units in a broad sense.

[0020] 4 is a diagram for explaining the execution modes of the processor according to the embodiment. The right column of the table lists three modes that the processor can execute, and the left column shows examples of safety requirement levels at which the execution modes are used.

[0021] The processor has three modes: DCLS mode, dynamic switching mode, and multi-core mode. In DCLS mode, paired cores always execute the same calculation and compare the outputs to detect processor failures. DCLS mode is used when running applications with strict safety requirements, such as ASIL C and D.

[0022] In multi-core mode, two cores perform different calculations, and fault detection is not performed by comparing the calculation results. Multi-core mode is used when running QM (Quality Management) level applications that do not have an ASIL assigned but require appropriate quality control measures.

[0023] In dynamic switching mode, core fault diagnosis is performed in DCLS mode, and functions other than fault diagnosis are performed in multi-core mode. Dynamic switching mode switches between DCLS mode and multi-core mode within a specified execution cycle. Dynamic switching mode is used when running applications that require safety requirements such as ASIL A and B.

[0024] 5 is a flowchart showing how to determine the execution mode of the processor in this embodiment. First, it is determined whether the safety requirement level required by the application is ASIL C or higher (S10). If the required safety requirement level is ASIL C or higher (YES in S10), DCLS mode is selected (S12). The DCLS mode selected here is a mode in which the system is always run in DCLS mode, and both the main functions and fault diagnosis are performed in DCLS mode. In DCLS mode, fault diagnosis is performed by hardware, so fault diagnosis by software is not required.

[0025] If the required safety requirement level is not ASIL C or higher (NO in S10), it is determined whether the required safety requirement level is ASIL A or higher (S11). If the required safety requirement level is ASIL A or higher (YES in S11), the dynamic switching mode is selected (S13). If the required safety requirement level is not ASIL A or higher (NO in S11), the multi-core mode is selected (S14). The multi-core mode selected here is a mode in which the system is always run in multi-core mode, and both the main function and fault diagnosis are run in multi-core mode.

[0026] 6 is a flowchart showing mode switching in the dynamic switching mode. The processor executes a main function other than fault diagnosis in the multi-core mode (S20). The processor determines whether or not a diagnosis time has arrived while the main function is being executed (S21). The diagnosis time is set to arrive at least once within a predetermined execution period.

[0027] If the diagnosis time has not yet arrived (NO in S21), the main function is executed until the diagnosis time arrives (S20). If the diagnosis time has arrived (YES in S21), the processor switches from multi-core mode to DCLS mode (S22), and the diagnostic code is executed in the processor to be diagnosed (S23). Specifically, the same operation is executed in the paired cores, and whether a fault has occurred is determined based on whether the operation results match (S24).

[0028] If it is determined that there is a fault (YES in S24), the processor issues a DCLS error fault notification and the processor abnormally terminates (S27). If the fault determination result indicates that there is no fault (NO in S24), a normal determination is made (S25), and the processor switches from DCLS mode to multi-core mode (S26) and executes its main function (S20).

[0029] As described above, in this embodiment, the main function is executed in multi-core mode, and when the time for diagnosis arrives, the mode is switched to DCLS mode to perform fault diagnosis, thereby ensuring safety while increasing the execution time in multi-core mode.

[0030] FIG. 7 is a diagram illustrating the difference between conventional fault diagnosis processing and the fault diagnosis processing of this embodiment. FIG. 7(a) shows conventional fault diagnosis processing, and FIG. 7(b) shows the fault diagnosis processing of this embodiment. Conventionally, when a main function is executed in multi-core mode, fault diagnosis is also performed in multi-core mode. As shown in FIG. 7(a), a diagnostic command is executed (S30), the execution result of the diagnostic command is compared with an expected value (S31), and it is determined whether the core is normal or abnormal (S32). For this reason, it is necessary to store the expected value in memory and to perform a comparison process.

[0031] In this embodiment, the main function is executed in multi-core mode, but when fault diagnosis is performed, the system switches to DCLS mode (S40) and executes the same diagnostic command on both cores (S41) to perform fault diagnosis. Comparison with expected values ​​is not required, and any abnormalities can be detected by DCLS. This eliminates the need for memory resources and enables high-speed diagnosis.

[0032] Fig. 8 is a schematic diagram comparing the processing time for fault diagnosis between the conventional technology and this embodiment. As shown in Fig. 8, in this embodiment, fault diagnosis is performed in DCLS mode, thereby shortening the diagnosis time and increasing the time allocated to executing the main function.

[0033] Although the processor according to the embodiment of the present invention has been described above, the processor of the present invention is not limited to the above-described embodiment. In the above-described embodiment, a processor equipped with a mechanism for performing DCLS mode has been described as an example, but it is also possible to significantly reduce the time required for fault diagnosis by incorporating a hardware comparator that compares the outputs of cores in a general homogeneous multi-core configuration.

[0034] Figure 9 shows an example of a processor equipped with a homo multi-core FPU. As shown in Figure 9(a), under normal circumstances, it operates as a 128-bit arithmetic unit (32 bits x 4), and the comparator is disabled. During fault diagnosis, as shown in Figure 9(b), the same data is input to the upper and lower bits. The same 32-bit x 2 data is input to the FPU, and a 64-bit operation is performed. The upper and lower operation results are compared by the comparator to detect errors.

[0035] FIG. 10 is a diagram showing an example of a processor equipped with two AD conversion units. The core is made up of a combination of AD conversion units and registers. As shown in FIG. 10(a), under normal circumstances, different input signals are input, AD conversion is performed by each AD conversion unit, and the conversion results are stored in the register. The comparator is disabled. During fault diagnosis, as shown in FIG. 10(b), the same input signal is input to the two AD conversion units, and the conversion results of each AD conversion unit are stored in the register. In this case, the comparator is enabled, and the comparator reads and compares the data in the register to detect errors.

[0036] As shown in the examples above, the processor of the present invention may be a processor having multiple cores, and may include a comparator that compares the calculation results of the multiple cores, and a control unit that performs core fault diagnosis by having the multiple cores execute the same calculation and compares the calculation results, and that performs functions other than fault diagnosis by having the multiple cores execute different calculations in parallel. [Explanation of symbols]

[0037] 1...first core, 2...second core, 3...comparator, 4. Multiplexer, 5. Gate, 6. Control section, 7. External host or CPU.

Claims

1. A processor with a dual-core lockstep mechanism, A dynamic switching mode is provided in which core fault diagnosis is performed in dual-core lockstep mode and functions other than fault diagnosis are performed in multi-core mode; A processor that operates in one of a mode that always executes dual-core lockstep mode, a mode that always executes multi-core mode, and the dynamic switching mode, depending on the application being executed.

2. The processor according to claim 1 , wherein in the dynamic switching mode, switching between a dual-core lockstep mode and a multi-core mode is performed within a predetermined execution period.

3. A processor having multiple cores, a comparator for comparing calculation results of the multiple cores; a control unit having a dynamic switching mode in which the core fault diagnosis is performed by making the multiple cores execute the same operation and comparing the operation results, and in which the functions other than the fault diagnosis are performed by making the multiple cores execute different operations in parallel; Equipped with A processor that operates in one of a mode that always executes dual-core lockstep mode, a mode that always executes multi-core mode, and the dynamic switching mode, depending on the application being executed.

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