Fault injection evaluation method and system, and computer program product and medium

Abstract

A fault injection evaluation method and system, and a computer program product and a medium. The fault injection evaluation method comprises: configuring a target number of cycles for a circuit under test (101), wherein the target number of cycles is the number of cycles during which said circuit operates after being reset; injecting a fault into said circuit (102); outputting a reset signal to said circuit, and acquiring a fault output result that is output by said circuit after the fault is injected (103); and on the basis of the fault output result and a reference output result, performing a comparison to acquire a fault evaluation result (104). By means of the method, it is not necessary to additionally provide a reference circuit, so that the structural complexity of the fault injection evaluation system can be reduced, and the consumption of resources required during evaluation can be reduced.

Description

Fault injection assessment methods and systems, computer program products, media

[0001] This application claims priority to Chinese Patent Application No. 202411041879.4, filed on July 30, 2024, entitled "Fault Injection Assessment Method and System, Computer Program Product, Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of FPGA technology, and in particular to a fault injection assessment method and apparatus, computer program, and medium. Background Technology

[0003] Static Random Access Memory (SRAM) type Field Programmable Gate Array (FPGA) chips are susceptible to radiation effects in the space environment, especially the Single Event Upset (SEU) effect. This study simulates SEUs in the space environment using fault injection to evaluate the radiation resistance of FPGA chips.

[0004] Traditional fault injection assessment systems include a host computer, the circuit under test, a reference circuit, an excitation circuit, and a result comparison circuit, which are relatively complex in structure and consume a lot of resources during fault injection assessment. Summary of the Invention

[0005] The purpose of this invention is at least to provide a fault injection assessment method, which requires a fault injection assessment system with a relatively simple structure and requires fewer resources during fault injection assessment.

[0006] In a first aspect, the present invention provides a fault injection assessment method, comprising: configuring a target number of cycles for a circuit under test, wherein the target number of cycles is the number of cycles the circuit under test operates after a reset; injecting a fault into the circuit under test; outputting a reset signal to the circuit under test and obtaining a fault output result of the circuit under test after the fault injection; and comparing the fault output result with a reference output result to obtain a fault assessment result.

[0007] A target number of cycles is configured for the circuit under test (DUT), and a fault is injected into the DUT. After fault injection, a reset signal is output to the DUT. Upon receiving the reset signal, the DUT begins processing the injected fault data and obtains the fault output result. By comparing the fault output result with the reference output result, the corresponding fault assessment result of the DUT can be obtained. The reference output result can be obtained by controlling the DUT to pre-calculate the reference signal. Therefore, no additional reference circuit is required, which reduces the structural complexity of the fault injection assessment system and the resources required for assessment.

[0008] Optionally, the reference output result is obtained in the following manner: configuring the target number of cycles for the circuit under test; outputting a reset signal to the circuit under test, and obtaining the result of the circuit under test running the reference signal as the reference output result.

[0009] Optionally, the fault injection assessment method further includes: disconnecting the gated clock of the circuit under test when configuring a target number of cycles for the circuit under test; and restoring the gated clock of the circuit under test after completing the configuration of the target number of cycles.

[0010] Optionally, the fault injection assessment method further includes: if the number of cycles the circuit under test has run after reset reaches the target number of cycles, disconnecting the gated clock of the circuit under test.

[0011] When configuring the target number of cycles for the circuit under test (DUT), disconnect the DUT's gated clock. After configuring the target number of cycles, restore the DUT's gated clock. When the DUT reaches the target number of cycles after resetting, disconnect the DUT's gated clock again. By disconnecting the DUT's gated clock, the operation of the DUT is paused, allowing for precise control over the timing of fault injection and fault assessment results, facilitating online debugging by testers.

[0012] Optionally, injecting a fault into the circuit under test includes: controlling a fault injection module to inject a fault into the circuit under test; the fault includes at least one of the following: single-bit error, multi-bit error.

[0013] Optionally, the fault injection assessment method further includes: obtaining fault assessment results corresponding to different target number of cycles; and determining the final fault assessment result based on the fault assessment results corresponding to different target number of cycles.

[0014] Optionally, determining the final fault assessment result based on the fault assessment results corresponding to different target cycle numbers includes: when the fault assessment result corresponding to the largest target cycle number is the first result, determining the final fault assessment result as the first result; the first result includes any one of the following: the circuit under test is operating normally, or the circuit under test is operating incorrectly.

[0015] Determining the final fault assessment result based on the fault assessment results corresponding to different target cycle numbers can improve the accuracy of the fault assessment results.

[0016] Secondly, the present invention also provides a fault injection assessment system, comprising: a host computer, a fault assessment module, and a circuit under test, wherein: the fault assessment module is adapted to configure a target number of cycles for the circuit under test, the target number of cycles being the number of cycles the circuit under test runs after a reset; inject a fault into the circuit under test; output a reset signal to the circuit under test and obtain a fault output result of the circuit under test after the fault injection; output the fault output result to the host computer; the host computer compares the fault output result with a reference output result to obtain a fault assessment result.

[0017] Thirdly, the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, wherein the computer program is executed by a processor to perform the steps of any of the fault injection assessment methods described above.

[0018] Fourthly, the present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of any of the fault injection assessment methods described above. Attached Figure Description

[0019] Figure 1 is a flowchart of a fault injection evaluation method according to an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a fault injection evaluation device in an embodiment of the present invention. Detailed Implementation

[0021] Existing fault injection assessment systems require the additional setup of a reference circuit identical to the circuit under test. When the circuit under test is large, this leads to a complex structure for the fault injection assessment system and consumes significant resources during the fault injection assessment process.

[0022] In this embodiment of the invention, the fault assessment result corresponding to the circuit under test can be obtained by comparing the fault output result with the reference output result. The reference output result can be obtained by controlling the circuit under test to pre-calculate the reference signal. Therefore, no additional reference circuit is required, thus reducing the structural complexity of the fault injection assessment system and the resources required for assessment.

[0023] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] This invention provides a fault injection assessment method. Referring to Figure 1, the following detailed steps will provide a comprehensive explanation. Referring to Figure 2, a fault injection assessment system according to an embodiment of this invention is shown. The following description is in conjunction with Figures 1 and 2.

[0025] In this embodiment of the invention, the fault injection assessment system may include a host computer 21, an assessment control module 22, and a circuit under test 23. The fault injection assessment system may also include an excitation circuit 24, which can provide an excitation clock for the assessment control module 22.

[0026] In this embodiment of the invention, the fault injection assessment method may include the following steps 101 to 104:

[0027] Step 101: Configure the target number of cycles for the circuit under test.

[0028] Step 102: Inject a fault into the circuit under test.

[0029] Step 103: Output a reset signal to the circuit under test and obtain the fault output result of the circuit under test after the fault is injected.

[0030] Step 104: Based on the comparison between the fault output result and the reference output result, obtain the fault assessment result.

[0031] In specific implementation, the evaluation control module 22 can be a hardware module, including a chip or chip module with data processing capabilities, such as a controller chip. The fault evaluation injection method provided in steps 101 to 104 above runs in the evaluation control module 22.

[0032] Alternatively, in some other embodiments, the evaluation control module 22 may execute steps 101 to 103 above, and the host computer 21 may execute step 104. That is, the evaluation control module 22 obtains the fault output result of the circuit under test 23; the host computer 21 compares the fault output result with the reference output result to obtain the fault evaluation result.

[0033] In specific implementations, the evaluation control module 22 can communicate with the host computer 21 via the Joint Test Action Group (JTAG) interface. Alternatively, the evaluation control module 22 can communicate with the host computer 21 via the Universal Asynchronous Receiver Transmitter (UART) interface. The evaluation control module 22 can also communicate with other control modules via the Advanced eXtensible Interface (AXI) protocol. These other control modules can perform the same or similar functions as the host computer 21.

[0034] In practice, testers can pre-configure the executable file or program corresponding to the aforementioned fault injection assessment method and input it into the host computer 21. The host computer 21 then writes the executable file or program corresponding to the fault injection assessment into the assessment control module 22, thereby enabling the assessment control module 22 to execute the fault injection assessment method. Testers can also trigger the assessment control module 22 to start executing the fault injection assessment method through the host computer 21.

[0035] In this embodiment of the invention, the inputs to the evaluation control module 22 may include the clock sti_clk of the excitation circuit 24 and the clock dut_clk of the circuit under test 23. The outputs of the evaluation control module 22 may include the gated clock gated_dut_clk corresponding to the gated circuit under test 23, the reset signal dut_rst corresponding to the circuit under test 23, and the reset signal sti_rst corresponding to the excitation circuit 24. When the circuit under test 23 receives the reset signal dut_rst, the circuit under test 23 is reset. When the excitation circuit 24 receives the reset signal sti_rst, the reset circuit is reset.

[0036] When the evaluation control module 22 is working, it can use the clock sti_clk of the excitation circuit 24 as the master clock; and perform gating processing on the clock dut_clk of the circuit under test 23 to obtain the gated clock gatedut_clk corresponding to the circuit under test 23.

[0037] In this embodiment of the invention, the evaluation control module 22 can configure the number of cycles the circuit under test 23 operates after a reset, that is, the number of cycles the circuit under test 23 operates after receiving a reset signal (dut_rst). When configuring the number of cycles the circuit under test 23 operates after a reset, the evaluation control module 22 can control the cutting off of the gated clock gatedut_clk corresponding to the circuit under test 23, that is, not outputting the gated clock gatedut_clk to the circuit under test 23. In this scenario, the circuit under test 23 is in a non-operating state.

[0038] In some embodiments, the evaluation control module 22 may include a counter register. The tester can set the value in the counter register through the host computer 21. The value in the counter register is the number of cycles the circuit under test 23 runs after reset. The value N in the counter register can be set according to the specific application scenario.

[0039] In this embodiment of the invention, the tester can send an enable command to the evaluation control module 22 via the host computer 21. The enable command enables the evaluation control module 22, i.e., controls it to start working. When the evaluation control module 22 starts working, it outputs a gated clock `gated_dut_clk` to the circuit under test (DUT) 23. After a first duration, the evaluation control module 22 outputs a reset signal `dut_rst` to the DUT 23. The reset signal `dut_rst` can last for a second duration. Once the evaluation control signal detects that the duration of the output reset signal `dut_rst` has reached the second duration, it can release the reset signal `dut_rst`.

[0040] After the reset signal `dut_rst` is released, the circuit under test (DUT) 23 can perform calculations on preset test data, which is reference data without injected faults. The DUT 23 performs calculations on the test data, with a calculation period of N. During operation, the end indication signal of the evaluation control module 22 is low. The preset test data can be `dut_data` provided by the excitation circuit 24.

[0041] The evaluation control module 22 detects that the circuit under test 23 has run for N cycles after reset, and then stops outputting the gated clock `gated_dut_clk`, thereby controlling the circuit under test 23 to stop working. In other words, the circuit under test 23 runs for N cycles after reset and then stops working. The evaluation control module 22 pulls the end indicator signal (done) from low to high. The host computer 21 can continuously read the end indicator signal. When the end indicator signal is read as high, the host computer 21 can output a end command to the evaluation control module 22.

[0042] The evaluation control module 22 acquires the output result of the circuit under test 23 as a reference output result. In some embodiments, the reference output result may also be referred to as the golden output result. The aforementioned reference output result is obtained by the circuit under test 23 after running the test data for N cycles.

[0043] In some embodiments, after obtaining the reference output result, the evaluation control module 22 can also send the reference output result to the host computer 21. Thus, the host computer 21 can obtain the reference output result.

[0044] In this embodiment of the invention, after obtaining the reference output result, the evaluation control module 22 can reconfigure the target cycle number M for the circuit under test 23. Then, the evaluation control module 22 can inject a fault into the circuit under test 23. The values ​​of M and N can be equal or unequal.

[0045] In practical implementation, the evaluation control module 22 can inject faults into the circuit under test 23 through a fault injection system. Fault types can include single-bit errors, multi-bit errors, etc. Fault injection methods can include fixed-point injection, random injection, and traversal injection. The fault injection system can include an external fault injection system and an internal fault injection system.

[0046] After a certain period of time, the evaluation control module 22 outputs a reset signal dut_rst to the circuit under test 23. Upon receiving the reset signal dut_rst, the circuit under test 23 is reset. After the evaluation control module 22 releases the reset signal, the circuit under test 23 performs calculations on the injected fault data.

[0047] After detecting that the number of cycles the circuit under test (DUT) 23 has run after reset has reached the value M of the counter register, the evaluation control module 22 stops outputting the gated clock `gated_dut_clk` to the DUT 23, thereby controlling the DUT 23 to stop working. The end indicator signal (done) of the evaluation control module 22 goes high. Since the evaluation control module 22 stops outputting the gated clock `gated_dut_clk` to the DUT 23, the DUT 23 is in a paused state. The evaluation control module 22 obtains the output value of the DUT 23 as the fault output result.

[0048] In some embodiments, the evaluation control module 22 can compare the fault output result with the reference output result to determine whether the injected fault affects the function of the circuit under test 23, thereby obtaining the fault evaluation result of the circuit under test 23.

[0049] In this scenario, both the fault output result and the reference output result are input to the evaluation control module 22. The evaluation control module 22 compares the fault output result with the reference output result and outputs the fault evaluation result to the host computer 21.

[0050] In other embodiments, the evaluation control module 22 can output the fault output result to the host computer 21. The host computer 21 can compare the fault output result with the reference output result to determine whether the injected fault affects the function of the circuit under test 23, thereby obtaining the fault evaluation result of the circuit under test 23.

[0051] In this embodiment of the invention, the fault assessment result may include normal operation, operation error, etc. The above-mentioned normal operation means that the injected fault does not cause the operation of the circuit under test 23 to be interrupted; the above-mentioned operation error means that the injected fault causes the operation of the circuit under test 23 to be interrupted.

[0052] In summary, by configuring the number of cycles the circuit under test (DUT) 23 runs after reset, and configuring the reset time of DUT 23, the gate clock of DUT 23 is cut off when configuring the number of cycles after reset; after fault injection is completed, the gate clock of DUT 23 is restored; after DUT 23 runs for N cycles after reset, the gate clock of DUT 23 is cut off again. Therefore, the timing of fault injection into DUT 23 can be precisely controlled.

[0053] In this embodiment of the invention, fault assessment results of the circuit under test 23 can be obtained under different runtime durations. The different runtime durations refer to the number of cycles the circuit under test 23 runs after reset.

[0054] In practice, the fault output results of the circuit under test 23 under different runtimes can be obtained by configuring the value of the counter register multiple times. Furthermore, based on the fault output results under different runtimes, the final fault assessment result is obtained.

[0055] When the circuit under test (DUT) 23 is run under injected fault conditions, it may have a self-correcting function. When the running time is short, the DUT 23 may be affected by the injected fault, leading to a difference between the fault output and the reference output. When the running time is long, the fault output of the DUT 23 may be corrected, making the fault output the same as the reference output. Therefore, by analyzing the fault output under different running times, accurate fault assessment results can be obtained.

[0056] In some embodiments, a first runtime T1, a second runtime T2, and a third runtime T3 can be set. The first runtime T1 is less than the second runtime T2, and the second runtime T2 is less than the third runtime T3.

[0057] If the fault assessment result corresponding to the first running time T1 is "running error", and the fault assessment results corresponding to the second running time T2 and the third running time T3 are both "running normally", then the fault assessment result is determined to be: the circuit under test 23 is running normally.

[0058] If the fault assessment result corresponding to the first running time T1 and the second running time T2 is "running error", and the fault assessment result corresponding to the third running time T3 is "running normally", then the fault assessment result is determined to be: the circuit under test 23 is running normally.

[0059] If the fault assessment results corresponding to the first running time T1, the second running time T2, and the third running time T3 are all "running error", then the fault assessment result is determined to be: the circuit under test 23 is running error.

[0060] Therefore, by updating the fault assessment results based on the fault assessment results corresponding to different runtime durations, the fault assessment results can be obtained more accurately.

[0061] In summary, in this embodiment of the invention, a target number of cycles is configured for the circuit under test (DUT), and a fault is injected into the DUT. After fault injection is completed, a reset signal is output to the DUT. Upon receiving the reset signal, the DUT begins to process the injected fault data and obtains a fault output result. By comparing the fault output result with a reference output result, the corresponding fault assessment result for the DUT can be obtained. The reference output result can be obtained by controlling the DUT to pre-calculate the reference signal. Therefore, no additional reference circuit is required, thus reducing the structural complexity of the fault injection assessment system and reducing the resources consumed during assessment.

[0062] Furthermore, in this embodiment of the invention, the evaluation control module can be implemented in software, which has strong versatility and portability, and can be applied to different models of SRAM-type FPGAs and different fault injection methods.

[0063] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0064] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0065] This invention also provides a computer-readable storage medium, which is a non-volatile or non-transient storage medium, storing a computer program thereon. When the computer program is run by a processor, it executes the steps of the fault injection evaluation method provided in any of the above embodiments.

[0066] This invention also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the fault injection assessment method provided in any of the above embodiments.

[0067] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0068] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A fault injection assessment method, characterized in that, include: Configure a target number of cycles for the circuit under test, wherein the target number of cycles is the number of cycles the circuit under test runs after a reset; Injecting a fault into the circuit under test; A reset signal is output to the circuit under test, and the fault output result of the circuit under test after the fault is injected is obtained; The fault assessment result is obtained by comparing the fault output result with the reference output result.

2. The fault injection assessment method as described in claim 1, characterized in that, The reference output result is obtained in the following way: Configure the target number of cycles for the circuit under test; A reset signal is output to the circuit under test, and the result of the circuit under test operating on the reference signal is obtained as the reference output result.

3. The fault injection assessment method as described in claim 1 or 2, characterized in that, Also includes: When configuring the target number of cycles for the circuit under test, disconnect the gated clock of the circuit under test; And, after configuring the target number of cycles, restore the gated clock of the circuit under test.

4. The fault injection assessment method as described in claim 3, characterized in that, Also includes: If the number of cycles the circuit under test has run after reset is detected to have reached the target number of cycles, the gate clock of the circuit under test is disconnected.

5. The fault injection assessment method as described in claim 1, characterized in that, The injection of faults into the circuit under test includes: The fault injection module injects a fault into the circuit under test; the fault includes at least one of the following: single-bit error, multi-bit error.

6. The fault injection assessment method as described in claim 1, characterized in that, Also includes: Obtain fault assessment results corresponding to different target cycle numbers; Based on the fault assessment results corresponding to different target cycle numbers, the final fault assessment result is determined.

7. The fault injection assessment method as described in claim 6, characterized in that, The determination of the final fault assessment result based on the fault assessment results corresponding to different target cycle numbers includes: When the fault assessment result corresponding to the maximum target number of cycles is the first result, the final fault assessment result is determined to be the first result; the first result includes any one of the following: the circuit under test is operating normally, or the circuit under test is operating incorrectly.

8. A fault injection assessment system, characterized in that, include: The host computer, fault assessment module, and circuit under test include: The fault assessment module is adapted to configure a target number of cycles for the circuit under test, the target number of cycles being the number of cycles the circuit under test will run after a reset; inject a fault into the circuit under test; output a reset signal to the circuit under test and obtain the fault output result of the circuit under test after the fault is injected; and output the fault output result to the host computer. The host computer compares the fault output result with the reference output result to obtain the fault assessment result.

9. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, characterized in that, The computer program is executed by the processor to perform the steps of the fault injection evaluation method according to any one of claims 1 to 7.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the fault injection evaluation method according to any one of claims 1 to 7.

Images