Substrate processing apparatus and substrate processing method

Abstract

To increase the throughput of a substrate processing device.SOLUTION: The substrate processing device includes: a carrier block; a first processing block composed of mutually laminated first lower side processing blocks and first upper side processing blocks; a second processing block composed of mutually laminated second lower side processing blocks and second upper side processing blocks; a relay block having an elevation transfer mechanism; and a bypass transfer mechanism provided in a bypass transfer path formation block, which is one of the upper side processing block and the lower side processing block, for each of the first processing block and the second processing block, to operate to form a forward path or a return path together with a main transfer mechanism of the bypass transfer path formation block, so that the bypass transfer path formation block transfers a substrate toward a downstream side block by one of a main transfer mechanism of the first processing block and a main transfer mechanism of the second processing block.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing apparatus and a substrate processing method. [Background technology]

[0002] In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as wafers) are transported between various processing modules to undergo various processes such as liquid processing and heat treatment. Patent Document 1 describes a coating and developing apparatus including processing blocks S2 and S4, each of which includes a plurality of unit blocks stacked on top of each other, each of which is provided with a plurality of processing modules, and a main arm provided for each unit block to transport wafers between the processing modules. The processing blocks S2 and S4 are sandwiched between a carrier block and an exposure device, and a block S3 is interposed between the processing blocks S2 and S4 to transport wafers up and down. Furthermore, the unit blocks below each processing block S2 and S4 are provided with a plurality of shuttle arms, which serve as a transport mechanism separate from the main arm and transport wafers without passing through the processing modules.

[0003] Wafers transported to block S3 using the shuttle arm of processing block S2 are sorted to the upper unit blocks of processing blocks S2 and S4, then returned to block S3 and transported to the exposure device using the shuttle arm of processing block S4. Thereafter, when processing is to be performed in one of processing blocks S2 and S4, the wafers are transported to the carrier block side using the shuttle arm so as to bypass the processing modules of the block that will not be processed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-258208 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a technique that can increase the throughput in a substrate processing apparatus. [Means for solving the problem]

[0006] The substrate processing apparatus of the present disclosure includes a first block, each block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; each of the plurality of stories and the main transport mechanism, and the first block and Left and right a second block adjacently connected to the first block; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on the opposite side to the first block; a control unit that controls the operation of each of the main transport mechanisms to form an outgoing path that is a path for transporting the substrate across the first block and the second block in a direction toward the fourth block, and a returning path that is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block; a bypass transport mechanism that operates to form the outgoing path or the return path in the bypass transport path forming block, and that allows the substrate to be transported toward a downstream block by one of the main transport mechanism of the first block and the main transport mechanism of the second block in the bypass transport path forming block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, the first bypass transport mechanism and the second bypass transport mechanism each transport the substrate along the left-right direction; The first bypass transport mechanism or the second bypass transport mechanism comprises a moving mechanism provided in the first block or the second block, respectively, a moving body that moves in the left-right direction relative to the moving mechanism, and a support that moves in the left-right direction relative to the moving body and supports the substrate. The substrate processing apparatus of the present disclosure includes a first block, each block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; each of the plurality of stories and the main transport mechanism, and the first block and Left and right a second block adjacently connected to the first block; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on the opposite side to the first block; a control unit that controls the operation of each of the main transport mechanisms to form an outgoing path that is a path for transporting the substrate across the first block and the second block in a direction toward the fourth block, and a returning path that is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block; a bypass transport mechanism that operates to form the outgoing path or the return path in the bypass transport path forming block, and that allows the substrate to be transported toward a downstream block by one of the main transport mechanism of the first block and the main transport mechanism of the second block in the bypass transport path forming block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, the first bypass transport mechanism and the second bypass transport mechanism each transport the substrate along the left-right direction; a transport path for the substrate by the first bypass transport mechanism; No. 1the bypass conveying path projects from the first block to the second block, a transport path for the substrate by the second bypass transport mechanism; No. 2 the bypass conveying path projects from the second block to the first block, the first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, and the second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, have different heights; first bypass substrate placement units provided on the upstream side and downstream side of the first bypass transport path, respectively, for transferring the substrate between the first bypass transport mechanism and the first bypass transport mechanism; second bypass substrate placement parts provided at different heights from the first bypass substrate placement part on the upstream and downstream sides of the second bypass transport path, and between which the substrate is transferred to and from the second bypass transport mechanism; will be established. [Effects of the Invention]

[0007] The present disclosure can increase the throughput in a substrate processing apparatus. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional plan view of a substrate processing apparatus according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a vertical sectional front view of the substrate processing apparatus. [Figure 3] FIG. 2 is a vertical sectional front view of the substrate processing apparatus. [Figure 4] FIG. 2 is a left side view of the substrate processing apparatus. [Figure 5] FIG. 2 is a vertical sectional side view of the substrate processing apparatus. [Figure 6] 5A to 5C are explanatory views showing the operation of a transfer mechanism provided in the substrate processing apparatus. [Figure 7] 5A to 5C are explanatory views showing the operation of a transfer mechanism provided in the substrate processing apparatus. [Figure 8] 5A to 5C are explanatory views showing the operation of a transfer mechanism provided in the substrate processing apparatus. [Figure 9] 2 is a schematic view of a transfer path in the substrate processing apparatus; FIG. [Figure 10] FIG. 10 is a cross-sectional plan view of a coating and developing apparatus according to a second embodiment. [Figure 11] FIG. 2 is a vertical sectional front view of the coating and developing apparatus. [Figure 12] FIG. 10 is a cross-sectional plan view of a coating and developing apparatus according to a third embodiment. [Figure 13] FIG. 2 is a vertical sectional front view of the coating and developing apparatus. [Figure 14] FIG. 2 is a right vertical cross-sectional side view of the coating and developing apparatus. DETAILED DESCRIPTION OF THE INVENTION

[0009] [First embodiment] A substrate processing apparatus 1 according to a first embodiment of the present disclosure will be described with reference to the cross-sectional plan view of FIG. 1 and the longitudinal front views of FIG. 2 and FIG. 3. FIGS. 2 and 3 show cross sections at different positions of the apparatus. The substrate processing apparatus 1 includes a carrier block D1, a first processing block D2, a second processing block D3, and an interface block D4, which are arranged in this order in a horizontal linear fashion, with adjacent blocks connected to each other. These blocks (carrier block, first and second processing blocks, and interface block) D1 to D4 are each provided with a housing and are separated from one another, and a transfer area for substrates, i.e., wafers W, is formed inside each housing.

[0010] In the following description, the arrangement direction of these blocks D1 to D4 is referred to as the left-right direction, with the carrier block D1 side being the left side and the interface block D4 being the right side. Furthermore, in the front-to-rear direction of the apparatus, when looking at the carrier block D1 from the left, the front is referred to as the front and the back is referred to as the rear. The interface block D4, which serves as a relay block, is connected to the exposure machine 20 from the right side. Due to this arrangement, the interface block D4 is adjacent to the second processing block D3 on the opposite side in the left-to-right direction from the side to which the first processing block D2 is adjacent.

[0011] Before describing each of blocks D1 to D4 in detail, we will describe the general configuration of substrate processing apparatus 1. Wafers W are transported to substrate processing apparatus 1 while stored in a carrier C, such as a front-opening unifying pod (FOUP), and a resist film is formed on the surface of the wafer W. Substrate processing apparatus 1 includes processing modules that perform various processes, such as a cleaning process, which is a liquid process, a development process, and a post-exposure bake (PEB) process for wafer W after exposure and before development, and also transfers wafer W to exposure machine 20 to expose the resist film before PEB.

[0012] The first processing block D2 and the second processing block D3 are each partitioned vertically into two. The lower and upper sides of the partitioned first processing block D2 are referred to as the first lower processing block D21 and the first upper processing block D22, respectively. The lower and upper sides of the partitioned second processing block D3 are referred to as the second lower processing block D31 and the second upper processing block D32, respectively. Therefore, the first lower processing block D21 and the first upper processing block D22 are stacked on top of each other, and the second lower processing block D31 and the second upper processing block D32 are stacked on top of each other. The first lower processing block D21 and the first upper processing block D22 are adjacent to each other, and the second lower processing block D31 and the second upper processing block D32 are adjacent to each other.

[0013] Each of these processing blocks (D21, D22, D31, D32) includes the above-mentioned processing modules and a transfer mechanism (main transfer mechanism) capable of transferring wafers to and from the processing modules. Furthermore, the first upper processing block D22 and the second upper processing block D32 are each provided with a transfer mechanism separate from the transfer mechanism for transferring wafers to and from the processing modules. Hereinafter, this separate transfer mechanism will be referred to as a shuttle. This shuttle is a bypass transfer mechanism that transfers wafers W toward downstream blocks without passing through the processing modules, and the first upper processing block D22 and the second upper processing block D32 in which this shuttle is provided are bypass transfer path forming blocks.

[0014] The first lower processing block D21 and the second lower processing block D31 form an outbound route for transporting wafers W from the carrier block D1 to the interface block D4. The first upper processing block D22 and the second upper processing block D32 form a return route for transporting wafers W that have been exposed in the exposure machine 20 from the interface block D4 to the carrier block D1, and the same types of processing modules are provided in both blocks so that the same processing can be performed. On the return route, wafers W are transported to a processing module by a transfer mechanism in one of the first upper processing block D22 and the second upper processing block D32 and processed therein, and then transported by a shuttle in the other block.

[0015] The first lower processing block D21 and second lower processing block D31 forming the outbound path may be collectively referred to as lower processing block G1, and the first upper processing block D22 and second upper processing block D32 forming the return path may be collectively referred to as upper processing block G2. By providing a shuttle as described above, wafers W are transported in upper processing block G2 via one of two transport paths. A module is a location other than the transport mechanism (including the shuttle) where wafers W are placed. A module that processes wafers W is referred to as a processing module as described above, but this processing also includes acquiring images for inspection.

[0016] The carrier block D1 will be described below with reference to the side view of Fig. 4. Carriers C are loaded and unloaded into and from the carrier block D1 by a carrier transport mechanism (external transport mechanism) (not shown) provided in a clean room in which the substrate processing apparatus 1 is installed. The carrier block D1 is a block that loads and unloads wafers W into and from the carriers C.

[0017] The aforementioned housing constituting carrier block D1 is designated 11. Housing 11 is formed in a rectangular shape, and its lower side protrudes to the left to form support base 12. Furthermore, on the left side surface of housing 11 above support base 12, two points spaced apart from each other in the vertical direction protrude to the left to form support bases 13 and 14. The lower support base and the upper support base are designated 13 and 14, respectively.

[0018] Each of the support bases 12 to 14 can accommodate, for example, four carriers C at intervals in the front-to-rear direction, and each of the support bases 12 to 14 has a stage for placing the carriers C thereon, and the stages are arranged, for example, in a 3 x 4 matrix when viewed from the left. The left end of the support base 12 protrudes further left than the support bases 13 and 14, and the stage of the support base 12 is provided on the right side of the support base 12, below the support bases 13 and 14. The interior of the support base 12 is used as an area for storing bottles containing processing liquid for liquid processing in the first processing block D2 and the second processing block D3, as described above.

[0019] Carriers C can be transferred between the stages by a carrier transfer mechanism 21, which will be described later. Regarding these stages, the two front stages of each of the support bases 13 and 14 are configured as movable stages 15 on which carriers C are placed to load and unload wafers W into and from the apparatus. Therefore, the movable stages 15 are arranged in a 2 × 2 matrix when viewed from the left. The movable stages 15 move between a load position on the right side for loading and unloading wafers W and an unload position on the left side for transferring carriers C to and from the carrier transfer mechanism 21. In this example, the movable stage 15 of the support base 12 serves as a stage (loader) on which carriers C are placed to unload unprocessed wafers W into the apparatus, while the movable stage 15 of the support base 13 serves as a stage (unloader) on which carriers C are placed to store processed wafers W in the apparatus. However, one movable stage 15 may serve as both a loader and an unloader.

[0020] Regarding the other stages, the two rear stages of the support bases 13 and 14 and the two stages on the support base 14 are configured as temporary placement stages 16. The other two stages on the support base 14 are configured as a carry-in stage 17 and an unloading stage 18. For example, the stage on the rear end side and the stage on the front end side of the support base 14 are the carry-in stage 17 and the unloading stage 18, respectively. These carry-in stage 17 and unloading stage 18 are stages on which the carrier C is placed when the external transport mechanism described above carries the carrier C into and out of the substrate processing apparatus 1, respectively.

[0021] The carrier C is transferred in the following order: carry-in stage 17 → movable stage 15 of support base 12 → movable stage 15 of support base 13 → carry-out stage 18. When transferring the carrier C between stages in this way, if the destination stage is not available (if it is occupied by another carrier C), the carrier C is placed on the temporary placement stage 16 and waits until the destination stage becomes available.

[0022] A carrier transfer mechanism 21 is provided above the left side of the support base 12. The carrier transfer mechanism 21 includes an articulated arm 22 that can hold a held portion provided on the upper part of the carrier C, and a movement mechanism 23 that can move the articulated arm 22 up and down and back and forth, and can transfer the carrier C between stages as described above.

[0023] Transfer openings 24 for loading and unloading wafers W are formed in the left wall of the housing 11, and are arranged in a 2 x 2 matrix to match the arrangement of the movable stages 15. A door 25 is provided at each transfer opening 24. The door 25 is capable of holding the lid of the carrier C on the movable stage 15 at the load position, and can move while holding the lid to open and close the transfer opening 24.

[0024] The transfer opening 24 faces a transfer area 31 for the wafer W formed within the housing 11, and the transfer area 31 is formed in a linear shape that is long from front to back in a plan view. A transfer mechanism 32 is provided on the front side of the transfer area 31. The transfer mechanism 32 includes a base that is movable back and forth, vertically movable, and rotatable about a vertical axis, and a wafer W holder that can move forward and backward on the base. The transfer mechanism 32 can access the carrier C on the moving stage 15 at the load position described above, and the module stack T1 and pre-processing inspection module 41 described below, to transfer the wafer W.

[0025] A pre-processing inspection module 41 is provided in the carrier block D1, and this pre-processing inspection module 41 images the surface of the wafer W before processing by the substrate processing apparatus 1. Image data obtained by this imaging is sent to the control unit 10, which will be described later, and the presence or absence of an abnormality in the wafer W is determined by the control unit 10 based on the image data. The pre-processing inspection module 41 is configured in the shape of a flat rectangular parallelepiped that is elongated from side to side, with its right side located in the center of the front and rear of the transfer region 31 and its left side penetrating the left wall of the housing 11 and protruding outside the housing 11.

[0026] The pre-processing inspection module 41 includes a stage 42 that is movable left and right within the module, a half mirror 43 provided above the movement path of the stage 42, an illumination unit 44 that irradiates light downward via the half mirror 43, and a camera 45 provided to the left of the half mirror 43 (see FIG. 3). A wafer W is delivered to the stage 42 located on the right side within the module by the transport mechanism 32. As the stage 42 to which the wafer W has been delivered moves leftward and passes below the half mirror 43, light is emitted from the illumination unit 44 and an image of the wafer W reflected on the half mirror 43 is captured by the camera 45, thereby acquiring the image data.

[0027] 1, a transfer mechanism 33 is provided in the transfer region 31 so as to be located behind the pre-processing inspection module 41 in a plan view. The transfer mechanism 33 includes a base that can be raised and lowered and rotated about a vertical axis, and a holder for the wafer W that can move forward and backward on the base, and can deliver the wafer W to and from a shuttle TRS12 of the module stack T1 and the first upper processing block D22, which will be described later.

[0028] Next, the module stack T1 will be described. This module stack T1 is configured by vertically stacking a transfer module TRS on which a wafer W is temporarily placed and a temperature adjustment module SCPL, and is provided in the front-to-rear center of the transfer region 31. Therefore, in a plan view, the module stack T1 is sandwiched in the front-to-rear direction between the transfer mechanisms 32 and 33, and is disposed overlapping on the right side of the pre-processing inspection module 41. Furthermore, with regard to the carrier stages described above, the two vertical rows of stages on the front side, including the moving stage 15, are disposed forward of the module stack T1. With regard to the two vertical rows of stages on the rear side, one row is located to the left of the module stack T1, and the other row is located rearward of the module stack T1.

[0029] The transfer module TRS includes, for example, multiple pins arranged horizontally, and the wafer W is transferred to and from these pins by the lifting and lowering motion of the transfer mechanism. The SCPL is configured, for example, by connecting a refrigerant flow path to a plate on which the wafer W is placed, thereby cooling the placed wafer W. The transfer mechanism lifts and lowers the wafer W to and from the plate. Note that SCPLs are also provided in blocks other than carrier block D1, and the SCPLs in blocks other than D1 have the same configuration as the SCPL in carrier block D1, for example. TRSs are also provided in blocks other than D1. These TRSs have the same configuration as the TRS in carrier block D1, except for the TRS for the shuttle that transfers the wafer W to and from the shuttle, which will be described later. Hereinafter, the SCPLs and TRSs at each location will be identified by numbers suffixed to the SCPLs and TRSs to distinguish them from one another. Furthermore, multiple TRSs and SCPLs at each location may be stacked, for example. In other words, multiple TRSs and SCPLs with the same number are provided, but for convenience of illustration, only one is shown. In this specification, a stack of modules means modules that are stacked in a plan view, and the modules may be separated from each other or may be in contact with each other.

[0030] Some of the modules constituting the module stack T1 are provided below the pre-processing inspection module 41, and some are provided above the pre-processing inspection module 41. For example, the modules are provided in the following order from bottom to top: TRS1, TRS2, SCPL1, TRS3, and SCPL2, with the pre-processing inspection module 41 located between SCPL1 and TRS3 (see FIG. 3). For example, TRS1, TRS2, and SCPL1 are each located at the height of the first lower processing block D21, and TRS3 and SCPL2 are each located at the height of the first upper processing block D22. The transport mechanism 33 can access each of the modules constituting the module stack T1, and the transport mechanism 32 can access TRS1 and TRS2.

[0031] TRS1 and TRS2 are used to transfer wafers W between the transfer mechanisms 32 and 33. SCPL1 is used to transfer wafers W between the first lower processing block D21 and the carrier block D1. Therefore, SCPL1 is also accessible to a transfer mechanism 6A of the first lower processing block D21, which will be described later. TRS3 is used to transfer wafers W between the first upper processing block D22 and the carrier block D1. Therefore, TRS3 is also accessible to a transfer mechanism 6B of the first upper processing block D22, which will be described later. SCPL2 is a module used to adjust the temperature of wafers W before they undergo development processing in the first upper processing block D22, and is accessed by the transfer mechanism 6B.

[0032] Next, the first processing block D2 will be described with reference to the longitudinal side view of Figure 5. The front side of the first processing block D2 is vertically partitioned to form eight levels, which are numbered E1 to E8 from bottom to top. The lower levels E1 to E4 are included in the first lower processing block D21, and the upper levels E5 to E8 are included in the first upper processing block D22. Each level forms an area where a liquid processing module can be installed.

[0033] First, the first upper processing block D22 will be described. Each of the stories E5 to E8 is provided with a developing module 51 as a liquid processing module. The developing module 51 includes two cups 52 arranged side by side and each containing a wafer W, and a nozzle (not shown). The developing module 51 supplies the developing liquid from the bottle to the surface of the wafer W by a pump (not shown), thereby processing the wafer W.

[0034] A transfer region 53 for wafers W is provided behind stories E5 to E8 and extends linearly in a plan view from the left end to the right end of the upper processing block D22. Therefore, the extension direction of the transfer region 53 is perpendicular to the extension direction of the transfer region 31 of the carrier block D1. The transfer region 53 extends from the height of story E5 to the height of story E8. In other words, the transfer region 53 is not divided into stories E5 to E8.

[0035] The processing modules are stacked, for example, in seven stages in the vertical direction behind the transport area 53, with two stacks of processing modules arranged side by side. That is, the stacks of processing modules and the cups 52 are each arranged along the extension direction of the transport area 53.

[0036] The stack of processing modules arranged side by side as described above is referred to as the rear processing unit 50. The processing modules constituting this rear processing unit 50 include a plurality of heating modules 54 and a plurality of post-processing inspection modules 57. The heating module 54 is a module that performs the PEB described above and includes a hot plate 55 on which a wafer W is placed and heated, and a cooling plate 56 that adjusts the temperature of the wafer W. The cooling plate 56 is movable between a front position where the wafer W is transferred by the lifting and lowering operation of the transfer mechanism 6B described below and a rear position where it overlaps with the hot plate 55. The lifting and lowering operation of pins (not shown) provided on the hot plate 55 cooperates with the movement of the cooling plate 56 to transfer the wafer W between the hot plate 55 and the cooling plate 56.

[0037] The post-processing inspection module 57 has the same configuration as the pre-processing inspection module 41, and is arranged so that the movement direction of the wafer W during imaging is the front-to-rear direction. The post-processing inspection module 57 acquires image data of the surface of the wafer W that has been processed by the substrate processing apparatus 1, more specifically, the surface of the wafer W on which a resist pattern has been formed by development, and transmits the image data to the control unit 10.

[0038] The transfer area 53, which is the main transfer path, is provided with the transfer mechanism 6B, which is the main transfer mechanism described above, and the transfer mechanism 6B includes a base 61 that is movable left and right, vertically movable, and rotatable about a vertical axis, and a holder 62 for the wafer W that can move forward and backward on the base 61. Note that each of the transfer mechanisms other than the shuttle in the substrate processing apparatus 1, including this transfer mechanism 6B, is provided with two holders, which can move forward and backward independently of each other on the base.

[0039] A moving mechanism 63 for moving the base 61 of the transfer mechanism 6B left and right is provided below the rear processing unit 50, and a flat space 71A is formed between the moving mechanism 63 and the rear processing unit 50. The space 71A extends from the left end to the right end of the first upper processing block D22. A shuttle and its associated TRS12 and TRS14 are installed in the space 71A, which will be described in detail later. The transfer mechanism 6B can transfer wafers W to and from each processing module in the first upper processing block D22, the TRS3 and SCPL2 of the carrier block D1, and the shuttle TRS14. In other words, the transfer mechanism 6B is shared by each liquid processing module provided on multiple stacked levels.

[0040] Next, the first lower processing block D21 will be described. The first lower processing block D21 has a configuration generally similar to the first upper processing block D22 already described, and the following description will focus on the differences from the first upper processing block D22. No processing modules are provided on story E1, and backside cleaning modules 47 are provided on stories E2 to E4 as liquid processing modules. The backside cleaning module 47 has a configuration similar to that of the developing module 51, except that instead of being provided with a nozzle for supplying a developing solution to the front surface of the wafer W, it is provided with a nozzle for supplying a cleaning solution to the backside of the wafer W.

[0041] The processing modules constituting the rear processing section 50 include an edge exposure module 48 for removing unnecessary resist film from the peripheral edge of the wafer W during development. The main transport mechanism provided in the transfer region 53 is shown as transfer mechanism 6A and has a configuration similar to the above-described transfer mechanism 6B. The transfer mechanism 6A delivers the wafer W to and from each processing module in the first lower processing block D21, the SCPL1 of the module stack T1, and the module stack T2, which will be described later. The first lower processing block D21 does not have a shuttle or a TRS for the shuttle.

[0042] Next, the second processing block D3 will be described. The second processing block D3 has a configuration substantially similar to that of the first processing block D2, and the following description will focus on the differences from the first processing block D2. First, the second upper processing block D32 differs from the first upper processing block D22 in that an SCPL3 forming a module stack T2 is provided at the left end of the transfer region 53 (see FIG. 3). The SCPL3 is a module for adjusting the temperature of wafers W before development processing in the second upper processing block D32.

[0043] The main transport mechanism in the second upper processing block D32 is designated 6D. A space 71B similar to space 71A in the first upper processing block D22 is formed between the rear processing unit 50 and a transfer mechanism 63 that moves the transfer mechanism 6D. Space 71B is located at the same height as space 71A and is connected to the space 71A. A shuttle and shuttle TRS11 and TRS13 are installed in space 71B, which will be described later. The transfer mechanism 6D transfers wafers W to and from each processing module in the upper processing block D22, a module stack T3 in the interface block D4 (described later), and the shuttle TRS11.

[0044] Regarding the layout of the modules in the second upper processing block D32, the rear-side processing section 50 and the cups 52 of the developing modules 51 are positioned to the right of the module stack T2 so that they can be transferred by the transport mechanism 6D. The layout of the liquid processing modules and rear-side processing section 50 is common to the first and second lower processing blocks D21, D31 and the first and second upper processing blocks D22, D32. Therefore, in the first lower processing block D21 and first upper processing block D22 described above, the rear-side processing section 50 and the cups 52 of the liquid processing modules are also located away from the left end of the block.

[0045] Next, regarding the second lower processing block D31, a TRS4 that forms a module stack T2 together with the SCPL2 is provided at the left end of the transfer region 53 (see FIG. 3). No liquid processing modules are provided on levels E1 and E2, and post-exposure cleaning modules 49 that clean the surfaces of wafers W after exposure by the exposure machine 20 are provided on levels E3 and E4. The post-exposure cleaning modules 49 have the same configuration as the developing module 51, except that the processing liquid supplied to the wafers W is a cleaning liquid instead of a developing liquid. Furthermore, no processing other than the cleaning is performed in the second lower processing block D31, and no rear processing unit 50 is provided behind the transfer region 53.

[0046] The main transport mechanism in the second lower processing block D31 is a transport mechanism 6C, which delivers wafers W to and from each processing module in the lower processing block D21 and a module stack T3 in the interface block D4 (described later).

[0047] The following describes interface block D4. Interface block D4 has a module stack T3 in the center between the front and rear. This module stack T3 is composed of stacked modules TRS5 to TRS8 and a temperature adjustment module ICPL. In addition to these, a buffer module for temporarily waiting wafer W may also be provided, but this will not be described here. ICPL is a module to which wafer W is transferred immediately before exposure by exposure machine 20, and like SCPL, it adjusts the temperature of the placed wafer W. TRS5 to TRS7 are provided at the height of lower processing block G1, and TRS8 is provided at the height of upper processing block G2. Transfer mechanisms 36 and 37 are provided in front and behind module stack T3, respectively.

[0048] Transfer mechanism 36 is configured similarly to transfer mechanism 32 in carrier block D1, and transfers wafers W between the exposure device 20, TRS5, and ICPL located near the bottom of module stack T3. Transfer mechanism 37, which is an elevation transfer mechanism, is configured similarly to transfer mechanism 38 in carrier block D1, and transfers wafers W between each module constituting module stack T3 and shuttle TRS13 in second upper processing block D32.

[0049] Next, the shuttles provided in the first upper processing block D22 and the second upper processing block D32 will be described as 7A and 7B, respectively. The shuttle 7A, which is the first bypass transport mechanism, includes a moving mechanism 72A, a moving body 73A, and a support 74A. The moving mechanism 72A is configured as an elongated member extending laterally and is installed to fit within the space 71A of the first upper processing block D22 described above. The moving body 73A is connected to the front side of the moving mechanism 72A and extends laterally. The support 74A is connected to the front side of the moving body 73A and is formed in the shape of a rectangular parallelepiped that is elongated laterally. The wafer W is supported on the support 74A and transported horizontally and linearly in the left-right direction.

[0050] The moving mechanism 72A allows the moving body 73A to move left and right relative to the moving mechanism 72A. The support 74A moves left and right relative to the moving body 73A in response to the movement of the moving body 73A relative to the moving mechanism 72A (see FIGS. 6 to 8). The moving body 73A moves between a right position where its right end is located to the right of the right end of the moving mechanism 72A (toward the interface block D4) and a left position where its left end is located to the left of the left end of the moving mechanism 72A (toward the carrier block D1). When the moving body 73A is located in the right position, the right end of the support 74A is located to the right of the right end of the moving body 73A (the state shown in FIG. 6). The position of the support 74A in this state is referred to as the right transfer position. When the moving body 73A is located in the left position, the left end of the support 74A is located to the left of the left end of the moving body 73A (the state shown in FIG. 8). The position of the support 74A in this state is referred to as the left transfer position.

[0051] The shuttle 7A transports the wafer W from the TRS 11 provided in the second upper processing block D32 to the TRS 12 provided in the first upper processing block D22. The TRS 11 includes a support plate 75 serving as a mounting unit main body formed to form a recess with an open left side in a plan view, three pins 76 protruding upward from the support plate 75, and an elevator mechanism (not shown) for raising and lowering the support plate 75. The elevator mechanism may be an actuator such as a cylinder or a motor, and is connected to the back side (lower side) of each support plate 75 and positioned so as not to interfere with the movement trajectories of the movable body 73A and the support 74A. As the support plate 75 rises and falls, the pins 76 move between an elevated position and a lowered position to support the underside of the wafer W. In plan view, the right end of support 74A at the right transfer position is accommodated in the recess formed by support plate 75, and wafer W can be transferred between support 74A and TRS 11 by raising and lowering pins 76. TRS 11 is provided to the right of module stack T2 so that wafer W can be transferred between support 74A and transfer mechanism 6B as well (see FIG. 1).

[0052] The TRS12 has the same configuration as the TRS11, except that the support plate 75 is formed to form a recess that is open on the right side in a plan view. The left end of the support 74A in the left transfer position is fitted into the recess formed by the support plate 75 in a plan view, allowing the transfer of wafers W between the support 74A and the TRS12. The TRS12 is provided at the left end of the first upper processing block D22 so that the wafers W can be transferred between the support 74A and the transfer mechanism 33 of the carrier block D1. As described above, the transfer of a substrate (wafer W) supported by the support 74 is performed by changing the relative left-right positions of multiple components, such as the movable body 73A and the support 74A, that are provided in the front-rear direction. By transferring the substrate in this manner, the TRS11 and TRS12, which are positioned to the left and right of the support 74A, are less likely to interfere with the movable body 73A, making it possible to arrange the pins 76 in three or more positions that can easily support the substrate.

[0053] Shuttle 7B, which is the second bypass transport mechanism, is located at a different height from shuttle 7A, for example, lower than shuttle 7A. Shuttle 7B is configured similarly to shuttle 7A, and the reference numerals for the components of shuttle 7B, such as the moving mechanism, moving body, and support, are denoted by adding a B instead of an A after the numeral to distinguish them from the components of shuttle 7A. Specifically, for example, the moving mechanism of shuttle 7B is denoted as 72B. This moving mechanism 72B is provided to fit within space 71B of the second upper processing block D32.

[0054] Shuttle 7B transports wafers W from TRS13 in second upper processing block D32 to TRS14 in first upper processing block D22. TRS13 has the same configuration as TRS11 and is located at the right end of second upper processing block D32 so that wafers W can be transferred to and from interface block D4. TRS14 has the same configuration as TRS12 and is located at the right end of first upper processing block D22 so that wafers W can be transferred to and from transfer mechanism 6B.

[0055] As described above, shuttle 7B is provided below shuttle 7A, and therefore the height at which the second bypass substrate mounting portions TRS13 and TRS14 are located is lower than the height at which the first bypass substrate mounting portions TRS11 and TRS12 are located. In other words, as shown in Fig. 2, the set of shuttle 7A, TRS11, and TRS12 and the set of shuttle 7B, TRS13, and TRS14 are provided at positions offset from each other in the longitudinal direction (vertical direction).

[0056] The transfer path (first bypass transfer path) for wafer W by shuttle 7A and the transfer path (second bypass transfer path) for wafer W by shuttle 7B are designated 77A and 77B, respectively. The transfer paths 77A and 77B are located at the same front-to-rear positions. In correspondence with the positions of TRS11 to TRS14, the transfer path 77A projects toward the second upper processing block D32, and the transfer path 77B projects toward the first upper processing block D22. This projection allows the right side of the transfer path 77A and the left side of the transfer path 77B to overlap in a plan view. The transfer paths 77A and 77B may be located, for example, away from the heating plate 55 of the heating module 54 and overlap the standby position of the cooling plate 56 in a plan view. By positioning the transfer paths relatively far from the heating plate 55, the effects of heat on the transferred wafer W can be more reliably reduced.

[0057] The transfer of the wafer W by the shuttle 7A will be described in sequence with reference to FIGS. 6 to 8. The transfer mechanism 6D in the second upper processing block D32 transfers the wafer W, which has been processed in each processing module in the second upper processing block D32, onto the pins 76 in the raised position of the TRS 11. The pins 76 move to their lowered positions, and the wafer W is transferred to the support 74A in the right transfer position described above (FIG. 6). While the movable body 73A and the support 74A each move to the left, the pins 76 of the TRS 11 return to their raised positions (FIG. 7).

[0058] When support 74A moves to the left transfer position described above, pins 76 of TRS12, which were in the lowered position, move to the raised position to support wafer W (FIG. 8). When support 74A moves toward the right transfer position, pins 76 return to the lowered position. Subsequently, transfer mechanism 33 of carrier block D1 receives wafer W. In this manner, shuttle 7A transfers wafer W toward carrier block D1, which is a downstream block. Shuttles 7B, TRS13, and TRS14 operate in the same manner as shuttles 7A, TRS11, and TRS12, respectively, and wafer W is transferred from TRS13 to TRS14. In other words, shuttle 7B transfers wafer W toward first upper processing block D22, which is a downstream block.

[0059] The substrate processing apparatus 1 also includes a control unit 10 (see FIG. 1). The control unit 10 is configured by a computer and includes a program, a memory, and a CPU. The program incorporates a group of steps that enable a series of operations in the substrate processing apparatus 1 to be performed. The program causes the control unit 10 to output control signals to each part of the substrate processing apparatus 1, thereby controlling the operation of each part. Specifically, the control unit 10 controls the operations of the transfer mechanisms 6A-6D, shuttles 7A and 7B, and each processing module. This allows the transfer of wafers W, the processing of wafers W, and the determination of abnormalities in wafers W, as described below. The above program is stored on a storage medium such as a compact disc, hard disk, or DVD, and is installed in the control unit 10.

[0060] Next, the processing and transportation of wafers W in the substrate processing apparatus 1 will be described with reference to Fig. 9, which shows an outline of the transport path. In Fig. 9, the transport mechanisms used for the transport of wafers W between modules are shown on or near some of the arrows indicating the transport of the wafers W. First, the wafer W is transported by the transport mechanism 32 from the carrier C placed on the moving stage 15 of the support base 12. Then, the wafer W is transported by the transport mechanism 32 to the pre-processing inspection module 41, where image data is acquired and the presence or absence of an abnormality is determined.

[0061] Thereafter, the wafer W is transferred to TRS1 by transfer mechanism 32, and then transferred to SCPL1 by transfer mechanism 33. The wafer W is then taken into the first lower processing block D21 by transfer mechanism 6A, and is transferred to the back surface cleaning module 47 and the edge exposure module 48 in that order for processing, and then transferred to TRS4 in the second lower processing block D31.

[0062] Next, the wafer W is transferred by the transfer mechanism 6C to the TRS5 in the interface block D4, and then transferred by the transfer mechanism 37 to the ICPL, and then transferred by the transfer mechanism 36 to the exposure machine 20, where the resist film on the surface of the wafer W is exposed according to a predetermined pattern. After exposure, the wafer W is transferred by the transfer mechanism 36 to the TRS6, and then transferred by the transfer mechanism 37 to the TRS7, and then taken into the lower processing block D31 again by the transfer mechanism 6C, and transferred to the post-exposure cleaning module 49, and then transferred to the TRS7 in the interface block D4, where the transfer mechanism 37 receives the wafer W.

[0063] The subsequent transfer path of the wafer W is divided into a path (referred to as the first path) in which the wafer W is processed in the first upper processing block D22, and a path (referred to as the second path) in which the wafer W is processed in the second upper processing block D32, as described above. Regarding the second path, the transfer mechanism 38 transfers the wafer W to the TRS8 of the module stack T3, and the transfer mechanism 6D takes the wafer W into the second upper processing block D32. The wafer W is then transferred in the order of the heating module 54, SCPL3, developing module 51, and post-processing inspection module 57. After a resist pattern is formed, image data is acquired and the presence or absence of anomalies is determined.

[0064] 6 to 8, the wafer W is then transferred in the order of transfer mechanism 6D → TRS11 → shuttle 7A → TRS12, and then transfer mechanism 33 of carrier block D1 receives the wafer W and transfers it to TRS2. In this manner, the wafer W is transferred toward the downstream block by transfer mechanism 6D, one of transfer mechanisms 6B and 6D that are the main transfer mechanisms of first upper processing block D22 and second upper processing block D22, which are bypass transfer path forming blocks, and shuttle 7A. The wafer W is then stored in carrier C on moving stage 15 of support table 13 by transfer mechanism 32.

[0065] Next, regarding the first path, the wafer W is transferred in the order of transfer mechanism 38 → TRS13 → shuttle 7B → TRS14 → transfer mechanism 6B, and the wafer W is taken into the first upper processing block D22. The wafer W is then transferred by transfer mechanism 6B in the order of heating module 54 → SCPL5 → developing module 51 → post-processing inspection module 57, and after undergoing processing similar to that of the wafer W on the second path, is transferred to TRS3 in carrier block D1. In this manner, the wafer W is transferred toward downstream blocks by transfer mechanisms 6B and 6D, which are the main transfer mechanisms of the first upper processing block D22 and the second upper processing block D22, which are bypass transfer path forming blocks, and shuttle 7B. The wafer W is then transferred to TRS2 by transfer mechanism 33, and thereafter, similar to the wafer W on the second path, by transfer mechanism 32 to carrier C on moving stage 15 of support table 13.

[0066] As described above, the substrate processing apparatus 1 is configured and transported. Therefore, the transfer mechanism 6B of the first upper processing block D22 and the transfer mechanism 6D of the second upper processing block D32 do not need to transport wafers W that are not processed in the blocks where the transfer mechanisms 6B and 6D are installed toward the carrier block D1. This reduces the load on each of the transfer mechanisms 6B and 6D, specifically the number of transfer processes required within the block. As described above, the first upper processing block D22 and the second upper processing block D32 each include multiple modules. This reduced load allows the transfer mechanisms 6B and 6D to quickly access each module, receive wafers W, and transport the wafers W to downstream modules. This means that the substrate processing apparatus 1 can process wafers W in multiple processing modules and quickly transport wafers W between modules. Therefore, the substrate processing apparatus 1 can achieve high throughput.

[0067] To avoid the need for the transport mechanisms 6B and 6D to move across the left and right blocks, the transport path 77A for the shuttle 7A extends to the second upper processing block D32, and the transport path 77B for the shuttle 7B extends to the first upper processing block D22. The transport paths 77A and 77B, which are provided across the left and right blocks, are offset in height and do not intersect with each other, allowing the shuttles 7A and 7B to transport independently. More specifically, during transport by one of the shuttles 7A and 7B, there is no need to stop the other shuttle to avoid interference with the other shuttle. This more reliably increases the throughput of the substrate processing apparatus 1. Furthermore, because the transport paths 77A and 77B, which are offset in height, overlap in plan view, the substrate processing apparatus 1 does not need to be extended in width from front to back, thereby reducing its footprint.

[0068] The height of the substrate processing apparatus 1 must be set so as not to interfere with the ceiling of the clean room. Meanwhile, liquid processing modules such as the developing module 51 are relatively tall because they include cups 52 for storing wafers W. However, in the substrate processing apparatus 1, shuttles 7A and 7B are provided above the rear processing section 50, which performs a type of processing different from the liquid processing described above. Therefore, within the limited height of the apparatus, the number of levels on which liquid processing modules are provided can be increased, and the height of the transfer area 53 can be sufficiently secured so that wafers W can be transferred between each level. Therefore, the substrate processing apparatus 1 can more reliably increase the throughput of wafers W.

[0069] Furthermore, shuttles 7A and 7B are located below rear-side processing unit 50 in upper processing block G2, i.e., at the height of lower processing block G1. In other words, shuttles 7A and 7B are located on the block G1 side of the upper processing block G2 and the lower processing block G1, which is connected from below to bypass transfer path forming block G2, relative to the stack of processing modules constituting rear-side processing unit 50. Suppose shuttles 7A and 7B are located at a relatively high position in upper processing block G2, and shuttle TRS11-TRS14 are also located at a relatively high position. In this case, transfer mechanisms 33 and 38, which deliver wafers W to TRS12 and TRS13, respectively, may need to be moved to positions above the positions of the modules constituting module stacks T1 and T3. In other words, locating shuttles 7A and 7B at the height of lower processing block G1 relative to rear-side processing unit 50 as described above reduces the amount of lift required by transfer mechanisms 33 and 38. Therefore, the arrangement of the shuttles 7A and 7B contributes to more reliably increasing the throughput.

[0070] 8, when the support 74A of the shuttle 7A is positioned at the left transfer position for transferring the wafer W, the support 74A is not positioned upstream of the pins 76 of the TRS 12 in the transfer path 77A in a plan view. By configuring the TRS 12 and the support 74A to achieve this layout, the support 74A can move toward the TRS 11 without interfering with the pins 76 of the TRS 12 while the wafer W remains supported by the pins 76 of the TRS 12, and receive the subsequent wafer W. The shuttles 7B and TRS 14 also have the same configuration as the shuttles 7A and TRS 12, respectively. Therefore, the support 74A of the shuttle 7B can move toward the TRS 13 without interfering with the pins 76 of the TRS 14 while the wafer W remains supported by the pins 76 of the TRS 14. Therefore, the shuttles 7A and 7B can continuously and quickly transfer wafers W, thereby more reliably increasing throughput.

[0071] The supports 74A and 74B of the shuttles 7A and 7B are not limited to the above-described configuration. For example, the supports 74A and 74B may be formed as relatively large disks, and a slit formed from the right end to the left and a slit formed from the left end to the right may be provided on the disk to avoid interference with the pins 76 of the TRS on the upstream side and the TRS on the downstream side of the transport path.

[0072] Furthermore, the shuttle 7A has a movable body 73A and a support 74A that slide laterally relative to the moving mechanism 72A. This configuration allows these components to be accommodated in the first processing block D2. Therefore, after the first processing block D2 is assembled in the equipment manufacturing factory, the width of the first processing block D2 can be reduced when transported to the clean room where the equipment will be installed. This simplifies the labor and equipment required for transportation. Because the shuttle 7B has the same configuration as the shuttle 7A, the labor and equipment required for transportation of the second processing block D3 can be simplified, similar to the first processing block D2. Furthermore, transporting the shuttles 7A and 7B accommodated in the first processing block D2 and the second processing block D3, respectively, contributes to quickly assembling the equipment and making it operational at the destination.

[0073] In the substrate processing apparatus 1 of the first embodiment, the liquid processing modules in the first lower processing block D21 and the second lower processing block D31 are not limited to those that perform cleaning, and may be liquid processing modules that perform processing before cleaning, for example. Below, a coating and developing apparatus that is a modification of the substrate processing apparatus 1 that is equipped with such a liquid processing module other than a cleaning module will be specifically described.

[0074] In this coating and developing apparatus, an anti-reflective coating forming module 81 is provided as a liquid processing module in the first lower processing block D21, and a resist film forming module 82 is provided as a liquid processing module in the second lower processing block D31. The anti-reflective coating forming module 81 and the resist film forming module 82 have the same configuration as the developing module 51, except that the processing liquids supplied to the wafer W are a coating liquid and a resist liquid for forming an anti-reflective coating, respectively. Note that the wafer W is transported to the coating and developing apparatus without the anti-reflective coating and the resist film formed thereon.

[0075] In this coating and developing apparatus, the rear processing section 50 of the first lower processing block D21 and the second lower processing block D31 includes heating modules 54. These heating modules 54 are used to remove solvent remaining in the formed film. In the coating and developing apparatus and the module stacks T1 to T3 in each apparatus described below, TRSs and SCPLs are arranged at appropriate heights and in appropriate numbers so that wafers W can be transported appropriately between the blocks.

[0076] In this coating and developing apparatus, the wafer W is transported in the following order: SCPL in the module stack T1 → anti-reflection coating forming module 81 → heating module 54 in the first lower processing block D21. Furthermore, the wafer W is transported in the following order: SCPL in the module stack T2 → resist film forming module 82 → heating module 54 in the second lower processing block D31 → module stack T3 in the interface block D4 → exposure machine 20. The exposed wafer W is transported along the same route as in the substrate processing apparatus 1. The back surface cleaning module 47 and post-exposure cleaning module 49 may be provided in the interface block D4, for example, and transported by the transport mechanism 38, or processing by these modules may be omitted.

[0077] Second Embodiment A coating and developing apparatus 8, which is a substrate processing apparatus according to a second embodiment, will be described with reference to the plan view of FIG. 10 and the front view of FIG. 11, focusing on differences from the coating and developing apparatus, which is a modification of the substrate processing apparatus 1 described above. The coating and developing apparatus 8 includes a third processing block D5 adjacent to the second processing block D3 and the interface block D4, located between these blocks. The third processing block D5 is configured substantially similarly to the second processing block D3 and is divided into a third lower processing block D51 and a third upper processing block D52. Therefore, in this coating and developing apparatus 8, the lower processing block G1 is composed of D21, D31, and D51, and the upper processing block G2 is composed of D22, D32, and D52. The third processing block D5 also includes a module stack T4, which is configured by stacking SCPLs and TRSs, similar to the module stack T2.

[0078] Regarding the third lower processing block D51, a protective film forming module 83 is provided as a liquid processing module on stories E2 to E4, and is configured similarly to the resist film forming module 82 except that it supplies a chemical solution for forming the protective film. Modules that make up the rear processing section 50 include a heating module 54 for removing solvent from the protective film and an edge exposure module 48. The main transport mechanism of the third lower processing block D51 is defined as a transport mechanism 6E.

[0079] Regarding the third upper processing block D52, back surface cleaning modules 47 are provided on stories E6 and E7, and a post-exposure cleaning module 49 is provided on story E8, but there is no rear processing section 50. Instead of being provided in the second upper processing block D32, the TRS 13 is provided behind the transport region 53 of the third upper processing block D52. The main transport mechanism of the third upper processing block D52 is designated as transport mechanism 6F.

[0080] In the carrier block D1 of the coating and developing apparatus 8, a hydrophobic treatment module 84 is provided behind the transfer mechanism 33, which supplies a processing gas to the wafer W to perform a hydrophobic treatment. As described above, the wafer W, whose image has been acquired in the pre-processing inspection module 41, is transferred by the transfer mechanism 32 to a TRS provided in the module stack T1 separately from the TRS1 to TRS3 described above, and is then transferred in the order of the transfer mechanism 33 → hydrophobic treatment module 84 → transfer mechanism 33 → SCPL1, and is taken into the first lower processing block D21.

[0081] As in the apparatus of the modified example of the first embodiment, the wafer W, which has been processed in the first lower processing block D21 and the second lower processing block D31 and on which an anti-reflection coating and a resist coating have been formed, is transferred to the module stack T4. The transfer mechanism 6E in the third lower processing block D51 transfers the wafer W to the protective film forming module 83, the heating module 54, and the edge exposure module 48, in that order, and then to the module stack T3. The wafer W is then transferred between the TRSs of the module stack T3, and then loaded into the third upper processing block D52 by the transfer mechanism 6F, and transferred to the back surface cleaning module 47. The wafer W then passes through the module stack T3 and the exposure machine 20, and is loaded again into the third upper processing block D52, and transferred to the post-exposure cleaning module 49.

[0082] The subsequent path splits into a first path for processing in the first upper processing block D22 and a second path for processing in the second upper processing block D32, similar to the substrate processing apparatus 1. That is, along the first path, the wafer W is transferred by the transfer mechanism 6F to the shuttle TRS 13 and then transferred to the first upper processing block D22, or along the second path, the wafer W is transferred via the module stack T4 to the second upper processing block D32. Thus, the configuration of the apparatus is not limited to two processing blocks connected laterally. The position of the shuttle TRS may be set appropriately depending on the configuration of the processing block.

[0083] Third Embodiment A coating and developing apparatus 9 according to the third embodiment will be described with reference to the plan view of FIG. 12, the longitudinal front view of FIG. 13, and the longitudinal side view of FIG. 14, focusing on differences from the coating and developing apparatus according to the modified first embodiment. In the coating and developing apparatus 9, no anti-reflective coating is formed, and resist film forming modules 82 are provided on stories E1 to E4 of the first lower processing block D21 and the second lower processing block D31. Therefore, the first lower processing block D21 and the second lower processing block D31 perform similar processing on wafers W. The first lower processing block D21 and the second lower processing block D31 are provided with shuttles 7C and 7D, respectively.

[0084] Unlike shuttles 7A and 7B, shuttles 7C and 7D transport wafers W from carrier block D1 to interface block D4. Specifically, shuttle 7C is used to transport wafers W to the second lower processing block D31 for processing without using transfer mechanism 6A, and shuttle 7D is used to transport wafers W processed in the first lower processing block D21 to interface block D4 without using transfer mechanism 6C. Like shuttles 7A and 7B, shuttles 7C and 7D are composed of a moving mechanism 72, a moving body 73, and a support 74, and the reference numerals for these components are denoted by the same alphabetic character as the shuttle, followed by a numeral. Therefore, for example, the reference numeral for the support of shuttle 7C is 74C.

[0085] Spaces 85A and 85B corresponding to the previously described spaces 71A and 71B are formed above rear processing section 50 in first lower processing block D21 and second lower processing block D31, respectively. Shuttle 7C is provided in space 85A, and shuttle 7D is provided in space 85B. TRSs for shuttle 7C are designated TRS15 and TRS16, and TRSs for shuttle 7D are designated TRS17 and TRS18. TRS15 and TRS17 are TRSs provided upstream of the shuttle transport path and have the same configuration as TRS12. TRS16 and TRS18 are TRSs provided downstream of the shuttle transport path and have the same configuration as TRS11.

[0086] Regarding the TRS15 and TRS16 for shuttle 7C, TRS15 is provided at the left end of the first lower processing block D21, and TRS16 is provided at a position to the left of the module stack T2 in the second lower processing block D31. Regarding the TRS17 and TRS18 for shuttle 7D, they are provided at the right end of the first lower processing block D21 and the right end of the second lower processing block D31, respectively. Like shuttles 7A and 7B, shuttles 7C and 7D are also provided at different heights; for example, shuttle 7C is located higher than shuttle 7D. Therefore, TRS15 and TRS16 are also located higher than TRS17 and TRS18.

[0087] In the interface block D4 of the coating and developing apparatus 9, a transport mechanism 38 having a similar configuration to the transport mechanism 38 is provided on the right side of the module stack T2, and a buffer module 86 is provided behind the transport mechanism 38 so as to be accessible by the transport mechanisms 37 and 38. In front of the transport mechanism 38, an edge exposure module 48 is provided so as to be accessible by the transport mechanism 38, and transport is possible in the order of edge exposure module 48 → buffer module 86 → ICPL → exposure machine 20 via the module stack T3.

[0088] As described in the second embodiment, a wafer W processed in the hydrophobization module 84 and transferred to SCPL1 of the module stack T1 is loaded into the first lower processing block D21 by the transfer mechanism 6A or transferred to the shuttle TRS15 by the transfer mechanism 33. The wafer W transferred to TRS15 is transferred in the order of shuttle 7C → TRS16 → transfer mechanism 6C, processed in the second lower processing block D31, and then transferred to the module stack T3, i.e., interface block D4. Meanwhile, a wafer W loaded into the first lower processing block D21 and processed therein is transferred in the order of TRS17 → shuttle 7D → TRS18, and then transferred by the transfer mechanism 37 to the interface block D4 for exposure. After exposure, the wafer W is transferred back to the carrier block D1 via the first and second paths using the shuttles 7A and 7B, respectively, as in the substrate processing apparatus 1.

[0089] In this way, the coating and developing apparatus 9 is provided with shuttles 7C and 7D for transporting wafers from the carrier block D1 to the interface block D4, and shuttles 7A and 7B for transporting wafers from the interface block D4 to the carrier block D1. This allows for higher throughput. The shuttles 7A and 7B reduce the load on the transport mechanisms 6A and 6B, respectively, resulting in higher throughput. Furthermore, the shuttles 7C and 7D are provided on the upper processing block G2 side relative to the rear processing unit 50. Therefore, similar to the arrangement of the shuttles 7A and 7B described above, the amount of lift of the transport mechanism 33 in the carrier block D1 and the transport mechanism 37 in the interface block can be reduced, thereby improving throughput.

[0090] In addition, the coating / developing apparatus 9 may be provided with only shuttles 7C and 7D, without shuttles 7A and 7B, i.e., transport between blocks D22 and D23 constituting the upper processing block G2 may be performed only by transport mechanisms 6B and 6D. In other words, the substrate processing apparatus may be configured with only one of a shuttle for the outbound route from the carrier block D1 side to the interface block D4 side, and a shuttle for the return route from the interface block D4 side to the carrier block D1 side. Also, instead of using the upper processing block G2 as the outbound route and the lower processing block G1 as the return route, the upper processing block G2 may be used as the return route and the lower processing block G1 as the outbound route.

[0091] Although a TRS is used to transfer wafers W between the shuttle and the transfer mechanisms 6A-6D, which are the main transfer mechanisms of the processing blocks, wafers W may also be transferred between the shuttle and the transfer mechanisms 6A-6D. However, as described above, the use of a TRS is preferable because the movement of the shuttle is restricted until the wafer W is received from the shuttle. Also, while the liquid processing modules are located in the front and the processing modules constituting the rear processing unit 50 are located in the rear, this layout may be reversed. For example, in the substrate processing apparatus 1, the TRS 12 for shuttle 7A may be located in carrier block D1, and the TRS 13 for shuttle 7B may be located in interface block D4. The transfer mechanisms 33 and 37 may be appropriately movable to accommodate the placement of the TRS for the shuttles. In other words, the TRS for the shuttles need not necessarily be located in the processing blocks.

[0092] The liquid processing performed by the apparatus is not limited to the above examples, and may include forming an insulating film by applying a chemical solution, applying an adhesive to bond wafers W to each other, etc. The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above embodiments may be omitted, substituted, modified, and combined in various ways without departing from the scope and spirit of the appended claims. [Explanation of symbols]

[0093] C Carrier D1 Carrier Block D2 First processing block D21 First lower processing block D22 First upper processing block D3 Second processing block D31 Second lower processing block D32 Second upper processing block D4 Interface Block E1~E8 layer W wafer 37 Transport mechanism 6A, 6B, 6C, 6D Conveyor mechanism 7A, 7B Shuttle

Claims

1. a first block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; second blocks each including the plurality of stories and the main transport mechanism, the second blocks being adjacent to and connected to the first block in the left-right direction; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on the opposite side to the first block; a control unit that controls the operation of each of the main transport mechanisms to form an outgoing path that is a path for transporting the substrate across the first block and the second block in a direction toward the fourth block, and a returning path that is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block; a bypass transport mechanism that operates to form the outgoing path or the return path in the bypass transport path forming block, and that allows the substrate to be transported toward a downstream block by one of the main transport mechanism of the first block and the main transport mechanism of the second block in the bypass transport path forming block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, the first bypass transport mechanism and the second bypass transport mechanism each transport the substrate along the left-right direction; The substrate processing apparatus includes a moving mechanism provided in the first block or the second block, a moving body that moves in the left-right direction relative to the moving mechanism, and a support body that moves in the left-right direction relative to the moving body and supports the substrate.

2. a first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, protrudes from the first block to the second block; 2. The substrate processing apparatus according to claim 1, wherein a second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, projects from the second block to the first block.

3. 3. The substrate processing apparatus according to claim 2, wherein the heights of the first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, and the height of the second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, are different from each other.

4. 4. The substrate processing apparatus according to claim 3, wherein the first bypass transport path and the second bypass transport path overlap each other in plan view.

5. a first bypass substrate placement unit provided on each of the upstream and downstream sides of the first bypass transport path, the first bypass substrate placement unit being configured to transfer the substrate between the first bypass transport mechanism and the first bypass transport mechanism; second bypass substrate placement parts provided at different heights from the first bypass substrate placement part on the upstream and downstream sides of the second bypass transport path, and between which the substrate is transferred to and from the second bypass transport mechanism; 5. The substrate processing apparatus according to claim 3, further comprising:

6. 6. The substrate processing apparatus according to claim 5, wherein the first bypass substrate mounting portion and the second bypass substrate mounting portion comprise a mounting portion main body that moves up and down, and a support portion that protrudes upward from the mounting portion main body and supports the underside of the substrate.

7. one of the first and second bypass transport mechanisms, a bypass transport path of the one of the first and second bypass transport paths of the bypass transport mechanism, and a bypass substrate platform onto which the substrate is transferred to the one of the first and second bypass platform, 7. The substrate processing apparatus according to claim 6, wherein when a support provided in the bypass transport mechanism for supporting the substrate is positioned at a position where the bypass transport mechanism transfers the substrate to the bypass substrate mounting section downstream of the bypass transport path, the support is not positioned upstream of the bypass transport path relative to the support section in a plan view.

8. the movable body moves relative to the moving mechanism between a position where it protrudes leftward from a left end of the moving mechanism and a position where it protrudes rightward from a right end of the moving mechanism; 8. The substrate processing apparatus according to claim 1, wherein the support moves between a position where it protrudes leftward from a left end of the movable body and a position where it protrudes rightward from a right end of the movable body.

9. a first block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; second blocks each including the plurality of stories and the main transport mechanism, the second blocks being adjacent to and connected to the first block in the left-right direction; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on the opposite side to the first block; a control unit that controls the operation of each of the main transport mechanisms to form an outgoing path that is a path for transporting the substrate across the first block and the second block in a direction toward the fourth block, and a returning path that is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block; a bypass transport mechanism that operates to form the outgoing path or the return path in the bypass transport path forming block, and that allows the substrate to be transported toward a downstream block by one of the main transport mechanism of the first block and the main transport mechanism of the second block in the bypass transport path forming block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, the first bypass transport mechanism and the second bypass transport mechanism each transport the substrate along the left-right direction; a first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, protrudes from the first block to the second block; a second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, protrudes from the second block to the first block; the first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, and the second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, have different heights; a first bypass substrate placement unit provided on each of the upstream and downstream sides of the first bypass transport path, the first bypass substrate placement unit being configured to transfer the substrate between the first bypass transport mechanism and the first bypass transport mechanism; second bypass substrate placement parts provided at different heights from the first bypass substrate placement part on the upstream and downstream sides of the second bypass transport path, and between which the substrate is transferred to and from the second bypass transport mechanism; The substrate processing apparatus is provided with:

10. 10. The substrate processing apparatus according to claim 9, wherein the first bypass transport mechanism or the second bypass transport mechanism comprises a moving mechanism provided in the first block or the second block, respectively; a moving body that moves in the left-right direction relative to the moving mechanism; and a support body that moves in the left-right direction relative to the moving body and supports the substrate.

11. a first block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; second blocks each including the plurality of stories and the main transport mechanism, the second blocks being adjacent to and connected to the first block in the left-right direction; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on an opposite side to the first block, transporting the substrate by each of the main transport mechanisms across the first block and the second block to form an outgoing path which is a path for transporting the substrate in a direction toward the fourth block, and a returning path which is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block, and a bypass transport mechanism provided in the bypass transport path forming block transports the substrate so as to form the outgoing path or the returning path; For the bypass transport path forming block, a step of transporting the substrate toward a downstream block by the bypass transport mechanism and one of the main transport mechanism of the first block and the main transport mechanism of the second block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, transporting the substrate along the left-right direction by the first bypass transport mechanism and the second bypass transport mechanism, a moving body that moves in the left-right direction relative to the moving mechanism; and a support body that moves in the left-right direction relative to the moving body and supports the substrate.

12. a first block including a plurality of stacked stories each including a processing module for processing substrates, and a main transport mechanism shared by the stories for transporting the substrates; second blocks each including the plurality of stories and the main transport mechanism, the second blocks being adjacent to and connected to the first block in the left-right direction; a third block connected to the first block on the opposite side to the second block; a fourth block connected to the second block on an opposite side to the first block, transporting the substrate by each of the main transport mechanisms across the first block and the second block to form an outgoing path which is a path for transporting the substrate in a direction toward the fourth block, and a returning path which is a path for transporting the substrate in a direction toward the third block at a position different above and below the outgoing path; a bypass transport path forming block is provided for each of the first block and the second block, and a bypass transport mechanism provided in the bypass transport path forming block transports the substrate so as to form the outgoing path or the returning path; For the bypass transport path forming block, a step of transporting the substrate toward a downstream block by the bypass transport mechanism and one of the main transport mechanism of the first block and the main transport mechanism of the second block; Equipped with If the bypass transport mechanisms in the first block and the second block are referred to as a first bypass transport mechanism and a second bypass transport mechanism, respectively, transporting the substrate along the left-right direction by the first bypass transport mechanism and the second bypass transport mechanism, a first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, protrudes from the first block to the second block; a second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, protrudes from the second block to the first block; the first bypass transport path, which is a transport path for the substrate by the first bypass transport mechanism, and the second bypass transport path, which is a transport path for the substrate by the second bypass transport mechanism, have different heights; a step of transferring the substrate between first bypass substrate placement units provided on the upstream side and downstream side of the first bypass transport path and the first bypass transport mechanism; a step of transferring the substrate between second bypass substrate placement parts provided at a height different from that of the first bypass substrate placement part on the upstream side and downstream side of the second bypass transport path and the second bypass transport mechanism; A substrate processing method comprising:

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