Method of manufacturing a shadow mask for stencil lithography

Abstract

The disclosure relates to a method of manufacturing a shadow mask (1) for stencil lithography The method comprises providing (S0) a blank multi-layer stack (1000); creating (S1) a first recess (22) that protrudes in a first direction (Z-) through a first thin-film layer (110) and into at least part of a support layer (120); depositing (S2) a metal layer (140) on a second thin-film layer (130) and depositing a resist layer (150) on the metal layer (140); creating (S3) a second recess (24a) that protrudes through the resist layer (150) in a second direction (Z+) opposite to the first direction (Z-); extending (S4) the second recess (24a) to an extended second recess (24b) that protrudes further through the metal layer (140) and through the second thin-film layer (130) in the second direction (Z+); creating (S5) a pattern of apertures (26) through the second- film layer (130).

Description

[0001] Method of manufacturing a shadow mask for stencil lithography

[0002] Field of the invention

[0003] The invention relates to a method of manufacturing a shadow mask for stencil lithography, in particular for resist-free fabrication of Josephson junctions.

[0004] Background art

[0005] A Josephson junction refers to two superconductors that are in close proximity to each other and that are separated by a thin barrier that joints the two superconductors to form the junction. Josephson junctions exhibit intriguing electrical phenomena known as Josephson effects and are a useful component in superconducting electronics. A Josephson junction can, for example, be used as a building block for defining a standard for the unit volt, for highly- sensitive magnetometers known as superconducting quantum interference devices, SQUIDS, and for realizing superconducting qubits in quantum computing, such as the transmon qubit.

[0006] However, fabricating a Josephson junction with control over the junction’s dimensions still poses a challenge. For instance, in the context of realizing superconducting qubits, the quality of the Josephson junction can affect qubit decoherence times and noise. The quality of the Josephson junction can in turn be negatively affected by contamination of surfaces occurring during fabrication.

[0007] For fabricating a desired Josephson junction feature, stencil lithography can be used to deposit materials in a certain target pattern on a substrate, the target pattern relating to the desired Josephson junction feature. For example, for creating a target pattern of Aluminium for a superconducting element / feature on a Silicon, Si, substrate, one may align a shadow mask with the substrate and create a flow of Aluminium atoms passing through the shadow mask for depositing and creating the Aluminium superconducting element / feature on the substrate. A final target pattern may be created by one or more such depositing steps. The quality of the target pattern on the substrate depends on the quality of patterns of the shadow mask.

[0008] So, there is an interest in improving manufacturing of shadow masks for fabrication of Josephson junctions.

[0009] Summary of the invention

[0010] A task set forth by the inventors is to improve manufacturing of shadow masks for fabrication of Josephson junction. The inventors solved the task by providing a method of manufacturing shadow masks for Josephson junction fabrication according to the appended independent claim. The method enables efficient manufacturing of shadow masks for improved fabrication of Josephson junctions. Advantageous aspects are provided by the appended dependent claims.

[0011] Further advantages are discussed further below in the detailed description.

[0012] Embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. However, the embodiments of the present disclosure are not limited to the specific embodiments and should be construed as including all modifications, changes, equivalent devices and methods, and / or alternative embodiments of the present disclosure.

[0013] The terms “have,” “may have,” “include,” and “may include” as used herein indicate the presence of corresponding features (for example, elements such as numerical values, functions, operations, or parts), and do not preclude the presence of additional features.

[0014] The terms “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” as used herein include all possible combinations of items enumerated with them. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” means (1) including at least one A, (2) including at least one B, or (3) including both at least one A and at least one B.

[0015] The terms such as “first” and “second” as used herein may modify various elements regardless of an order and / or importance of the corresponding elements, and do not limit the corresponding elements. These terms may be used for the purpose of distinguishing one element from another element. For example, a first element may be referred to as a second element without departing from the scope the present invention, and similarly, a second element may be referred to as a first element.

[0016] It will be understood that, when an element (for example, a first element) is “(operatively or communicatively) coupled with / to” or “connected to” another element (for example, a second element), the element may be directly coupled with / to another element, and there may be an intervening element (for example, a third element) between the element and another element. To the contrary, it will be understood that, when an element (for example, a first element) is “directly coupled with / to” or “directly connected to” another element (for example, a second element), there is no intervening element (for example, a third element) between the element and another element.

[0017] The expression “configured to (or set to)” as used herein may be used interchangeably with “suitable for” “having the capacity to” “designed to” “adapted to” “made to,” or “capable of’ according to a context. The term “configured to (set to)” does not necessarily mean “specifically designed to” in a hardware level. Instead, the expression “apparatus configured to...” may mean that the apparatus is “capable of...” along with other devices or parts in a certain context.

[0018] The terms used in describing the various embodiments of the present disclosure are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. All of the terms used herein including technical or scientific terms have the same meanings as those generally understood by an ordinary skilled person in the related art unless they are defined otherwise. The terms defined in a generally used dictionary should be interpreted as having the same or similar meanings as the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings unless they are clearly defined herein. According to circumstances, even the terms defined in this disclosure should not be interpreted as excluding the embodiments of the present disclosure.

[0019] The person skilled in the art will understand that the features described above and / or below may be combined in any way deemed useful. The drawings of the present disclosure show examples / embodiments of the invention, which will be described in detail hereinafter. It is to be understood that one or more of elements / components shown and / or described in one or more of these examples / embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples / embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another.

[0020] Brief description of the drawings

[0021] The present invention is discussed in more detail below, with reference to the attached drawings, in which:

[0022] Fig- 1 illustrates fabricating a Josephson junction feature by a shadow mask.

[0023] Fig- 2 shows a method of manufacturing a shadow mask according to the present invention.

[0024] Fig- 3 shows a preferred manner of creating a first recess.

[0025] Fig. 4 shows a preferred manner of creating a pattern of apertures. Detailed description

[0026] Stencil lithography is used to deposit materials in a certain target pattern on a substrate. To that end, a shadow mask for stencil lithography can be manufactured as outlined for example in Chapter 5 of the Ph.D. thesis of Michael a Eichinger, [Eichinger], The target pattern can relate to a desired feature that one wishes to create on the substrate such as a Josephson junction feature.

[0027] A stencil used in stencil lithography is a hard mask / shadow mask made of inorganic materials. The quality of the target pattern on the substrate depends on the quality of patterns created in the shadow mask. For example, for creating a target pattern of Aluminium for a superconducting element / feature on a Silicon, Si, substrate, one may align the shadow mask with the substrate and create a flow of Aluminium atoms for depositing and creating the Aluminium superconducting element / feature on the substrate. The target pattern may be created by one or more such depositing steps.

[0028] Fig- 1 illustrates a stencil / shadow mask (1) that may be used to deposit and create a Josephson junction feature on a substrate via a pattern of apertures (26) of the stencil. As illustrated, the creating of the Josephson junction feature may involve one or more deposition steps, for example one or more deposition steps of the superconducting material Al.

[0029] When manufacturing the shadow mask, an initial membrane is typically provided in the form of a blank multi-layer stack (1000) as shown in Fig. 2, top left part relating to step SO. Fig- 2 shows a cross-section side-view. The multi-layer stack (1000) has a support layer (120) that is surrounded by thin-film layers (110, 130). For manufacturing a shadow mask, a task is to create a pattern of apertures (26) through which a flux of atoms can be sent for depositing and creating target features on a substrate. The thin-film layers are typically based on a semiconductor material.

[0030] One of the two thin-film layers (e.g., 110) relates to an outer layer that, after manufacturing, is configured to receive a flux of atoms when using the shadow mask in stencil lithography. Such thin-film layer may also be referred to as a window layer. In other words, when using the shadow mask, a flux of atoms such as Aluminium atoms is targeted at the window layer which receives the flux of atoms and guides the flux of atoms towards the other thin-film layer. The other thin-film layer (e.g. 130) relates to the other outer layer opposite to the window layer and is, after manufacturing, configured to comprise a pattern of apertures (26) protruding therethrough. The other thin-film layer may also be referred to as a feature-pattern layer as it exhibits the pattern of apertures (26) by which a target pattern on a substrate can be created via stencil lithography. For example, when placing the shadow mask (1) on a desired position for creating a target pattern such as a Josephson junction feature on a substrate, the flux of atoms created by an e-beam evaporator is received through the window layer and can pass through the pattern of apertures (26) of the feature-pattern layer, so that the target pattern is created on the substrate.

[0031] A goal of the present invention is to manufacture a shadow mask (1) with a pattern of apertures (26) for stencil lithography with high precision while maintaining a high quality of the shadow mask (1).

[0032] To that end, a method of manufacturing a shadow mask (1) for stencil lithography is provided. The method comprises: providing (SO) a blank multi-layer stack (1000) comprising a first thin-film layer (110), a support layer (120) of monocrystalline Silicon, Si, and a second thin-film layer (130), the support layer (120) being surrounded by the first and second thin-film layers (110, 130); creating (SI) a first recess (22) that protrudes in a first direction (Z.) through the first thin-film layer (110) and into at least part of the support layer (120); depositing (S2) a metal layer (140) on the second thin-film layer (130) and depositing a resist layer (150) on the metal layer (140); creating (S3), by photolithography and subsequent development, a second recess (24a) that protrudes through the resist layer (150) in a second direction (Z+) opposite to the first direction (Z.), the second recess (24a) being opposite to the first recess (22); extending (S4), by reactive ion etching, the second recess (24a) to an extended second recess (24b) that protrudes further through the metal layer (140) and through the second thin- film layer (130) in the second direction (Z+); creating (S5) a pattern of apertures (26) through the second-film layer (130), by removing (S5-1) the resist layer (150) and the metal layer (140) and subsequently extending (S5-3) the first recess (22) further in the first direction (Z.) until the first recess (22) meets the extended second recess (24b) so as to together form the pattern of apertures (26).

[0033] The inclusion of the metal layer (140) overcomes a cracking problem that occurs when directly depositing the resist layer (150), as this resist layer (150) can exhibit cracks after the development process. Such cracks are however detrimental to the quality of the final shadow mask by obtaining a lower resolution of created patterns. The metal layer (140) acts as an adhesion layer for the resist layer (150) and moreover acts as a discharging layer. By including the metal layer (140), the number of cracks can be reduced. The providing (SO) of the blank multi-layer stack (1000) may involve creating membranes from an initial silicon wafer serving as basis for the support layer (120). The thin- film layers (110, 130) may be deposited on both sides of the silicon wafer. The thin-film layers are preferably deposited using a low-pressure chemical vapour deposition (LPCVD) process.

[0034] The first recess (22) may be understood as an opening through which aluminium can pass through the shadow mask (1). The first recess (22) may also be called a window which is created on a window side of the shadow mask (1). The window is suitable for receiving a flux of atoms for depositing and creating a target feature on a substrate when using the shadow mask.

[0035] Preferred steps Sl-1, Sl-2, S 1-3, Sl-4, S 1-5 are illustrated in Fig. 3.

[0036] Preferably, the creating of the first recess (22) is combined with creating (Sl-2, SI -3, Sl-5) markers (21, 23) that are suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (1) for stencil lithography.

[0037] Preferably, the creating (SI) of the first recess (22) comprises etching (Sl-5) by Potassium Hydroxide, KOH, through the Si of the support layer (120).

[0038] Preferably, the creating (SI) of the first recess (22) comprises spinning (Sl-1) a polymethylmethacrylate, PMMA, layer (109) on the first thin-film layer (110) and using the KOH to etch through the Si of the support layer (120).

[0039] The PMMA is an electron beam resist that can thus be initially spun on the window side of the blank multi-layer stack (1000).

[0040] In general, an Electron Beam Pattern Generator (EBPG) can be used to expose resist to write desired patterns on a resist.

[0041] The markers (21, 23) can thus be created by exposing a part of the resist to an electron beam from the EBPG, developing the exposed part of the resist by using a developer solution and etching through the developed resist. After the remaining resist is stripped, KOH can be used to etch the silicon symmetrically and in the first direction, i.e. in a direction vertically down (Z.) as also illustrated in Figs. 2-3. The KOH etch of silicon through the marker areas can be stopped mid-way before the etching reaches second thin-film layer (130). Thereby, the marker areas for the markers (21, 23) can be fully etched while the first recess (22) protrudes only through a part of the support layer (120).

[0042] Preferably, the monocrystalline Si of the support layer (120) is a <100> Si. Thereby, when etching with for example KOH, a truncated-cone shape can be obtained as the etching is then inherently symmetric, as also illustrated in Figs. 2-4. The wafer can be cleaned, for example with an MF -21 A developer, to remove any residues that were formed due precipitation after etching with KOH.

[0043] Preferably, the metal of the metal layer (140) is Chromium, Cr.

[0044] Chromium can act as an adhesion promoter and can effectively reduce a number of cracks. However, the inventors also found out that Cr can be more difficult to get fully etched and can lead to non-optimal patterns of apertures, so that for example Josephson junction features can not be fully etched at parts where Cr is still present.

[0045] More preferably, the metal of the metal layer (140) is Niobium Titanium Nitride, NbTiN. As compared to Cr, using NbTiN has the additional advantage that the etching does not leave any residues behind. Moreover, NbTiN can be dry etched for example by fluorine radicals, which ensures etching below developed resist with efficient removal of residues.

[0046] Preferably, the resist is Polymethylmethacrylate, PMMA, or a Chemical Semi Amplified Resist, CSAR, preferably the CSAR.

[0047] In particular, the combination of NbTiN and CSAR is preferred. For example, a same etching recipe can be used for both NbTiN and CSAR. Moreover, the inventors have found that NbTiN has a particularly good compatibility as an adhesion and discharging layer for CSAR to support etching for longer time scales.

[0048] In an alternative embodiment, the metal layer 140 is based on one selected from Niobium, Gold, Titanium and TitaniumNitride.

[0049] As the Chemical Semi Amplified Resist, CSAR, various resists are known, for example, the resist CSAR62 as manufactured by AllResist GmbH could be chosen.

[0050] Preferably, the thin-film layers are based on Silicon Nitride, SisN4, or Silicon Carbide, SiC.

[0051] Preferably, the reactive ion etching is based on Trifluorom ethane, CHF3.

[0052] Preferably, the method comprises creating markers (21, 23), the markers being suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (1) for stencil lithography.

[0053] The second recess (24a) is opposite to the first recess (22) so that in the final step (S5) of the manufacturing, the patterns of apertures (26) is obtained. Preferably, the creating (S3) of the second recess (24a) by photolithography comprises using an electron beam to write, on the resist layer (150), a pattern for the second recess (24a) and using the pattern as mask for developing the second recess (24a) by a developer solution.

[0054] Preferably, the extending (S4) of the second recess (24a) by reactive ion etching comprises using one or more reactive ion etchers, RIEs, to etch away material from the metal layer (140) and the second thin-film layer (130) based on using the second recess (24a) as mask to obtain the extended second recess (24b).

[0055] Preferably, the metal layer (140) is based on Chromium, Cr, or Niobium Titanium Nitride, NbTiN.

[0056] Preferably, the first and second thin-film layers (110, 130) are based on Silicon Nitride, SisN4, or Silicon Carbide, SiC.

[0057] Preferably, the reactive ion etching is based on a Trifluoromethane, CHF3, plasma.

[0058] In an example, the RIE etch rate may be between 100 and 120 nm / min.

[0059] Preferably, the resist is Polymethylmethacrylate, PMMA, or a Chemical Semi Amplified Resist, CSAR.

[0060] For example, the gases SFe and CHF3 can be used to etch Sis The gas SFe etches SisN4 isotropically while the gas CHF3 etches SisN4 anisotropically. When the second thin-film layer (130) is based on SisN4, then preferably the gas CHF3 is used for etching.

[0061] Various developer solutions can be used depending on the resist. For example, exposed CSAR can be developed by rinsing in pentyl acetate (PA) followed by isopropanol (IP A) and deionized water (DI). As another example, exposed PMMA can be developed using various developers such as MIBK1PA 1 :3, IPA:H2O 3: 1, IPA: H2O 7:3 and IP A: H2O 10: 1. Furthermore, the temperature during the development process may be controlled to affect contrast and width of the developed resist. For example, for PMMA, preferably relatively-cold IPA: H2O 3:1 is used to attain vertical walls. Sonication may be performed for effective development of small features.

[0062] Preferably, the metal layer (140) has a thickness in between lOnm and 700nm, more preferably in between 50nm and 500nm, yet more preferably in between 50nm and 400nm, even more preferably in between 50nm and 200nm, yet even more preferably in between 50nm and 150nm, most preferably in between 80nm and 120nm.

[0063] Preferably, the resist layer (150) has a thickness in between 500nm and 1.5pm, more preferably in between 500nm and 1.2pm, yet more preferably in between 550nm and 800nm, most preferably in between 550nm and 600nm. A resist-layer thickness of above 600nm may also result in formation of cracks in the resist layer (150), which can be healed and are preferably healed by performing a post-development bake before the etching process.

[0064] Preferably, the creating (S5) of the pattern of apertures (26) further comprises: spinning (S5-2) a spin-protective layer (160) on the second thin-film layer (130) before the extending (S5-3) of the first recess (22), and removing (S5-4) the spin-protective layer (160) after the extending (S5-3) of the first recess (22).

[0065] The spin-protective layer (160) can stop a RIE, used during the extending (S5-3) of the first recess (22), from entering through the second thin-film layer (130). For example, when KOH is used and the thin-film layers are based on SislS , then Si could be etched which can lead to creation of suspended SislS and unwanted corners in the SislS layer that can cause high stress and undesired cracks. By inclusion of the spin-protective layer (160), such disadvantages can be reduced. Preferably, the spin-protective layer (160) is PMMA.

[0066] Preferably, the first and second thin-film layers (110, 130) are based on Silicon Nitride, SisN4, the metal of the metal layer (140) is based on Niobium Titanium Nitride, NbTiN, and the resist layer (150) is based on a Chemical Semi Amplified Resist, CSAR.

[0067] Preferably, the extending (S4) of the second recess (24a) by reactive ion etching is based on a Trifluoromethane, CHF3, plasma.

[0068] Preferably, the pattern of apertures (26) relates to a Josephson junction feature.

[0069] Preferably, the thin-film layers (110, 130) of the blank multi-layer stack (1000) have a thickness in between 200nm and 600nm and the support layer (120) of the blank multi-layer stack (1000) has a thickness in between 200pm and 400pm.

[0070] More preferably, the thin-film layers (110, 130) of the blank multi-layer stack (1000) have a thickness in between 300nm and 500nm and the support layer (120) of the blank multilayer stack (1000) has a thickness in between 220pm and 300pm.

[0071] In an example, the thin-film layers (110, 130) had a thickness of 480nm and the support layer (120) a thickness of 260pm.

[0072] Preferably, a width of the apertures (26) in a direction perpendicular to the first and second directions (Z+, Z.) is in between 50nm and 300nm.

[0073] The following list of references is referred to in the present document and is incorporated herein by way of reference. List of references

[0074] [Eichinger] Michaela Eichinger. Novel Methods and Materials for Superconducting Qubits and Circuits. Ph.D. Thesis, The Faculty of Science, Niels Bohr Institute, The University of Copenhagen. April 2023.

Claims

What is claimed is:

1. Method of manufacturing a shadow mask (1) for stencil lithography, the method comprising in a sequence: providing (SO) a blank multi-layer stack (1000) comprising a first thin-film layer (110), a support layer (120) of monocrystalline Silicon, Si, and a second thin-film layer (130), the support layer (120) being surrounded by the first and second thin-film layers (110, 130); creating (SI) a first recess (22) that protrudes in a first direction (Z.) through the first thin-film layer (110) and into at least part of the support layer (120); depositing (S2) a metal layer (140) on the second thin-film layer (130) and depositing a resist layer (150) on the metal layer (140); creating (S3), by photolithography and subsequent development, a second recess (24a) that protrudes through the resist layer (150) in a second direction (Z+) opposite to the first direction (Z.), the second recess (24a) being opposite to the first recess (22); extending (S4), by reactive ion etching, the second recess (24a) to an extended second recess (24b) that protrudes further through the metal layer (140) and through the second thin- film layer (130) in the second direction (Z+); creating (S5) a pattern of apertures (26) through the second-film layer (130), by removing (S5- 1) the resist layer (150) and the metal layer (140) and subsequently extending (S5-3) the first recess (22) further in the first direction (Z.) until the first recess (22) meets the extended second recess (24b) to form the pattern of apertures (26), wherein the metal layer (140) is based on Chromium, Cr, or Niobium Titanium Nitride, NbTiN, wherein the first and second thin-film layers (110, 130) are based on Silicon Nitride, SisN^ and the resist layer (150) is based on a Chemical Semi Amplified Resist, CSAR.

2. The method according to claim 1, wherein the creating (S3) of the second recess (24a) by photolithography comprises using an electron beam to write, on the resist layer (150), a pattern for the second recess (24a) and using the pattern as mask for developing the second recess (24a) by a developer solution.

3. The method according to any one of the preceding claims, wherein the extending (S4) of the second recess (24a) by reactive ion etching comprises using one or more reactive ion etchers, RIEs, to etch away material from the metal layer (140) and the second thin-film layer (130) based on using the second recess (24a) as mask to obtain the extended second recess (24b).

4. The method according to any one of the preceding claims, wherein the metal layer (140) is alternatively based on Niobium or Gold or Titanium or TitaniumNitride5. The method according to any one of the preceding claims, wherein the first and second thin- film layers (110, 130) are based on Silicon Carbide, SiC.

6. The method according to any one of the preceding claims, wherein the reactive ion etching is based on a Trifluoromethane, CHF3, plasma.

7. The method according to any one of the preceding claims, wherein the providing of the membrane (10) comprises creating (Sl-2, Sl-3, S 1-5) markers (21, 23) on the membrane (10), the markers (21, 23) being suitable for aligning the shadow mask (1) on a substrate when using the shadow mask (10) for stencil lithography.

8. The method according to any one of the preceding claims, wherein the creating (SI) of the first recess (22) comprises etching (SI -5) by Potassium Hydroxide, KOH, through the Si of the support layer (120).

9. The method according to the preceding claim, wherein the creating (SI) of the first recess (22) comprises spinning (S 1 - 1 ) a polymethylmethacrylate, PMMA, layer (109) on the first thin- film layer (110) and using the KOH to etch through the Si of the support layer (120).

10. The method according to any one of the preceding claims, wherein the creating (S5) of the pattern of apertures (26) further comprises: spinning (S5-2) a spin-protective layer (160) on the second thin-film layer (130) before the extending (S5-3) of the first recess (22), and removing (S5-4) the spin-protective layer (160) after the extending (S5-3) of the first recess (22).

11. The method according to the preceding claim, wherein the extending (S4) of the second recess (24a) by reactive ion etching is based on a Trifluoromethane, CHF3, plasma.

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