Clock output phase alignment control circuit

Abstract

To solve a problem in which it is difficult to select whether two clock outputs from a redundant clock transmission panel are to be in the same phase or in opposite phases.SOLUTION: Each of two clock transmission panels of a clock output phasing control circuit is composed of two clock transmission panels forming a redundant configuration of 0 system and 1 system includes a startup time adjustment unit that makes a difference in a startup time of the two clock transmission panels, a frequency division unit that generates both a positive phase output and a negative phase output of the clock divided by 2, and a selector that selects either the positive phase output or the negative phase output. The clock output phasing control circuit further includes a supervisory control circuit that controls the selector.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a clock transmission circuit of a clock transmission device, and more particularly to a clock output phase alignment control circuit configured to include two clock transmission panels forming a redundant configuration of 0 system and 1 system. [Background technology]

[0002] Patent Document 1 discloses a clock transmission circuit including two clock transmission panels that form a redundant configuration of 0 system and 1 system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2017-126821 Summary of the Invention [Problem to be solved by the invention]

[0004] In devices that transmit clocks (such as network devices), the clock frequency inside the device may differ from the clock frequency transmitted from the device. This is to speed up the detection of clock anomalies within the device and the speed at which redundant systems are switched over within the device. For example, the device's internal clock is handled as a 10 MHz clock, and the final stage within the clock transmission panel divides it by 2 to output a 5 MHz clock. In this case, the 5 MHz clock frequency output from the device becomes the input standard for the clock transmission device connected downstream of that clock transmission device.

[0005] When each of the redundantly configured clock transmitting panels divides the internal clock by 2 and outputs it as described above, the division timing is determined by the initial startup timing of each clock transmitting panel, so it was not possible to know whether the two clock outputs from the redundantly configured clock transmitting panels would be in phase or out of phase.

[0006] An object of the present invention is to provide a clock output phase alignment control circuit that can control whether two clock outputs from a redundantly configured clock transmission panel are output in the same phase or in opposite phases. [Means for solving the problem]

[0007] A clock output phase alignment control circuit according to one aspect of the present invention includes: A clock output phase alignment control circuit including two clock transmission panels forming a redundant configuration of a 0 system and a 1 system, Each of the two clock transmission panels comprises: a start-up time adjustment unit that sets a difference between the start-up times of the two clock transmission panels; a frequency divider unit that generates both a positive phase output and a negative phase output of the clock that has been divided by 2; a selector for selecting either the positive phase output or the negative phase output, and further comprising a monitoring control circuit that controls the selector. It is structured as follows. Further, a control method by a clock output phase alignment control circuit according to another aspect of the present invention comprises: A control method using a clock output phase alignment control circuit including two clock transmission panels that form a redundant configuration of 0 system and 1 system, Differentiating the start times of the two clock transmission panels; generating both positive and negative phase outputs of the divided-by-two clock; selecting one of the positive phase output and the negative phase output; The device is configured to include: Furthermore, a program according to another aspect of the present invention includes: The computer of the clock output phase alignment control circuit is composed of two clock transmission panels that form a redundant configuration of 0 system and 1 system. Differentiating the start times of the two clock transmission panels; generating both positive and negative phase outputs of the divided-by-two clock; selecting one of the positive phase output and the negative phase output; is configured to execute [Effects of the Invention]

[0008] By having the above-described configuration, the present invention can control whether the two clock outputs of a redundantly configured clock transmission panel are output in phase or out of phase. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing an example of a panel configuration of a clock transmission circuit according to a first embodiment of the present invention. [Figure 2] FIG. 10 is a diagram illustrating an example of an output clock (0 system) and an output clock (1 system). [Figure 3] 4 is a flowchart showing an example of the operation of the first exemplary embodiment of the present invention. [Figure 4] FIG. 10 is a diagram showing an example of a panel configuration of a clock transmission circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

[0011] Fig. 1 is a diagram showing an example of a panel configuration of a clock transmission circuit according to a first embodiment of the present invention. As shown in Fig. 1, the panel configuration of the clock transmission circuit of a clock transmission device, in particular the clock handled inside the device, which is individually divided by two in a clock transmission panel having a redundant configuration at the final stage of the device and then output, is composed of a clock receiving panel (system 0) 103, a clock receiving panel (system 1) 104, a clock switching panel (system 0) 105, a clock switching panel (system 1) 106, a clock transmitting panel (system 0) 107, and a clock transmitting panel (system 1) 108.

[0012] The clock receiving panel (0 system) 103 is composed of a bipolar-unipolar conversion unit 201, an abnormality monitoring unit 202, and a branching unit 203, which receive as input the clock A01 output from the oscillator (0 system) 101. The clock receiving panel (1 system) 104 is composed of a bipolar-unipolar conversion unit 301, an abnormality monitoring unit 302, and a branching unit 303, which receive as input the clock B01 output from the oscillator (1 system) 102. The clock switching panel (0 system) 105 is composed of a selector 204, an abnormality monitoring unit 205, and a branching unit 206, which receive as input the clock A02 and clock B02 output from the clock receiving panel (0 system) 103 and the clock receiving panel (1 system) 104. The clock switching panel (1 system) 106 is composed of a selector 304, an abnormality monitoring unit 305, and a branching unit 306, which inputs clocks A03 and B03 output from the clock receiving panel (0 system) 103 and the clock receiving panel (1 system) 104.

[0013] The clock transmission panel (0 system) 107 is composed of a selector 207 that receives clocks A04 and B04 as inputs, an abnormality monitoring unit 208, a frequency dividing unit 209, a selector 210, a unipolar-to-bipolar conversion unit 211, an operation status unit 212, a startup time adjusting unit 213, and a monitoring and control circuit (0 system) 400. The monitoring and control circuit (0 system) 400 is composed of a control unit 401, abnormality monitoring units 402 and 403, and a phase comparison unit 404. The clock transmission panel (1 system) 108 is composed of a selector 307 that receives clocks A05 and B05 as inputs, an abnormality monitoring unit 308, a frequency dividing unit 309, a selector 310, a unipolar-to-bipolar conversion unit 311, an operation status unit 312, a startup time adjusting unit 313, and a monitoring and control circuit (1 system) 500. The monitoring control circuit (system 1) 500 comprises a control unit 501, abnormality monitoring units 502 and 503, and a phase comparison unit 504.

[0014] The clock output phase alignment control circuit in this embodiment is composed of startup time adjustment units 213, 313 that differentiate the startup times of the clock transmitting panel (system 0) 107 and the clock transmitting panel (system 1) 108, frequency division units 209, 309 that generate both positive-phase and negative-phase outputs of a clock that has been divided by 2 within each panel, selectors 210, 310 that select the positive-phase clock and the negative-phase clock, and monitoring control circuits 400, 500 that control the selectors. The monitoring control circuits 400, 500 are composed of a phase comparison unit 404, 504 that compares the phases of the clocks A09, B09 after the selector of the clock transmitting panel (0 system) 107 and the clock transmitting panel (1 system), an abnormality monitoring unit 402, 502 that monitors abnormalities in the clock A09 after the selector of the clock transmitting panel (0 system), an abnormality monitoring unit 403, 503 that monitors abnormalities in the clock B09 after the selector of the clock transmitting panel (1 system), and a control unit 401, 501 that controls whether the output clocks A06, B06 from the clock transmitting panels 107, 108 are in phase or out of phase.

[0015] The control unit 401 receives as inputs the monitoring result signals A07, B07 from the abnormality monitoring units 208, 308, phase selection setting information from a phase selection setting switch that sets whether the output clocks A06, B06 are in phase or out of phase, an operation status unit 212 that manages the operation status of the clock transmission panel (0 system) 107, the monitoring result signals from the abnormality monitoring units 402, 403, the comparison result signal from the phase comparison unit 404, and a monitoring control result signal B10 from the control unit 501, and outputs a control signal A08 to the selector 210 and a monitoring control result signal A10 to the control unit 501. The control unit 501 receives as inputs the monitoring result signals A07, B07 from the abnormality monitoring units 208, 308, phase selection setting information from a phase selection setting switch that sets whether the output clocks A06, B06 are in phase or out of phase, an operation status unit 312 that manages the operation status of the clock transmitting panel (system 1) 108, the monitoring result signals from the abnormality monitoring units 502, 503, a comparison result signal from a phase comparison unit 504, and a monitoring control result signal A10 from the control unit 401, and outputs a control signal B08 to the selector 310 and a monitoring control result signal B10 to the control unit 401. Note that the phase selection may be set by a method other than setting by a switch set on the panel, for example, setting by a nonvolatile memory.

[0016] Next, the operation of this embodiment will be described.

[0017] As shown in Figure 2, whether the output clocks of system 0 and system 1 are output in phase or out of phase is determined by the initial activation timing of the clock transmitting panel (system 0) 107 and the clock transmitting panel (system 1) 108. Figure 2 (1) shows an example in which the clock output (system 0) A09 output from the clock transmitting panel (system 0) 107 and the clock output (system 1) B09 output from the clock transmitting panel (system 1) 108 are in phase. On the other hand, Figure 2 (2) shows an example in which the clock output (system 0) A09 and the clock output (system 1) B09 are out of phase.

[0018] A flowchart showing an example of the operation of this embodiment is shown in Fig. 3. As shown in Figs. 1 and 3, this embodiment performs the following operations.

[0019] After the device / panel is started (S101), the start-up time adjustment units 213 and 313 first complete the start-up of the 0-system and 1-system panels with a time difference (S102). The start-up time adjustment units 213 and 313 do not require a different type of panel for the 0-system and 1-system panels. They obtain slot ID information for each slot of the 0-system and 1-system clock transmission panels from the backboard (not shown) of the unit on which the panel is mounted, and can set a difference in start-up time based on that information, thereby reliably determining the active panel at initial start-up. The start-up time adjustment units 213 and 313 can prevent chattering when determining the active system, making it possible to reliably determine the non-active panel that will be switched in this embodiment. At this point, the selectors 210 and 310 for the 0-system and 1-system, respectively, are initially set to the positive phase side selection state for both systems (S103). Note that the positive phase side clocks selected by the selectors 210 and 310 may be in phase or out of phase with each other.

[0020] Next, the monitoring control circuits 400, 500 for both systems 0 and 1 check the implementation status of both systems 0 and 1 (S104), and then check the abnormality monitoring units 208, 308 inside the panel to check that there are no abnormalities in the pre-divided clocks of both systems 0 and 1 (S105).Furthermore, the abnormality monitoring units 402, 502 inside the monitoring control circuits check that there are no abnormalities in the post-divided clocks of both systems 0 and 1 (S106).Then, the monitoring control results of the monitoring control circuits 400, 500 for systems 0 and 1 are communicated between the control unit 401 for system 0 and the control unit 501 for system 1 (A10, B10) to determine whether there is a discrepancy in the monitoring control results (S107).If there is a discrepancy, no control is performed on the selectors 210, 310, and the control of the selectors 210, 310 is maintained at the previous value until the discrepancy is resolved. In this embodiment, if all of these states (S104, S105, S106, S107) are not OK, control is not performed on the selectors 210 and 310 for the 0 system and the 1 system. If all of the above conditions are OK, the state transitions to the next state (S108). The clock output phase synchronization circuit of this embodiment switches the selector on the non-operating system side.

[0021] Specifically, if system 0 is in operation in S108, the monitoring control circuit 500 on the system 1 side, which is the non-operating system, is activated, and if system 1 is in operation in S108, the monitoring control circuit 400 on the system 0 side, which is the non-operating system, is activated. Thereafter, in S109 and S110, the phase comparator 404 or 504 on the non-operating system side determines whether the phase comparison result is the same phase or opposite phase, and in S111, S112, S113, and S114, it is determined whether to make no change or switch the selector on the non-operating system side to the opposite side according to each condition, and this is executed (S115, S116, S117, S118, S119, S120, S121, and S122).

[0022] For example, in the case of 0-system operation (Yes in S108), if the phase selection setting values ​​are the same phase (Yes in S109), and if clocks A09 and B09 are the same phase (Yes in S111), the control unit 501 of the monitoring control circuit 500 does not change the selection state of selectors 210 and 310 (S115), and if they are opposite phases (No in S111), performs control to switch selector 310 to the opposite side without changing the selection state of selector 210 (S116). Also, if the phase selection setting values ​​are opposite phases (No in S109), and if clocks A09 and B09 are the same phase (Yes in S112), the control unit 501 switches selector 310 to the opposite side without changing the selection state of selector 210 (S117), and if they are opposite phases (No in S112), does not change the selection state of selectors 210 and 310.

[0023] Furthermore, in the case of single-system operation (No in S108), if the phase selection setting values ​​are the same phase (Yes in S110), and if clocks A09 and B09 are the same phase (Yes in S113), the control unit 401 of the monitoring control circuit 400 does not change the selection state of selectors 210 and 310 (S119), and if they are opposite phases (No in S113), switches selector 210 to the opposite side and does not change the selection state of selector 310 (S120). Furthermore, if the phase selection setting values ​​are opposite phases (No in S110), and if clocks A09 and B09 are the same phase (Yes in S114), the control unit 401 switches selector 210 to the opposite side and does not change the selection state of selector 310 (S121), and if they are opposite phases (No in S114), does not change the selection state of selectors 210 and 310.

[0024] By performing the above operations, it becomes possible to select whether the outputs of the clock transmitting panels are output in phase or out of phase according to the phase selection setting. Furthermore, in the present invention, if a panel is removed or inserted after the above states (S123, S124, S125, S126), or if some abnormality occurs in the panel itself, the system is configured to transition to the state (S104) and repeat the subsequent flow.

[0025] As described above, according to this embodiment, by having a startup time adjustment unit that differentiates the startup times of the clock transmitting panel (0 system) and the clock transmitting panel (1 system) to prevent chattering when determining the operating system, a frequency dividing unit that generates both a positive phase output and a negative phase output of a clock that has been divided by 2 within the output panel, a selector that selects between the positive phase clock and the negative phase clock, and a monitoring control circuit that controls the selector, it is possible to select whether the two clock outputs are to be output in phase or in opposite phases.

[0026] Furthermore, if the frequency dividers in the clock transmission panels for systems 0 and 1 were synchronized with each other, it would be possible to specify the phase relationship between the output clocks of systems 0 and 1, but the division timing would also need to be synchronized with the startup timing of each panel, which would increase the circuit scale and make design difficult. According to this embodiment, it is possible to select whether the two clock outputs are output in phase or out of phase, without requiring a circuit that synchronizes the frequency dividers in the panels for systems 0 and 1 with each other.

[0027] In this way, the ability to select whether the two clock outputs are in phase or out of phase has the following additional advantages. Specifically, when distributing to a subsequent clock device as a redundant system, setting the output to in phase prevents significant phase jumps from occurring when switching systems. On the other hand, when evaluating a standalone device, setting the output to out of phase makes it easy to monitor the output clock waveform and check whether switching has occurred during evaluation. Furthermore, in the embodiment of Figure 1, this function can be realized without the need to install a new monitoring and control panel.

[0028] [Second embodiment] 4 is a diagram showing an example of the panel configuration of a clock transmission circuit according to a second embodiment of the present invention. The clock transmission circuit according to this embodiment includes a monitor and control circuit panel 109 and an operation status unit 412 instead of the monitor and control circuit (0 system) 400, monitor and control circuit (1 system) 500, operation status unit 212, and operation status unit 312 in the clock transmission circuit shown in FIG.

[0029] The monitoring control circuit panel 109 is composed of a control unit 401, abnormality monitoring units 402 and 403, and a phase comparison unit 404. The abnormality monitoring unit 402 monitors for abnormalities in the clock A09 after selection of the clock transmitting panel (system 0) 107. The abnormality monitoring unit 403 monitors for abnormalities in the clock B09 after selection of the clock transmitting panel (system 1) 108. The phase comparison unit 404 compares the phases of the clock A09 and the clock B09. The control unit 401 receives as input the monitoring results A07 and B07 of the abnormality monitoring units 208 and 308, the setting of a phase selection setting switch that sets whether the output clocks A06 and B06 are in phase or out of phase, the operation status 412 of the clock transmitting panel (system 0) 107 and the clock transmitting panel (system 1) 108, the monitoring results of the abnormality monitoring units 402 and 403, and the comparison result of the phase comparison unit 404, and outputs control signals A08 and B08 to the selectors 210 and 310.

[0030] In this embodiment, the monitoring and control circuits that were respectively mounted on the 0-system and 1-system panels in the embodiment shown in Fig. 1 are integrated into one monitoring and control panel. This increases the variety of panels required for the device, but eliminates the need to determine whether the monitoring and control results of the 0-system and 1-system monitoring and control circuits 400, 500 in Fig. 1 and Fig. 3 match (S107).

[0031] Although several embodiments of the present invention have been described, the clock transmission panel (system 0) 107, clock transmission panel (system 1) 108, monitoring control circuit (panel) 109, and other circuits may have a computer system built therein. The above-described processing steps are stored in the form of a program on a computer-readable recording medium, and the computer performs the above processing by reading and executing this program. The computer may be configured, for example, with a CPU, main memory, storage, and an interface, but is not limited to these. Although the present invention has been described above with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. [Industrial Applicability]

[0032] The present invention can be applied to devices that transmit clocks, such as a network device equipped with two clock panels that form a redundant configuration. [Explanation of symbols]

[0033] 101 Oscillator (0 system) 102 Oscillator (1st series) 103 Clock receiving panel (0 series) 104 Clock receiving panel (1 series) 105 Clock Switch Panel (0 Series) 106 Clock Switch Panel (1 Series) 107 Clock transmission panel (0 series) 108 Clock transmission panel (1 series) 109 Monitoring control circuit (panel) 201 Bipolar-unipolar converter 202 Abnormality Monitoring Department 203 Branch 204 Selector 205 Abnormality monitoring section 206 Branch 207 Selector 208 Abnormality Monitoring Department 209 Frequency divider 210 Selector 211 Unipolar-bipolar converter 212 Operational Status Section 213 Start-up time adjustment section 301 Bipolar-unipolar converter 302 Abnormality monitoring section 303 Branch 304 Selector 305 Abnormality monitoring section 306 Branch 307 Selector 308 Abnormality monitoring section 309 Frequency divider 310 Selector 311 Unipolar-bipolar converter 312 Operational Status Department 313 Start-up time adjustment section 400 Monitoring control circuit (0 system) 401 Control Unit 402 Abnormality monitoring section 403 Abnormality Monitoring Department 404 Phase comparator 500 Monitoring control circuit (system 1) 501 Control section 502 Abnormality monitoring section 503 Abnormality Monitoring Department 504 Phase comparator A01 oscillator (0 system) output clock A02 Clock receiving panel (0 system) output clock A03 Clock receiving panel (0 system) output clock A04 Clock Switch Panel (0 system) output clock A05 Clock switching panel (0 system) output clock A06 Clock transmission panel (0 system) output clock (0 system) A07 Undivided clock abnormality monitoring result signal A08 Clock transmission panel (0 system) selector control signal A09 Clock after selecting the clock transmission panel (0 system) A10 Monitoring control circuit (0 system) monitoring control result signal A11 Clock transmission panel (0 system) slot ID information B01 Oscillator (1 system) output clock B02 Clock receiving panel (1st system) output clock B03 Clock receiving panel (1 system) output clock B04 Clock switching panel (system 1) output clock B05 Clock Switch Panel (1 system) Output Clock B06 Clock transmission panel (1 system) output clock (1 system) B07 Undivided clock abnormality monitoring result signal B08 Clock transmission panel (system 1) selector control signal B09 Clock after selection of clock transmission panel (0 system) B10 Monitoring control circuit (system 1) monitoring control result signal B11 Clock transmission panel (1st series) slot ID information

Claims

1. A clock output phase alignment control circuit including two clock transmission panels forming a redundant configuration of a 0 system and a 1 system, Each of the two clock transmission panels comprises: a frequency divider that divides an input clock by two and outputs both a positive phase output and a negative phase output of the divided clock; a selector for selecting either the positive phase output or the negative phase output, and further comprising a monitoring control circuit that controls the selector. Clock output phase alignment control circuit.

2. The monitoring control circuit includes: a phase comparator that compares the phases of the clocks selected by the selectors of the two clock transmission panels; an abnormality monitoring unit that monitors abnormalities in the clocks selected by the selectors of the two clock transmission panels; a control unit that controls the selector, 2. The clock output phase alignment control circuit according to claim 1.

3. the control unit receives as input information from a phase selection setting switch that sets whether the output clocks of the two clock transmission panels are in phase or out of phase.

3. The clock output phase alignment control circuit according to claim 2.

4. The monitoring control circuits are distributed and mounted on the two clock transmission panels.

2. The clock output phase alignment control circuit according to claim 1.

5. The monitoring control circuit is mounted on a panel independent of the two clock transmission panels.

2. The clock output phase alignment control circuit according to claim 1.

6. A control method using a clock output phase alignment control circuit including two clock transmission panels that form a redundant configuration of 0 system and 1 system, Dividing the input clock by two and outputting both a positive phase output and a negative phase output of the divided clock; selecting one of the positive phase output and the negative phase output; A control method using a clock output phase alignment control circuit including:

7. A computer of a clock output phase alignment control circuit including two clock transmission panels forming a redundant configuration of 0 system and 1 system, Dividing the input clock by two and outputting both a positive phase output and a negative phase output of the divided clock; selecting one of the positive phase output and the negative phase output; A program that executes the following.

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