Microprocessor architecture, clock signal generation method and storage medium

Abstract

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, and is applied to the technical field of computers, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises a basic clock unit and a frequency modulation clock unit. The frequency modulation clock unit comprises a first gating unit and at least two parallel initial signal generation units, the control unit configures first configuration information and first gating information, and the basic clock unit generates a basic clock signal; each initial signal generation unit generates a respective corresponding initial clock signal according to the first configuration information and the basic clock signal, and the first gating unit determines a target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. The clock signal source provided by the invention can effectively simplify the adjustment process of the clock frequency, improve the adjustment efficiency of the clock frequency, and meet the actual application requirements.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a microprocessor architecture, a clock signal generation method, and a storage medium. Background Technology

[0002] In modern computer technology, microprocessor architectures consist of multiple functional units, such as processor cores, GPU (Graphics Processing Unit) cores, and NOC (Network-on-Chip). These functional units all operate under the drive of a clock signal provided by a clock source. Providing a stable and reliable clock signal is one of the key conditions for the normal operation of a microprocessor architecture. With the development of DVFS (Dynamic Voltage and Frequency Scaling) and DFS (Dynamic Frequency Scaling) technologies, higher demands are placed on the clock signal source's ability to adjust the clock frequency.

[0003] In existing microprocessor architectures, clock signal sources are mostly built based on PLL (Phase-Locked Loop) modules, which have advantages such as simple structure and low jitter. However, when applied to DVFS or DFS technologies, they suffer from low frequency modulation efficiency and difficulty in responding to frequency adjustment requirements in a timely manner. Summary of the Invention

[0004] The purpose of this application is to provide a microprocessor architecture, a clock signal generation method, and a storage medium to improve the efficiency of clock frequency adjustment and meet the clock signal adjustment requirements in practical applications.

[0005] In a first aspect, this application provides a microprocessor architecture, including:

[0006] At least one functional unit, said functional unit being used to implement a preset function of the microprocessor architecture;

[0007] At least one clock signal source, each of the clock signal sources being connected to one or more of the functional units;

[0008] The control unit is used to configure the first configuration information and the first strobe information;

[0009] The clock signal source includes:

[0010] The basic clock unit is used to generate the basic clock signal;

[0011] The frequency modulation clock unit is connected to both the basic clock unit and the functional unit.

[0012] The frequency modulation clock unit includes:

[0013] At least two parallel initial signal generation units, each of the initial signal generation units being used to generate its own corresponding initial clock signal based on the first configuration information and the basic clock signal;

[0014] The first gating unit is used to output the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal.

[0015] Based on the above, the microprocessor architecture provided in this application configures first configuration information and first gating information in the control unit. Each initial signal generation unit in the frequency modulation clock unit generates its own corresponding initial clock signal according to the first configuration information and the basic clock signal provided by the basic clock unit. The first gating unit outputs the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. Compared with related technologies, in the microprocessor architecture provided in this application, the basic clock unit of the clock signal source is connected in series with each frequency modulation clock unit, and each initial signal generation unit in the frequency modulation clock unit is connected in parallel, thereby constructing a series-parallel hybrid clock source structure. By configuring the first configuration information and the first gating information, different clock signals can be selected to meet the requirements, effectively simplifying the clock frequency adjustment process, improving the clock frequency adjustment efficiency, and meeting the needs of practical applications.

[0016] In one optional implementation, the control unit is further configured to configure second configuration information to the base clock unit;

[0017] The basic clock unit includes:

[0018] A system-level configuration unit is used to store the second configuration information;

[0019] A basic signal generation unit receives a reference clock signal and generates the basic clock signal according to the second configuration information and the reference clock signal.

[0020] In the microprocessor architecture provided in this application, an optional implementation of a basic clock unit is provided, which includes a system-level configuration unit and a basic signal generation unit. The basic signal generation unit generates a basic clock signal according to the second configuration information stored in the system-level configuration unit and the reference clock signal, so as to meet the requirements of the initial signal generation units connected to the subsequent stage of the basic clock unit to output the initial clock signal. The basic clock signal can be adjusted by updating the second configuration information, which effectively simplifies the adjustment process of the basic clock signal and helps to improve the adjustment efficiency of the clock frequency.

[0021] In one optional implementation, the basic signal generation unit includes any one of a phase-locked loop (PLL), a delay phase-locked loop (DLL), a digital phase-locked loop (DPLL), and an all-digital phase-locked loop (ADPLL).

[0022] In the microprocessor architecture provided in this application, multiple optional implementations of the basic signal generation unit are provided. The basic signal generation unit is implemented using different forms of phase-locked loops. The existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design and improve the design efficiency. Furthermore, the basic signal generation unit is used to provide the basic clock signal. When a PLL is selected for implementation, its low jitter and safe and stable technical advantages can be fully utilized, which helps to improve the reliability of the basic clock signal.

[0023] In one optional implementation, the frequency modulation clock unit further includes:

[0024] The unit-level configuration unit is connected to each of the initial signal generation units, the control unit, and the first gating unit, respectively.

[0025] The unit-level configuration unit is used to store the first configuration information and the first gating information.

[0026] In the microprocessor architecture provided in this application, an optional implementation of a frequency modulation clock unit is provided, which includes a unit-level configuration unit. Users can configure the aforementioned first configuration information and the first gating unit through the unit-level configuration unit, thereby completing the clock frequency setting of each initial clock signal and the final selection of the target clock signal. The configuration process is simple and easy to implement. Furthermore, each frequency modulation clock unit is equipped with a unit-level configuration unit, which can realize the customized clock signal configuration of different functional units, thereby meeting the different clock frequency application requirements of different functional units.

[0027] In one optional implementation, the frequency modulation clock unit further includes:

[0028] The second gating unit has its input terminals connected to both the first gating unit and the basic signal generation unit, and its output terminal connected to the functional unit.

[0029] The control unit is also used to configure second strobe information;

[0030] The second gating unit is used to output the target clock signal or the base clock signal according to the second gating information.

[0031] In the microprocessor architecture provided in this application, the frequency modulation clock unit includes a second gating unit. The second gating unit selects whether to output a target clock signal or a base clock signal to the functional unit. As mentioned above, adjusting the clock frequency may cause abnormal operation of the functional unit or even the microprocessor architecture. Therefore, in the event of an abnormality, the base clock signal can be selected to be output to the functional unit by configuring the second gating information, thereby ensuring the safe operation of the functional unit. In other words, this application provides a safety protection mechanism that switches between the target clock signal and the base clock signal by configuring the second gating information to meet the risk avoidance requirements in abnormal situations.

[0032] In one alternative implementation, the system-level configuration unit is further configured to store the second strobe information.

[0033] In the microprocessor architecture provided in this application, the second strobe information is stored in the system-level configuration unit. Since the second strobe unit of each frequency modulation clock unit is connected to the system-level configuration unit, updating the second strobe information stored in the system-level configuration unit can realize the synchronous adjustment of all frequency modulation clock units. When a system-level anomaly occurs in the microprocessor architecture, by updating the second strobe information in the system-level configuration unit, the clock signals of all functional units can be adjusted to the base clock signal at the same time, thereby realizing system-level frequency modulation control, ensuring the overall operational safety of the microprocessor architecture, and having high clock adjustment efficiency to meet the needs of practical applications.

[0034] In one optional implementation, the frequency modulation clock unit further includes:

[0035] The early warning unit, connected to the first gating unit, is used to output a preset gating signal in response to an early warning event of the functional unit;

[0036] The first gating unit is further configured to: in response to the preset gating signal, determine the initial clock signal with the lowest clock frequency among the initial clock signals as the target clock signal.

[0037] In the microprocessor architecture provided in this application, an early warning unit is set in the frequency modulation clock unit. The early warning unit detects early warning events of the functional unit and outputs a preset gating signal when an early warning event occurs. The first gating unit responds to the preset gating signal and determines the initial clock signal with the lowest clock frequency among all initial clock signals as the target clock signal. That is, the operation safety of the functional unit is ensured by reducing the clock frequency. Since the preset gating signal is directly triggered by the early warning unit, a rapid response to early warning events can be achieved, which helps to improve the operation safety of the functional unit.

[0038] In one optional implementation, the initial signal generation unit includes any one of a phase-locked loop (PLL), a delay phase-locked loop (DLL), a digital phase-locked loop (DPLL), and an all-digital phase-locked loop (ADPLL).

[0039] In the microprocessor architecture provided in this application, multiple optional implementations of the initial signal generation unit are provided. The initial signal generation unit is implemented using different forms of phase-locked loops. The existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design and improve the design efficiency. Furthermore, the initial signal generation unit is used to provide the initial clock signal. When using ADPLL for implementation, its advantages of small area and low power consumption can be fully utilized, which helps to reduce the overall area and power consumption of the clock signal source.

[0040] Secondly, this application provides a clock signal generation method applied to a microprocessor architecture as described in any embodiment of the first aspect, wherein the microprocessor architecture includes a control unit, a clock signal source, and functional units for implementing preset functions of the microprocessor architecture, and the method includes the following steps performed by the control unit:

[0041] The basic clock unit in the clock signal source is controlled to generate a basic clock signal;

[0042] Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source;

[0043] The frequency modulation clock unit includes a first gating unit and at least two parallel initial signal generation units, wherein,

[0044] Each of the initial signal generation units is used to generate its own corresponding initial clock signal based on the first configuration information and the basic clock signal;

[0045] The first gating unit is used to output the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal.

[0046] Based on the above, the clock signal generation method provided in this application involves a control unit first controlling a basic clock unit to output a basic clock signal, and then configuring a first configuration information and a first gating information to a frequency modulation clock unit. Each initial signal generation unit in the frequency modulation clock unit generates its own corresponding initial clock signal according to the first configuration information and the aforementioned basic clock signal. The first gating unit outputs the initial clock signal generated by the initial signal generation unit indicated by the first gating information as a target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. Compared with related technologies, the clock signal generation method provided in this application can achieve rapid and smooth adjustment of the clock frequency by configuring the first configuration information and the first gating information, thereby improving the stability and efficiency of clock frequency adjustment and meeting the needs of practical applications.

[0047] In one optional implementation, the at least two parallel initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit;

[0048] Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including:

[0049] The first clock frequency corresponding to the first initial signal generation unit, the second clock frequency corresponding to the second initial signal generation unit, and the third clock frequency corresponding to the third initial signal generation unit are respectively configured, wherein the first clock frequency is less than the second clock frequency, and the second clock frequency is less than the third clock frequency.

[0050] In addition, the first strobe information is configured according to the operating status of the functional unit.

[0051] In the clock signal generation method provided in this application, the first configuration information includes a first clock frequency, a second clock frequency, and a third clock frequency, wherein the first clock frequency is less than the second clock frequency, and the second clock frequency is less than the third clock frequency, thereby providing three clock signals with different clock frequencies to meet the clock signal application requirements in different scenarios.

[0052] In one optional implementation, configuring the first strobe information based on the operating state of the functional unit includes:

[0053] When a functional unit needs to operate at a reduced frequency, a first strobe configuration value is configured. The first strobe configuration value is used to instruct the first strobe unit to determine the initial clock signal generated by the first initial signal generation unit according to the first clock frequency as the target clock signal.

[0054] When the functional unit is in normal operation, a second strobe configuration value is configured. The second strobe configuration value is used to instruct the first strobe unit to determine the initial clock signal generated by the second initial signal generation unit according to the second clock frequency as the target clock signal.

[0055] When a functional unit needs to operate at an increased frequency, a third strobe configuration value is configured. The third strobe configuration value is used to instruct the first strobe unit to determine that the initial clock signal generated by the third initial signal generation unit according to the third clock frequency is the target clock signal.

[0056] In the clock signal generation method provided in this application, the frequency modulation clock unit can provide three clock signals to form a tiered configuration of high, medium and low clock frequencies. By configuring the gating configuration value of the first gating information, the selection of the first initial clock signal, the second initial clock signal and the third initial clock signal can be realized to meet the application requirements in different scenarios.

[0057] In one optional implementation, the at least two initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit;

[0058] Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including:

[0059] When a functional unit needs to operate at a higher frequency, the following operations should be performed:

[0060] Configure the steady-state clock frequency corresponding to the second initial signal generation unit, wherein the steady-state clock frequency is the clock frequency used when the functional unit is operating normally;

[0061] The clock frequencies corresponding to the first initial signal generation unit and the third initial clock unit are alternately increased, and the gating configuration value of the first gating unit is updated, so that the first gating unit determines the initial clock signal of the higher clock frequency among the first initial signal generation unit and the third initial clock unit as the target clock signal.

[0062] In the clock signal generation method provided in this application, a second initial signal generation unit provides a second initial clock signal according to a steady-state clock frequency. The first initial signal generation unit and the third initial signal generation unit alternately increase the frequency to improve the frequency increase efficiency of the functional unit. At the same time, the second initial signal generation unit maintains the output of the second initial clock signal unchanged, which can be used for emergency avoidance to ensure the safe operation of the functional unit.

[0063] In one optional implementation, configuring first strobe information to the frequency modulation clock unit in the clock signal source further includes:

[0064] When the functional unit needs to operate at a reduced frequency or is in normal operating condition, the strobe configuration value is configured as the second strobe configuration value. The second strobe configuration value is used to instruct the first strobe unit to determine that the initial clock signal generated by the second initial signal generation unit according to the steady-state clock frequency is the target clock signal.

[0065] In the clock signal generation method provided in this application, since the second initial signal generation unit provides the second initial clock signal according to the steady-state clock frequency, and the steady-state clock frequency is the clock frequency used when the functional unit is running normally, the second initial clock signal can be output as the target clock signal by configuring the first gating unit to operate at a lower frequency or in normal operation, thus ensuring the safe operation of the functional unit.

[0066] In one optional implementation, configuring first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source includes:

[0067] Repeat the first preset configuration operation until the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency;

[0068] The first preset configuration operation includes:

[0069] Simultaneously configure the clock frequency of other initial signal generation units besides the target initial signal generation unit, wherein the target initial signal generation unit is the initial signal generation unit currently providing the target clock signal;

[0070] Furthermore, after each of the other initial signal generation units outputs an initial clock signal at the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially determines the initial clock signal of each of the other initial signal generation units as the target clock signal according to a preset cyclic order.

[0071] In the clock signal generation method provided in this application, the clock frequencies of other initial signal generation units besides the target initial signal generation unit are configured simultaneously, which can effectively shorten the overall time for the initial signal generation unit to stably output the initial clock signal. Furthermore, by determining the initial clock signals of each of the other initial signal generation units as the target clock signal in a preset cyclic order, the sequential output of each initial clock signal can be realized, thereby realizing the clock signal switching of the ring architecture and effectively improving the adjustment efficiency of the clock signal.

[0072] In one optional implementation, simultaneously configuring the clock frequencies of other initial signal generation units besides the target initial signal generation unit includes:

[0073] Obtain the initial clock frequency, the preset frequency modulation step size, and the preset target frequency;

[0074] Based on the initial clock frequency, the preset frequency modulation step size, and the preset target frequency, a plurality of intermediate clock frequencies are determined.

[0075] The clock frequencies of each of the other initial signal generation units are configured simultaneously according to the plurality of intermediate clock frequencies, so that each of the other initial signal generation units corresponds to an intermediate clock frequency.

[0076] In the clock signal generation method provided in this application, the intermediate clock frequencies involved in the frequency adjustment process are determined based on the initial clock frequency, the preset frequency modulation step size, and the preset target clock frequency. The clock frequencies of each initial clock generation unit are configured according to the obtained results, which helps to improve the efficiency of clock frequency adjustment.

[0077] In one optional implementation, the at least two initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit;

[0078] Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including:

[0079] Repeat the second preset configuration operation until the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency;

[0080] The second preset configuration operation includes:

[0081] Simultaneously, the first clock frequency of the first initial signal generation unit and the second clock frequency of the second initial signal generation unit are configured, the difference between the second clock frequency and the first clock frequency is half of the preset frequency modulation step size, and the initial clock signal of the third initial signal generation unit is used as the current target clock signal, and the difference between the second clock frequency and the clock frequency of the current target clock signal is the preset frequency modulation step size.

[0082] Furthermore, after the first initial signal generation unit and the second initial signal generation unit output the initial clock signal according to the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially uses the initial clock signals of the first initial signal generation unit and the second initial signal generation unit as the target clock signal.

[0083] The clock signal generation method provided in this application sets a target clock frequency and a transition clock frequency before frequency modulation. The frequency difference between the transition clock frequency and the current clock frequency is half a preset frequency modulation step size, and the frequency difference between the target clock frequency and the current clock frequency is a preset frequency modulation step size. When switching from the current clock frequency to the target clock frequency, the frequency is first adjusted to the transition clock frequency, and then adjusted from the transition clock frequency to the target clock frequency. This setting can improve the smoothness of the frequency adjustment process and ensure the stability of functional units and microprocessor architecture. Furthermore, configuring the transition clock frequency and the target clock frequency simultaneously can shorten the clock signal stabilization time and improve the efficiency of clock adjustment.

[0084] In one optional implementation, the frequency modulation clock unit further includes a second gating unit, and the method further includes:

[0085] Configure a second strobe information, which is used to instruct the second strobe unit to output the target clock signal or the base clock signal.

[0086] The clock signal generation method provided in this application selects to output either a target clock signal or a base clock signal to a functional unit through a second gating unit. As mentioned above, adjusting the clock frequency may cause abnormal operation of the functional unit or even the microprocessor architecture. Based on this, in the event of an abnormality, the base clock signal can be selected to be output to the functional unit by configuring the second gating information, thereby ensuring the safe operation of the functional unit. In other words, this application provides a safety protection mechanism that achieves the switching between the target clock signal and the base clock signal by configuring the second gating information, meeting the risk avoidance requirements in abnormal situations.

[0087] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the clock signal generation method as described in any of the second aspects of this application. Attached Figure Description

[0088] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0089] Figure 1 This is a structural block diagram of a microprocessor architecture provided in an embodiment of this application.

[0090] Figure 2 This is a structural block diagram of another microprocessor architecture provided in an embodiment of this application.

[0091] Figure 3 This is a structural block diagram of another microprocessor architecture provided in an embodiment of this application.

[0092] Figure 4 This is a flowchart of a clock signal generation method provided in an embodiment of this application.

[0093] Figure 5 A flowchart of another clock signal generation method provided in an embodiment of this application.

[0094] Figure 6 This is a schematic diagram illustrating the clock signal switching effect provided in an embodiment of this application.

[0095] Figure 7 A flowchart of another clock signal generation method provided in an embodiment of this application.

[0096] Figure 8 This is a schematic diagram illustrating another clock signal switching effect provided in an embodiment of this application.

[0097] Figure 9 A flowchart of another clock signal generation method provided in the embodiments of this application.

[0098] Figure 10 This is a schematic diagram illustrating another clock signal switching effect provided in an embodiment of this application.

[0099] Figure 11 This is a schematic diagram illustrating another clock signal switching effect provided in an embodiment of this application.

[0100] Figure 12 A flowchart of another clock signal switching method provided in an embodiment of this application.

[0101] Figure 13 This is a schematic diagram illustrating another clock signal switching effect provided in an embodiment of this application.

[0102] Figure 14 This is a schematic diagram illustrating another clock signal switching effect provided in an embodiment of this application. Detailed Implementation

[0103] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0104] To address the problem of low frequency modulation efficiency and difficulty in timely response to frequency adjustment requirements when the clock signal source in the existing microprocessor architecture is applied to DVFS or DFS technology, this application provides a microprocessor architecture in which the clock signal source includes a basic clock unit and a frequency modulation clock unit. The basic clock unit and the frequency modulation clock unit are connected in series, and the initial signal generation units in the frequency modulation clock unit are connected in parallel, thereby constructing a hybrid series-parallel clock source structure. By configuring the first configuration information and the first strobe information, different clock signals can be selected, effectively simplifying the clock frequency adjustment process, improving the clock frequency adjustment efficiency, and meeting the needs of practical applications.

[0105] Based on the above, this application provides a microprocessor architecture including a control unit, at least one functional unit, and at least one clock signal source. Each clock signal source is connected to at least one functional unit and provides a clock signal to the connected functional unit. Based on this, in... Figure 1 In the microprocessor architecture provided in the illustrated embodiment, a clock signal source is shown as an example, labeled as clock signal source 20. Correspondingly, a functional unit is also shown as an example, labeled as functional unit 30. The clock signal source 20 includes a basic clock unit 21 and a frequency modulation clock unit 22. The frequency modulation clock unit 22 includes a first gating unit 221 and at least two parallel initial signal generation units. In this embodiment, N initial signal generation units are shown, where N≥2.

[0106] Control unit 10 is used to configure first configuration information and first strobe information to clock signal source 20, in combination with Figure 1 As shown, the control unit 10 is connected to each initial signal generation unit in the frequency modulation clock unit 22 and the gating control terminal of the first gating unit 221. Based on this connection, the control unit 10 configures corresponding configuration information to each initial signal generation unit and configures first gating information to the first gating unit 221. It should be noted that, in order to more clearly illustrate the connection relationship between the various components of the clock signal source provided in this embodiment, the connection relationship between the control unit 10 and each initial signal generation unit is illustrated with a bidirectional arrow. The specific connection relationship is subject to the above description.

[0107] In one optional implementation, the control unit 10 may be a dedicated control module for the clock signal source 20, controlling the operation of the clock signal source 20. In another optional implementation, the control unit 10 may also be understood as part of the control logic in the microprocessor architecture, which is stored in the microprocessor architecture in the form of firmware and executed by the relevant control module in the microprocessor architecture.

[0108] In one optional implementation, the first configuration information includes the clock frequency required by each initial signal generation unit to generate the initial clock signal. By configuring the clock frequency in the first configuration information, the frequency modulation clock unit 22 can be instructed to output a clock signal of the corresponding clock frequency. Of course, the first configuration information may also include other information for instructing the initial signal generation unit to generate the initial clock signal, which will not be listed here. As long as it does not exceed the core concept of this application, it also falls within the scope of protection of this application.

[0109] The basic clock unit 21 is connected to the input terminal of each initial signal generation unit in the frequency modulation clock unit 22, and is used to provide basic clock signals to each initial signal generation unit respectively.

[0110] The output terminals of each initial signal generation unit in the frequency modulation clock unit 22 are respectively connected to the gating input terminal of the first gating unit 221, combined with Figure 1 As shown, each initial signal generation unit is connected in parallel between the base clock unit 21 and the first gating unit 221. In the frequency modulation clock unit 22 provided in this embodiment, each initial signal generation unit is used to generate its own corresponding initial clock signal according to the first configuration information and the base clock signal. Based on the foregoing, the first configuration information includes the clock frequency corresponding to each initial signal generation unit. The initial signal generation unit generates an initial clock signal of the corresponding clock frequency according to its own corresponding clock frequency and the base clock signal. In this embodiment and subsequent embodiments, the clock frequencies included in the first configuration information can be set according to the frequency modulation requirements. Therefore, the initial clock signals output by each initial signal generation unit are independent of each other and are usually of different frequencies.

[0111] In practical applications, the initial signal generation unit can be implemented in various ways, such as by selecting PLL (Phase-Locked Loop), DLL (Delay Locked Loop, also known as Digital Phase-Locked Loop), DPLL (Digital Phase-Locked Loop), and ADPLL (All Digital Phase-Locked Loop). Any type of phase-locked loop (PLL) is available. PLLs offer advantages such as low jitter and reliability, and their analog filters effectively suppress high-frequency noise. They are widely used in traditional chip architectures. However, PLLs have disadvantages including a larger footprint in the microprocessor architecture, higher power consumption, higher power requirements for analog components, more complex power supply, poorer dynamic response, and a longer lock-in time for the output clock signal. In contrast, DLLs are often used for precise clock frequency adjustment, offering advantages such as accurate zero-delay control, faster lock-in time, and a highly stable clock signal. Furthermore, ADPLLs employ a fully digital structure, making them more suitable for advanced miniaturization processes. They have no analog components, resulting in a smaller footprint. They are also less sensitive to power supply noise, offer higher stability, require no external power supply, and their lock-in time can be optimized to a minimum, reaching several nanoseconds. Specific implementation details for various PLLs can be found in relevant technical documentation and will not be elaborated upon here.

[0112] Based on the above, this embodiment provides multiple optional implementations of the initial signal generation unit. Different forms of phase-locked loops are used to implement the initial signal generation unit, which can take advantage of the existing advantages of the corresponding phase-locked loop technology, simplify the design difficulty, and improve the design efficiency. Furthermore, the initial signal generation unit is used to provide the initial clock signal. When using ADPLL for implementation, its advantages of small area and low power consumption can be fully utilized, which helps to reduce the overall area and power consumption of the clock signal source.

[0113] Furthermore, based on the technical principle of phase-locked loops, given a fixed base clock signal, the clock frequency of the final output clock signal of the phase-locked loop can be adjusted by changing the division ratio of the phase-locked loop. Therefore, as an optional implementation method, the first configuration information may also include the division ratio corresponding to each initial signal generation unit. Each initial signal generation unit can output the corresponding initial clock signal based on the base clock signal and its own corresponding division ratio.

[0114] The first gating unit 221 has at least two gating input terminals, one gating output terminal, and one or more gating control terminals, combined with Figure 1As shown, each gating input segment of the first gating unit 221 is connected to an initial signal generation unit, receiving the initial clock signal generated by the connected initial signal generation unit. The gating output terminal serves as the output terminal of the frequency modulation clock unit 22 and is connected to the functional unit 30. The gating input terminal of the first gating unit 221 is connected to the control unit 10. As mentioned above, the control unit 10 outputs first gating information, which is used to indicate the target initial signal generation unit in each initial signal generation unit, thereby using the initial clock signal output by the target initial signal generation unit as the target clock signal. In other words, the first gating information is used to indicate the target clock signal in each initial clock signal. The first gating unit 221 determines the target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the functional unit 30. It can be understood that in practical applications, by adjusting the first gating information, the first gating unit 221 can be controlled to output initial clock signals of different clock frequencies as target clock signals.

[0115] In one optional implementation, the first gating unit 221 can be implemented using a MUX (multiplexer). For example, the MUX can be a glitch-free clock switch. Based on this, the first gating information can include the gating configuration value of the MUX. By configuring a certain gating input terminal and a gating output terminal in the MUX through the gating configuration value, the initial clock signal output by the initial signal generation unit connected to that gating input terminal is used as the target clock signal output. Of course, the first gating unit 221 can also be implemented in other ways, which will not be detailed here. Without departing from the core concept of this application, they also fall within the scope of protection of this application.

[0116] Functional unit 30 can be any functional unit in the microprocessor architecture, used to implement the preset functions of the microprocessor architecture. For example, functional unit 30 can be a processor core, which runs under the target clock signal after receiving the target clock signal output by the frequency modulation unit 22; or functional unit 30 can be a GPU core, which can execute preset image processing tasks after receiving the target clock signal output by the frequency modulation unit 22.

[0117] It is understandable that a microprocessor architecture includes multiple functional units, each of which performs different preset functions. Consequently, the clock frequencies used by each functional unit may also differ. Therefore, in practical applications, based on the specific settings of the functional units in the microprocessor architecture, a larger number of frequency-modulated clock units can be set in the clock signal source, or even one frequency-modulated clock power supply can correspond to one functional unit, thereby achieving customized adjustment of the clock frequency to meet the operational needs of different functional units.

[0118] In summary, the microprocessor architecture provided in this application includes a clock signal source comprising a basic clock unit and a frequency modulation clock unit. The basic clock unit generates a basic clock signal, and the frequency modulation clock unit is connected to the functional units in the microprocessor architecture. The control unit configures first configuration information and first gating information to the frequency modulation clock unit. The frequency modulation clock unit includes a first gating unit and at least two parallel initial signal generation units. Each initial signal generation unit generates its corresponding initial clock signal based on the first configuration information and the aforementioned basic clock signal. The first gating unit outputs the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. Compared with related technologies, in the clock signal source provided in this application, the basic clock unit is connected in series with each frequency modulation clock unit, and each initial signal generation unit in the frequency modulation clock unit is connected in parallel, thereby constructing a series-parallel hybrid clock source structure. By configuring the first configuration information and the first gating information, a clock signal that meets the frequency modulation requirements can be selected, effectively simplifying the clock frequency adjustment process, improving the clock frequency adjustment efficiency, and meeting the needs of practical applications.

[0119] Furthermore, based on the aforementioned clock signal output process, it can be seen that the target clock signal specifically output to the functional unit is provided by the frequency modulation clock unit. The clock frequency of the target clock signal can be changed by configuring the first configuration information and the first strobe information. The clock frequency adjustment process is not limited by the basic clock unit. Multiple initial signal generation units connected in parallel can achieve seamless switching of clock signals with different clock frequencies, making the frequency modulation process more flexible.

[0120] This application also provides another microprocessor architecture, see [link to application]. Figure 2 As shown, compared to the previous embodiments, in the microprocessor architecture provided in this embodiment, the basic clock unit 21 includes a system-level configuration unit 211 and a basic signal generation unit 212, and the frequency modulation clock unit 22 includes a unit-level configuration unit 222.

[0121] Combination Figure 2 As shown, the system-level configuration unit 211 is connected to the control unit 10 and the basic signal generation unit 212 respectively. The control unit 10 is also used to configure the second configuration information to the basic clock unit 21. Based on this, the system-level configuration unit 211 can be used to store the second configuration information. Referring to the optional implementation of the first configuration information mentioned above, the second configuration information mentioned in this embodiment can be the clock frequency or the frequency division ratio. Of course, it can also be other configuration information used to instruct the basic signal generation unit 212 to generate the basic clock signal, which will not be listed here.

[0122] In one optional implementation, the system-level configuration unit 211 can be implemented using a register set. The register set serves as an intermediary for the exchange of second configuration information between the control unit 10 and the basic signal generation unit 212. In practical applications, the intermediary role of the system-level configuration unit 211 is mainly reflected in the following: the control unit 10 writes the second configuration information into the system-level configuration unit 211, which stores it; the basic signal generation unit 212 can obtain the second configuration information by accessing the system-level configuration unit 211. Of course, other methods for realizing information exchange between the control unit 10 and the basic signal generation unit 212 are also optional, and will not be detailed here.

[0123] The basic signal generation unit 212 receives a reference clock signal and second configuration information stored in the system-level configuration unit 211, and generates a basic clock signal based on the second configuration information and the reference clock signal. The reference clock signal can be provided by other clock signal sources in the microprocessor architecture or by a crystal oscillator; this application does not limit the specific source of the reference clock signal.

[0124] This embodiment provides an optional implementation of a basic clock unit, which includes a system-level configuration unit and a basic signal generation unit. The basic signal generation unit generates a basic clock signal based on the second configuration information stored in the system-level configuration unit and a reference clock signal, thereby meeting the requirements of the initial signal generation units connected to the subsequent stage of the basic clock unit to output initial clock signals. Users can adjust the basic clock signal by updating the second configuration information, which effectively simplifies the adjustment process of the basic clock signal and helps to improve the adjustment efficiency of the clock frequency.

[0125] In one optional implementation, referring to the aforementioned implementation of the initial signal generation unit, the basic signal generation unit 212 can be any one of PLL, DLL, DPLL, and ADPLL. Of course, the basic signal generation unit 212 can also be implemented using other related technologies, which will not be detailed here. This embodiment provides multiple optional implementations of the basic signal generation unit. By using different forms of phase-locked loops to implement the basic signal generation unit, the existing advantages of the corresponding phase-locked loop technologies can be utilized to simplify the design and improve design efficiency. Furthermore, the basic signal generation unit is used to provide the basic clock signal. When using a PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the basic clock signal.

[0126] Taking the basic signal generation unit implemented using a PLL as an example, the second configuration information includes the frequency division ratio. A typical PLL structure includes a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider. The first input of the phase detector receives the reference clock signal. The output of the phase detector, the charge pump, the low-pass filter, and the VCO are connected in series. The output of the VCO serves as the output of the PLL. The input of the frequency divider is connected to the output of the VCO, and the output of the frequency divider is connected to the second input of the phase detector, forming a closed control path. The frequency divider acquires the clock signal output by the VCO and divides the current clock signal output by the VCO according to the frequency division ratio configured in the second configuration information to obtain the frequency-divided sampled clock signal. The phase detector adjusts the control signal output to the charge pump based on the phase and frequency deviations between the sampled clock signal and the sampled clock signal, ultimately adjusting the clock signal output by the VCO until the deviation between the reference clock signal and the sampled clock signal is within a preset deviation range. That is, the PLL completes the locking of the output clock signal and outputs the basic clock signal. As for the specific process by which the PLL outputs the base clock signal based on the reference clock signal and the frequency division ratio, it can be implemented by referring to relevant technologies, and will not be described in detail here.

[0127] Furthermore, the frequency modulation clock unit 22 includes a unit-level configuration unit 222, combined with... Figure 2 As shown, the unit-level configuration unit 222 is connected to each initial signal generation unit, the control unit 10, and the first gating unit 221, respectively. It serves as an intermediate medium for information transmission between the control unit 10 and each initial signal generation unit and the first gating unit 221. The intermediate medium function of the unit-level configuration unit 222 can be referred to the relevant content of the aforementioned system-level configuration unit 211, and will not be repeated here. The unit-level configuration unit 222 is used to store the first configuration information and the first gating information. Referring to the implementation method of the aforementioned system-level configuration unit 211, the unit-level configuration unit 222 can also be implemented using a register group or other methods.

[0128] In this embodiment, the configuration of the first configuration information and the first gating unit can be realized through the unit-level configuration unit, thereby completing the clock frequency setting of each initial clock signal and the final selection of the target clock signal. The configuration process is simple and easy to implement. Furthermore, when the clock signal source includes multiple frequency modulation clock units, each frequency modulation clock unit is set with a unit-level configuration unit, which can realize the customized clock signal configuration of different functional units, thereby meeting the application requirements of different functional units for different clock frequencies.

[0129] As for Figure 2 The functions of the other components of the clock signal source and their interconnections in the illustrated embodiment can be found by referring to... Figure 1 The relevant content of the illustrated embodiment will not be repeated here.

[0130] This application also provides another microprocessor architecture, see [link to application]. Figure 3 As shown, compared to the previous embodiments, in the microprocessor architecture provided in this embodiment, the frequency modulation clock unit 22 of the clock signal source 20 includes a second gating unit 223 and an early warning unit 224.

[0131] Combination Figure 3 As shown, the second gating unit 223 has a first gating input terminal, a second gating input terminal, a gating output terminal, and a gating control terminal. The first gating input terminal is connected to the gating output terminal of the first gating unit 221, the second gating input terminal is connected to the output terminal of the basic signal generation unit 212 in the basic clock unit 21, and receives the basic clock signal output by the basic signal generation unit 212. The gating control terminal of the second gating unit 223 is connected to the system-level configuration unit 211 in the basic clock unit 21, and the gating output terminal of the second gating unit 223 is connected to the functional unit 30.

[0132] Based on the above connection relationship, the control unit 10 is also used to configure the second gating information, that is, to configure the second gating information in the system-level configuration unit 211. The second gating information is used to instruct the second gating unit 223 to output the basic clock signal or the target clock signal determined by the first gating unit 221 to the functional unit 30.

[0133] To meet the clock frequency requirements of each functional unit in the microprocessor architecture, each initial signal generation unit in the frequency modulation clock unit 22 will perform frequency upsampling processing on the basic clock signal. In other words, the clock frequency of the initial clock signal output by each initial signal generation unit is higher than the clock frequency of the basic clock signal. Correspondingly, the clock frequency of the target clock signal determined in each initial clock signal must also be higher than the clock frequency of the basic clock signal. Therefore, the basic clock signal can be used as the clock signal for the functional unit during emergency avoidance. The basic clock signal is a clock signal that can ensure the safe and stable operation of the functional unit in emergency scenarios.

[0134] Based on the above, in one optional implementation, the second strobing information includes an operating configuration value or a risk avoidance configuration value. The operating configuration value instructs the second strobing unit 223 to output a target clock signal, while the risk avoidance configuration value instructs the second strobing unit 223 to output a base clock signal. Specifically, when the timing margin of the current clock signal of the functional unit 30 is insufficient, requiring frequency reduction for emergency risk avoidance, the second strobing information is the risk avoidance configuration value. The second strobing unit 223 responds to the risk avoidance configuration value by outputting a base clock signal, ensuring that the functional unit 30 can operate safely without timing chaos due to insufficient timing margin. Conversely, when the functional unit 30 is operating normally, the second strobing information is the operating configuration value, and the second strobing unit 223 responds to the operating configuration value by outputting a target clock signal to the functional unit 30, ensuring normal operation of the functional unit 30. Based on the foregoing, it can be understood that in practical applications, there is no specific requirement for the magnitude of the operating configuration value and the risk avoidance configuration value; simply selecting different configuration values ​​is sufficient.

[0135] In this embodiment, the target clock signal or the base clock signal is selected to be output to the functional unit through the second gating unit. As mentioned above, adjusting the clock frequency may cause abnormal operation of the functional unit or even the microprocessor architecture. Based on this, in the event of an abnormality, the base clock signal can be selected to be output to the functional unit by configuring the second gating information, thereby ensuring the safe operation of the functional unit. In other words, this application provides a safety protection mechanism that realizes the switching between the target clock signal and the base clock signal by configuring the second gating information to meet the risk avoidance requirements in abnormal situations.

[0136] Furthermore, the second gating information is stored in the system-level configuration unit, enabling centralized control of different frequency-modulated clock units. In conjunction with the foregoing, in practical applications, the clock signal source provided in the various embodiments of this application may include multiple (i.e., at least two) frequency-modulated clock units. In this case, the gating control terminal of the second gating unit in each frequency-modulated clock unit is connected to the system-level configuration unit in the basic signal unit. Based on this, when the control unit configures the second gating information to the system-level configuration unit, centralized and unified control of each frequency-modulated clock unit can be achieved. This is of great significance for improving the overall security of the microprocessor architecture. Updating the second gating information stored in the system-level configuration unit enables synchronous adjustment of all frequency-modulated clock units. When a system-level anomaly occurs in the microprocessor architecture, by updating the second gating information in the system-level configuration unit (i.e., configuring it as a risk-avoidance configuration value), the clock signals of all functional units can be simultaneously adjusted to the basic clock signal, thereby achieving system-level risk-avoidance control, ensuring the overall operational safety of the microprocessor architecture, and providing high clock adjustment efficiency to meet practical application requirements.

[0137] Furthermore, in combination Figure 3As shown, the frequency modulation clock unit 22 also includes an early warning unit 224. The early warning unit 224 is used to detect early warning events of the functional unit 30. For example, the early warning event may be insufficient timing margin or excessive temperature of the functional unit 30. The early warning unit 224 is connected to the gating control terminal of the first gating unit 221. In response to the detected early warning event, the early warning unit 224 outputs a preset gating signal. The first gating unit 221 responds to the preset gating signal, determines the initial clock signal with the lowest clock frequency among the obtained initial clock signals as the target clock signal, and outputs it to the functional unit 30, thereby achieving the purpose of reducing the clock frequency of the functional unit 30. Compared with the aforementioned system-level risk avoidance mechanism based on the system-level configuration unit 211 and the second gating unit 223, the risk avoidance measure based on the cooperation of the early warning unit 224 and the first gating unit 221 can be defined as a unit-level risk avoidance mechanism, that is, ensuring the operational safety of the functional unit 30 by reducing the clock frequency. Furthermore, since the preset gating signal is directly triggered by the early warning unit, a rapid response to the early warning event can be achieved, which helps to improve the operational safety of the functional unit.

[0138] It is understandable that the aforementioned system-level and unit-level risk avoidance mechanisms can work together to provide hierarchical risk avoidance protection for functional units. For example, when a functional unit experiences an early warning event, the early warning unit first triggers the aforementioned unit-level risk avoidance mechanism to initially reduce the clock frequency of the target clock signal, i.e., to perform initial frequency reduction on the functional unit. If the early warning event is not eliminated after frequency reduction, the aforementioned system-level risk avoidance mechanism can perform a second level of risk avoidance, directly switching the clock signal of the functional unit to the basic clock signal with the lowest clock frequency, thereby ensuring the safe operation of the functional unit and further improving system stability.

[0139] Furthermore, combining Figure 3 As shown, the gating control terminal of the first gating unit 221 is connected to the unit-level configuration unit 222 and the early warning unit 224 respectively. In practical applications, both the control unit 10 and the early warning unit 224 can control the gating status of the first gating unit 221. The specific control process can be referred to the above content and will not be repeated here.

[0140] This application also provides a clock signal generation method for providing a clock signal to any functional unit in a microprocessor architecture. The clock signal generation method provided in this application is applied to the microprocessor architecture provided in the foregoing embodiments, i.e., implemented based on the microprocessor architecture provided in the foregoing embodiments, and is specifically executed by a control unit. Of course, in some cases, the clock signal generation method provided in this application can also be pre-stored as system firmware in the microprocessor architecture and executed by relevant control modules within the microprocessor architecture.

[0141] See Figure 4As shown, the clock signal generation method provided in this application embodiment may include the following steps.

[0142] S100 controls the basic clock unit in the clock signal source to generate the basic clock signal.

[0143] Based on the optional implementation of the basic clock unit provided in the foregoing embodiments, the control unit configures the second configuration information to the basic clock unit, and the basic clock unit generates a basic clock signal based on the obtained second configuration information and the reference clock signal. The specific generation process of the basic clock signal can be found in the relevant content of the foregoing embodiments, and will not be repeated here.

[0144] S110. Configure the first configuration information and the first strobe information to the frequency modulation clock unit in the clock signal source.

[0145] Based on the basic clock unit outputting basic clock signals to each initial signal generation unit in the frequency modulation clock unit, the control unit further configures the frequency modulation clock unit with first configuration information and first gating information. As can be seen from the above, the first configuration information can be the clock frequency corresponding to each initial signal generation unit. Of course, it can also be other information, which will not be repeated here. The first gating information is used to instruct the first gating unit to determine the target clock signal among each initial clock signal.

[0146] Based on the above, each initial signal generation unit in the frequency modulation clock unit generates its own corresponding initial clock signal according to its own clock frequency recorded in the first configuration information and the basic clock signal provided by the basic clock unit. The clock frequencies of each initial clock signal are independent of each other and are usually different frequencies.

[0147] Furthermore, the first gating unit in the frequency modulation clock unit takes the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal and outputs it to the functional unit connected to the clock signal source, so that the functional unit operates based on the obtained target clock signal. For example, the functional unit can be a processor core, and after obtaining the target clock signal output by the frequency modulation unit, the processor core operates under the target clock signal; or, for example, the functional unit can be a GPU core, and after obtaining the target clock signal output by the frequency modulation unit, the GPU core can execute a preset image processing task, etc.

[0148] In summary, the clock signal generation method provided in this application involves a control unit first controlling a basic clock unit to output a basic clock signal, and then configuring first configuration information and first strobe information to a frequency modulation clock unit. Each initial signal generation unit in the frequency modulation clock unit generates its own corresponding initial clock signal based on the first configuration information and the aforementioned basic clock signal. The first strobe unit outputs the initial clock signal generated by the initial signal generation unit indicated by the first strobe information as a target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. Compared with related technologies, the clock signal generation method provided in this application can select a clock signal that meets the frequency modulation requirements by configuring the first configuration information and the first strobe information, effectively simplifying the clock frequency adjustment process, improving the clock frequency adjustment efficiency, and meeting the needs of practical applications.

[0149] Furthermore, embodiments of this application provide another clock signal generation method, applied to a clock signal source including three initial signal generation units, namely a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit. Based on this, see [link to relevant documentation]. Figure 5 As shown, the clock signal generation method provided in this embodiment may include the following steps.

[0150] S200 controls the basic clock unit in the clock signal source to generate the basic clock signal.

[0151] In one optional implementation, the specific implementation process of S200 can be referred to Figure 4 The details of S100 in the illustrated embodiment will not be repeated here.

[0152] S210, respectively configure the first clock frequency corresponding to the first initial signal generation unit, the second clock frequency corresponding to the second initial signal generation unit, and the third clock frequency corresponding to the third initial signal generation unit.

[0153] As mentioned above, the first configuration information configured by the control unit may include the clock frequency corresponding to each initial signal generation unit. Based on this, when the frequency modulation clock unit includes three initial signal generation units, the first configuration information includes the first clock frequency corresponding to the first initial signal generation unit, the second clock frequency corresponding to the second initial signal generation unit, and the third clock frequency corresponding to the third initial signal generation unit.

[0154] It should be emphasized that in this embodiment, the first clock frequency is lower than the second clock frequency, and the second clock frequency is lower than the third clock frequency. In other words, the first clock frequency is the lowest and can be used as the emergency avoidance clock frequency. The second clock frequency is in the middle and can be used as the clock frequency when the functional unit is running normally. The third clock frequency is the highest and can be used when the functional unit is up-frequency processed to improve the operating performance of the functional unit.

[0155] In one optional implementation, the frequency difference between the first clock frequency and the second clock frequency, as well as the frequency difference between the second clock frequency and the third clock frequency, can both be set as preset frequency modulation step sizes during the adjustment of the functional unit's clock frequency. For example, if the preset frequency modulation step size is 50MHz, then the first clock frequency is 2700MHz, the second clock frequency is 2750MHz, and the third clock frequency is 2800MHz. Of course, the frequency differences between the aforementioned different clock frequencies can also be other values, and this application does not specifically limit them.

[0156] After the control unit completes the configuration of the first configuration information, the three initial signal generation units output the initial clock signal according to their respective clock frequencies.

[0157] S220. Configure the first strobe information according to the operating status of the functional unit.

[0158] Based on the aforementioned application scenarios with different clock frequencies, when a functional unit needs to operate at a lower frequency, the control unit configures a first gating configuration value to the first gating unit. This instructs the first gating unit to determine the initial clock signal generated by the first initial signal generation unit according to the first clock frequency as the target clock signal, and outputs the target clock signal to the functional unit. This enables the functional unit to be protected in emergency situations. For example, if a functional unit experiences a warning event such as insufficient timing margin, timing disorder, or excessively high operating temperature due to an excessively high clock frequency, the first initial signal generation unit can be gating to provide the functional unit with the target clock signal with the lowest clock frequency, thereby ensuring the safe operation of the functional unit.

[0159] When the functional unit is in normal operation, the control unit configures a second strobe configuration value to instruct the first strobe unit to determine the initial clock signal generated by the second initial signal generation unit according to the second clock frequency as the target clock signal. As mentioned above, the second clock frequency can be the clock frequency for safe and stable operation of the functional unit. Therefore, when the functional unit is in normal operation, the clock signal corresponding to the second clock frequency is output.

[0160] Correspondingly, when the timing margin of the functional unit is sufficient and its performance can be further improved, that is, when the functional unit needs to operate at a higher frequency, the control unit configures a third strobe configuration value to instruct the first strobe unit to determine the initial clock signal generated by the third initial signal generation unit according to the third clock frequency as the target clock signal, and outputs the target clock signal to increase the clock frequency corresponding to the functional unit.

[0161] Based on the foregoing, it can be understood that in practical applications, there is no specific requirement for the size relationship between the first strobe configuration value, the second strobe configuration value, and the third strobe configuration value; different configuration values ​​can be selected for the first strobe configuration value, the second strobe configuration value, and the third strobe configuration value.

[0162] Based on the above clock signal adjustment process, see [link to relevant documentation]. Figure 6 Where ADPLL_H represents the initial clock signal generated according to the third clock frequency, ADPLL_M represents the initial clock signal generated according to the second clock frequency, and ADPLL_L represents the initial clock signal generated according to the first clock frequency. In conjunction with the target clock signal switching process, under normal operation, the functional unit defaults to using the initial clock signal corresponding to ADPLL_M as the target clock signal. At time t4, frequency boosting begins, increasing the clock frequency by one level, and the initial clock signal corresponding to ADPLL_H is used as the target clock signal. At time t7, the frequency boosting operation begins to exit and return to the normal clock frequency. At time t9, a timing abnormality is detected, and the initial clock signal corresponding to ADPLL_L is used as the target clock signal to perform frequency reduction protection for the functional unit.

[0163] In summary, the clock signal generation method provided in this embodiment configures the clock frequency corresponding to each initial signal generation unit in a stepwise manner, that is, the first clock frequency is less than the second clock frequency, and the second clock frequency is less than the third clock frequency. This can provide three initial clock signals with different clock frequencies, forming a stepwise configuration of high, medium and low clock frequencies. By configuring the gating configuration value of the first gating information, the selection of the aforementioned three initial clock signals can be realized, thereby meeting the application requirements in different scenarios.

[0164] This application also provides another clock signal generation method, similarly applied to a clock signal source including three initial signal generation units. The frequency modulation clock unit of this clock signal source includes a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit. Based on this, see [link to relevant documentation]. Figure 7 As shown, the clock signal generation method provided in this embodiment may include the following steps.

[0165] S300 controls the basic clock unit in the clock signal source to generate the basic clock signal.

[0166] In one optional implementation, the specific implementation process of S300 can be referred to Figure 4 The details of S100 in the illustrated embodiment will not be repeated here.

[0167] S310, in response to the frequency upsampling command, configure the steady-state clock frequency corresponding to the second initial signal generation unit, and alternately increase the clock frequencies corresponding to the first initial signal generation unit and the third initial clock unit.

[0168] The clock signal generation method provided in this embodiment is mainly used to meet the frequency upscaling requirements of functional units. During actual operation, the system program or application program monitors parameters that may affect the performance of the functional units, such as load, timing margin, and operating temperature margin. If the system program determines that the functional unit meets the frequency upscaling requirements based on the aforementioned parameters, it can send an upscaling command to the control unit. The specific process for determining whether the functional unit meets the frequency upscaling requirements can be implemented with reference to relevant technologies; this application does not limit this process.

[0169] Of course, in some cases, the functional unit can also initiate the frequency increase request itself.

[0170] In response to the upsampling command, the control unit first configures the steady-state clock frequency corresponding to the second initial signal generation unit. This steady-state clock frequency is the clock frequency used when the functional unit is operating normally. Based on this, the initial clock signal generated by the second initial signal generation unit according to the steady-state clock frequency can ensure the stable operation of the functional unit.

[0171] It should be noted that since the functional unit can issue a frequency upsampling request, it indicates that the functional unit is in operation. In one optional implementation, the clock signal required for the current operation of the functional unit can be provided by another clock signal source. That is, the clock signal source provided in this embodiment is specifically used to respond to the frequency upsampling request. In another optional implementation, before performing this step, the control unit can first configure another set of first configuration information and first strobe information, and control the clock signal unit to provide a clock signal that meets the requirements for the operation of the functional unit. It can be understood that the clock frequency at this time can be the aforementioned steady-state clock frequency. That is, before responding to the frequency upsampling request of the functional unit, the control unit controls the clock signal source to output the target clock signal corresponding to the steady-state clock frequency, thereby ensuring the steady-state operation of the functional unit. It can also be understood that the process of configuring the steady-state clock frequency at this time can be a repetitive configuration operation, and the second initial signal generation unit can maintain the currently output clock frequency.

[0172] Furthermore, while maintaining the steady-state clock frequency corresponding to the second initial signal generation unit unchanged, the clock frequencies corresponding to the first initial signal generation unit and the third initial clock unit are alternately increased. For example, if the current clock frequency corresponding to the first initial signal generation unit is 2700MHz and the clock frequency corresponding to the third initial signal generation unit is 2750MHz, during the alternating increase, the clock frequency corresponding to the first initial signal generation unit is increased to 2800MHz and the clock frequency corresponding to the third initial signal generation unit is increased to 2850MHz. In the next round of adjustment, the clock frequency corresponding to the first initial signal generation unit is increased to 2850MHz and the clock frequency corresponding to the third initial signal generation unit is increased to 2900MHz, and so on, until the clock frequency corresponding to one of the initial signal generation units reaches the preset target frequency corresponding to the functional unit.

[0173] S320. Update the gating configuration value of the first gating unit so that the first gating unit determines the initial clock signal with the higher clock frequency among the first initial signal generation unit and the third initial clock unit as the target clock signal.

[0174] While alternately increasing the clock frequencies of the first initial signal generation unit and the third initial signal generation unit, the gating configuration value of the first gating unit needs to be updated synchronously so that the first gating unit uses the initial clock signal with the higher clock frequency among the first initial signal generation unit and the third initial clock unit as the target clock signal. In other words, in practical applications, this step is executed synchronously with the aforementioned S310. After completing the clock frequency configuration for any round, once the initial clock signal output by the initial signal generation unit stabilizes, the control unit configures the gating configuration value of the first gating unit to output the initial clock signal with the higher clock frequency among the first initial signal generation unit and the third initial clock unit as the target clock signal to the functional unit, thereby realizing the frequency upsampling processing of the functional unit.

[0175] Combination Figure 8As shown, ADPLL_H represents the initial clock signal output by the third initial signal generation unit, ADPLL_M represents the initial clock signal output by the second initial signal generation unit, and ADPLL_L represents the initial clock signal output by the first initial signal generation unit. From time t0 to t3, the second initial signal generation unit outputs the initial clock signal according to the steady-state clock frequency. The first gating unit outputs this initial clock signal as the target clock signal to the functional unit. Frequency boosting begins at time t3 and the first frequency boosting is completed at time t4. At this time, the initial clock signal output by the third initial signal generation unit is used as the target clock signal. Since the first and third initial signal generation units alternate frequency boosting, at time t5, the clock frequency of the initial clock signal output by the first initial signal generation unit is higher than the clock frequency of the initial clock signal output by the third initial signal generation unit. The first gating unit switches its output and outputs the initial clock signal output by the first initial signal generation unit as the target clock signal to the functional unit. This process repeats, with the first and third initial signal generation units alternately outputting target clock signals with continuously increasing clock frequencies to achieve the purpose of increasing the clock frequency of the functional unit. During this process, the second initial signal generation unit maintains a constant steady-state clock frequency.

[0176] Furthermore, Figure 8 The process of the first initial signal generation unit and the third initial signal generation unit alternately reducing the clock frequency until the clock signal output steady-state clock frequency is restored is also shown. That is, the control unit responds to the frequency reduction command of the functional unit and alternately reduces the clock frequency configured by the first initial signal generation unit and the third initial signal generation unit. Correspondingly, after each round of clock frequency reduction configuration operation is completed, the gating configuration value of the first gating unit is updated so that the first gating unit outputs the initial clock signal of the lower clock frequency of the first initial signal generation unit and the third initial clock unit as the target clock signal to the functional unit, thereby realizing the frequency reduction processing of the functional unit.

[0177] Furthermore, in practical applications, the initial clock signal output by the second initial signal generation unit according to the steady-state clock frequency can not only be used as the target clock signal during normal operation of the functional unit, but also as an emergency avoidance clock signal. Considering the working principle of the microprocessor architecture, under frequency ramping operation, warning events such as insufficient timing margin and excessively high operating temperature may occur. Therefore, if, during the process of ramping up the clock frequency of the functional unit as described above, the aforementioned warning event requiring a reduction in the functional unit's operating frequency occurs, a second gating configuration value can be directly configured to the first gating unit. This second gating configuration value instructs the first gating unit to determine the initial clock signal generated by the second initial signal generation unit according to the steady-state clock frequency as the target clock signal and output this target clock signal to the functional unit, thereby reducing the clock frequency of the functional unit immediately and ensuring the safe operation of the functional unit.

[0178] In summary, the clock signal generation method provided in this application involves a second initial signal generation unit providing an initial clock signal according to a steady-state clock frequency, and the first and third initial signal generation units alternately increasing the frequency to improve the frequency increase efficiency of the functional unit. When the functional unit needs to operate at a lower frequency, configuring the first gating unit to output the initial clock signal from the second initial signal generation unit as the target clock signal ensures the safe operation of the functional unit.

[0179] This application also provides another clock signal generation method, see [link to relevant documentation]. Figure 9 As shown, the clock signal generation method provided in this embodiment includes the following steps.

[0180] S400 controls the basic clock unit in the clock signal source to generate the basic clock signal.

[0181] In one optional implementation, the specific implementation process of S400 can be referred to Figure 4 The details of S100 in the illustrated embodiment will not be repeated here.

[0182] S410, simultaneously configure the clock frequency of other initial signal generation units besides the target initial signal generation unit.

[0183] As mentioned above, the frequency modulation clock unit of the clock signal source includes at least two initial signal generation units. In this embodiment, the initial signal generation unit that currently provides the target clock signal to the functional unit is designated as the target initial signal generation unit, and the initial signal generation units other than the target initial signal generation unit are uniformly defined as other initial signal generation units.

[0184] Based on the above premise, as an optional implementation, before executing the first preset configuration operation corresponding to S410-S420, the clock frequency of the target initial signal generation unit can be configured as the initial clock frequency. This initial clock frequency can be any clock frequency that allows the functional unit to operate safely. This application does not limit the specific value of the initial clock frequency. At the same time, the gating configuration value of the first gating unit is configured so that the first gating unit determines that the initial clock signal output by the target initial signal generation unit according to the initial clock frequency is the target clock signal, and then provides the target clock signal of the initial clock frequency to the functional unit, ensuring that the functional unit is in normal operating condition before the frequency adjustment process begins.

[0185] Furthermore, a preset frequency modulation step size and a preset target frequency are obtained. The preset frequency modulation step size refers to the change in clock frequency during each round of frequency adjustment. The preset target frequency is the final clock frequency that needs to be achieved during the frequency modulation process. In practical applications, the preset target frequency can be the highest clock frequency allowed by the functional unit, or any clock frequency below the highest clock frequency. This application does not limit the specific values ​​of the preset frequency modulation step size and the preset target frequency.

[0186] After determining the initial clock frequency, preset frequency modulation step size, and preset target frequency, multiple intermediate clock frequencies can be determined based on these parameters. This means determining the frequency points traversed during frequency adjustment, or the frequency change path. For example, if the initial clock frequency is 800MHz, the preset frequency modulation step size is 25MHz, and the preset target frequency is 950MHz, then the intermediate clock frequencies are 825MHz, 850MHz, 875MHz, 900MHz, and 925MHz. The corresponding complete frequency change paths are 800MHz, 825MHz, 850MHz, 875MHz, 900MHz, 925MHz, and 950MHz.

[0187] After determining each intermediate clock frequency and the corresponding frequency change path, the clock frequency of each other initial signal generation unit is configured simultaneously according to multiple intermediate clock frequencies. Each other initial signal generation unit corresponds to an intermediate clock frequency, and each other initial signal generation unit generates the corresponding initial clock signal according to its corresponding intermediate clock frequency.

[0188] Understandably, during any clock frequency configuration process, the number of intermediate clock frequencies configured depends on the number of other initial signal generation units. The more other initial signal generation units there are, the more intermediate clock frequencies can be configured in a single configuration process. Consequently, the number of configurations required to reach the preset target frequency is reduced. Of course, the more initial signal generation units there are, the larger the area occupied by the microprocessor architecture becomes, and the overall cost of the clock signal source also increases. Therefore, in practical applications, it is necessary to balance the relationship between the number of initial signal generation units and clock adjustment efficiency.

[0189] It is also understandable that for any initial signal generation unit, from the time it receives its own corresponding clock frequency to the time it stably outputs the initial clock signal according to the obtained clock frequency, a certain period of time is required. This period of time is the locking time of the initial signal generation unit. Assuming the locking time is t0, related technologies use the method of outputting the clock signals corresponding to each intermediate clock frequency one by one when adjusting the frequency. The total locking time required for M intermediate clock frequencies is M times t0, i.e., Mt0. Compared with related technologies, this embodiment configures the intermediate clock frequencies of multiple other initial signal generation units at the same time. Assuming there are a total of N other initial signal generation units, the overall locking time can be shortened to Mt0 / N. Obviously, the clock signal generation method provided by this application embodiment can effectively improve the efficiency of clock frequency adjustment.

[0190] It should be noted that the clock signal generation method provided in this embodiment can be used to respond to a frequency up request to increase the clock frequency of the functional unit, or it can be used to respond to a frequency down request to decrease the clock frequency of the functional unit. The difference in practical application is that the frequency up process needs to monitor whether the functional unit meets the frequency up conditions, while the frequency down process can appropriately ignore this process.

[0191] Specifically, when responding to a frequency upsampling request, it is necessary to obtain the status information of the functional unit, such as the clock frequency range supported by the current operating voltage (which can be determined based on the voltage / frequency table provided by the chip manufacturer), the current operating temperature, etc. Based on the obtained status information, it is determined whether the frequency upsampling conditions are met. If the conditions are met, the clock frequencies of other initial signal generation units can be configured. If the conditions are not met, corresponding measures are taken, such as increasing the operating voltage of the functional unit or improving heat dissipation efficiency. Under the premise that the frequency upsampling conditions are met, the clock frequency configuration process is executed. The specific judgment process for whether a functional unit meets the frequency upsampling conditions can be found in relevant technical implementations and will not be detailed here.

[0192] It should be noted that the process of determining whether the above-mentioned functional unit meets the upsampling conditions can be carried out synchronously with the process of configuring the clock frequency of each other initial signal generation unit (because the final output is determined by the first gating unit), which helps to improve the efficiency of clock frequency adjustment.

[0193] When responding to a frequency reduction request from a functional unit, since the next clock frequency will definitely be lower than the clock frequency of the clock signal currently used by the functional unit, the frequency reduction process will not cause timing disorder in the functional unit. Therefore, the frequency reduction operation can be performed directly.

[0194] S420. After each of the other initial signal generation units outputs an initial clock signal according to the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially determines the initial clock signal of each of the other initial signal generation units as the target clock signal according to a preset cyclic order.

[0195] For functional units, when adjusting the clock frequency, excessive fluctuations in the clock frequency should be avoided as much as possible, especially during the up-frequency process. Excessive changes in the clock frequency can easily lead to timing chaos. Based on this, after each of the other initial signal generation units outputs the initial clock signal according to the corresponding clock frequency, the gating configuration value of the first gating unit can be updated. This allows the first gating unit to sequentially determine the initial clock signals of each of the other initial signal generation units as the target clock signals according to a preset cyclic order. That is, the first gating unit sequentially uses the initial clock signals of each of the other initial signal generation units as the target clock signals in the order of clock frequency from low to high (corresponding to the up-frequency process) or from high to low (corresponding to the down-frequency process) and outputs them to the functional unit. This ensures that the clock frequency of the functional unit changes in a stepwise manner according to the aforementioned preset frequency modulation step size, without excessive fluctuations.

[0196] It is understandable that, in this process, the initial signal generation unit that outputs the target clock signal last will serve as the target initial signal generation unit in the next round, that is, the initial signal generation unit that currently provides clock signals to the functional unit.

[0197] S430: Determine whether the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency. If yes, execute S440; otherwise, return to execute S410.

[0198] After completing the aforementioned frequency adjustment process, it is determined whether the clock frequency of the target clock signal output to the functional unit has reached the preset target frequency. If it has not reached the target frequency, the process returns to step S410, thus forming a cyclical clock frequency adjustment mode. If the preset target frequency is reached, step S440 is executed.

[0199] S440, Exit.

[0200] When the clock frequency of the clock signal output from the frequency modulation clock unit to the functional unit reaches the preset target frequency, the current frequency adjustment process is exited.

[0201] In summary, the clock signal generation method provided in this application provides initial clock signals with different clock frequencies as target clock signals by sequentially controlling each initial clock signal to cyclically provide initial clock signals with different clock frequencies. Each initial clock generation unit forms a ring architecture, and the clock frequencies of other initial signal generation units besides the target initial signal generation unit are configured. This can effectively shorten the overall duration of the initial signal generation unit's stable output of the initial clock signal and effectively improve the adjustment efficiency of the clock signal.

[0202] See Figure 10 The diagram shown illustrates the switching effect of the clock signal during the frequency upsampling process. Taking a clock signal source consisting of three initial signal generation units as an example, ADPLL_H represents the initial clock signal output by the third initial signal generation unit, ADPLL_M represents the initial clock signal output by the second initial signal generation unit, and ADPLL_L represents the initial clock signal output by the first initial signal generation unit. The first adjustment begins at time t3, and continuous frequency upsampling adjustment is performed from time t4 to t8. The preset target frequency is reached at time t8, the frequency upsampling process stops, and the system enters a stable operating state at time t8.

[0203] It should be noted that, based on the frequency adjustment process described above, in any round of frequency upsampling, the clock frequency of the target initial signal generation unit remains unchanged until the first gating unit switches over in the next round. The clock frequencies of other initial signal generation units can be adjusted to be higher than the clock frequency of the target initial signal generation unit. Therefore, the initial clock signal provided by the target initial signal generation unit can be used as the clock signal during emergency avoidance. That is, during the frequency upsampling process, if a warning event occurs in the functional unit, the first gating unit can be directly controlled to output the initial clock signal of the target initial signal generation unit to ensure the safe operation of the functional unit.

[0204] Accordingly, see Figure 11 The diagram shown illustrates the switching effect of the clock signal during the frequency reduction process. Taking three initial signal generation units as an example, the first frequency reduction operation begins at time t3, and continuous frequency reduction adjustment is performed from time t4 to t8. The preset target frequency is reached at time t8, the frequency reduction process stops, and the system enters a stable operating state at time t8.

[0205] This application also provides another clock signal generation method, which is also applied to a clock signal source including three initial signal generation units. Specifically, the frequency-modulated clock unit of the clock signal source includes a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit. Based on this, see [link to relevant documentation]. Figure 12As shown, the clock signal generation method provided in this embodiment may include the following steps.

[0206] S500 controls the basic clock unit in the clock signal source to generate the basic clock signal.

[0207] In one optional implementation, the specific implementation process of S500 can be referred to Figure 4 The details of S100 in the illustrated embodiment will not be repeated here.

[0208] After the basic clock unit outputs the basic clock signal, the subsequent second preset configuration operation can be executed until the exit condition is met. The second preset configuration operation mainly includes S510 and S520.

[0209] S510, simultaneously configure the first clock frequency of the first initial signal generation unit and the second clock frequency of the second initial signal generation unit.

[0210] In the aforementioned embodiments, the clock frequency difference between any two adjacent initial clock signals in the output sequence is a preset frequency modulation step size. Considering the working characteristics of the functional unit, if the preset frequency modulation step size is set too large, it can easily cause voltage jitter, and in severe cases, it may even cause abnormal operation of the functional unit. Therefore, it is desirable for the frequency adjustment process of the functional unit to be as smooth as possible.

[0211] Based on the above premises, in this embodiment, the difference between the second clock frequency and the first clock frequency is half of a preset frequency modulation step size. The initial clock signal of the third initial signal generation unit is used as the current target clock signal, and the difference between the second clock frequency and the clock frequency of the current target clock signal is the preset frequency modulation step size. In other words, under the premise that the initial clock signal output by the third initial signal generation unit is used as the current target clock signal, the clock frequencies of the first initial signal generation unit and the second initial signal generation unit are configured. The difference between the second clock frequency of the second initial signal generation unit and the clock frequency of the current target clock signal is the preset frequency modulation step size, and the first clock frequency of the first initial signal generation unit is used as the transition clock frequency between the two. The difference between the first clock frequency and the second clock frequency is half of the preset frequency modulation step size. For example, the clock frequency of the initial clock signal of the third initial signal generation unit is 2800MHz, and the preset frequency modulation step size is 50MHz. Based on this, the second clock frequency is 2850MHz, and the first clock frequency is 2825MHz.

[0212] As for the process of determining the intermediate clock frequencies during the adjustment of the clock frequency of a functional unit from the initial clock frequency to the preset target frequency, please refer to the aforementioned process. Figure 9 The relevant content of the illustrated embodiment will not be repeated here.

[0213] S520. After the first initial signal generation unit and the second initial signal generation unit output the initial clock signal according to the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially uses the initial clock signals of the first initial signal generation unit and the second initial signal generation unit as the target clock signal.

[0214] After configuring the first clock frequency and the second clock frequency, the first initial signal generation unit and the second initial signal generation unit can generate corresponding initial clock signals according to their respective clock frequencies. Based on this, the gating configuration value of the first gating unit is further updated, controlling the first gating unit to sequentially use the initial clock signals of the first initial signal generation unit and the second initial signal generation unit as target clock signals, and output them to the functional units respectively. As can be seen from the foregoing, by introducing a transition clock frequency based on the preset frequency modulation step size, the frequency modulation process becomes smoother, effectively overcoming the problems caused by the aforementioned excessively large preset frequency modulation step size.

[0215] It is understandable that after this step, the target clock signal finally output to the functional unit is provided by the second initial signal generation unit. When the adjustment is performed in the next round, the first initial signal generation unit is still configured with a transition clock frequency. The clock frequency difference between the second initial signal generation unit and the third initial signal generation unit is a preset frequency modulation step size. The first initial signal generation unit plays the role of smoothing the frequency modulation process.

[0216] S530: Determine whether the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency. If not, return to execute S510; if yes, execute S540.

[0217] After completing the second preset configuration operation, determine whether the clock frequency of the target clock signal output to the functional unit has reached the preset target frequency. If it has reached the preset target frequency, execute S540. Otherwise, if it has not reached the preset target frequency, return to execute S510.

[0218] S540, Exit.

[0219] When the clock frequency of the clock signal output from the frequency modulation clock unit to the functional unit reaches the preset target frequency, the current frequency adjustment process is exited.

[0220] In summary, the clock signal generation method provided in this application, based on a preset frequency modulation step size, sets a transition clock frequency. During the transition from the current clock frequency to the next clock frequency, the frequency is first adjusted to the transition clock frequency, and then adjusted from the transition clock frequency to the next clock frequency. This effectively halve the preset frequency modulation step size, improving the smoothness of the frequency adjustment process and ensuring the stability of the functional units and the microprocessor architecture. Furthermore, configuring two clock frequencies simultaneously can shorten the clock signal lock-in time and improve the efficiency of clock adjustment.

[0221] Furthermore, referring to the foregoing embodiments, the clock signal generation method provided in this embodiment can be used to increase the clock frequency of the functional unit in response to a frequency up request, or to decrease the clock frequency of the functional unit in response to a frequency down request.

[0222] See Figure 13 The diagram shows the switching effect of the clock signal during the frequency upsampling process. ADPLL_H represents the initial clock signal output by the third initial signal generation unit, ADPLL_M represents the initial clock signal output by the first initial signal generation unit, and ADPLL_L represents the initial clock signal output by the second initial signal generation unit. The initial clock signal output by the third initial signal generation unit is used as the target clock signal from time t0 to t3. The first adjustment begins at time t3. From time t4 to t9, the frequency is continuously adjusted according to half of the preset frequency adjustment step size. The preset target frequency is reached at time t9, the frequency upsampling process stops, and the system enters a stable operating state at time t9.

[0223] Accordingly, see Figure 14 The diagram showing the switching effect of the clock signal during the frequency reduction process illustrates that, taking the three initial signal generation units as an example, the first frequency reduction operation begins at time t3. From time t4 to t9, the frequency is continuously adjusted according to half of the preset frequency adjustment step size. At time t9, the preset target frequency is reached, the frequency reduction process stops, and the system enters a stable operating state at time t9.

[0224] Referring to the foregoing, the frequency modulation clock unit of the clock signal source provided in this application is further equipped with a second gating unit, which receives the target clock signal and the basic clock signal output by the first gating unit. Since the clock frequency of the initial clock signal output by each initial signal generation unit is higher than the clock frequency of the basic clock signal, the basic clock signal can be used as the clock signal for emergency avoidance of the functional unit. The basic clock signal is a clock signal that can ensure the safe and stable operation of the functional unit in emergency situations. Here, the emergency situation mainly refers to situations that may affect the reliable operation of the microprocessor architecture during its operation, such as insufficient timing margin or excessively high operating temperature of the microprocessor architecture, which will not be detailed here.

[0225] Based on the above, the control unit can further configure second gating information, instructing the second gating unit to output a base clock signal to the functional unit or to output a target clock signal determined by the first gating unit. In an optional implementation, the second gating information includes an operating configuration value or a risk avoidance configuration value. Specifically, when the timing margin of the current clock signal of the functional unit is insufficient and it needs to operate at a reduced frequency for emergency risk avoidance, the second gating information is the aforementioned risk avoidance configuration value. The second gating unit responds to the risk avoidance configuration value by outputting a base clock signal to ensure that the functional unit can operate safely without timing chaos due to insufficient timing margin. Correspondingly, when the functional unit is operating normally, the second gating information is the aforementioned operating configuration value. The second gating unit responds to the operating configuration value by outputting a target clock signal to the functional unit to ensure that the functional unit operates normally.

[0226] It should be noted that the method provided in this embodiment can be used in combination with the signal generation method provided in any of the foregoing embodiments. In case of an abnormality, the basic clock signal can be output to the functional unit by configuring the second strobe information, thereby ensuring the safe operation of the functional unit. Under normal circumstances, the target clock signal is output to the functional unit to ensure the stable operation of the functional unit.

[0227] Furthermore, in some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions for implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors execute the clock signal generation method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0228] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the clock signal generation methods according to various embodiments of this application as described above.

[0229] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0230] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0231] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0232] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0233] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0234] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0235] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A microprocessor architecture, characterized in that, include: At least one functional unit, said functional unit being used to implement a preset function of the microprocessor architecture; At least one clock signal source, each of the clock signal sources being connected to one or more of the functional units; The control unit is used to configure the first configuration information and the first strobe information; The clock signal source includes: The basic clock unit is used to generate the basic clock signal; The frequency modulation clock unit is connected to both the basic clock unit and the functional unit. The frequency modulation clock unit includes: At least two parallel initial signal generation units, each of the initial signal generation units being used to generate its own corresponding initial clock signal based on the first configuration information and the basic clock signal; The first gating unit is used to output the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal.

2. The microprocessor architecture according to claim 1, characterized in that, The control unit is also configured to configure second configuration information to the basic clock unit; The basic clock unit includes: A system-level configuration unit is used to store the second configuration information; A basic signal generation unit receives a reference clock signal and generates the basic clock signal according to the second configuration information and the reference clock signal.

3. The microprocessor architecture according to claim 2, characterized in that, The basic signal generation unit includes any one of phase-locked loop (PLL), delay phase-locked loop (DLL), digital phase-locked loop (DPLL), and all-digital phase-locked loop (ADPLL).

4. The microprocessor architecture according to claim 2, characterized in that, The frequency modulation clock unit also includes: The unit-level configuration unit is connected to each of the initial signal generation units, the control unit, and the first gating unit, respectively. The unit-level configuration unit is used to store the first configuration information and the first gating information.

5. The microprocessor architecture according to claim 2, characterized in that, The frequency modulation clock unit also includes: The second gating unit has its input terminals connected to both the first gating unit and the basic signal generation unit, and its output terminal connected to the functional unit. The control unit is also used to configure second strobe information; The second gating unit is used to output the target clock signal or the base clock signal according to the second gating information.

6. The microprocessor architecture according to claim 5, characterized in that, The system-level configuration unit is also used to store the second strobe information.

7. The microprocessor architecture according to claim 1, characterized in that, The frequency modulation clock unit also includes: The early warning unit, connected to the first gating unit, is used to output a preset gating signal in response to an early warning event of the functional unit; The first gating unit is further configured to: in response to the preset gating signal, determine the initial clock signal with the lowest clock frequency among the initial clock signals as the target clock signal.

8. The microprocessor architecture according to any one of claims 1 to 7, characterized in that, The initial signal generation unit includes any one of phase-locked loop (PLL), delay phase-locked loop (DLL), digital phase-locked loop (DPLL), and all-digital phase-locked loop (ADPLL).

9. A method for generating a clock signal, characterized in that, Applied to a microprocessor architecture as described in any one of claims 1 to 8, the microprocessor architecture including a control unit, a clock signal source, and functional units for implementing preset functions of the microprocessor architecture, the method includes the following steps performed by the control unit: The basic clock unit in the clock signal source is controlled to generate a basic clock signal; Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source; The frequency modulation clock unit includes a first gating unit and at least two parallel initial signal generation units, wherein, Each of the initial signal generation units is used to generate its own corresponding initial clock signal based on the first configuration information and the basic clock signal; The first gating unit is used to output the initial clock signal generated by the initial signal generation unit indicated by the first gating information as the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal.

10. The clock signal generation method according to claim 9, characterized in that, The at least two parallel initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit; Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including: The first clock frequency corresponding to the first initial signal generation unit, the second clock frequency corresponding to the second initial signal generation unit, and the third clock frequency corresponding to the third initial signal generation unit are respectively configured, wherein the first clock frequency is less than the second clock frequency, and the second clock frequency is less than the third clock frequency. In addition, the first strobe information is configured according to the operating status of the functional unit.

11. The clock signal generation method according to claim 10, characterized in that, The configuration of the first strobe information based on the operating status of the functional unit includes: When a functional unit needs to operate at a reduced frequency, a first strobe configuration value is configured. The first strobe configuration value is used to instruct the first strobe unit to determine the initial clock signal generated by the first initial signal generation unit according to the first clock frequency as the target clock signal. When the functional unit is in normal operation, a second strobe configuration value is configured. The second strobe configuration value is used to instruct the first strobe unit to determine the initial clock signal generated by the second initial signal generation unit according to the second clock frequency as the target clock signal. When a functional unit needs to operate at an increased frequency, a third strobe configuration value is configured. The third strobe configuration value is used to instruct the first strobe unit to determine that the initial clock signal generated by the third initial signal generation unit according to the third clock frequency is the target clock signal.

12. The clock signal generation method according to claim 9, characterized in that, The at least two parallel initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit; Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including: When a functional unit needs to operate at a higher frequency, the following operations should be performed: Configure the steady-state clock frequency corresponding to the second initial signal generation unit, wherein the steady-state clock frequency is the clock frequency used when the functional unit is operating normally; The clock frequencies corresponding to the first initial signal generation unit and the third initial clock unit are alternately increased, and the gating configuration value of the first gating unit is updated, so that the first gating unit determines the initial clock signal of the higher clock frequency among the first initial signal generation unit and the third initial clock unit as the target clock signal.

13. The clock signal generation method according to claim 12, characterized in that, Configuring first strobe information to the frequency modulation clock unit in the clock signal source further includes: When the functional unit needs to operate at a reduced frequency or is in normal operating condition, the strobe configuration value is configured as the second strobe configuration value. The second strobe configuration value is used to instruct the first strobe unit to determine that the initial clock signal generated by the second initial signal generation unit according to the steady-state clock frequency is the target clock signal.

14. The clock signal generation method according to claim 9, characterized in that, Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including: Repeat the first preset configuration operation until the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency; The first preset configuration operation includes: Simultaneously configure the clock frequency of other initial signal generation units besides the target initial signal generation unit, wherein the target initial signal generation unit is the initial signal generation unit currently providing the target clock signal; Furthermore, after each of the other initial signal generation units outputs an initial clock signal at the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially determines the initial clock signal of each of the other initial signal generation units as the target clock signal according to a preset cyclic order.

15. The clock signal generation method according to claim 14, characterized in that, The simultaneous configuration of the clock frequencies of other initial signal generation units besides the target initial signal generation unit includes: Obtain the initial clock frequency, the preset frequency modulation step size, and the preset target frequency; Based on the initial clock frequency, the preset frequency modulation step size, and the preset target frequency, a plurality of intermediate clock frequencies are determined. The clock frequencies of each of the other initial signal generation units are configured simultaneously according to the plurality of intermediate clock frequencies, so that each of the other initial signal generation units corresponds to an intermediate clock frequency.

16. The clock signal generation method according to claim 9, characterized in that, The at least two parallel initial signal generation units include: a first initial signal generation unit, a second initial signal generation unit, and a third initial signal generation unit; Configure first configuration information and first strobe information to the frequency modulation clock unit in the clock signal source, including: Repeat the second preset configuration operation until the clock frequency of the target clock signal output to the functional unit reaches the preset target frequency; The second preset configuration operation includes: Simultaneously, the first clock frequency of the first initial signal generation unit and the second clock frequency of the second initial signal generation unit are configured, the difference between the second clock frequency and the first clock frequency is half of the preset frequency modulation step size, and the initial clock signal of the third initial signal generation unit is used as the current target clock signal, and the difference between the second clock frequency and the clock frequency of the current target clock signal is the preset frequency modulation step size. Furthermore, after the first initial signal generation unit and the second initial signal generation unit output the initial clock signal according to the corresponding clock frequency, the gating configuration value of the first gating unit is updated so that the first gating unit sequentially uses the initial clock signals of the first initial signal generation unit and the second initial signal generation unit as the target clock signal.

17. The clock signal generation method according to any one of claims 9 to 16, characterized in that, The frequency modulation clock unit further includes a second gating unit, and the method further includes: Configure a second strobe information, which is used to instruct the second strobe unit to output the target clock signal or the base clock signal.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the clock signal generation method as described in any one of claims 9 to 17.

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