Nonlinear Distortion Compensation System for Wireless Power Amplifiers Based on Harmonic Analysis

Abstract

Digital predistortion systems typically aim to reduce the effects of nonlinear responses of radio power amplifiers in order to improve the spectral performance of wireless communication networks. The present invention relates to a system with improved robustness and agility. Rather than analyzing the ongoing error between the intended and actual amplifier output in the background during normal operation, or performing iterative adaptation, the amplifier's response is rapidly probed in the foreground by applying sinusoidal tones with variable frequency and amplitude according to a predetermined sequence. Harmonics generated due to the amplifier's nonlinear response are extracted from its output signal. By establishing an approximate correspondence between their amplitudes and individual parameters of an algebraic relationship, the present invention allows for direct calculation of said parameters to compensate for the amplifier's nonlinear response in the appropriate algebraic relationship. The possibility of ongoing adjustment of the parameters based on additional transducers is also described.

Description

[Technical Field]

[0001] The present invention relates to the field of so-called "digital predistortion systems", i.e. systems suitable for preprocessing baseband signals to be transmitted after amplification by a radio amplifier, distorting the signals in such a way as to at least partially compensate for the amplifier's nonlinear distortion (e.g. gain compression), thereby improving the fidelity of the radio transmission.

[0002] This type of system is frequently used to improve the performance of wireless transmission networks and reduce the requirements placed on the performance of radio amplifiers. In particular, digital predistortion systems make it possible to overcome the non-ideal behavior of a wide range of amplifiers, resulting in a significant reduction in the cost and power required for a given transmission application.

[0003] This type of system is also used to improve the dynamic performance of amplifiers driving loads other than antennas, such as long cable connections. [Background technology]

[0004] Known digital predistortion systems first include one or more means for evaluating an algebraic relation (usually a polynomial). When the parameters of this relation are set to appropriate values ​​and applied to a modulated signal prior to input to a power amplifier in a transmitter, the algebraic relation can at least partially compensate for the nonlinear distortion introduced by the amplifier. The parameter values ​​are often determined and iteratively adjusted based on an error signal whose amplitude should be minimized toward zero, typically obtained by calculating the difference between the signal output by the amplifier after proper demodulation and the original signal. Continuous adjustment of the parameters is performed using an optimization algorithm that, under normal conditions, tracks the amplifier's behavior and compensates for its nonideal characteristics. This approach (known as "adaptive digital predistortion") is common in the presence of amplifiers whose characteristics tend to change as a function of previous inputs (known as the "memory effect"), but is also widely applied to more recent types of amplifiers whose output can be more closely approximated as an instantaneous function of the input.

[0005] Known digital predistortion systems rely on the availability of an accurate continuous representation of the amplifier's output, since even minimal external interference can lead to large parameter estimation errors or, even worse, the creation of uncontrollable oscillations. This is a significant drawback, since next-generation communication systems will require higher carrier frequencies and denser transmitter arrays, which will increase the contamination between signals belonging to adjacent channels in the array, inevitably introducing instabilities in the parameter adjustment process. Objective of the Invention

[0006] The object of the present invention is to overcome the aforementioned drawbacks by presenting a nonlinear distortion compensation system which, by its operating principle, is more robust and self-contained than existing systems of the same type.

[0007] The object of the present invention is a digital predistortion system comprising: first means for obtaining (preferably from a first-in, first-out buffer memory, preferably connected to another device) a first baseband signal comprising digital values ​​representing data to be transmitted; first means for evaluating an algebraic expression (preferably comprising a memoryless polynomial) from said first baseband signal given a set of parameter values ​​(preferably comprising coefficients of a memoryless polynomial); a first memory array (preferably consisting of a static random access memory) suitable for storing values ​​of said parameters (supplied to said first evaluation means); generating means (preferably consisting of an analog frequency synthesizer combined with a variable gain amplifier and analog switches, or a digital-to-analog converter for direct radio frequency synthesis combined with a digital signal synthesizer and a digital multiplexer switch, such as can be found for example in the type ZU48DR of the company Xilinx) for generating from a value determined by evaluating said algebraic expression or according to a sine wave having a controllable amplitude and frequency determined by a corresponding first digital value upon assertion of a first logic signal; · Local oscillator means for providing a carrier signal having a known frequency (e.g., Analog Devices ADF5356); first modulation means (preferably consisting of an upconverter circuit manufactured by Analog Devices, e.g. type ADMV1013) for obtaining a higher frequency analog signal from the analog signal (provided by the generating means) by mixing the analog signal (provided by the generating means) with the carrier signal (provided by the local oscillator means); first radio power amplification means for the high frequency analog signal emitted by the first modulation means (preferably consisting of a radio power amplifier realized using complementary metal oxide semiconductor technology, such as for example the SUMMIT 3741 type from MixComm); means (preferably consisting of a power divider, for example of type EP2KA+ manufactured by Mini-Circuits) for extracting a portion of the signal radiated by the first radio power amplifier before it reaches a first load (preferably consisting of a transmitting antenna connected by a suitable matching circuit and an auxiliary circuit); first demodulation means, preferably consisting of a downconverter circuit such as the type ADMV1014 manufactured by Analog Devices, for obtaining a lower frequency analog signal from the signal portion emitted by the extraction means by mixing the signal portion emitted by the extraction means with the carrier signal emitted by the oscillation means; · Means for measuring spectral amplitudes at selected frequencies determined by corresponding second digital values ​​from the low frequency analog signal provided by the demodulation means.

[0008] For convenience, in this specification and the following description, the expressions "parameter value" and "spectral amplitude" refer to complex as well as real numbers, and are therefore suitable for representing phase as well as magnitude and their relationships.

[0009] According to the present invention, the digital predistortion system also includes: a second memory array (preferably consisting of a static random access memory) suitable for storing the spectral amplitude values ​​emitted by the measurement means; the control means is adapted to control the process of measuring the nonlinear distortion introduced by the first radio power amplifier by, upon assertion of the second logic signal, providing via corresponding first and second digital values ​​the amplitude and frequency settings of the analog signal (emitted by the generating means for which the first logic signal is asserted), while storing the spectral amplitude (emitted by the measuring means) in the second memory array, and finally asserting a third logic signal when the measurement is completed. first calculation means for calculating the value of the parameter to be supplied to the first evaluation means from the spectral amplitudes stored in a second other memory array, the first calculation means being adapted to, when the third logic signal is asserted, determine, based on a number of measurements of the spectral amplitude, a value to which the parameter should be set so that the output of the first radio power amplifier has as linear a relationship as possible to the first baseband signal appearing after being modulated to a higher frequency by mixing with the carrier signal radiated by the local oscillator means, i.e., so as to compensate as accurately as possible for non-linear distortion introduced by the first radio power amplifier.

[0010] Established theorems related to Fourier series expansions show that inputting a sinusoidal function as a variable into a nonlinear algebraic equation consisting of polynomials will produce odd and even harmonics whose amplitude and phase can be analytically derived and numerically calculated. The same is true if a sinusoidal wave is treated as a baseband signal and modulated to a higher frequency determined by a carrier signal before inputting the equation. Thus, a relationship exists between the parameter values ​​belonging to the equation and the harmonics it generates in response to a given sinusoidal input. Advantageously for the present application, if the equation is solely a function of the instantaneous value of the sinusoidal function (e.g., composed of so-called memoryless polynomials) and evaluates to a value that monotonically increases with respect to the input, the relationship is virtually unambiguous (T.W. Korner, Fourier Analysis, Cambridge University Press, Cambridge UK, 2022).

[0011] Incidentally, the nonlinear response of wireless power amplifiers realized using complementary metal-oxide semiconductor (CMOS) technology can be expressed as an algebraic equation consisting of fourth-order memoryless polynomials with coefficients such that the output amplitude increases monotonically with respect to the input amplitude (RG Saez, NM Marques, LDMOS versus GaN RF Power Amplifier Comparison Based on the Computing Complexity Needed to Linearize the Output, Electronics 2019; 8(11), 1260; S. Mariappan, J. Rajendran, H. Ramiah, NM Noh, AA Manaf, The Evolution of Integrated CMOS Power Amplifiers for Next Generation Mobile Wireless Transceivers, J Circuits Syst Comput 2019; 29(07), 2030007).

[0012] Numerous numerical methods are known for representing algebraic expressions, such as memoryless polynomials and their inverses, in approximate form. For example, as long as a training set is available that contains cases covering a sufficiently large number of possible combinations of inputs and coefficient values, it is possible to train an artificial neural network, such as one with a multilayer perceptron topology, to calculate the coefficient values ​​of a memoryless polynomial based on a large number of inputs and the values ​​(outputs) taken by the network. The accuracy of the calculation depends on the number and distribution of these input-output combinations (K. Hornik, M. Stinchcombe, H. White, Multilayer feedforward networks are universal approximators, Neural Netw 1989; 2(5), 359-366; S. Geva, J. Sitte, A constructive method for multivariate function approximation by larger perceptrons, IEEE Trans Neural Netw 1992; 3(4), 621-624). Thus, it is possible to train an artificial neural network, such as one having a multilayer perceptron topology, to calculate the coefficient values ​​of a memoryless polynomial representing the nonlinear response of a wireless power amplifier implemented using complementary metal-oxide semiconductor (CMOS) technology based on measuring the harmonics generated by the wireless power amplifier in response to a large number of sinusoidal inputs.

[0013] Although memoryless polynomials do not have exact inverses except in special cases, it is possible to calculate approximate inverses consisting of higher-order memoryless polynomials in limited domains (M.F. Gonzalez-Cardel, R. Diaz-Uribe, An analysis on the inversion of polynomials, Rev. Mex. de Fis. 2006; 2, 163-171). Advantageously, it has been shown that an artificial neural network, such as one with a multilayer perceptron topology, can be trained to directly calculate the coefficient values ​​of a memoryless polynomial representing the approximate inverse of the nonlinear response of a wireless power amplifier implemented using complementary metal-oxide-silicon (CMOS) technology based on the harmonics generated by the same in response to a large number of sinusoidal inputs. Therefore, when the memoryless polynomial representing the approximate inverse is applied to the wireless power amplifier after appropriate modulation, the output of the wireless power amplifier will be more linearly related to the signal than if the signal were directly input to the wireless power amplifier.

[0014] Artificial neural networks with a multilayer perceptron topology are practically known. More specifically, and advantageously for the present application, such networks can be implemented directly and efficiently in hardware by combining a memory array for storing the corresponding coefficients and offset values, multipliers, adders, and a means for evaluating the activation functions (P. Lee, I. Lazzizzera, A. Zorat, A. Sartori, G. Tecchiolli, "Advances in the design of the TOTEM neurochip", Nucl Instrum Methods Phys Res B 1997; 389(1), 134-137, N. Nedjah, R. Martins da Silva, L. de Macedo Mourelle). Compact and efficient hardware implementation of an artificial neural network with a customized topology. Expert Syst Appl 2012; 39(10), 9191-9206). However, to our knowledge, existing digital predistortion systems do not measure the harmonics generated by a wireless power amplifier in response to a large number of sinusoidal inputs and process the resulting measurements with an artificial neural network to calculate parameter values ​​suitable for compensating for the nonlinear distortion introduced by the wireless power amplifier. Instead, they primarily rely on continuous or iterative calculations of the difference between the signal output by the wireless power amplifier, appropriately demodulated and scaled, and the original signal, implementing a feedback loop that can become unstable in the presence of external interference (L. Guan and A. Zhu, Green Communications: Digital Predistortion for Wideband RF Power Amplifiers, IEEE Microw Mag, 15(7), 84-99).The present invention addresses these shortcomings by describing a system for measuring the nonlinear distortion introduced by a radio power amplifier and performing subsequent calculations not continuously in the background (i.e., without interrupting the normal transmission of baseband signals), but rather in the foreground (i.e., without interrupting the normal transmission of baseband signals) in response to the assertion of an externally supplied logic signal, only once for a short period of time, thereby ensuring that such measurements can be performed in the absence of sources of interference, such as the simultaneous operation of other transmitters.

[0015] For example, US Patent No. 7,333,559 B2 describes a digital predistortion device for compensating for the nonlinearity of a wideband power amplifier. The invention is based on a closed-loop arrangement of two predistortion devices exchanging feedback and updating information obtained from continuous analysis of the input and output signals. The related adaptation method requires the application of a signal containing one or more sinusoids, but does not mention measuring the harmonics generated thereby. Instead, a fundamentally different approach is proposed, using a secant algorithm and normalized least mean squares adaptation.

[0016] Similarly, US 8,805,304 B2 describes a linearizer based on analyzing the signal output by an error monitor receiver connected to the output of a wireless power amplifier. There is no mention of measuring the harmonics generated by the wireless power amplifier. Instead, the linearizer proposes minimizing the mean square error by iterative adjustment.

[0017] Furthermore, US 10,469,109 B2 describes a predistortion system based on the operation of multiple processing systems, in which separate receiving devices provide feedback to signals received from multiple transmitters, allowing for adjustment of the same predistortion coefficients. A calibration procedure applying multiple phase shift settings is described. In the invention, a training processor cycles through different sets of predistortion coefficients, ultimately comparing the composite received signal with a test signal transmitted by the array to select the one with the lowest measured distortion. There is no mention of measuring the harmonics emitted by individual transmitters and using the measurements as a basis for directly calculating the predistortion coefficients to be applied to each transmitter.

[0018] Furthermore, EP 1 205 024 B1 describes a process for determining predistortion parameters based on a system identification approach, in which a stimulus signal is continuously and repeatedly applied during a model adaptation process, which is also based on determining an error signal and applying an algorithm such as least squares or Kalman filtering. Again, there is no mention of measuring the harmonics generated by the amplifier and using these measurements as a basis for directly determining the predistortion parameters.

[0019] Similarly, US 10,720,891 B2 describes an amplifier linearization system based on adaptively determining predistortion coefficients based on an error signal. According to this invention, the iterative learning process is expressed as a system of linear equations and a conjugate gradient algorithm is applied to reduce instability of the iterative learning process. Again, there is no mention of measuring the harmonics generated by the amplifier and directly determining the predistortion parameters based on the measurements.

[0020] On the other hand, US 8,736,365 B2 describes a predistortion module that operates based on measuring the continuous output of a thermally coupled, miniaturized version of the same, rather than measuring the nonlinear distortion introduced by the wireless power amplifier. The invention does not describe measuring the nonlinear distortion introduced by the wireless power amplifier. Instead, the invention is based on the assumption that the miniaturized version operates similarly and, when properly interconnected, can modify the signal to partially compensate for the nonlinear distortion introduced by the wireless power amplifier. Furthermore, the invention does not mention measuring the harmonics generated by the wireless power amplifier and using the measurements as a basis for directly determining predistortion parameters.

[0021] On the other hand, WO 2018 / 185532 A1 describes a predistortion system that attenuates the effects of interference from nearby transmitters in an array by incorporating a crosstalk model within a continuous adaptation scheme driven by an error signal. Again, there is no mention of measuring the harmonics generated by the amplifiers and directly determining the predistortion parameters based on those measurements.

[0022] Similarly, WO 2019 / 190515 A1 describes a method for canceling the effects of crosstalk during the process of training a predistortion circuit based on receiving multiple feedback signals individually, but again does not mention measuring the harmonics generated by the amplifier and directly determining the predistortion parameters based on the measurements.

[0023] On the other hand, US 5,089,782 describes a vector network analyzer that measures nonlinear radio devices and determines their characteristics by measuring the harmonics generated in response to sinusoidal signals, but does not mention using the harmonics generated by an amplifier in response to a number of such inputs as a means of obtaining the coefficients of a memoryless polynomial representing that response and / or its inverse.

[0024] Other innovative features of the invention are set out in the following description and are referred to in the dependent claims.

[0025] According to one aspect of the invention, the measuring means comprises: a first filtering means for filtering the analog signal from the low-frequency analog signal provided by the first demodulation means, which includes only frequencies within a specified interval and attenuates all frequencies outside said interval (preferably consisting of a band-pass filter network, for example type BPF-C510+ manufactured by Mini-Circuits); second means for synthesizing a sinusoidal analog signal, the frequency of which is determined by said corresponding second digital value (preferably consisting of a fractional phase locked loop, for example of the type HMC704LP4E manufactured by Analog Devices); second demodulation means (preferably consisting of a downconverter circuit, for example of type AD8348 manufactured by Analog Devices), for obtaining a low-frequency analog signal from the output of the first filtering means by mixing it with the output of the second synthesis means; A signal that includes only frequencies within a specified interval from the low-frequency analog signal transmitted by the second demodulation means and attenuates all frequencies outside that interval. second filtering means (preferably consisting of a low-pass filter network, for example type LPF-B0R6+ manufactured by Mini-Circuits); second means for converting digital values ​​from the output of the second filtering means (preferably consisting of an analog-to-digital converter of the successive approximation type, for example the type AD4002 manufactured by Analog Devices); The output of the second conversion means, which represents the spectral amplitude, is provided as an input to control means for storing corresponding values ​​in a second memory array.

[0026] According to this aspect of the invention, a process for measuring harmonics generated by a first wireless power amplifier in response to a sinusoidal input includes sequentially setting a second synthesis means to all corresponding frequencies and obtaining digital values ​​corresponding to their spectral amplitudes from a second conversion means. The first filtering means is provisioned such that a corresponding designated interval encompasses frequencies corresponding to all harmonics of interest, and the second filtering means is provisioned such that the corresponding designated interval extends to zero and encompasses frequencies up to several orders of magnitude lower than the frequencies associated with the harmonics of interest. As a result, the second conversion means can advantageously operate at conversion rates several orders of magnitude lower than the frequencies associated with the harmonics of interest, thereby enabling the use of known architectures known to minimize converter size, complexity, and power consumption.

[0027] According to one aspect of the invention, the measuring means comprises: filtering means (preferably consisting of a bandpass filter network of the type BPF-C510+ manufactured by Mini-Circuits) for extracting from the low-frequency analog signal emitted by the first demodulation means a signal containing only frequencies within a specified interval, attenuating all frequencies outside of it; second means for converting a digital value from the output of said filtering means (preferably consisting of a flash type analog-to-digital converter, for example an analog-to-digital converter of the AD9625 type manufactured by Analog Devices); · a third memory array (preferably consisting of a static random access memory) adapted to store the output of the second conversion means and connected to said second conversion means via suitable interface means (preferably consisting of a register or set of registers); second calculating means (e.g., an Analog Devices ADSP-TS101S digital signal processor) for implementing a discrete or high-speed version of a Fourier transform of the spectral amplitude from the digital values ​​emitted by the second converting means at a frequency determined by the corresponding second digital value;

[0028] According to this aspect of the invention, the process of measuring the harmonics generated by the first radio power amplifier in response to the sine wave input involves converting the time-domain analog signal containing all harmonics to the digital domain only once, and then sequentially calculating the spectral amplitudes one by one. The filtering means is provisioned so that a corresponding designated interval encompasses frequencies corresponding to all harmonics of interest. Advantageously, this aspect of the invention benefits from the fast conversion speeds made available by known architectures and the fact that, after the output of the second converting means is stored in the third memory array, the second calculating means is operable to sequentially calculate the spectral amplitudes at any time, independent of the signal currently input to the filtering means. This significantly reduces the length of the time interval during which the generating means must be configured to generate a sine wave instead of the analog signal corresponding to the first baseband input, thereby reducing the duration of the foreground calibration process during which the transmitter is unavailable for its intended use.

[0029] According to one aspect of the invention, the control means comprises: a fourth memory array (preferably consisting of a pre-programmed read-only memory) suitable for storing amplitude and frequency settings supplied via first digital values ​​to the generating means to control the characteristics of the associated sine wave, and frequency settings supplied via second digital values ​​to the measuring means to control the frequency at which the spectral amplitude is measured; · means for interfacing the fourth memory array to the generating means and the measuring means (preferably consisting of a register or a set of registers); · further interface means for the output of the measurement means to the second memory array (preferably consisting of a register or a set of registers and an address generator); first sequencing means (preferably comprising a finite state machine or set thereof) for controlling the operation of said interface means in accordance with the contents of a fourth memory array, responsive to assertion of a second logic signal (generated external to the system and indicating a request to begin foreground calibration) and terminating with assertion of a third logic signal (generated by the first sequencing means and indicating the end of the measurement phase of the calibration process);

[0030] According to this aspect of the invention, the process of measuring harmonics generated by the first wireless power amplifier is controlled entirely by hardware means in response to assertion of a logic signal and does not require the execution of software code by a microcontroller or microprocessor. According to a predetermined sequence stored in the fourth memory array, the process emits combinations of amplitude and frequency settings to the generating means, which then sequentially emits a sequence of frequencies corresponding to the harmonics of interest to the measuring means, which then emits further combinations of amplitude and frequency settings to the generating means, and stores the output of the measuring means in the second memory array until a sufficient number of combinations of amplitude and frequency of the generated signal have been emitted. Advantageously, this aspect of the invention reduces the complexity of the hardware required to control the measurement process with respect to the use of a microprocessor or microcontroller executing software code, allowing it to be efficiently implemented in a completely self-contained and independent manner, for example, for each wireless power amplifier instantiated in a large array.

[0031] According to one aspect of the present invention, the first calculation means comprises: a first set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store a first group of coefficient values ​​used in that calculation; a first addressing means (preferably comprising a multiplexer and an address decoder) for one of the memory arrays in the first set of memory arrays; first means for multiplying values ​​contained in a second memory array by corresponding first coefficient values ​​stored in the array addressed by said first addressing means (preferably comprising a pipelined single-cycle hardware multiplier); a second set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store the first group of offset values ​​used in that calculation; second addressing means (preferably consisting of a multiplexer and an address decoder) for one of the memory arrays in the second set of memory arrays; · first adding means (preferably comprising a pipelined single-cycle hardware adder) for adding the output of the first multiplying means to a corresponding first offset value stored in the array addressed by the second addressing means; second means for evaluation of the activation function as a function of the output of said first summing means (preferably consisting of a look-up table containing values ​​obtained by a hyperbolic tangent function or consisting of an interpolator combined with a look-up table containing same); a third set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store a second group of coefficient values ​​used in the calculation; third addressing means (preferably consisting of a multiplexer and an address decoder) for one memory array of the third set of memory arrays; · second multiplication means (preferably comprising a pipelined single-cycle hardware multiplier) for multiplying the output of the second evaluation means by corresponding second coefficient values ​​stored in the array addressed by the third addressing means; a fourth set of memory arrays (preferably consisting of a set of preprogrammed read-only memories) each corresponding to one parameter and adapted to store a second group of offset values ​​calculated and used in said calculation; · fourth addressing means (preferably consisting of a multiplexer and an address decoder) for one memory array among those included in said fourth set of memory arrays; · second adding means (preferably comprising a pipelined single-cycle hardware adder) of the output of said second multiplying means to a corresponding second offset value stored in the array addressed by the fourth addressing means; third means for evaluation of the activation function as a function of the output of the second summation means (preferably consisting of a look-up table containing values ​​obtained by a linear function or consisting of an interpolator combined with a look-up table containing same); · means for interfacing the third evaluation means with the first memory array (preferably consisting of a register or set of registers and an address generator), such that the output of the former is stored in the latter; second sequencing means (preferably comprising a finite state machine or set thereof) for sequencing the operation of the first, second, third and fourth addressing means and interface means in response to assertion of a third logic signal (generated by the control means and signalling the end of the measurement phase of the calibration process);

[0032] According to this aspect of the invention, the process of calculating the parameters of the algebraic expression (preferably consisting of coefficients of a memoryless polynomial) is realized entirely in hardware using an architecture known to be suitable for implementing artificial neural networks with a two-layer perceptron topology (P.L. Lee, I. Lazzizzera, A. Zorat, A. Sartori, G. Tecchiolli, Advances in the design of the TOTEM neurochip, Nucl Instrum Methods Phys Res B 1997; 389(1), 134-137; N. Nedjah, R. Martins da Silva, L. de Macedo Mourelle. Compact yet efficient hardware implementation of artificial neural networks with customized topology. Expert Syst Appl 2012; 39(10), 9191-9206). This type of network is known to be a universal approximator and, as a result, is suitable for approximately representing the relationship between the spectral amplitude of harmonics and the parameters of the algebraic expression (preferably consisting of coefficients of a memoryless polynomial) required for amplifier linearization. Hornik, M. Stinchcombe, H. White, Multilayer feedforward networks are universal approximators, Neural Netw 1989; 2(5), 359-366; S. Geva, J. Sitte, A constructive method for multivariate function approximation by multilayer perceptrons, IEEE Trans Neural Netw 1992; 3(4), 621-624).Advantageously, this aspect of the invention reduces the complexity of the hardware required to implement the computational process relative to using a microprocessor or microcontroller running software code, allowing the computation to be efficiently implemented in a completely self-contained and independent manner for, for example, each wireless power amplifier instantiated in a large array. Further advantageously, this aspect of the invention allows the multiplication means, summation means, and evaluation means to be shared across the parameters being computed, further reducing the size of the hardware required and making it largely independent of the number of parameters being computed.

[0033] According to one aspect of the present invention, the digital predistortion system also comprises: · means for converting at least one physical magnitude (preferably consisting of voltage and / or current and / or temperature) characteristic of either the first radio power amplifier or the first load, or both; amplifying means (preferably consisting of an operational amplifier connected according to an active filter topology, e.g., Texas Instruments TLC274 type) of the output of the converting means adapted to magnify fluctuations associated with the operation of either the first radio power amplifier (e.g., in response to fluctuations in the local power supply voltage) or the first load (e.g., in response to changes associated with the beam steering dynamics), or both; a third amplifier means for converting the output of the amplifier means into a digital value (preferably a successive approximation type analog-to-digital converter, such as the AD4002 type manufactured by Analog Devices); a fifth memory array (preferably consisting of a static random access memory) adapted to store a number of outputs of said third conversion means and connected to said first calculation means, the values ​​contained therein being available to the latter together with the values ​​contained in said second memory array; · Means (preferably consisting of a register or set of registers and an address generator) for interfacing said third means with said fifth memory array so that the output of the former is stored in the latter.

[0034] This aspect of the invention introduces the possibility of reacting to changes in the operating conditions of a first wireless power amplifier and / or a first load connected thereto without requiring continuous measurement of the harmonics generated by the wireless amplifier. To achieve this functionality, because wireless power amplifiers are highly sensitive to changes in the load and the physical magnitudes characterizing the load that occur during normal operation, the effects of which can be estimated a priori (S.K. Dhar, M. Helaoui, F.M. Ghannouchi, Temperature Dependent Robust Behavioral Modeling of Non-Linear Power Amplifier, 2018 Asia-Pacific Microwave Conference 2018, pp. 378-380), one or more associated physical magnitude values ​​are provided to the first calculation means along with the spectral amplitude. Advantageously, this feature of the invention allows for consistently high accuracy in linearizing the response of the first wireless power amplifier without requiring continuous measurement of the harmonics generated thereby (foreground calibration), and instead by one or more transducers that indirectly track changes in its operating conditions, so that their operation does not interfere with the continued normal operation of the transmitter. In effect, this feature of the present invention introduces a form of background calibration into the digital predistortion system.

[0035] According to one feature of the invention, the digital predistortion system also comprises a modifying means for modifying values ​​of parameters belonging to the algebraic formula stored in the first memory array when interposed between the first memory array and the first calculating means, the modifying means comprising: a sixth memory array (preferably comprising static random access memory) adapted to store multiple outputs of said third conversion means; · means for interfacing the third conversion means with a sixth memory array (preferably comprising a register or set of registers and an address generator), for causing the output of the former to be stored in the latter whenever said third logic signal is asserted; · means for subtracting values ​​contained in the sixth memory array from values ​​contained in said fifth memory array (preferably comprising a pipelined single-cycle hardware adder having a negative sign input); a seventh memory array (preferably consisting of pre-programmed read-only memory) adapted to store a number of coefficient values ​​corresponding to the values ​​stored in said fifth and sixth memory arrays; third multiplication means (preferably comprising a pipelined single-cycle hardware multiplier) of the output of the subtraction means by a corresponding coefficient value stored in said seventh memory array; an eighth memory array (preferably consisting of a pre-programmed read-only memory) adapted to store values ​​of a number of parameters belonging to the algebraic formula output by said first calculation means and connected in place of the first memory array; third adding means (preferably comprising a pipelined single-cycle hardware adder) of the output of the third multiplying means to a value contained in said eighth memory array; Another set of interfacing means (preferably consisting of a register or set of registers and an address generator) with the first memory array of the third adding means, so that the output of the former is stored in the latter.

[0036] This aspect of the invention provides the ability to react to rapid changes in the operating conditions of a wireless amplifier and / or its connected load by enabling the parameters of an algebraic expression (preferably, the coefficients of a memoryless polynomial) to be adjusted more quickly than would be possible by recalculating them using the first calculation means. To achieve this functionality, a perturbation-based approach is introduced, whereby values ​​of transformed physical magnitudes corresponding to measured harmonics are captured, and fluctuations around those values ​​are subsequently calculated in real time to adjust the parameters of the algebraic expression (preferably, the coefficients of a memoryless polynomial; M.H. Holmes, Introduction to perturbation methods, Springer, New York, 2013). Advantageously, this feature of the invention enables consistently high accuracy to be achieved in linearizing the response of the first wireless power amplifier without requiring frequent measurements of the harmonics generated by the same (foreground calibration), based on the assumption that the first wireless power amplifier is highly sensitive to changes in several physical magnitudes that characterize it and / or its load. This occurs quickly during normal operation and its effects can be estimated a priori (SK Dhar, M. Helaoui, FM Ghannouchi, Temperature Dependent Robust Behavioral Modeling of Non-Linear Power Amplifier, 2018 Asia-Pacific Microwave Conference 2018, 378-380). Effectively, this feature of the present invention introduces a form of continuous background calibration to the proposed digital predistortion system.

[0037] According to one aspect of the present invention, the digital predistortion system also comprises: selection means (preferably an analog microwave switch, e.g. Microchip MMS006AA) for selecting an input from an output of one of the extraction means to the first demodulation means when a fourth logic signal (generated by the control means controlling the source of the measurement signal) is not asserted, and otherwise when the fourth logic signal is asserted; The control means is also adapted to additionally emit a fourth logic signal, such that the output of the measurement means is stored in the second memory array both when the logic signal is asserted and when it is not asserted, thus separately measuring the response of the combination of the first modulation means, the first demodulation means, and the measurement means without the same response further combined with the nonlinear distortion introduced by the first wireless power amplifier.

[0038] This feature of the invention introduces the possibility of compensating for non-ideal frequency responses and / or nonlinearities of the measurement means. Advantageously, this feature of the invention allows for greater accuracy in linearizing the response of the radio power amplifier, since the parameters of the algebraic expression (preferably the coefficients of the memoryless polynomial) are tailored to more selectively reflect the distortions introduced thereby, allowing for compensation of the response of the measurement means (by the first calculation means). Furthermore, this feature of the invention relaxes the design requirements imposed on the measurement means, since it increases the tolerance for nonlinearities in the demodulation, filtering, and conversion means included in the measurement means (D.E. Root, J. Wood, N. Tufillaro, New techniques for non-linear behavioral modeling of microwave / RF ICs from simulation and nonlinear microwave measurements, Proceedings of the 40th annual Design Automation Conference 2003, pp. 85-90).

[0039] According to one aspect of the present invention, the digital predistortion system also comprises: a second load (preferably consisting of a resistor, for example, type CH0603-50RJNTA from Vishay Sfernice); switching means (preferably an analog microwave switch, e.g. Microchip type MMS006AA) of the output of said first radio power amplifier between a first load and a second load, adapted to switch the output to said second load whenever a first logic signal is asserted (indicating the generation of an analog signal comprising a sine wave);

[0040] This feature of the invention introduces the possibility of preventing the output of the radio power amplifier from reaching the first load while the generating means is radiating a sine wave. Advantageously, when the first load includes an antenna, this feature of the invention allows compliance with the requirements of some wireless transmission standards, as specified in the 3GPP specifications, which prohibit the radiation of continuous wave signals (E. Dahlman, S. Parkvall, J. Skold, 5G NR: The Next Generation Wireless Access Technology, Academic Press, Cambridge MA, USA, 2020).

[0041] According to one aspect of the present invention, the digital predistortion system also comprises: second means for obtaining a second baseband signal consisting of digital values ​​representative of the data to be transmitted (preferably from another device, connected to the same device, preferably consisting of a buffer memory of the first-in-first-out type); · fourth evaluation means (preferably comprising a combination of pipelined single-cycle hardware multipliers and adders) for evaluating an algebraic expression (preferably comprising a memoryless polynomial) from a second baseband signal given a set of parameter values ​​(preferably comprising coefficients of a memoryless polynomial) stored in a first memory array; fourth conversion means (preferably consisting of a digital-to-analog converter intended for direct radio frequency synthesis, for example of the type AD9737A manufactured by Analog Devices) from the digital values ​​emitted by said fourth evaluation means of the analog signal; second modulation means (preferably consisting of an upconverter circuit of the type ADMV1013 manufactured by Analog Devices) for obtaining an analog signal of a higher frequency from the analog signal (provided by the fourth conversion means) by mixing the analog signal (provided by the fourth conversion means) with a carrier signal (provided by the local oscillator means); second radio power amplification means for the high frequency analog signal (emitted by the second modulation means) (preferably consisting of a radio power amplifier realized using complementary metal oxide semiconductor technology, such as that found in the type SUMMIT 3741 of the company MixComm); A third load (preferably consisting of a transmitting antenna connected by suitable matching and auxiliary circuits) connected to the output of said second radio power amplification means.

[0042] This feature of the present invention introduces the possibility of applying a single set of algebraic parameters (preferably, memoryless polynomial coefficients) to linearize multiple radio power amplifiers. Advantageously, this feature of the present invention allows for a reduction in the amount of circuitry required to linearize multiple amplifiers that are expected to have similar characteristics in construction. For example, in the presence of a large array of transmitters, this alleviates design difficulties associated with the high area occupancy that occurs when instantiating multiple copies of an entire digital predistortion system. [Brief explanation of the drawings]

[0043] Further objects and advantages of the present invention will become apparent from the following detailed description of embodiments thereof and from the accompanying drawings, given purely by way of non-limiting example. [Figure 1] 1 shows a schematic diagram of a digital predistortion system according to the present invention; [Figure 2] 2 shows a schematic diagram of one form of realisation of a generating means forming part of the system in FIG. 1; [Figure 3] 2 shows a schematic diagram of another form of realisation of the generating means forming part of the system in FIG. 1; [Figure 4] 2 shows a schematic diagram of one form of realization of the measurement means forming part of the system in FIG. 1; [Figure 5] 2 shows a schematic diagram of another form of realization of the measurement means forming part of the system of FIG. 1; [Figure 6] 2 shows a schematic diagram of one form of realisation of the control means forming part of the system in FIG. 1; [Figure 7] 2 shows a schematic diagram of one form of implementation of a first computing means forming part of the system of FIG. 1; [Figure 8] 2 is a schematic diagram of a variation of the system of FIG. 1 including means for converting at least one physical dimension representative of the radio power amplifier and / or load characteristics. [Figure 9] FIG. 2 is a schematic diagram showing one implementation of a correction means forming part of the system of FIG. 1; [Figure 10] 2 is a schematic diagram of another variant of the system of FIG. 1 with additional selection means between the output of one of the extraction means and the output of the modulation means; [Figure 11] 2 shows a schematic diagram of another variant of the system in FIG. 1, with additional switching means between the first and second loads; [Figure 12] 2 shows a schematic diagram of another variant of the system of FIG. 1, comprising additional acquisition means, evaluation means, conversion means, modulation means, amplification means and a load. Detailed Description of the Invention

[0044] In the following description of this specification, the drawings may refer to elements that are not explicitly shown in the drawing but are shown in other drawings, and the scales and proportions of the different elements depicted do not necessarily correspond to those in reality.

[0045] FIG. 1 shows a nonlinear distortion compensation system 1 applied to a first radio power amplifier 2, which distorts the signal input to the amplifier in a way that at least partially compensates for the nonlinear distortion (e.g., gain compression) introduced by the amplifier itself, thus improving the fidelity of the radio transmission.

[0046] The system 1 according to the invention comprises first means 3 for acquiring a first baseband signal consisting of digital values, preferably consisting of a first-in-first-out type buffer memory connected thereto from another device. The system further comprises a first memory array 4, preferably consisting of a static random access memory suitable for storing values ​​of a number of parameters consisting of coefficients of memoryless polynomials belonging to an algebraic expression. The signal acquired by the first acquisition means 3 is sent to first means 5, preferably consisting of a combination of pipelined single-cycle hardware multipliers and adders, which evaluates the algebraic expression obtained from the first baseband signal combined with the parameters stored in the first memory array 4, preferably consisting of a memoryless polynomial.

[0047] The signal output by the first evaluation means 5 is preferably sent to means 6 consisting of a digital-to-analog converter intended for direct high-frequency synthesis, either in combination with an analog frequency synthesizer in combination with a variable gain amplifier and an analog switch, or in combination with a digital signal synthesizer and a digital multiplexer switch, in order to generate an analog signal from the digital value determined by the algebraic formula emitted by the evaluation means 5 or in accordance with a sine wave having a controllable amplitude and frequency determined by the first digital value 7 upon assertion of a first logic signal 8. The analog signal thus generated is supplied to first modulation means 9, preferably consisting of an up-converter circuit, alongside a carrier signal with a known frequency emitted by local oscillator means 10, in order to obtain an analog signal of a higher frequency.

[0048] The high frequency analog signal emitted by the first modulation means 9 is then input to a radio power amplifier 2, preferably realized using complementary metal oxide semiconductor technology. Its output is preferably transmitted to means 11, preferably consisting of a power splitter, for extracting a portion of the signal emitted by the radio power amplifier 2 before it reaches a first load 12, preferably consisting of a transmitting antenna and connected by appropriate matching and auxiliary circuitry. The signal fraction extracted by the extraction means 11 is fed to first demodulation means 13, preferably consisting of a downconverter circuit, together with a carrier signal with a known frequency emitted by local oscillator means 10, to obtain a lower frequency analog signal.

[0049] The low-frequency analog signal emitted by the first demodulation means 13 is input to means 14 for measuring the spectral amplitude at selected frequencies, determined by second digital values ​​15. As can be seen in Figure 1, the operation of the generating means 6 and the measuring means 14 is determined by the operation of further means 17 for controlling the process of measuring the non-linear distortion introduced by the first radio power amplifier 2, which, during the measurement process initiated by the external assertion of a second logic signal 18, gives the setting of the amplitude and frequency of the analog signal emitted by the generating means 6 by means of a corresponding first digital value 7 and asserts a first logic signal 8 connected thereto, and simultaneously stores the spectral amplitude obtained by the measuring means 14 at each frequency determined by the corresponding second digital value 15 in a second memory array 16, preferably consisting of a static random access memory.

[0050] Finally, the contents of the second memory array 16 are supplied to the first means 20 which, based on the assertion of a third logic signal 19 emitted by the control means 17 upon completion of the measurement process, determines the values ​​of a number of parameters, preferably consisting of coefficients of a memoryless polynomial, belonging to an algebraic formula and stored in the first memory array 4, so that the output of the first radio power amplifier 2, after being modulated to a higher frequency by mixing it with a carrier signal emitted by the local oscillator means, is as linearly related as possible to the first baseband signal, i.e. compensates as accurately as possible the non-linear distortion introduced by the first radio amplifier 2.

[0051] 2 shows an implementation of the nonlinear distortion compensation system 1, according to which the generating means 6 comprises first means 21, preferably consisting of a digital-to-analog converter intended for direct radio frequency synthesis, for converting the output of the first evaluating means 5 into an analog signal along with first means 22a, preferably consisting of an analog frequency synthesizer in combination with a variable gain amplifier, for synthesizing a sinusoidal analog signal having an amplitude and frequency determined by a corresponding first digital value 7. The outputs of the first converting means 21 and the first synthesizing means 22a are fed to first means 23a, preferably consisting of an analog switch, adapted to select the analog signal output by the first converting means 21 if a first logic signal 8 is not asserted, or otherwise the analog signal output by the first synthesizing means 22a if the first logic signal 8 is asserted, and to feed the selected signal as input to the first modulating means 9.

[0052] 3 shows another embodiment of the nonlinear distortion compensation system 1, according to which the generating means 6 includes first means 22b, preferably consisting of a digital signal synthesizer, for synthesizing a digital value corresponding to a sine wave having an amplitude and frequency determined by a first corresponding digital value 7. The outputs of the first synthesizing means 22b and the first evaluating means 5 are fed to first means 23b, preferably consisting of a digital multiplexer switch, adapted to select the digital value output by the first evaluating means 5 if the first logic signal 8 is not asserted, or otherwise to select the digital value output by the first synthesizing means 22b if the first logic signal 8 is asserted. The output of the first selecting means 23b is then input to first means 21, preferably consisting of a digital-to-analog converter intended for direct high-frequency synthesis, which converts it into an analog signal and supplies it as input to the first modulating means 9.

[0053] It is widely known to those skilled in the art that the embodiments shown in Figures 2 and 3 are equivalent in function and purpose and may be used interchangeably depending on practical design considerations (TJ Rouphael, RF and Digital Signal Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach, Newnes, London, UK, 2008).

[0054] 4 shows an embodiment of the measuring means 14, characterized in that it comprises first means 24, preferably consisting of a band-pass filter network, connected to the output of the first demodulation means 13, for filtering by attenuating all frequencies outside a specific range, and second means 25, preferably consisting of a fractional phase-locked loop, for synthesizing a sinusoidal analog signal having a frequency determined by the second digital value 15. The outputs of the first filtering means 24 and the synthesizing means 25 are then connected to second means 26, preferably consisting of a down-converter circuit, which demodulates the output of the filtering means 24 to a lower frequency by mixing it with the output of the second synthesizing means 25. The output of the demodulation means 26 is input to second means 27, which preferably comprises a low pass filter network for filtering by attenuating all frequencies outside a specified range, the output of which is provided to second means 28, preferably comprising a successive approximation type analogue to digital converter for converting it to a digital value which is provided as an input to the control means 17.

[0055] FIG. 5 shows an embodiment of the measuring means 14, characterized in that the measuring means includes first means 24, preferably with a bandpass filter network for filtering by attenuating all frequencies outside a specified range, receiving the output of the first demodulation means 13 as input and providing its output to second means 30, preferably consisting of a flash-type analog-to-digital converter for converting it to a digital value. The output of the converting means 30 is then provided to first means 32, preferably consisting of a register or set of registers, for interfacing with a third memory array 31, preferably consisting of a static random access memory, so that the output of the former is stored in the latter. The contents of the third memory array 31 are made available to second means 33, preferably consisting of a digital signal processor implementing a discrete or high-speed version of the Fourier transform, which calculates the spectral amplitude of the signal output by the filtering means 29 at the frequency determined by the second corresponding digital value 15. The output of the second calculating means 33 is finally provided as an input to the control means 17.

[0056] 6 shows an embodiment of the control means 17, characterized in that it includes a fourth memory array 34, preferably consisting of a preprogrammed read-only memory, adapted to store a predetermined sequence of digital values. The output from this memory is connected to the generating means 6 and the measuring means 14 through corresponding interfaces 35, 36, both preferably consisting of a register or set of registers, delivering the first and second digital values ​​7, 15, respectively. The measuring means 14 and the second memory array 16 are connected to each other by receiving the output of the measuring means 14 as input and connecting their outputs to the second memory array 16, so that the output of the former means is stored in the latter memory. The control means 17 further comprises a first means 38, preferably a finite state machine or set thereof, for sequencing, based on the assertion of the second logic signal 18, by providing an addressing output thereto in accordance with a predetermined sequence comprised of included in the fourth memory array 34, the emission of the first and second digital values ​​7, 15 by the interface means 35, 36, and the measurement means 14, by the interface means 37, to the second memory array 16, and asserting a third logic signal 19 upon completion of the predetermined sequence.

[0057] 7 shows an embodiment of the calculation means 20, comprising a first set of memory arrays 39, preferably comprising a set of preprogrammed read-only memories, each set corresponding to one parameter to be calculated and adapted to store a first group of coefficient values ​​used in that calculation, and connecting their outputs to first means 40, preferably consisting of a multiplexer and an address decoder, for addressing one of the memory arrays in the set of first memory arrays 39. The output of the first addressing means 40, together with the output of the second memory array 16, is connected to the input of first means 41, preferably consisting of a pipelined single-cycle hardware multiplier, for multiplying the value contained therein by the corresponding first coefficient value stored in the array addressed by the first addressing means 40. The calculation means 20 preferably comprises a set of pre-programmed read-only memories, each corresponding to one parameter to be calculated and adapted to store a first group of offset values ​​used in the calculation, with their outputs connected to second means 43, preferably comprising a multiplexer and an address decoder, for addressing one of the set of second memory arrays 42. The output of the second addressing means 43 is connected, alongside the output of the first multiplication means 41, to the input of first means 44 for summing the output of the first addressing means 44 with the corresponding first offset value stored in the array addressed by the second addressing means 43. The output of the first addition means 44 is then sent to second means 45, preferably comprising a pipelined single-cycle hardware adder, for evaluating an activation function as a function of the output of the first addition means 44. Each corresponds to one parameter to be calculated and is adapted to store a second group of coefficient values ​​used in that calculation, and their outputs are connected to third means 47, preferably consisting of a multiplexer and an address decoder, for addressing one of the memory arrays in the set of third memory arrays 46.The output of the third addressing means 47 is connected to the input of second means 48, which, together with the output of the second evaluation means 45, preferably consists of a look-up table containing values ​​obtained by a hyperbolic tangent function, or an interpolator combined with a look-up table containing such, and which preferably consists of a pipelined single-cycle hardware multiplier, for multiplying the output of the second evaluation means 45 by a corresponding second coefficient value stored in the array addressed by the third addressing means 47. The calculation means 20 further comprises a set of fourth memory arrays 49, preferably consisting of a set of pre-programmed read-only memories, each corresponding to one parameter to be calculated and adapted to store a second group of offset values ​​used in the calculation, the outputs of which are connected to fourth means 50, preferably consisting of a multiplexer and an address decoder, for addressing one of the memory arrays included in the fourth set of memory arrays 49. The output of the fourth addressing means 50 is connected to the input of second means 51, preferably consisting of a pipelined single-cycle hardware adder, which sums the output of the second multiplying means 48 with a corresponding second offset value stored in the array addressed by the fourth addressing means 50. The output of the second summing means 51 is communicated to third means 52, preferably consisting of a look-up table containing values ​​obtained by a linear function, or an interpolator combined with a look-up table containing such, for evaluating an activation function as a function of the output of the second summing means 51. The calculation means 20 also comprises means 53, preferably consisting of a register or set of registers and an address generator, for interfacing the evaluation means 52 with the second memory array 4, receiving the output of the evaluation means 52 as input and connecting its output to the second memory array 4 so that the output of the former means is stored in the latter memory.The calculation means 20 further comprises second means 54, preferably consisting of a finite state machine or set thereof, for sequencing, at least once upon assertion of the third logic signal 19, the operation of the first, second, third and fourth addressing means 40, 43, 47, 50 and the interface means 53 according to a hardwired sequence, by means of outputs connected to all of the means; thus, all values ​​of the parameters to be stored in the first memory array 4 are calculated based on the values ​​contained in the second memory array 16 and stored in the first memory array 4.

[0058] 8 shows an embodiment of the nonlinear distortion compensation system 1, which further comprises conversion means 55 representing a characteristic of the first radio power amplifier 2 and / or the first load 12 consisting of at least one physical magnitude, preferably voltage and / or current and / or temperature, characterized in that the output of the conversion means 55, connected to the input of the amplification means 56, preferably consists of an operational amplifier connected according to an active filter topology, thereby being able to magnify fluctuations associated with the operation of either the first radio power amplifier 2 and / or the first load 12. The output of the amplification means 56 is then connected to the input of third means 57, preferably consisting of an analog-to-digital converter of the successive approximation type, for converting it into a digital value. According to this embodiment, the system means 1 also comprises means 59, preferably consisting of a register or a set of registers and an address generator, consisting of the third conversion means 57 and a fifth memory array 58, preferably a static random access memory, which receives the output of the conversion means 57 as input and connects its output to the fifth memory array 58, so that the output of the former means is stored in the latter memory. Finally, the contents of the fifth memory array 58 are supplied to the first calculation means 20 so that the values ​​contained therein are available on the same basis as the values ​​contained in the second memory array 16 .

[0059] 9 shows an embodiment of the nonlinear distortion compensation system 1, characterized in that the system further comprises correction means 60, characterized in that the correction means includes means 62, preferably consisting of a register or set of registers and an address generator, for interfacing the third conversion means 57 with a sixth memory array 61, preferably consisting of a static random access memory, the output of which is stored in the latter whenever the third logic signal 19 is asserted. The contents of the sixth memory array 61, together with the contents of the fifth memory array 58, are provided to means 63 for subtracting the former from the latter. The output of the subtraction means 63 is preferably consisting of a pipelined single-cycle hardware adder with a negative sign input, connected to the input of third means 65, preferably consisting of a read-only memory preprogrammed to multiply it by corresponding coefficient values ​​stored in a seventh memory array 64. When the correction means 60 is present, the output of the first calculation means 20 is connected to the input of eight memory arrays 66, preferably consisting of static random access memories, instead of the first memory array 4. The output of the third multiplication means 65 is connected to third means 67 for summing the outputs of the multiplication means 65 together with the outputs of the eight memory arrays 66, preferably consisting of a pipelined single-cycle hardware multiplier, to the value contained in the eight memory arrays 66. According to this embodiment, the modifying means 60 also comprises means 68, preferably consisting of a register or set of registers and an address generator, and means 68 for interfacing with the first memory array 4, preferably consisting of a pipelined single-cycle hardware adder, for storing the output of the former means in the latter memory.

[0060] 10 shows an embodiment of the nonlinear distortion compensation system 1, characterized in that the system further comprises second means 69, preferably consisting of an analog microwave switch, for selecting one output of the extraction means 11 if the fourth logic signal 70 is not asserted, or otherwise selecting the output of the first modulation means 9 if the fourth logic signal 70 is asserted, and for providing the selected signal as input to the first demodulation means 13. Unlike the configuration shown in FIG. 1, the extraction means 11 and the first demodulation means 13 are not connected directly, but via the second selection means 69.

[0061] 11 shows an embodiment of the nonlinear distortion compensation system 1, characterized in that the system further comprises a second load 71, preferably a resistor, connected to one of the two outputs of means 72, preferably an analog microwave switch, having its other output connected to the first load 12 for switching, such that if the first logic signal 8 is not asserted, one output of the extraction means 11 is transmitted to the first load 12, otherwise, if the first logic signal 8 is asserted, the same output of the extraction means 11 is transmitted to the second load 71. In contrast to the embodiment of FIG. 1, the extraction means 11 and the first load 12 are not connected directly, but via the switching means 72.

[0062] 12 shows an embodiment of the nonlinear distortion compensation system 1, characterized in that the system further comprises second means 72 for obtaining, by connection thereto, a second baseband signal consisting of digital values, preferably from another device, preferably consisting of a first-in-first-out type buffer memory, the output of which is connected to an input of fourth means 73, preferably consisting of a pipelined single-cycle hardware multiplier and adder combination, for evaluating an algebraic expression based on the parameter values ​​stored in the first memory array 4. The output of the fourth evaluation means 73 is provided as an input to fourth means 74, preferably consisting of a digital-to-analog converter for direct radio frequency synthesis and connected to an input of second means 75 for converting it into an analog signal, preferably consisting of an up-converter circuit, for modulating it to a higher frequency by mixing it with a carrier signal emitted by the local oscillator 10. The output of the second modulation means 75 is then connected to the input of a second radio power amplifier 76, preferably consisting of a radio power amplifier implemented using complementary metal oxide semiconductor technology, the output of which is connected to a third load 77, preferably consisting of a transmit antenna, connected by suitable matching and auxiliary circuitry.

[0063] Based on the description provided of the preferred exemplary embodiments, it is clear that several modifications can be made by those skilled in the art without departing from the scope of the invention as defined by the following claims.

Claims

1. A system (1) for compensating for nonlinear distortion introduced by a first wireless power amplifier (2), comprising: first acquisition means (3) for obtaining a first baseband signal consisting of digital values; a first memory array (4) for storing values ​​of a plurality of parameters belonging to an algebraic formula; first evaluation means (5) for evaluating said algebraic expression based on parameter values ​​stored in said first memory array (4) as a function of the output of said first acquisition means (3); means (6) for generating: ° an analog signal based on the output of said first evaluation means (5) when the first logic signal (8) is not asserted; Otherwise, ° when said first logic signal (8) is asserted, an analog signal comprising a sine wave having an amplitude and frequency determined by a corresponding first digital value (7); first modulation means (9) for modulating the output of said generating means (6) to a higher frequency by mixing it with a carrier signal emitted by a local oscillator (10); - the first radio power amplifier (2) having as input the output of the first modulation means (9); means (11) for extracting a portion of the signal emitted by said first radio power amplifier (2) before it reaches a first load (12); first demodulation means (13) for demodulating one output of said extraction means (11) to a lower frequency by mixing it with the carrier signal emitted by said local oscillator (10); - means (14) having as input the output of said first demodulation means (13) for measuring the spectral amplitude of a signal at a frequency determined by a corresponding second digital value (15); a second memory array (16) adapted to store a plurality of outputs of said measuring means (14); - means (17) for controlling the process of measuring the nonlinear distortion introduced by said first radio power amplifier (2); and the control means (17) asserts the first logic signal (8) simultaneously with issuing a predetermined sequence of first and second digital values ​​(7, 15) upon assertion of a second logic signal (18), stores the output of the measurement means (14) in the second memory array (16), and asserts a third logic signal (19) upon completion of the predetermined sequence; The system further comprises: - first calculation means (20) for calculating, upon assertion of the third logic signal (19), based on the values ​​contained in the second memory array (16), the values ​​of the parameters stored in the first memory array (4) and storing them, thereby supplying them to the first evaluation means (5) so that the output of the first radio power amplifier (2) is as linearly related as possible to the signal output by the first acquisition means (3) as it appears after being modulated to a higher frequency by mixing with the carrier signal emitted by the local oscillator (10); The generating means (6) has any of the following: - first conversion means (21) for converting the output of the first evaluation means (5) into an analog signal; - first synthesis means (22a) for synthesizing a sinusoidal analog signal having an amplitude and frequency determined by said corresponding first digital value (7); - first selection means (23a) for selecting: ° the analog signal output by the first conversion means (21) when the first logic signal (8) is not asserted; Otherwise, ° an analog signal output by the first synthesis means (22a) when the first logic signal (8) is asserted; and providing said selected signal as an input to said first modulation means (9); Or: - first synthesis means (22b) for synthesizing a digital value representing a sine wave having an amplitude and a frequency determined by said corresponding first digital value (7); - first selection means (23b) for selecting: ° the digital value output by the first evaluation means (5) when the first logic signal (8) is not asserted; Otherwise, ° the digital value output by the first synthesis means (22b) when the first logic signal (8) is asserted; - first conversion means (21) for converting the output of said first selection means (23b) into an analog signal and providing it as an input to said first modulation means (9); A nonlinear distortion compensation system comprising:

2. 2. The nonlinear distortion compensation system (1) according to claim 1, wherein the measuring means (14) comprises: first filtering means (24) for filtering the output of said first demodulation means (13) by attenuating all frequencies outside a specified range; second synthesis means (25) for synthesizing a sinusoidal analog signal having a frequency determined by a corresponding second digital value (15); second demodulation means (26) for demodulating the output of the first filtering means (24) to a lower frequency by mixing it with the output of the second combining means (25); second filtering means (27) for filtering the output of said second demodulation means (26) by attenuating all frequencies outside a specified range; second supply means (28) for converting the output of said second filtering means (27) into a digital value and supplying it as an input to said control means (17); A nonlinear distortion compensation system comprising:

3. 2. The nonlinear distortion compensation system (1) according to claim 1, wherein the measuring means (14) comprises: means (29) for filtering the output of said first demodulation means (13) by attenuating all frequencies outside a specified range; - second conversion means (30) for converting the output of said filtering means (29) into a digital value; a third memory array (31) adapted to store a plurality of outputs of said second conversion means (30); first interface means (32) for interfacing said second conversion means (30) with said third memory array (31), such that the output of the former is stored in the latter; second calculation means (33) for calculating, based on the values ​​contained in the third memory array (31), the spectral amplitude of the signal output by the filtering means (29) at a frequency determined by a corresponding second digital value (15) and supplying this as an input to the control means (17); A nonlinear distortion compensation system comprising:

4. In the nonlinear distortion compensation system (1) according to any one of claims 1 to 3, the control means (17) comprises: a fourth memory array (34) adapted to apply predetermined sequences of first and second digital values ​​(7, 15) to said generating means (6) and said measuring means (14) via corresponding second and third interface means (35, 36), respectively; fourth interface means (37) for interfacing said measurement means (14) with said second memory array (16), such that the output of the former is stored in the latter; first sequencing means (38) for, upon assertion of the second logic signal (18), releasing the first and second digital values ​​(7, 15) by calculation of the second and third interface means (35, 36) according to a predetermined sequence contained in the fourth memory array (34), storing the output of the measurement means (14) in the second memory array (16) by the fourth interface means (37), and asserting the third logic signal (19) at the completion of the predetermined sequence; A nonlinear distortion compensation system comprising:

5. In the nonlinear distortion compensation system (1) according to any one of claims 1 to 3, the first calculation means (20) comprises: a first set of memory arrays (39) each corresponding to one parameter to be calculated and adapted to store a first group of coefficient values ​​used in the calculation; first addressing means (40) for addressing one of the memory arrays included in said first set of memory arrays (39); first multiplying means (41) for multiplying the values ​​contained in the second memory array (16) by corresponding first coefficient values ​​stored in the array addressed by the first addressing means (40); a second set of memory arrays (42) adapted to store a first group of offset values, each corresponding to one parameter to be calculated, used in the calculation; second addressing means (43) for addressing one of the memory arrays included in said second set of memory arrays (42); first summing means (44) for summing the output of said first multiplying means (41) with a corresponding first offset value stored in the array addressed by said second addressing means (43); second evaluation means (45) for evaluating an activation function as a function of the output of said first summing means (44); a third set of memory arrays (46) adapted to store a second group of coefficient values, each corresponding to one parameter to be calculated and used in the calculation; third addressing means (47) for addressing one of the memory arrays included in said third set of memory arrays (46); second multiplying means (48) for multiplying the output of said second evaluation means (45) by a corresponding second coefficient value stored in the array addressed by said third addressing means (47); a fourth set of memory arrays (49) adapted to store a second group of offset values, each corresponding to one parameter to be calculated and used in the calculation; fourth addressing means (50) for addressing one of the memory arrays included in said fourth set of memory arrays (49); second summing means (51) for summing the output of said second multiplying means (48) with a corresponding second offset value stored in the array addressed by said fourth addressing means (50); a third evaluation means (52) for evaluating an activation function as a function of the output of the second summing means (51); fifth interface means (53) for interfacing said third evaluation means (52) with the first memory array (4) so ​​that the output of the former is stored in the latter; second sequence means (54) for operating the first, second, third and fourth addressing means (40, 43, 47, 50) and the fifth interface means (53) according to a hardwired sequence at least once upon assertion of the third logic signal (19), such that all values ​​of parameters to be stored in the first memory array (4) are calculated based on values ​​contained in the second memory array (16) and stored in the first memory array (4); A nonlinear distortion compensation system comprising:

6. The nonlinear distortion compensation system (1) according to any one of claims 1 to 3, further comprising: - means (55) for converting at least one physical magnitude characteristic of the first radio power amplifier (2) and / or the first load (12); - means (56) for amplifying the output of the converting means (55) to magnify fluctuations associated with the operation of either the first radio power amplifier (2) and / or the first load (12); - third conversion means (57) for converting the output of said amplification means (56) into a digital value; a fifth memory array (58) adapted to store a plurality of outputs of said third conversion means (57) and connected to said first calculation means (20) so that the values ​​contained therein are available to the latter together with the values ​​contained in said second memory array (16); sixth interface means (59) for interfacing said third conversion means (57) with said fifth memory array (58) so that the output of the former is stored in the latter; A nonlinear distortion compensation system comprising:

7. The nonlinear distortion compensation system (1) according to claim 6, further comprising: - modification means (60) interposed between said first memory array (4) and said first calculation means (20) for modifying the values ​​of the parameters belonging to the algebraic formulas stored in said first memory array (4); Equipped with ° a sixth memory array (61) adapted to store a plurality of outputs of said third conversion means (57); ° seventh interface means (62) for interfacing said third conversion means (57) with said sixth memory array (61) such that an output of the former is stored in the latter whenever said third logic signal (19) is asserted; ° subtraction means (63) for subtracting values ​​contained in said sixth memory array (61) from values ​​contained in said fifth memory array (58); ° a seventh memory array (64) adapted to store a plurality of coefficient values ​​corresponding to the values ​​stored in said fifth and sixth memory arrays (58, 61); ° third multiplying means (65) for multiplying the output of said subtraction means (63) by corresponding coefficient values ​​stored in said seventh memory array (64); ° eight memory arrays (66) adapted to store values ​​of a plurality of parameters belonging to the algebraic formula output by the first calculation means (20) and connected to the same parameters instead of the first memory array (4); ° third adding means (67) for adding the output of said third multiplying means (65) to the values ​​contained in said eight memory arrays (66); ° seventh interface means (68) for interfacing said third summing means (67) with said first memory array (4) so ​​that the output of the former is stored in the latter; and therefore said first memory array (4) and said calculation means (20) are connected by the same means, A nonlinear distortion compensation system comprising:

8. The nonlinear distortion compensation system (1) according to any one of claims 1 to 3, further comprising a second selection means for selecting: an output of said extraction means (11) when the fourth logic signal (70) is not asserted; Otherwise, the output of the first modulation means (9) when the fourth logic signal (70) is asserted; and providing the selected signal as an input to the first demodulation means (13) such that the extraction means (11) and the first demodulation means (13) are connected by the same means; the control means (17) is adapted to emit the fourth logic signal (70) in addition to the first logic signal (8) upon assertion of the second logic signal (18), and measures the response of the combination of the first modulation means (9), the first demodulation means (13) and the measurement means (14) separately without the nonlinear distortion introduced by the first radio power amplifier (2) and the same response additionally combined with the nonlinear distortion introduced by the first radio power amplifier (2), such that the output of the measurement means (14) is stored in the second memory array (16) both when the fourth logic signal (70) is asserted and when it is not asserted. A nonlinear distortion compensation system comprising:

9. The nonlinear distortion compensation system (1) according to any one of claims 1 to 3, further comprising: a second load (71); - means (72) for switching between: ° one output of said extraction means (11) for transmission to said first load (12) when said first logic signal (8) is not asserted; Otherwise, ° one output of said extraction means (11) for transmission to said second load (71) when said first logic signal (8) is asserted; Equipped with Thus, the extraction means (11) and the second load (71) are connected by the same means. A nonlinear distortion compensation system comprising:

10. The nonlinear distortion compensation system (1) according to any one of claims 1 to 3, further comprising: - second acquisition means (72) for acquiring a second baseband signal consisting of digital values; fourth evaluation means (73) for evaluating an algebraic expression as a function of the output of said second obtaining means (72) and for evaluating the algebraic expression based on the parameter values ​​stored in said first memory array (4); - fourth conversion means (74) for converting the output of the fourth evaluation means (73) into an analog signal; second modulation means (75) for modulating the output of said fourth conversion means (74) to a higher frequency by mixing it with the carrier signal emitted by said local oscillator (10); a second radio power amplifier (76) having as input the output of said second modulation means (75); a third load (77) connected to the output of the second radio power amplifier (76); A nonlinear distortion compensation system comprising:

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