Circuit correction method applied to circuit pattern misalignment

Abstract

To provide a circuit correction method and a circuit structure, which are adopted for a pattern deviation having excellent electric quality by collection of a circuit position and an impedance.SOLUTION: A method contains: a step of installing a chip onto a carrier; a step of performing circuit position collection of a pattern of a re-wiring layer by measuring an off-set amount of the chip, and calculating an impedance difference before and after the correction of the circuit position collection; a step of evaluating a circuit occupation ratio and an impedance change range that require the impedance correction from a pattern of the re-wiring layer on the basis of the impedance difference; a step of determining a plan of a correction position and the circuit occupation ratio, and adjusting the line width, the area, the length, the diagram, or the combination of them of the circuit in the circuit occupation ratio on the basis of the impedance difference; a step of outputting an image file of the pattern obtained by performing the circuit position correction of the re-wiring layer and impedance correction; and a step of forming the re-wiring layer onto a carrier on the basis of the image file, and electrically connecting the re-wiring layer to the chip.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit correction method and a circuit structure, and also to a circuit correction method and a circuit structure that are applied to pattern misalignment. [Background technology]

[0002] In the chip-first chip packaging process, contact signals cannot be connected accurately due to chip misalignment, so a compensation design for the conductive circuit corresponding to the chip offset is performed to ensure accurate connection between the chip and the conductive circuit. However, after the compensation design, the length of the conductor wire changes, changing the impedance value of the circuit, which causes the electrical quality of the chip package to differ from what was expected.

[0003] On the other hand, in the redistribution layer first (RDL first) chip packaging process, the difference in thermal expansion coefficients between dielectric and metal materials causes different offsets in the circuits on a large substrate, resulting in offsets in all the circuits on each layer. To prevent inaccurate connection to the pads when the chip is finally bonded to the redistribution layer, the pad positions can be corrected by adjusting the circuit layer. However, after the correction design, the circuit's electrical quality will not match the expected quality because the length of the conductors will change and the impedance value of the circuit will change. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a circuit correction method applied to pattern misalignment, which can make the circuit structure have excellent electrical quality through circuit position correction and impedance correction.

[0005] Embodiments of the present invention provide circuit structures with excellent electrical qualities. [Means for solving the problem]

[0006] One embodiment of the present invention provides a circuit correction method applicable to pattern misalignment, including the steps of: placing at least one chip on a carrier; measuring the offset amount of the chip to perform circuit position correction on a default redistribution layer pattern, and calculating the impedance difference of the redistribution layer pattern before and after the circuit position correction; evaluating, based on the impedance difference, the circuit occupancy rate and impedance change range of the redistribution layer pattern that require impedance correction after the circuit position correction; determining a correction position and circuit occupancy plan, and, based on the impedance difference, adjusting the line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy rate; outputting an image file of the redistribution layer pattern after the circuit position correction and impedance correction; and forming a redistribution layer on the carrier based on the image file, and electrically connecting the redistribution layer to the chip.

[0007] One embodiment of the present invention provides a circuit correction method applicable to pattern misalignment, including the steps of stacking a multilayer circuit on a carrier; measuring the offset amount of the multilayer circuit and performing circuit position correction on a default pattern of an upper circuit to be formed on the multilayer circuit so as to enable normal signal connection; calculating the impedance difference between the pattern of the upper circuit after the circuit position correction and the default pattern; adjusting the line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy of the pattern of the upper circuit after the circuit position correction based on the impedance difference to achieve impedance correction; outputting the pattern of the upper circuit after the circuit position correction and impedance correction; and forming the upper circuit on the multilayer circuit based on the pattern of the upper circuit after the circuit position correction and impedance correction.

[0008] One embodiment of the present invention provides a circuit structure including a carrier, a redistribution layer, and at least one chip. The redistribution layer is disposed on the carrier and has a normal circuit and an impedance compensation structure connected to each other, the impedance compensation structure being located in a first region and the normal circuit being located in a second region. The impedance compensation structure has a circuit occupancy rate and has a different line width, area, length, shape, or combination thereof from the normal circuit. The at least one chip is disposed on the carrier and electrically connected to the redistribution layer. The impedance of the circuit structure does not change due to chip misalignment. [Effects of the Invention]

[0009] The circuit correction method applied to the pattern misalignment in the embodiment of the present invention forms a redistribution layer or an upper circuit by circuit position correction and impedance correction, so that a circuit structure with excellent electrical quality can be formed. The circuit structure in the embodiment of the present invention adopts an impedance correction structure, so that the circuit structure has excellent electrical characteristics. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a flowchart of a circuit correction method applied to pattern misalignment in one embodiment of the present invention. [Figure 2A] 2 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2B] 2 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2C] 2 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2D] 2 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2E]2 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 3] FIG. 2D is a curve diagram showing the change in impedance of the circuit of FIG. 2C with line width correction. [Figure 4A] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4B] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4C] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4D] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4E] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4F] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4G] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4H] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4I] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4J] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 4K] 2A and 2B are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1. [Figure 5A] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5B] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5C] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5D] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5E] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5F] FIG. 2 is a top view schematic diagram of a circuit structure of one embodiment of the present invention after impedance correction. [Figure 6] 10 is a process flowchart of a circuit correction method applied to pattern misalignment according to another embodiment of the present invention. [Figure 7A] 7 is a top schematic view showing one step of the process of the circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7B] 7 is a top schematic view showing one step of the process of the circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7C] 7 is a top schematic view showing one step of the process of the circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7D] 7 is a top schematic view showing one step of the process of the circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7E] 7 is a top schematic view showing one step of the process of the circuit correction method applied to the pattern misalignment of FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a flowchart of a circuit correction method applied to pattern misalignment according to one embodiment of the present invention, and FIGS. 2A to 2E are top schematic views illustrating the process of the circuit correction method applied to the pattern misalignment of FIG. 1. Referring to FIGS. 1 and 2A to 2E, the circuit correction method applied to pattern misalignment according to this embodiment includes the following steps. First, as shown in FIG. 2A, step S110 is performed to place at least one chip 110 on a carrier 120. For example, the chip 110 is bonded to the carrier 120. During the bonding process, an offset amount relative to the default position of the chip may exist due to alignment errors and other factors. Next, as shown in FIGS. 2B and 2C, step S120 is performed to measure the offset amount of the chip 110 and perform circuit position correction with respect to the default redistribution layer pattern 200 (shown in FIG. 2B). After the circuit position correction, a redistribution layer pattern 300 (shown in FIG. 2C) is formed. The impedance difference between the redistribution layer pattern before and after the circuit position correction (i.e., the impedance difference between the redistribution layer pattern 200 and the redistribution layer pattern 300) is calculated. Then, as shown in FIG. 2D , step S130 is performed to evaluate the circuit occupancy rate and impedance change range of the redistribution layer pattern 300 after circuit position correction based on the impedance difference. In this embodiment, the circuit occupancy rate of region A1 is, for example, 20%, the circuit occupancy rate of region A2 is, for example, 50%, and the circuit occupancy rate of region A3 is, for example, 10%. Here, the circuit occupancy rate refers to the ratio of the area of ​​the circuit 310 in the region where impedance correction is to be performed (e.g., region A1, region A2, or region A3) to the area of ​​the entire circuit 310 including the contacts 301 and 302. Next, a correction position and circuit occupancy plan are determined (i.e., which region of the circuit 310 to use for impedance correction and its circuit occupancy rate are determined), and the line width, area, length, shape, or a combination thereof of the circuit 310 within the circuit occupancy rate is adjusted based on the impedance difference. In this embodiment, for example, a case where the line width of the circuit 310 is adjusted is taken as an example.

[0012] In this embodiment, step S140 is continued to determine whether the line width adjustment range for impedance compensation is smaller than the assistable range of the exposure machine. If the answer is "No," the following step S150 is continued. If the answer is "Yes," a circuit occupancy ratio solution is reselected. For example, the circuit occupancy ratio is reduced (i.e., a smaller circuit occupancy ratio is selected). Specifically, when an exposure machine fabricates a circuit using a photolithography process, there is a detection limit. If the line width change is too small, the exposure machine cannot detect it and the process becomes unfeasible. In this case, by reducing the circuit occupancy ratio, the degree of line width adjustment corresponding to the impedance difference can be increased, thereby enabling the exposure machine to detect it and reaching the assistable range.

[0013] Next, step S150 is performed to output an image file in which the circuit position and impedance of the redistribution layer pattern have been corrected. Then, as shown in FIG. 2E, step S160 is performed to form the redistribution layer 400 on the carrier 120 based on the image file, and the redistribution layer 400 is electrically connected to the chip 110. Here, as can be seen from the enlarged view in FIG. 2E, the circuit 310 of the redistribution layer 400 has a wider line width.

[0014] FIG. 3 is a curve diagram showing the change in impedance of the circuit of FIG. 2C with linewidth correction. Referring to FIGS. 2C, 2D, and 3, the impedance value of the circuit 310 of the redistribution layer pattern 300 after circuit position correction, but before impedance correction (e.g., linewidth correction), is between approximately 1.75 and 1.76, which is slightly different from the design value between 1.67 and 1.68. As can be seen from the change curve in FIG. 3, when the linewidth of the circuit 310 is corrected by 4.4 micrometers, the impedance of the circuit 310 can be restored to the design value. The detection range for linewidth correction of an exposure machine is, for example, 2 to 5 micrometers, and 4.4 micrometers falls within this range, so the linewidth correction of 4.4 micrometers fits within the supportable range of the exposure machine.

[0015] Table 1 below shows some examples of the above circuit occupancy rate schemes (i.e., the correction schemes of Table 1).

[0016] [Table 1]

[0017] For example, in correction scheme A, if the circuit occupancy rate is 10% and the absolute value of the impedance difference is 10% or less, the linewidth or area ratio of the circuit 310 (i.e., the linewidth correction in Table 1) is adjusted to be greater than 0% and less than or equal to 100% in response. Here, the linewidth correction may be an increase in linewidth or a decrease in linewidth. Similarly, if the circuit occupancy rate is 10% and the absolute value of the impedance difference is greater than 10% and less than or equal to 20%, the linewidth or area ratio of the circuit 310 (i.e., the linewidth correction in Table 1) is adjusted to be greater than 100% and less than or equal to 200% in response. The physical meanings of other situations in Table 1 can be inferred from this. For example, in correction scheme B, if the circuit occupancy rate is 20% and the absolute value of the impedance difference is 10% or less, the linewidth or area ratio (i.e., the linewidth correction in Table 1) is adjusted to be greater than 0% and less than or equal to 50% in response. The physical meanings of other situations and other correction schemes in Table 1 can be inferred from this. In other embodiments, other correction schemes may simultaneously select two regions in circuit 310 with different circuit occupancy rates and perform impedance correction (e.g., linewidth correction). For example, two regions in circuit 310 with circuit occupancy rates of 10% and 20%, respectively, are selected, and impedance correction (e.g., linewidth correction) is performed on both of them. In other embodiments, three or more regions in circuit 310 with different circuit occupancy rates may simultaneously be selected and impedance correction (e.g., linewidth correction) is performed.

[0018] In this embodiment, a region (e.g., region A1) in the redistribution layer pattern 300 after circuit position correction where the line spacing is relatively large is used as an impedance correction region. In this embodiment, the chip 110 is a low-frequency signal chip. For example, in one embodiment, the chip 110 is a display panel driving chip, and its frequency is in the range of 1 Hz to 10 kHz. Alternatively, in one embodiment, the chip 110 is a micro light-emitting diode chip.

[0019] The circuit correction method applied to the pattern misalignment of this embodiment forms the redistribution layer 400 through circuit position correction and impedance correction, thereby forming a circuit structure with excellent electrical quality. In addition, the circuit correction method applied to the pattern misalignment of this embodiment is applicable to a chip first process.

[0020] 4A to 4K illustrate various embodiments of the impedance compensation shown in FIG. 1, each showing a schematic top view of the circuit before and after impedance compensation. Referring to FIG. 4A, if the impedance of the circuit 310 increases after circuit position compensation, the line width of the circuit 310 can be increased to lower the impedance and form an impedance compensation structure 312a. Referring to FIG. 4B, if the impedance of the circuit 310 decreases after circuit position compensation, both sides of the circuit can be bent 90 degrees to increase the circuit length, thereby increasing the impedance and forming an impedance compensation structure 312b. Referring to FIG. 4C, if the impedance of the circuit 310 decreases after circuit position compensation, one side of the circuit can be bent 90 degrees to increase the circuit length, thereby increasing the impedance and forming an impedance compensation structure 312c. Referring to FIG. 4D, if the impedance of the circuit 310 decreases after circuit position compensation, the impedance can be increased by bending the circuit 45 degrees to increase the circuit length, thereby forming an impedance compensation structure 312d. Referring to FIG. 4E, when the impedance of the circuit 310 increases after the circuit position correction, the impedance can be reduced by adding at least one wide block 311e to the circuit, thereby forming an impedance compensation structure 312e. Referring to FIG. 4F, when the impedance of the circuit 310 decreases after the circuit position correction, the connection between the partial region 311f of the circuit and other regions can be reduced. For example, the impedance can be increased by shrinking the connection portion 313f, thereby forming an impedance compensation structure 312f.

[0021] Referring to FIG. 4G, when the impedance of the circuit 310 decreases after the circuit position correction, the line width of the circuit can be reduced to increase the impedance, thereby forming an impedance compensation structure 312g. Referring to FIG. 4H, when the impedance of the circuit 310 decreases after the circuit position correction, the partial region 311h of the circuit can be removed to increase the impedance, thereby forming an impedance compensation structure 312h. Here, the partial region 311h is, for example, a square region. Referring to FIG. 4I, when the impedance of the circuit 310 decreases after the circuit position correction, the partial region 311i of the circuit can be removed to increase the impedance, thereby forming an impedance compensation structure 312i. Here, the partial region 311i is, for example, a circular region. In other embodiments, the partial region 311i may have a different shape. Referring to FIG. 4J, when the impedance of the circuit 310 decreases after the circuit position correction, the partial region 311j of the circuit can be removed to increase the impedance, thereby forming an impedance compensation structure 312j. Here, the partial region 311j is, for example, located on the edge of the circuit and is, for example, a square region. However, in other embodiments, the partial region 311j may be a region of another shape. Referring to FIG. 4K, when the impedance of the circuit 310 increases after the circuit position correction, a portion of the circuit can be enlarged to form an enlarged region 311k, thereby lowering the impedance and forming an impedance correction structure 312k. In other embodiments, the enlarged region 311k may be another region capable of increasing the line width.

[0022] 5A to 5E are schematic top views of circuit structures according to several embodiments of the present invention, before and after impedance compensation. First, referring to FIG. 5A, the circuit structure 500 of this embodiment includes a carrier 120, a redistribution layer 400, and at least one chip 110. The redistribution layer 400 has a normal circuit 314 and at least one impedance compensation structure 312 disposed on the carrier 120 and connected to each other. The impedance compensation structure 312 may have a different line width, area, length, shape, or a combination thereof from the normal circuit 314. In FIG. 5A, the impedance compensation structure 312 has a different line width or area. In this embodiment, the line width and area of ​​the impedance compensation structure 312 are larger than those of the normal circuit 314, thereby effectively lowering the impedance of the circuit. The at least one chip 110 is disposed on the carrier 120 and electrically connected to the redistribution layer 400. In this embodiment, the at least one chip 110 is a plurality of chips 110, and can be divided into a driving chip 112 and a micro light-emitting diode chip 114, and the driving chip 112 is used to drive the micro light-emitting diode chip 114 through the redistribution layer 400 to make it emit light.

[0023] In this embodiment, the circuit structure 500 can be fabricated by the circuit compensation method applied to the pattern misalignment of Figure 1. By adopting the impedance compensation structure 312, the circuit structure 500 can have excellent electrical quality.

[0024] The circuit structure 500 can also be applied to a circuit structure such as that shown in FIG. 2E. The impedance compensation structure 312 is located in a first region (e.g., region A1, A2, or A3 in FIG. 2E), and the normal circuit 314 is located in a second region (e.g., the remaining region other than the first region). The circuit occupancy rate of the impedance compensation structure 312 may be as described in the embodiment of Table 1 above. For example, the circuit structure created in compensation scheme A has a circuit occupancy rate of 10%, an absolute value of the impedance difference caused by chip misalignment of the normal circuit 314 in the redistribution layer 400 is 10% or less, and the ratio of the line width change or area change of the impedance compensation structure 312 to the normal circuit 314 is greater than 0% but less than 100%. The circuit structure generated by compensation scheme B has a circuit occupancy rate of 20%, an absolute value of the impedance difference caused by the chip misalignment of the normal circuit 314 of the redistribution layer 400 is 10% or less, and the ratio of the line width change or area change of the impedance compensation structure 312 to the normal circuit 314 is greater than 0% and less than 50%. The details of the other compensation schemes of the embodiments in Table 1 above can be inferred from this and will not be repeated here.

[0025] Furthermore, in one embodiment, as shown in FIG. 5F , the line spacing D1 of the end E1 where the normal circuit 314 and the impedance compensation structure 312 connect to each other is larger than the average line spacing of the normal circuit 314. For example, the end E1 where the normal circuit 314 and the impedance compensation structure 312 connect to each other is located in an area with a relatively large line spacing (e.g., the line spacing D1 in area A1 of FIG. 5F is larger than the line spacing D2 between the normal circuits 314 in area A2, and the impedance compensation structure 312 is located in area A1). Here, the average line spacing of the normal circuits 314 can be defined as the area of ​​the spacing region between two adjacent normal circuits 314 divided by the total length of one of the two adjacent normal circuits 314.

[0026] 5B to 5E are similar to the circuit structure 500 of FIG. 5A, but differ mainly in the impedance compensation structure employed in the redistribution layer. Each will be described in detail below.

[0027] Referring to Figure 5B, the redistribution layer 400a of the circuit structure 500a of this embodiment employs the impedance compensation structure 312j of Figure 4J to increase the impedance of the circuit. Referring to Figure 5C, the redistribution layer 400b of the circuit structure 500b of this embodiment employs the impedance compensation structure 312' to decrease the impedance of the circuit. Here, the impedance compensation structure 312' is similar to the impedance compensation structure 312 of Figure 5A, but by comparison, the impedance compensation structure 312' has a smaller area and is more numerous.

[0028] Referring to Figure 5D, the redistribution layer 400c of the circuit structure 500c of this embodiment employs the impedance compensation structure 312c of Figure 4C to increase the impedance of the circuit. Referring to Figure 5E, the redistribution layer 400d of the circuit structure 500d of this embodiment employs a structure similar to Figure 4F to reduce the connection between the partial region 311f and other regions of the circuit, thereby increasing the impedance and forming the impedance compensation structure 312f'. In other embodiments, the redistribution layer of the circuit structure may employ the impedance compensation structures 312a-312k of Figures 4A-4K to increase or decrease the impedance.

[0029] FIG. 6 is a flowchart of a circuit correction method applied to pattern misalignment according to another embodiment of the present invention, and FIGS. 7A to 7E are top schematic views illustrating the process of the circuit correction method applied to pattern misalignment in FIG. 6. Referring to FIGS. 6 and 7A to 7E, the circuit correction method applied to pattern misalignment according to this embodiment includes the following steps. First, as shown in FIG. 7A, step S210 is performed to stack a multilayer circuit 210 on a carrier 120. Here, this multilayer circuit 210 is, for example, a redistribution layer. In this embodiment, the carrier 120 is, for example, larger in size than a G2.5 generation display panel, for example, with a length and width greater than 370 mm and 470 mm, respectively. That is, the carrier 120 is, for example, a large carrier. During the manufacturing process of the redistribution layer, offset situations are likely to occur in the circuits on the large carrier due to differences in the thermal expansion coefficients of dielectric materials and metal materials, which results in offsets in the circuits on each layer of the multilayer circuit 210. At this time, step S220 is subsequently performed to measure the offset of the multilayer circuit 210 and perform circuit position correction on the default upper circuit pattern 220 (e.g., as shown in FIG. 7B ) to be formed on the multilayer circuit 210. For example, as shown in FIG. 7C , the upper circuit pattern 320 is corrected to ensure proper signal connection. Specifically, the circuit correction method applied to the pattern misalignment of this embodiment can be applied to a redistribution layer first (RDL first) process. Because the multilayer circuit 210 already has an offset, when the default upper circuit pattern 220 is formed on it, the pad position 222 of the default upper circuit pattern 220 may be offset from the default pad position P1 to which the chip 110 is to be bonded. After the circuit position correction, the pad position 322 of the upper circuit pattern 320 is adjusted to coincide with the default pad position P1.

[0030] Next, step S230 is performed to calculate the impedance difference between the pattern 320 (e.g., as shown in FIG. 7C ) after the circuit position correction of the upper circuit and the default pattern 220 (e.g., as shown in FIG. 7B ). Then, step S240 is performed to achieve impedance correction by adjusting the line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy of the upper circuit pattern 320 after the circuit position correction based on the impedance difference. That is, the upper circuit pattern 330 is corrected as shown in FIG. 7C . Here, the method for adjusting the circuit occupancy and line width, area, length, shape, or a combination thereof may be the same as in the above-mentioned embodiments, and therefore will not be described again here. That is, before impedance correction, the circuit occupancy and impedance change range of the upper circuit pattern 320 after the circuit position correction that require impedance correction can be evaluated based on the impedance difference. Next, a plan for the correction position and circuit occupancy is determined, and impedance correction is performed. In one embodiment, the area of ​​the upper circuit pattern 320 after the circuit position correction, where the line spacing is relatively large, is used as the area for impedance correction.

[0031] Then, step S250 is executed to determine whether the line width adjustment range of the impedance compensation is smaller than the auxiliary range of the exposure machine. If the answer is "No," the following step S260 is executed. If the answer is "Yes," a circuit occupancy ratio scheme is reselected. For example, the circuit occupancy ratio is reduced (i.e., a smaller circuit occupancy ratio is selected). The method for reselecting the circuit occupancy ratio scheme is the same as that described in the above embodiment, and will not be described again here.

[0032] Next, step S260 is performed to output upper circuit pattern 330 (for example, as shown in FIG. 7D) after circuit position correction and impedance correction. Thereafter, as shown in FIG. 7E, step S270 is performed to form upper circuit 410 on multilayer circuit 210 based on upper circuit pattern 330 after circuit position correction and impedance correction.

[0033] In this embodiment, the circuit correction method applied to the pattern misalignment further includes the steps of placing at least one chip 110 on the upper circuit 410 and electrically connecting the chip 110 to the upper circuit 410. The chip 110 is the chip 110 described in the above embodiment, and therefore will not be described again here.

[0034] In the circuit correction method applied to the pattern misalignment of this embodiment, the upper circuit is formed by circuit position correction and impedance correction, so that the circuit structure 500e having excellent electrical quality can be formed.

[0035] As described above, the circuit correction method applied to the pattern misalignment in the embodiment of the present invention forms a redistribution layer or an upper circuit by circuit position correction and impedance correction, and therefore, a circuit structure with excellent electrical quality can be formed. The circuit structure in the embodiment of the present invention employs an impedance correction structure, and therefore, the circuit structure has excellent electrical characteristics.

[0036] Although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention, and a person having ordinary knowledge in the art can make some changes and improvements without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be defined by the claims set forth below. [Industrial Applicability]

[0037] The circuit correction method and circuit structure applied to the pattern misalignment of the present invention can be used in the process and structure of chip packaging. [Explanation of symbols]

[0038] 110 chips 112 Drive Chip 114 Micro Light Emitting Diode Chip 120 Career 200, 300 Redistribution layer pattern 210 Multilayer circuit 220 Upper Circuit Default Pattern 222, 322 pad positions 301, 302 Contact 310 circuits 311e Block 311f, 311h, 311i, 311j partial area 311k Expanded Area 312, 312', 312a, 312b, 312c, 312d, 312e, 312f, 312f', 312g, 312h, 312i, 312j, 312k Impedance compensation structure 313f connection 314 Normal circuit 320, 330 Upper circuit pattern 400, 400a, 400b, 400c, 400d redistribution layer 410 Upper Circuit 500, 500a, 500b, 500c, 500d, 500e circuit structure A1, A2, A3 area D1, D2 line spacing E1 end P1 Pad default position S110~S160, S210~S270 steps

Claims

1. placing at least one chip on a carrier; measuring an offset amount of the chip, correcting a circuit position with respect to a default redistribution layer pattern, and calculating an impedance difference between before and after the circuit position correction of the redistribution layer pattern; a step of evaluating a circuit occupancy rate and an impedance change range that require impedance correction in the pattern of the rewiring layer after circuit position correction based on the impedance difference; determining a correction position and circuit occupancy scheme, and adjusting the line width, area, length, shape, or a combination thereof, of the circuit within the circuit occupancy based on the impedance difference; outputting an image file of the rewiring layer pattern after the circuit position correction and the impedance correction have been performed; forming the redistribution layer on the carrier based on the image file, and electrically connecting the redistribution layer to the chip; A circuit correction method applied to a circuit pattern deviation, comprising:

2. 2. The circuit correction method applied to circuit pattern misalignment according to claim 1, wherein, when the circuit occupancy rate is 10% and the absolute value of the impedance difference is 10% or less, the ratio of the line width or the area is adjusted in response to the circuit occupancy rate to be greater than 0% and less than 100%.

3. 2. The circuit correction method applied to circuit pattern misalignment according to claim 1, wherein, when the circuit occupancy rate is 20% and the absolute value of the impedance difference is 10% or less, the ratio of the line width or the area is adjusted in response to the circuit occupancy rate to be greater than 0% and less than 50%.

4. 2. The circuit correction method applied to a circuit pattern misalignment according to claim 1, wherein a region of the pattern of the rewiring layer after the circuit position correction, in which the line spacing is relatively large, is used as the region of the impedance correction.

5. 2. The circuit correction method for circuit pattern misalignment according to claim 1, further comprising the step of reselecting the circuit occupancy rate scheme in response to the impedance correction when the line width adjustment range of the impedance correction is smaller than the auxiliary range of the exposure machine.

6. laminating a multi-layer circuit on a carrier; measuring an offset amount of the multilayer circuit and correcting the circuit position with respect to a default pattern of an upper circuit to be formed on the multilayer circuit so that signals can be connected normally; calculating an impedance difference between the pattern after the circuit position correction of the upper circuit and a default pattern; adjusting the line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy of the pattern of the upper circuit after the circuit position correction based on the impedance difference to achieve impedance correction; outputting a pattern of the upper circuit after the circuit position correction and the impedance correction; forming the upper circuit on the multilayer circuit based on the pattern of the upper circuit after the circuit position correction and the impedance correction are performed; A circuit correction method applied to a circuit pattern deviation, comprising:

7. The circuit correction method applied to circuit pattern misalignment according to claim 6, further comprising the steps of: placing at least one chip on the upper circuit; and electrically connecting the chip to the upper circuit.

8. a step of evaluating, before the impedance correction, a circuit occupancy rate and a change range of impedance that require impedance correction among the patterns of the upper circuit after the circuit position correction is performed, based on the impedance difference; determining a correction position and a circuit occupancy rate scheme and performing the impedance correction; The circuit correction method applied to a circuit pattern misalignment according to claim 6, further comprising:

9. 9. The circuit correction method applied to circuit pattern misalignment according to claim 8, wherein, when the circuit occupancy rate is 10% and the absolute value of the impedance difference is 10% or less, the ratio of the line width or the area is adjusted in response to the circuit occupancy rate to be greater than 0% and less than 100%.

10. 9. The circuit correction method applied to circuit pattern misalignment according to claim 8, wherein when the circuit occupancy rate is 20% and the absolute value of the impedance difference is 10% or less, the ratio of the line width or the area is adjusted to be greater than 0% and not greater than 50%.

11. 9. The circuit correction method for circuit pattern misalignment according to claim 8, further comprising the step of reselecting the circuit occupancy rate scheme in response to the impedance correction when the line width adjustment range of the impedance correction is smaller than the auxiliary range of the exposure machine.

12. 7. The circuit correction method applied to a circuit pattern misalignment according to claim 6, wherein an area of ​​the pattern of the upper circuit after the circuit position correction, where the line spacing is relatively large, is used as the area of ​​the impedance correction.

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