Multilayer electronic component and its manufacturing method

Abstract

To provide a reliable multilayer electronic component and a method of manufacturing the same.SOLUTION: A multilayer electronic component includes: a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body. The dielectric layer includes a plurality of dielectric crystal grains. The dielectric crystal grains include one or more first dielectric crystal grains in which a sum of lengths of defects in a dielectric crystal grain is 150 nm or more.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component and a method for manufacturing the same. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products, such as visual devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and serve to charge and discharge electricity.

[0003] Such multilayer ceramic capacitors have the advantages of being small in size, having high capacitance, and being easy to mount, and can be used as components in various electronic devices. As various electronic devices, such as computers and mobile devices, become smaller and have higher output, there is an increasing demand for multilayer ceramic capacitors that are smaller in size and have higher capacitance.

[0004] In addition, as the market for MLCCs for automotive electrical equipment expands in addition to IT applications, there is a growing demand for products with high rated voltage and excellent reliability within the same capacity range. Attempts have been made to improve reliability by adding various additives to dielectric powders, but even with the same dielectric composition, significant differences in reliability can occur depending on the microstructure, the distribution and degree of solid solution of additive elements, and process conditions. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Publication No. 10-2016-0073243 Summary of the Invention [Problem to be solved by the invention]

[0006] One of the problems to be solved by the present invention is to provide a highly reliable multilayer electronic component and a method for manufacturing the same.

[0007] One of the problems to be solved by the present invention is to provide a multilayer electronic component having excellent room temperature dielectric constant, DC-bias characteristics, and high temperature withstand voltage characteristics, and a method for manufacturing the same.

[0008] One of the problems to be solved by the present invention is to provide a multilayer electronic component that can satisfy the X7R or X7S capacitance-temperature characteristics, and a method for manufacturing the same.

[0009] One of the problems to be solved by the present invention is to provide a highly reliable multilayer electronic component and a method for manufacturing the same by generating defects in crystal grains.

[0010] One of the problems to be solved by the present invention is to provide a multilayer electronic component in which Si element exists in a solid solution state in the grain boundary region of the crystal lattice of a dielectric, and a method for manufacturing the same.

[0011] However, some of the problems that the present invention aims to solve are not limited to the above content, and can be more easily understood in the course of describing specific embodiments of the present invention. [Means for solving the problem]

[0012] A multilayer electronic component according to one embodiment of the present invention includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the body, wherein the dielectric layer includes a plurality of dielectric crystal grains, and the plurality of dielectric crystal grains may include one or more first dielectric crystal grains in which the sum of lengths of defects in the dielectric crystal grains is 150 nm or more.

[0013] According to another embodiment of the present invention, a method for manufacturing a multilayer electronic component includes: milling a dielectric composition containing a dielectric powder as a main component and including a solvent and a dispersant; adding a binder to the dielectric composition and further milling the resulting mixture to form a slurry; forming ceramic green sheets using the slurry; printing a conductive paste for internal electrodes on the ceramic green sheets and laminating them to form a laminate; firing the laminate to form a body including dielectric layers and internal electrodes; and forming external electrodes on the body, wherein the milling step can be performed to include at least one first dielectric crystal grain in which the sum of lengths of defects in the dielectric crystal grains included in the dielectric layer is 150 nm or more. [Effects of the Invention]

[0014] One of the various effects of the present invention is that it improves the reliability of multilayer electronic components.

[0015] One of the various effects of the present invention is that it improves the room temperature dielectric constant, DC-bias characteristics, and high temperature withstand voltage characteristics of a multilayer electronic component.

[0016] One of the various effects of the present invention is that it can satisfy the X7R or X7S capacitance-temperature characteristics of a multilayer electronic component.

[0017] One of the various effects of the present invention is that defects are generated within the dielectric crystal grains, thereby improving the reliability of the multilayer electronic component.

[0018] One of the various effects of the present invention is that the Si element can exist in a solid solution state in the grain boundary region of the crystal lattice of the dielectric.

[0019] However, the various beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a schematic perspective view of a multilayer electronic component according to an embodiment of the present invention; [Figure 2] 1 is an exploded perspective view schematically illustrating a main body of a multilayer electronic component according to an embodiment of the present invention. [Figure 3] 2 is a schematic cross-sectional view taken along line II' of FIG. 1. [Figure 4] 2 is a schematic cross-sectional view taken along line II-II' in FIG. 1. [Figure 5] 4 is a schematic enlarged view of a region P in FIG. 3. [Figure 6] 1 is a schematic representation of a dielectric grain containing dislocations. [Figure 7] (a) is a TEM image of a comparative example that does not contain dislocations inside the dielectric crystal grains, and (b) is a TEM image that includes an amorphous layer in the region near the grain boundary of the dielectric crystal lattice. [Figure 8] This is a TEM image showing that domain boundaries are formed inside the dielectric crystal grains. [Figure 9] This is a TEM image showing dislocations formed inside dielectric crystal grains. [Figure 10] (a) is a TEM image of an embodiment including dislocations inside dielectric crystal grains, (b) is an HRTEM image of a grain boundary of a dielectric crystal lattice, and (c) is a STEM-EDS analysis graph of the percentage (at%) of Si element at the dotted line in (b). [Figure 11]11(a) is a TEM image of another embodiment including dislocations inside dielectric crystal grains, (b) is an HRTEM image of a grain boundary of a dielectric crystal lattice, and (c) is a STEM-EDS analysis graph of the percentage (at%) of Si element at the dotted line in FIG. 11(b). [Figure 12] 10A to 10C are manufacturing process diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shape and size of elements in the drawings may be exaggerated for clarity, and elements designated by the same reference numerals in the drawings are the same elements.

[0022] In addition, in the drawings, parts that are not relevant to the description are omitted in order to clearly explain the present invention, and the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to those shown. Components that have the same function within the same concept will be described using the same reference numerals. Furthermore, throughout the specification, when a part is said to "include" a certain component, this does not mean that other components are excluded, but that the part may further include other components, unless otherwise specified.

[0023] In the drawings, the first direction can be defined as the stacking direction or thickness T direction, the second direction can be defined as the length L direction, and the third direction can be defined as the width W direction.

[0024] Multilayer electronic components FIG. 1 is a schematic perspective view of a laminated electronic component according to one embodiment of the present invention, FIG. 2 is an exploded perspective view of the main body of a laminated electronic component according to one embodiment of the present invention, FIG. 3 is a schematic cross-sectional view taken along line I-I' in FIG. 1, FIG. 4 is a schematic cross-sectional view taken along line II-II' in FIG. 1, FIG. 5 is a schematic enlarged view of region P in FIG. 3, and FIG. 6 is a schematic view of a dielectric crystal grain including dislocations.

[0025] A multilayer electronic component according to one embodiment of the present invention will be described in detail below with reference to Figures 1 to 6. Although a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, the present invention can also be applied to various electronic products that use a dielectric composition, such as inductors, piezoelectric elements, varistors, thermistors, etc.

[0026] A multilayer electronic component 100 according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122, and external electrodes 131 and 132 disposed on the body 110. The dielectric layer 111 includes a plurality of dielectric crystal grains, and the plurality of dielectric crystal grains may include one or more first dielectric crystal grains 10 and 11, in which the sum of the lengths of defects in the dielectric crystal grains is 150 nm or more.

[0027] The body 110 is formed by alternately laminating dielectric layers 111 and internal electrodes 121 and 122 .

[0028] Although there is no particular limitation on the specific shape of the body 110, as shown in the figure, the body 110 may have a hexahedral shape or a similar shape. Due to shrinkage of the ceramic powder contained in the body 110 during the firing process, the body 110 may have a substantially hexahedral shape, although not a hexahedral shape with perfectly straight lines.

[0029] The main body 110 can have a first surface 1 and a second surface 2 that face each other in a first direction, a third surface 3 and a fourth surface 4 that are connected to the first and second surfaces 1 and 2 and face each other in a second direction, and a fifth surface 5 and a sixth surface 6 that face each other in a third direction.

[0030] The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0031] The main body 110 includes an active portion Ac that forms a capacitance and includes a first internal electrode 121 and a second internal electrode 122 that are disposed inside the main body 110 and are alternately disposed so as to face each other with the dielectric layer 111 interposed therebetween, and upper and lower cover portions 112 and 113 that are respectively disposed on both end surfaces of the active portion Ac in the first direction, and can include margin portions 114 and 115 that are disposed on both end surfaces of the active portion Ac in the third direction.

[0032] The raw material for forming the dielectric layer 111 is not limited as long as sufficient capacitance can be obtained. Generally, perovskite (ABO3)-based materials can be used. For example, barium titanate-based materials, lead composite perovskite-based materials, or strontium titanate-based materials can be used. The barium titanate-based material can include BaTiO3-based ceramic powder. Examples of the ceramic powder include BaTiO3, (Ba 1-y , 1-y , y , 1-x , x , <00000​​​​​​​​​​​​​​​​​​​​

[0033] Furthermore, the raw material for forming the dielectric layer 111 may be a powder of barium titanate (BaTiO3) or the like to which various ceramic additives, organic solvents, binders, dispersants, etc. may be added depending on the purpose of the present invention.

[0034] Meanwhile, the dielectric layer 111 may include a dielectric composition described below, and more specifically, the dielectric layer 111 may be formed by sintering the dielectric composition.

[0035] The minor components contained in the dielectric composition may be added as additives in the form of oxides or carbonates, but may exist in the form of a solid solution in BaTiO3 after the dielectric composition is sintered, rather than in the form of oxides or carbonates. However, the content ratio of the major elements of the minor components may be maintained approximately the same before and after sintering, and the content of each element in the dielectric layer 111 after sintering may be calculated based on the contents of the major components and minor components contained in the dielectric composition before sintering.

[0036] Furthermore, the quantitative content of each element contained in the dielectric layer 111 can be measured using a destructive method.

[0037] Specifically, in the measurement method using the destructive method, the multilayer electronic component is crushed, the internal electrodes are removed, and the dielectric portion is selected. The selected dielectric is then quantitatively analyzed for its dielectric components using an apparatus such as an inductively coupled plasma spectroscopy (ICP-OES) or an inductively coupled plasma mass spectrometry (ICP-MS).

[0038] Meanwhile, as the market for MLCCs for automotive electronics expands in addition to IT applications, demand for products with higher rated voltages and superior reliability within the same capacity range is increasing. It is generally known that the smaller the grain size and the more grain boundaries there are, the higher the reliability of a dielectric. The influence of fixed-valence acceptor, variable-valence acceptor transition metal elements, and rare earth elements among the additive elements in MLCC dielectric compositions on reliability is well known. Therefore, conditions for high reliability are generally determined by optimizing the composition ratio of the dielectric additive elements, including these elements. Since the commercialization of BME (Base Metal Electrode) MLCCs, efforts to optimize their composition have been ongoing to improve reliability. However, even with the same dielectric composition, significant differences in reliability can occur depending on the microstructure, the distribution and degree of solid solution of additive elements, and process conditions. Therefore, achieving a specific dielectric microstructure in addition to compositional factors can dramatically improve reliability.

[0039] Current high-capacity BME MLCC dielectrics, such as X5R, X7R, X8R, and Y5V, are based on materials co-doped with fixed valence acceptors (such as Mg and Al) and rare earth elements (such as Y, Dy, Ho, and Er) acting as donors on BaTiO3 or other matrix materials partially containing Ca and Zr. Additives such as variable valence acceptors (such as Mn, V, and Cr), extra Ba, and SiO2 or sintering aids containing SiO2 are also added. To achieve the proper capacitance and insulating properties of high-capacity MLCCs when fired in a reducing atmosphere, suppression of grain growth and reduction resistance are necessary. Adding an appropriate amount of fixed valence acceptors (such as Mg) can achieve these two effects. However, adding only fixed-valence acceptors such as Mg results in poor dielectric strength and reliability. Adding variable-valence acceptors, such as Mn and V, along with transition metal elements and rare earth elements, improves dielectric strength and reliability. Most of these elements are co-doped and dissolve in the shell region of the BaTiO3 matrix crystal grains, forming a core-shell structure that enables stable capacitance and reliability over temperature in MLCCs. Therefore, it is expected that good reliability will be achieved only if these additive elements remain in the secondary phase without segregation and are fully dissolved in the BaTiO3 crystal lattice in the shell region.

[0040] In particular, among the additive elements, Si, which acts as a sintering aid, has an ionic radius of 0.4 Å, which is much smaller than the Ti ionic radius of BaTiO3, 0.61 Å, and is known to be insoluble in the BT lattice. Generally, Si reacts with BaTiO3 to form a secondary phase after sintering.

[0041] However, according to one embodiment of the present invention, defects are disposed inside the dielectric crystal grains, which promotes the diffusion of additive elements into the crystal grains, thereby increasing the reliability of the multilayer electronic component.

[0042] In addition, in BaTiO3, the dissolution of additive elements in the crystal lattice occurs through grain growth or lattice diffusion. Excessive grain growth facilitates the dissolution of additives, increasing the effective doping concentration, but can cause various problems such as reduced temperature-capacity characteristics, DC-bias characteristics, and reliability. Therefore, it is necessary to ensure that the dissolution of additives is facilitated while suppressing grain growth.

[0043] Therefore, according to one embodiment of the present invention, defects are arranged inside the dielectric crystal grains, which can promote the diffusion of additive elements or facilitate the dissolution of Si into the BT crystal lattice in the grain boundary region.

[0044] The multilayer electronic component 100 according to an embodiment of the present invention may include a plurality of dielectric crystal grains in the dielectric layer 111, and the plurality of dielectric crystal grains may include one or more first dielectric crystal grains 10, 10′ in which the sum of the lengths of defects in the dielectric crystal grains is 150 nm or more.

[0045] If the first dielectric crystal grains 10, 10' are not included, in which the sum of the lengths of defects within the dielectric crystal grains is 150 nm or more, the effect of promoting the diffusion of the additive element into the interior of the crystal grains according to the present invention and the effect of promoting the solid solution of Si in the BT crystal lattice in the crystal grain boundary region may be insufficient.

[0046] The length of the defects can be measured by disassembling the multilayer electronic component, observing the dielectric crystal grains forming the dielectric layer using a TEM (Transmission Electron Microscope Energy Dispersive X-ray Spectroscopy), and measuring the length of the defects contained inside the dielectric crystal grains using the TEM device.

[0047] More specifically, the length of defects located within a dielectric crystal grain can be determined by measuring the length of the defects in an image obtained by scanning a TEM sample prepared with a focused ion beam (FIB) in a bright field or dark field image mode. When there are multiple defects, the lengths of all the defects measured by the above method can be added together to determine the length.

[0048] Meanwhile, in the present invention, the defect may include at least one of a line defect (one-dimensional) and a planar defect (two-dimensional).

[0049] Here, a line defect refers to a line-shaped crystal defect that occurs when the atomic arrangement within a crystal grain having the same crystal structure is displaced due to stress, and is also called a dislocation.

[0050] Planar defects can refer to twin planes or twin boundaries, domain boundaries, or grain boundaries. A twin refers to a boundary surface that has the same structure when rotated 180° around the plane, and twins observed in a TEM image appear as substantially straight lines over a wider area. Also, referring to FIG. 8, domain boundaries can be observed inside dielectric crystal grains. When domain boundaries indicated by arrows in FIGS. 8(a) and 8(b) are formed within dielectric crystal grains, bands of a certain thickness can appear repeated like steps.

[0051] According to an embodiment of the present invention, the defects may be dislocations. That is, the multilayer electronic component 100 according to an embodiment of the present invention may include a plurality of dielectric crystal grains in the dielectric layer 111, and the plurality of dielectric crystal grains may include one or more first dielectric crystal grains 10, 10′ in which the sum of the lengths of dislocations within the dielectric crystal grains is 150 nm or more.

[0052] When the defects are dislocations, the effect of promoting the diffusion of the additive element into the interior of the crystal grains and the effect of promoting the solid solution of Si in the BT crystal lattice in the grain boundary region according to the present invention can be significantly improved. In other words, in order to realize the effect of increasing reliability described in this specification, it can be said that it is more preferable that the defects are dislocations.

[0053] The hard milling conditions for forming dislocations activate the surface of BT (BaTiO3-based) particles, promoting the solid solution reaction between BT and additives, and allowing Si to exist in a solid solution state in the BT crystal lattice in the grain boundary region rather than as a secondary phase, further improving reliability.

[0054] When dislocations exist within the crystal grains at a certain level or above, reliability can be significantly improved. In an environment that generates dislocations, the surface of the BaTiO3 base powder is activated, enabling the solid solution of Si elements in the grain boundary region of the BaTiO3 crystal lattice. In this case, the reliability of the multilayer electronic component can be further improved.

[0055] As mentioned above, dislocations, which are line defects, are distinguished from planar defects such as twins, domain boundaries, and grain boundaries, which are planar defects. The specific method for distinguishing dislocations from planar defects is as follows:

[0056] In the case of dislocations, which are line defects, the dislocations are clearly distinguished from the interior of the crystal grains. For example, the dark black line shape inside the crystal grains pointed to by the arrows in FIG. 9(a) corresponds to the dislocation, and the crystal grains containing the dislocations indicated by the arrows are relatively bright white or gray. It can be observed that the light and dark colors of the crystal grains at points or regions symmetrical to the dislocation are substantially the same. However, the observation of a dislocation as a black line shape is due to the observation environment, and it is not always observed as black. Rather than showing a continuous shape from one crystal boundary to another within a crystal grain, dislocations may only contact one crystal boundary and not completely cross the crystal grain, or may form a shape that does not contact the crystal grain boundaries within a dielectric crystal grain. Furthermore, dislocations may generally be observed as curved or bent lines rather than as completely straight lines, but are not limited thereto.

[0057] Grain boundaries, which are planar defects, are similar to dislocations in that they exhibit dark, light-dark black surrounding the grains, as shown in Figure 9(a). However, different grains at symmetrical points or regions about the grain boundary may have substantially different light-dark colors. For example, the grain containing the dislocation indicated by the arrow in Figure 9(a) may be a relatively light-dark white or gray, while the adjacent grains around the grain boundary may be a relatively dark, light-dark gray or a color close to black. However, like dislocations, grain boundaries are not always observed as dark, light-dark black.

[0058] In the case of domain boundaries, which are another type of planar defect, it can be observed that the light and dark colors are substantially different at points or regions symmetrical with respect to the domain boundary, as shown in Figures 8(a) and 8(b). For example, it can be observed that, based on the domain boundary indicated by the arrow, a certain area of ​​relatively bright white and a certain area of ​​relatively dark black or gray are alternately repeated like steps.

[0059] In this way, the difference between dislocations and planar defects can be distinguished depending on whether there is a difference in brightness between regions symmetrical with respect to the defect, or depending on the thickness or shape of the defect. This means that regions showing substantially the same brightness correspond to the result of the same atomic crystal lattice orientation, and regions showing different brightness correspond to the result of different atomic crystal lattice orientations.

[0060] In short, a dislocation is a linear defect in which the atomic arrangement is shifted within a crystal grain having a certain crystal structure. The atoms within a single crystal grain, excluding the dislocation, have the same crystal orientation, and therefore can exhibit substantially the same brightness and darkness when observing the microstructure. However, in the case of a planar defect, adjacent regions based on the planar defect, for example, adjacent regions based on a grain boundary or domain boundary, can exhibit substantially different brightness and darkness when observing the microstructure, because the atomic arrangement has different crystal lattice directions.

[0061] A more specific method for distinguishing between dislocations, which are line defects, and planar defects can be determined from images taken with an Annular Bright Field-STEM (ABF-STEM) at a magnification of 40,000x or more. While domain boundaries are observed as repeated, step-like bands of a certain thickness, dislocations appear as single lines that are thinner than planar defects or can be considered to have no thickness. For example, the image in Figure 9 was taken using a JEOL ARM200F model at an accelerating voltage of 200 kV, an OL aperture of 40 μm, a magnification of 40,000x, and bright field measurement conditions. The line defect, indicated by the arrow, appears as a single line within the grain. In other words, dislocation defects can be clearly distinguished from other types of defects, such as twin planes, domain boundaries, and grain boundaries, which can be observed in the microstructure.

[0062] If the distinction is not clear even with these methods, the presence or absence of line defects, planar defects, etc. can be determined by observing the atomic crystal lattice arrangement using a high-magnification device capable of observing the atomic crystal lattice arrangement, such as an HRTEM (High Resolution TEM), and then using the characteristics of each defect as generally defined or as described above as the basis for judgment.

[0063] On the other hand, the length of dislocations can be measured using the above-mentioned method for measuring the length of defects.

[0064] Specifically, in an image obtained by scanning a TEM sample prepared with a focused ion beam (FIB) in a bright field or dark field image mode, dislocations are selected using the method of distinguishing defects located within dielectric crystal grains into planar defects and line defects as described above, and the length of the dislocations is then measured. When multiple dislocations exist, the lengths of all the dislocations measured by the above method can be added together to obtain the length of the dislocations.

[0065] Hereinafter, regarding defects, dislocations, which are line defects, will be described as an example, but this is not particularly limited to this, and may include cases where defects other than dislocations are formed within the dielectric crystal grains, thereby ensuring the effect of promoting the diffusion of the additive element according to the present invention into the interior of the crystal grains and the effect of promoting the solid solution of Si in the BT crystal lattice in the crystal grain boundary region.

[0066] 5 and 6, in one embodiment of the present invention, the first dielectric crystal grains 10, 10' in which the sum of the lengths of the dislocations 11 is 150 nm or more may refer to a first dielectric crystal grain 10' in which the length of one dislocation 11 is 150 nm or more, or may refer to a first dielectric crystal grain 10 in which the sum of the lengths of two or more dislocations 11 is 150 nm or more. As described above, the shape and number of dislocations 11 are not limited, and as long as the length of one dislocation 11 or the sum of the lengths of two or more dislocations 11 is 150 nm or more, the effect of increasing reliability aimed at by the present invention can be achieved.

[0067] That is, when the plurality of dielectric crystal grains contain at least one first dielectric crystal grain 10, 10' in which the sum of the lengths of the dislocations 11 within the dielectric crystal grain is 150 nm or more, the reliability of the laminated electronic component can be increased, and in particular, the additive Si can be easily dissolved in the BT lattice, thereby further increasing the reliability.

[0068] At this time, the reliability tends to increase as the sum of the lengths of the dislocations 11 in the dielectric crystal grains increases.

[0069] If the sum of the lengths of the dislocations 11 in the dielectric crystal grains is less than 150 nm, it may be difficult to fully achieve the target reliability, and in particular, the solid solution in the grain boundary region of Si may not be smooth, making it even more difficult to achieve the target reliability.

[0070] An embodiment of the present invention may include one or more first grain boundaries 12 having a Si content of 3.0 at % or more within 2 nm from the center in the direction perpendicular to the grain boundary.

[0071] If the amount of Si present is less than 3.0 at % within 2 nm in the direction perpendicular to the grain boundary, it may be difficult to achieve the effect of increasing reliability that is intended to be achieved by adding Si.

[0072] Here, the term "grain boundary" refers to the boundary between two adjacent crystal grains, and the boundary between two adjacent crystal grains can be considered as one crystal grain boundary. That is, one crystal grain can have as many grain boundaries as the number of adjacent crystal grains. Referring to FIG. 5, the central crystal grain is adjacent to six crystal grains, and therefore has six grain boundaries. In this case, if one of the six grain boundaries has a Si content of 3.0 at% or more within 2 nm in a direction perpendicular to the grain boundary, it can be considered to include one first crystal grain boundary 12.

[0073] In one embodiment of the present invention, the first grain boundary 12 may have a perovskite (ABO3) structure.

[0074] The material having a perovskite structure may include, for example, a BT (BaTiO3)-based dielectric material, and may also include a material in which Ba or Ti sites are substituted with other elements, but is not particularly limited thereto.

[0075] On the other hand, in one embodiment of the present invention, at least a portion of Si may be dissolved in the perovskite structure.

[0076] As described above, Si has a smaller ionic radius than Ti and is generally difficult to dissolve in a BT lattice having a perovskite structure, but when one or more dielectric crystal grains 10, 10' in which the sum of the lengths of dislocations 11 is 150 nm or more is contained within the dielectric crystal grain, as in one embodiment of the present invention, Si can dissolve in the grain boundaries having a perovskite structure rather than precipitating as a secondary phase. By dissolving the additive Si in the grain boundaries having a perovskite structure, the target effect of increasing reliability can be more easily achieved.

[0077] Meanwhile, in one embodiment of the present invention, the first grain boundary 12 may be a grain boundary between the first dielectric crystal grains 10 and 10'.

[0078] That is, the Si content may be 3.0 at % or more within 2 nm from the center in the direction perpendicular to the grain boundary of the crystal grain in contact with the first dielectric crystal grains 10, 10', which includes dislocations 11 having a sum of lengths of 150 nm or more within the dielectric crystal grains.

[0079] However, this is not particularly limited, and when a dielectric crystal grain in which the sum of the lengths of dislocations 11 within the dielectric crystal grain is less than 150 nm is used as the second dielectric crystal grain, the grain boundary between two adjacent second dielectric crystal grains can also include a first grain boundary 12 having a Si content of 3.0 at% or more within 2 nm in the perpendicular direction.

[0080] That is, in a dielectric layer 111 containing a plurality of dielectric crystal grains, when any of the plurality of dielectric crystal grains contains one or more first dielectric crystal grains 10, 10' in which the sum of the lengths of dislocations 11 is 150 nm or more, Si can be dissolved in the grain boundaries of the first dielectric crystal grains 10, 10', or Si can also be dissolved in the grain boundaries of any second dielectric crystal grains in which the sum of the lengths of dislocations 11 is less than 150 nm, thereby realizing the desired effect of increased reliability.

[0081] On the other hand, the upper limit of the sum of the lengths of the dislocations 11 in the first dielectric crystal grains 10, 10' does not need to be particularly limited, but as a preferred example, it may be less than 843 nm. That is, in one embodiment of the present invention, the sum of the lengths of the dislocations 11 in the first dielectric crystal grains 10, 10' may be 150 nm or more and less than 843 nm.

[0082] If the sum of the lengths of the dislocations 11 is less than 150 nm, as described above, it may be difficult to fully achieve the desired effect of increasing reliability. On the other hand, if the sum of the lengths of the dislocations 11 is 843 nm or more, excessive dislocations may be generated, causing Si in the BT lattice to dissolve at a rate of 3.0 at % or more, thereby achieving the target of increasing reliability, but there is a risk of a problem of a decrease in dielectric constant.

[0083] That is, in order to satisfy the requirement that the sum of the lengths of the dislocations 11 be within a range that does not result in a dielectric constant below the target value, it is preferable to control the sum of the lengths of the dislocations 11 to be less than 843 nm. However, this is not limited to this, and in order to achieve the goal of increased reliability, the sum of the lengths of the dislocations 11 may be 843 nm or more.

[0084] Meanwhile, the dielectric layer 111 may include one or more first dielectric crystal grains 10, 10' in which the sum of the lengths of the dislocations 11 is 150 nm or more within a 2 μm×2 μm region.

[0085] This may mean that when the inside of the dielectric layer 111 is observed using a measurement device, first dielectric crystal grains 10, 10' in which the sum of the lengths of dislocations 11 is 150 nm or more may be present within any 2 μm × 2 μm area.

[0086] More specifically, when ten regions each having a size of 2 μm×2 μm are arbitrarily selected in the cross section of the length-thickness direction (LT) of the body 110 in the dielectric layer 111 arranged in the active portion Ac and observed with a transmission electron microscope (TEM), if one or more first dielectric crystal grains 10, 10′ are observed in all of the ten regions, it can be considered that the 2 μm×2 μm region contains one or more first dielectric crystal grains 10, 10′ in which the sum of the lengths of the dislocations 11 is 150 nm or more.

[0087] In this case, one or more first grain boundaries 12 having a Si content of 3.0 at % or more can be included within 2 nm from the center of the grain boundary in the direction perpendicular to the grain boundary in the arbitrary 2 μm×2 μm region.

[0088] More specifically, an embodiment of the present invention will be described below with reference to FIGS.

[0089] First, FIGS. 9(a) and 9(b) are TEM (Transmission Electron Microscope) images in which the sum of the lengths of dislocations formed inside the dielectric crystal grains satisfies 150 nm or more.

[0090] 9(a) and 9(b), the arrows indicate dislocations, and the reliability tends to increase as the sum of the lengths of dislocations formed inside the dielectric crystal grains increases. When the sum of the lengths of dislocations is 150 nm or more, the target effect of increasing reliability can be achieved. Specific examples of reliability evaluations using different sums of dislocation lengths and their effects will be described later.

[0091] Meanwhile, referring to FIG. 10 according to an embodiment of the present invention, FIG. 10a is a TEM image in which dislocations are formed inside the first dielectric crystal grains 10, 10′, FIG. 10b is a High Resolution TEM (HRTEM) image in which a line-profile is applied to measure the percentage (at%) of Si element in a direction perpendicular to the first grain boundary 12 of the second dielectric crystal grain adjacent to the first dielectric crystal grains 10, 10′ and does not contain dislocations, and FIG. 10(c) is a graph showing a line-profile of the percentage (at%) of Si element analyzed by STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectroscopy) at the dotted line in FIG. 10(b). The x-axis represents the distance gb1 to the left (-) and gb1' to the right (+) relative to the first grain boundary 12, and the y-axis represents the percentage (at%) of Si atoms relative to the sum of the elements (Ba + Ti + Si + RE) by distance relative to the first grain boundary 12, i.e., the percentage (at%) of Si atoms relative to the total number of Ba, Ti, Si, and RE atoms. Here, RE refers to rare earth elements including one or more of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd, and Yb. Referring to Figure 10(c), it can be seen that a peak of Si element percentage of 3.0 at% or more is present within ±2 nm of the first grain boundary 12 (0 nm point). Furthermore, referring to Figure 10(b), since no amorphous layer or secondary phase as shown in Figure 7(b) is formed around the first crystal grain boundary 12, it can be confirmed that the main component base material (BaTiO3) maintains the perovskite crystal lattice, and therefore it can be seen that the Si detected at the first crystal grain boundary 12 exists in a solid solution state.

[0092] 11(a) is a TEM image of a crystal grain having a dislocation length of 150 nm or more, FIG. 11(b) is an HRTEM image of a first dielectric crystal grain 10, 10' having a dislocation length of 150 nm or more, where a line-profile is used to measure the percentage (at%) of Si in a direction perpendicular to the first grain boundary 12. FIG. 11(c) is a graph showing a line-profile of the percentage (at%) of Si analyzed by STEM-EDS along the dotted line in FIG. 11(b). The x-axis represents the distance (-) from the first grain boundary 12, with the left gb2 being negative and the right gb2' being positive. The y-axis represents the percentage (at%) of Si relative to the sum of the elements (Ba + Ti + Si + RE) by distance from the first grain boundary 12. That is, it means the percentage (at%) of the number of Si atoms relative to the total number of Ba, Ti, Si, and RE atoms. Referring to Figure 11(c), it can be seen that a peak where the percentage of Si elements is 3.0 at% or more exists within ±2 nm of the first crystal grain boundary 12 (0 nm point). Furthermore, referring to Figure 11(b), similar to Figure 10(b), no amorphous layer or secondary phase like that in Figure 7(b) is formed around the first crystal grain boundary 12, confirming that the main component base material (BaTiO3) maintains a perovskite crystal lattice. This indicates that the Si detected at the first crystal grain boundary 12 exists in a solid solution state.

[0093] The following specifically describes the minor components that may be contained in the dielectric composition described above.

[0094] a) First subcomponent According to an embodiment of the present invention, the dielectric composition further includes a first minor component including one or more oxides or carbonates of a variable valence acceptor element, and the variable valence acceptor element includes one or more of Mn, V, Cr, Fe, Ni, Co, Cn, and Zn. The content of the variable valence acceptor element included in the first minor component may be 0.2 mol to 1.4 mol relative to 100 mol of the main component.

[0095] The variable valence acceptor element contained in the first minor component may serve to lower the firing temperature of a multilayer ceramic capacitor to which the dielectric composition is applied and improve high-temperature withstand voltage characteristics.

[0096] If the content of the variable valence acceptor element contained in the first minor component is less than 0.2 mol, the high temperature withstand voltage characteristics may be deteriorated, and if it exceeds 1.4 mol, the RC value may be deteriorated.

[0097] The content of the first minor component may be based on the content of one or more elements selected from Mn, V, Cr, Fe, Ni, Co, Cu, and Zn contained in the first minor component, regardless of the added form such as oxide or carbonate. When two or more variable valence acceptor elements are contained, the total content thereof may be based on the content of the first minor component.

[0098] b) Second subcomponent According to an embodiment of the present invention, the dielectric composition further includes a second minor component including at least one of an oxide or a carbonate of Mg, and the content of Mg element included in the second minor component may be 2.0 mol or less relative to 100 mol of the main component.

[0099] The second minor component Mg can increase the RC value, but if the content of Mg element exceeds 2.0 mol, the high-temperature withstand voltage characteristics may be deteriorated.

[0100] c) Third subcomponent According to an embodiment of the present invention, the dielectric composition further includes a third minor component including one or more of oxides and carbonates of rare earth elements, and the rare earth elements include one or more of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd, and Yb. The content of the rare earth elements included in the third minor component may be 0.6 mol or more and 3.0 mol or less with respect to 100 mol of the main component.

[0101] The rare earth element contained in the third minor component can improve high-temperature voltage resistance characteristics. If the content of the rare earth element is less than 0.6 mol or more than 3.0 mol, the high-temperature voltage resistance characteristics may be deteriorated.

[0102] The content of the third minor component may be based on the content of at least one element selected from Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd, and Yb contained in the third minor component, regardless of the added form such as oxide or carbonate. When two or more rare earth elements are contained, the total content thereof may be based on the content.

[0103] d) Fourth subcomponent According to an embodiment of the present invention, the dielectric composition further includes a fourth minor component including at least one of oxides and carbonates of at least one element selected from Ba and Ca, and the total content of at least one element selected from Ba and Ca included in the fourth minor component may be 4.8 mol or less relative to 100 mol of the main component. The lower limit of the total content of at least one element selected from Ba and Ca included in the fourth minor component does not need to be particularly limited, and it is preferable that the total content is more than 0 mol relative to 100 mol of the main component, and more preferably 0.24 mol or more to further improve the RC value.

[0104] Here, Ba and Ca can play a role in increasing the dielectric constant and RC value. However, if the total content of one or more of Ba and Ca exceeds 4.8 mol per 100 mol of the main component, the room temperature dielectric constant and high temperature withstand voltage may decrease.

[0105] e) Fifth subcomponent According to an embodiment of the present invention, the dielectric composition further includes a fifth minor component including one or more of an oxide of Si, a carbonate of Si, and a glass containing Si, and the content of the Si element included in the fifth minor component may be 0.8 mol to 3.0 mol relative to 100 mol of the main component.

[0106] If the content of Si element contained in the fifth minor component is less than 0.8 mol or more than 3.0 mol, the sintered density may be low, and the room temperature dielectric constant and high temperature withstand voltage may be deteriorated.

[0107] Meanwhile, according to an embodiment of the present invention, the dielectric composition may further include a fourth subcomponent and a fifth subcomponent at the same time.

[0108] When the sum of the contents of one or more elements of Ba and Ca contained in the fourth minor component is defined as 4s and the content of Si element contained in the fifth minor component is defined as 5s, 4s / 5s may be 1.60 or less. If the 4s / 5s exceeds 1.60, the room temperature dielectric constant and high temperature withstand voltage may be reduced.

[0109] The thickness td of the dielectric layer 111 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacity of the multilayer electronic component, the thickness of the dielectric layer 111 may be 0.6 μm or less, and more preferably 0.4 μm or less. Generally, when the dielectric layer 111 is formed thin, at a thickness of 0.6 μm or less, there is a risk of reduced reliability, especially when the thickness of the dielectric layer 111 is 0.4 μm or less.

[0110] As described above, according to one embodiment of the present invention, it is possible to ensure good room temperature dielectric constant, DC-bias characteristics, high temperature withstand voltage characteristics, etc., and therefore it is possible to ensure excellent reliability even when the thickness of the dielectric layer 111 is 0.4 μm or less.

[0111] Therefore, when the thickness of the dielectric layer 111 is 0.4 μm or less, the effects of the present invention become more pronounced, and it becomes easier to achieve a smaller multilayer electronic component with a higher capacity.

[0112] Here, the thickness td of the dielectric layer 111 may refer to the thickness td of the dielectric layer 111 disposed between the first and second internal electrodes 121 and 122.

[0113] On the other hand, the thickness td of the dielectric layer 111 can refer to the average thickness td of the dielectric layer 111.

[0114] The average thickness td of the dielectric layer 111 can be measured by scanning an image of a cross section of the body 110 in the length and thickness direction (LT) using a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, in the scanned image, the thickness of one dielectric layer 111 can be measured at 30 equally spaced points in the length direction to obtain an average value. The 30 equally spaced points may be designated as active portions Ac. Furthermore, by extending this average measurement to 10 dielectric layers 111 and measuring the average value, the average thickness td of the dielectric layers 111 can be further generalized. Here, the average thickness td of the dielectric layers 111 may refer to the average size of the dielectric layers 111 in the first direction.

[0115] The internal electrodes 121 and 122 may be alternately stacked with the dielectric layer 111. The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122, and the first and second internal electrodes 121 and 122 may be alternately arranged to face each other with the dielectric layer 111 constituting the body 110 sandwiched therebetween, and may be exposed to third and fourth surfaces 3 and 4 of the body 110, respectively.

[0116] More specifically, the first internal electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4. A first external electrode 131 may be disposed on the third surface 3 of the body 110 and connected to the first internal electrode 121, and a second external electrode 132 may be disposed on the fourth surface 4 of the body 110 and connected to the second internal electrode 122.

[0117] That is, the first internal electrode 121 may be connected to the first external electrode 131 but not to the second external electrode 132, and the second internal electrode 122 may be connected to the second external electrode 132 but not to the first external electrode 131. In this case, the first and second internal electrodes 121 and 122 may be electrically isolated from each other by the dielectric layer 111 disposed therebetween.

[0118] Meanwhile, the body 110 may be formed by alternately stacking ceramic green sheets on which the first internal electrodes 121 are printed and ceramic green sheets on which the second internal electrodes 122 are printed, and then firing the stacked sheets.

[0119] There are no particular limitations on the material forming the internal electrodes 121 and 122, and any material with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 can include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0120] The internal electrodes 121 and 122 may be formed by printing a conductive paste for internal electrodes, which may include at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, on a ceramic green sheet. The conductive paste for internal electrodes may be printed by screen printing or gravure printing, but the present invention is not limited thereto.

[0121] Meanwhile, there is no need to particularly limit the thickness te of the internal electrodes 121, 122. Although one embodiment of the present invention has been described using a multilayer ceramic capacitor having a size of 3216 (3.2 mm × 1.6 mm) as an example, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the thickness te of the internal electrodes 121, 122 may be 0.6 μm or less, and more preferably 0.4 μm or less.

[0122] Generally, when the internal electrodes 121, 122 are formed thinly, with a thickness of 0.6 μm or less, there is a risk of reliability decreasing, especially when the thickness of the internal electrodes 121, 122 is 0.4 μm or less.

[0123] As described above, according to one embodiment of the present invention, it is possible to ensure good room temperature dielectric constant, DC-bias characteristics, high temperature withstand voltage characteristics, etc., and therefore it is possible to ensure excellent reliability even when the thickness of the internal electrodes 121, 122 is 0.4 μm or less.

[0124] Therefore, when the thickness of the internal electrodes 121, 122 is 0.4 μm or less, the effect of the present invention becomes more pronounced, and it becomes easier to achieve a smaller size and a higher capacity of the multilayer electronic component.

[0125] Here, the thickness te of the internal electrodes 121 and 122 may refer to the average thickness te of the internal electrodes 121 and 122.

[0126] The average thickness te of the internal electrodes 121, 122 can be measured by scanning an image of a cross section of the body 110 in the length and thickness direction (LT) using a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, in the scanned image, the thickness of each internal electrode 121, 122 can be measured at 30 equally spaced points in the length direction to determine an average value. The 30 equally spaced points can be designated as active portions Ac. Furthermore, if this average measurement is extended to 10 internal electrodes 121, 122, the average thickness te of the internal electrodes 121, 122 can be further generalized. Here, the average thickness te of the internal electrodes 121, 122 can refer to the average size of the internal electrodes 121, 122 in the first direction.

[0127] The cover parts 112 and 113 may include an upper cover part 112 disposed on an upper part of the active part Ac in the first direction, and a lower cover part 113 disposed on a lower part of the active part Ac in the first direction.

[0128] The upper cover part 112 and the lower cover part 113 may be formed by stacking a single dielectric layer 111 or two or more dielectric layers 111 in a first direction on the upper and lower surfaces of the active part Ac, respectively, and may basically serve to prevent damage to the internal electrodes 121, 122 due to physical or chemical stress.

[0129] The upper cover part 112 and the lower cover part 113 do not include the internal electrodes 121, 122 and may include the same material as the dielectric layer 111. That is, the upper cover part 112 and the lower cover part 113 may include a ceramic material, for example, a barium titanate (BaTiO)-based ceramic material.

[0130] There is no need to particularly limit the thickness tc of the cover portions 112, 113. However, in order to more easily achieve miniaturization and high capacity of the multilayer electronic component, the thickness tc of the cover portions 112, 113 may be 100 μm or less, preferably 30 μm or less, and for ultra-small products, more preferably 20 μm or less.

[0131] Here, the thickness tc of the cover portions 112 and 113 may refer to the average thickness tc of the cover portions 112 and 113.

[0132] The average thickness tc of the covers 112, 113 can be measured by scanning an image of a cross section of the body 110 in the length and thickness direction (LT direction) using a scanning electron microscope (SEM) at 10,000 magnifications. More specifically, in the scanned image, the thickness of each cover 112, 113 can be measured at 30 equally spaced points in the second direction to obtain an average value. The 30 equally spaced points may be designated as the upper cover 112. Furthermore, by extending this average measurement to the lower cover 113, the average thickness td of the covers 112, 113 can be further generalized. Here, the average thickness tc of the covers 112, 113 may refer to the average size of the covers 112, 113 in the first direction.

[0133] The margin portions 114, 115 may include a first margin portion 114 disposed on the fifth surface 5 of the main body 110 and a second margin portion 115 disposed on the sixth surface 6. That is, the margin portions 114, 115 may be disposed on both end surfaces of the main body 110 in the width direction.

[0134] As shown in the figure, the margin portions 114 and 115 may refer to the areas between the widthwise end faces of the first and second internal electrodes 121 and 122 and the boundary surface of the body 110, based on the thickness and widthwise (WT) cross-section of the body 110.

[0135] The margin portions 114 and 115 basically serve to prevent damage to the internal electrodes 121 and 122 due to physical or chemical stress.

[0136] The margin portions 114, 115 may be formed by applying a conductive paste to the ceramic green sheet except for the areas where the margin portions 114, 115 are to be formed, to form the internal electrodes 121, 122. As described above, in order to suppress steps due to the internal electrodes 121, 122, the laminated internal electrodes 121, 122 may be cut so as to be exposed on the fifth and sixth surfaces 5, 6 of the main body 110, and then a single dielectric layer 111 or two or more dielectric layers 111 may be laminated in the width direction on both end surfaces of the active portion Ac to form the margin portions 114, 115.

[0137] There is no need to particularly limit the width of the first and second marginal portions 114, 115. However, in order to more easily achieve a smaller size and higher capacity of the multilayer electronic component 100, the width of the first and second marginal portions 114, 115 may be 100 μm or less, preferably 30 μm or less, and more preferably 20 μm or less for ultra-small products.

[0138] Here, the width of the margins 114 and 115 may refer to the average width of the margins 114 and 115 .

[0139] The average width of the margin portions 114, 115 can be measured by scanning an image of a cross section of the body 110 in the width and thickness directions (WT) using a scanning electron microscope (SEM) at 10,000 magnifications. More specifically, in the scanned image, the widths of one margin portion 114, 115 can be measured at 10 equally spaced points in the thickness direction to obtain an average value. The 10 equally spaced points may be designated as the first margin portion 114. Furthermore, by extending this average measurement to the second margin portions 114, 115 and measuring the average value, the average width of the margin portions 114, 115 can be further generalized. Here, the average width of the margin portions 114, 115 may refer to the average size of the margin portions 114, 115 in the third direction.

[0140] In one embodiment of the present invention, a structure in which the ceramic electronic component 100 has two external electrodes 131, 132 is described, but the number and shape of the external electrodes 131, 132 can be changed depending on the shape of the internal electrodes 121, 122 and other purposes.

[0141] The outer electrodes 131 and 132 may be disposed on the body 110 and connected to the inner electrodes 121 and 122 .

[0142] More specifically, the external electrodes 131, 132 may include first and second external electrodes 131, 132 disposed on the third and fourth surfaces 3, 4 of the body 110, respectively, and connected to the first and second internal electrodes 121, 122. That is, the first external electrode 131 may be disposed on the third surface 3 of the body and connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body and connected to the second internal electrode 122.

[0143] On the other hand, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as a metal, and the specific material may be determined taking into consideration electrical properties, structural stability, etc., and may further have a multi-layer structure.

[0144] For example, the external electrodes 131 and 132 may include electrode layers 131a, 132a, 131b, and 132b disposed on the main body 110 and plating layers 131c and 132b disposed on the electrode layers 131a, 132a, 131b, and 132b.

[0145] To give a more specific example of the electrode layers 131a, 132a, 131b, and 132b, the electrode layers 131a, 132a, 131b, and 132b may be fired electrodes containing a conductive metal and glass, or may be resin-based electrodes containing a conductive metal and resin.

[0146] The electrode layers 131a, 132a, 131b, and 132b may also be in a form in which a fired electrode and a resin-based electrode are sequentially formed on the main body.

[0147] In addition, the electrode layers 131a, 132a, 131b, and 132b may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0148] The conductive metal contained in the electrode layers 131a, 132a, 131b, and 132b may be a material with excellent electrical conductivity. For example, the conductive metal may include, but is not limited to, one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0149] In one embodiment of the present invention, the electrode layers 131a, 132a, 131b, and 132b may have a two-layer structure including first electrode layers 131a and 132a and second electrode layers 131b and 132b, whereby the external electrodes 131 and 132 may include first electrode layers 131a and 132a including a conductive metal and glass and second electrode layers 131b and 132b disposed on the first electrode layers 131a and 132a and including a conductive metal and resin.

[0150] The first electrode layers 131a and 132a contain glass, thereby improving the bonding strength with the main body 110, and the second electrode layers 131b and 132b contain resin, thereby improving the bending strength.

[0151] The conductive metal used for the first electrode layers 131a, 132a is not particularly limited as long as it can be electrically connected to the internal electrodes 121, 122 to form capacitance, and may include, for example, one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The first electrode layers 131a, 132a may be formed by coating a conductive paste prepared by adding glass frit to the conductive metal powder, followed by firing.

[0152] The conductive metal included in the second electrode layers 131b and 132b may serve to electrically connect the second electrode layers 131b and 132b to the first electrode layers 131a and 132a.

[0153] The conductive metal included in the second electrode layers 131b and 132b is not particularly limited as long as it is a material that can be electrically connected to the electrode layers 131a and 132a, and may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0154] The conductive metal contained in the second electrode layers 131b and 132b may include one or more of spherical particles and flaky particles. That is, the conductive metal may be composed of only flake-shaped particles, only spherical particles, or a mixture of flake-shaped and spherical particles. Here, the spherical particles may include particles that are not perfectly spherical, for example, particles having a length ratio of their major axis to their minor axis (major axis / minor axis) of 1.45 or less. The flaky particles refer to particles having a flat and elongated shape and are not particularly limited, but may include, for example, particles having a length ratio of their major axis to their minor axis (major axis / minor axis) of 1.95 or more. The lengths of the major and minor axes of the spherical particles and flaky particles can be measured from images obtained by scanning first and second direction cross sections (LT cross sections) cut at the center of the ceramic electronic component in the third direction using a scanning electron microscope (SEM).

[0155] The resin contained in the second electrode layers 131b and 132b serves to ensure bonding and shock absorption. The resin contained in the second electrode layers 131b and 132b is not particularly limited as long as it has bonding and shock absorption properties and can be mixed with conductive metal powder to form a paste, and may include, for example, an epoxy resin.

[0156] In addition, the second electrode layers 131b and 132b may include a plurality of metal particles, an intermetallic compound, and a resin. The inclusion of the intermetallic compound may further improve electrical connectivity with the first electrode layers 131a and 132a. The intermetallic compound may connect the plurality of metal particles to improve electrical connectivity and may surround the plurality of metal particles to connect them to each other.

[0157] The intermetallic compound may include a metal having a melting point lower than the curing temperature of the resin. That is, since the intermetallic compound includes a metal having a melting point lower than the curing temperature of the resin, the metal melts during the drying and curing process, forming an intermetallic compound with a portion of the metal particles and surrounding the metal particles. In this case, the intermetallic compound may preferably include a low-melting point metal of 300°C or less.

[0158] For example, it may contain Sn, which has a melting point of 213°C to 220°C. During the drying and hardening process, Sn melts, and the molten Sn wets high-melting-point metal particles such as Ag, Ni, or Cu by capillary action, reacting with some of the Ag, Ni, or Cu metal particles to form intermetallic compounds such as Ag3Sn, Ni3Sn4, Cu6Sn5, and Cu3Sn. The Ag, Ni, or Cu that did not participate in the reaction remains in the form of metal particles.

[0159] Therefore, the plurality of metal particles may include one or more of Ag, Ni, and Cu, and the intermetallic compound may include one or more of Ag3Sn, Ni3Sn4, Cu6Sn5, and Cu3Sn.

[0160] The plating layers 131c and 132c serve to improve mounting characteristics. The type of the plating layers 131c and 132c is not particularly limited, and may be a single layer containing one or more of nickel (Ni), tin (Sn), palladium (Pd), and alloys thereof, or may be formed of multiple layers.

[0161] As a more specific example of the plating layers 131c, 132c, the plating layers 131c, 132c may be Ni plating layers or Sn plating layers, and may be formed in a form in which a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layers 131a, 132a, 131b, 132b, or in a form in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed. Also, the plating layers 131c, 132c may include a plurality of Ni plating layers and / or a plurality of Sn plating layers.

[0162] Meanwhile, the size of the multilayer electronic component 100 does not need to be particularly limited. In one embodiment of the present invention, a multilayer electronic component having a 3216 (length x width, 3.2 mm x 1.6 mm) size has been described, but the effects of improving DC-bias characteristics, high-temperature withstand voltage characteristics, etc. according to the present invention can also be realized to achieve an effect of increased reliability in multilayer electronic components of various sizes, for example, 1005 (length x width, 1.0 mm x 0.5 mm) size, 0402 (length x width, 0.4 mm x 0.2 mm) size, etc.

[0163] Manufacturing method for multilayer electronic components FIG. 12 is a manufacturing process diagram showing a method for manufacturing a multilayer electronic component according to another embodiment of the present invention.

[0164] Hereinafter, a method for manufacturing a multilayer electronic component according to another embodiment of the present invention will be described, taking a multilayer ceramic capacitor as an example, but the present invention is not limited thereto. Note that, in the description of the method for manufacturing a multilayer electronic component according to one embodiment of the present invention, descriptions that overlap with those of the multilayer electronic component described above will be omitted.

[0165] A method for manufacturing a multilayer electronic component according to another embodiment of the present invention includes the steps of: milling a dielectric composition containing a dielectric powder as a main component, a solvent, and a dispersant (S1); adding a binder to the dielectric composition and further milling the resulting mixture to form a slurry (S2); forming ceramic green sheets using the slurry (S3); printing a conductive paste for internal electrodes on the ceramic green sheets and laminating them to form a laminate (S4); firing the laminate to form a body including dielectric layers and internal electrodes (S5); and forming external electrodes on the body (S6). The milling step (S1) may be performed to form at least one first dielectric crystal grain in which the sum of lengths of defects in the dielectric crystal grains included in the dielectric layer is 150 nm or more.

[0166] In the present invention, the type of defect does not need to be particularly limited, and the defect may be one or more of a line defect (one-dimensional) and a planar defect (two-dimensional).

[0167] However, as described above, when the defects are dislocations, the effect of promoting the diffusion of the additive element into the interior of the crystal grains and the effect of promoting the solid solution of Si in the BT crystal lattice in the grain boundary region according to the present invention can be significantly improved. In other words, in order to realize the effect of increasing reliability described in this specification, it is more preferable that the defects are dislocations.

[0168] Hereinafter, regarding defects, dislocations, which are line defects, will be described as an example, but this is not particularly limited to this, and may include cases where defects other than dislocations are formed within the dielectric crystal grains, thereby ensuring the effect of promoting the diffusion of the additive element according to the present invention into the interior of the crystal grains and the effect of promoting the solid solution of Si in the BT crystal lattice in the crystal grain boundary region.

[0169] A method for manufacturing a multilayer electronic component according to an embodiment of the present invention may include a step (S1) of milling a dielectric composition containing a dielectric powder as a main component, a solvent, and a dispersant.

[0170] One embodiment of the present invention may include providing a dielectric composition containing BaTiO3-based dielectric powder as a main component, a solvent, and a dispersant.

[0171] There is no particular limitation on the method for producing the base material of BaTiO3-based main component, and it can be produced by, for example, hydrothermal synthesis, solid phase method, oxalate method, etc.

[0172] The average diameter size of the dielectric powder may be 50 nm or more and 300 nm or less, preferably 100 nm or more and 200 nm or less, and more preferably 140 nm or more and 160 nm or less.

[0173] A dielectric composition can be prepared by adding a solvent and a dispersant to the dielectric powder. The solvent may be a common solvent used in manufacturing multilayer electronic components, such as an ethanol / toluene solvent, and the dispersant may be a common dispersant.

[0174] Meanwhile, the method of milling the dielectric composition may be batch milling using zirconia beads as a mixing / dispersing medium, but is not particularly limited thereto, and various milling methods such as wet / dry milling may be used as needed.

[0175] Milling can be performed to form one or more first dielectric crystal grains 10, 10' in which the sum of the lengths of dislocations in the dielectric crystal grains included in the dielectric layer is 150 nm or more. Milling can form dislocations in the dielectric composition, and the formed dislocations can remain in the dielectric layer 111 of the chip-shaped multilayer electronic component 100, which is the final product, even after a firing process.

[0176] Here, it is sufficient to perform milling so as to include one or more first dielectric crystal grains 10, 10' in which the sum of the lengths of dislocations within the dielectric crystal grains contained in the dielectric layer 111 is 150 nm or more, and the specific conditions can be determined appropriately taking into account conditions such as milling time, dielectric powder, beads, etc.

[0177] In one preferred example, the dielectric composition can be milled in batches for 4 hours or more.

[0178] When milling is carried out for 4 hours or more, it may be easy to produce a dielectric crystal grain having a total length of dislocations formed in the grains of the dielectric material of 150 nm or more.

[0179] On the other hand, if milling is performed for less than four hours, it is difficult to form a sufficient sum of dislocation lengths, which may make it difficult to achieve the desired effect of increasing reliability, and the Si crystal lattice solid solution may not be smooth, which may result in only a slight effect of increasing reliability.

[0180] In one embodiment of the present invention, the dielectric composition may be milled in a batch for at least 4 hours and less than 30 hours.

[0181] As the milling time of the dielectric composition increases, the sum of the lengths of dislocations formed in the dielectric composition may tend to increase.

[0182] On the other hand, if milling is performed for less than 4 hours, the same problems as those described above may occur, and if milling is performed for 30 hours or more, the sum of dislocation lengths may be greater than 843 nm, which may facilitate the realization of the reliability improvement effect and the smooth Si solid solution, but may cause the problem of a decrease in dielectric constant.

[0183] The dielectric composition may be formed by further adding an additive to the dielectric powder.

[0184] As described above, the additives added to the dielectric powder may refer to minor components in the dielectric composition or minor components in the dielectric crystal grains after sintering. The description of the minor components is the same as that described above and will be omitted.

[0185] Thereafter, a step (S2) of adding a binder to the dielectric composition and further milling the mixture to prepare a slurry may be included.

[0186] The binder may be a commonly used binder, and the additional milling is performed for 4 to 6 hours, preferably 5 hours, to uniformly mix the materials contained in the slurry.

[0187] Thereafter, a step (S3) of forming a ceramic green sheet using the prepared slurry may be included.

[0188] The ceramic green sheet can be produced by mixing ceramic powder, a binder, a solvent, etc. to produce a slurry, and then cutting the slurry into a sheet having a thickness of several μm by a doctor blade method or the like.

[0189] Thereafter, a step (S4) of printing a conductive paste for an internal electrode on the ceramic green sheet and laminating the printed conductive paste on the ceramic green sheet to form a laminate may be included.

[0190] The internal electrode patterns can be formed by applying a conductive paste for the internal electrodes onto ceramic green sheets. The method for forming the internal electrode patterns is not particularly limited, but can be formed by screen printing or gravure printing. The green sheets on which the internal electrode patterns are printed can be stacked and pressed in the stacking direction to form a laminate having the internal electrode patterns.

[0191] Thereafter, the laminate may be fired to form a body including the dielectric layers and the internal electrodes (S5).

[0192] The laminate can be cut into regions corresponding to individual multilayer electronic components, with the ends of the internal electrode patterns alternately exposed through the side surfaces. The cut laminate can then be formed into chips, which can then be fired. The firing process can be performed in a reducing atmosphere, and the firing process can be performed while controlling the temperature rise rate.

[0193] In one embodiment of the present invention, when the firing process is performed in the step (S5) of forming the body, the firing process can be performed in a reducing atmosphere of 0.1% to 3.0% H2 / 97.0% to 99.9% N2 (H2O / H2 / N2 atmosphere), more preferably 0.1% to 0.5% H2 / 99.5% to 99.9% N2 (H2O / H2 / N2 atmosphere).

[0194] More specifically, a hydrogen concentration of 0.1% corresponds to an electromotive force of 680 mV on an oxygen partial pressure meter, and a hydrogen concentration of 0.5% corresponds to an electromotive force of 760 mV. The higher the hydrogen concentration, the higher the electromotive force on the oxygen partial pressure meter.

[0195] If the hydrogen concentration in the atmosphere is less than 0.1%, the amount of dissolved Si in the crystal lattice will be low, which may result in a deterioration in reliability. Therefore, when firing is performed in an atmosphere with a hydrogen concentration of 0.1% or more, preferably 0.5% or more, the reliability improvement effect of the present invention can be improved. The higher the hydrogen concentration, the greater the amount of dissolved Si, which can improve the reliability improvement effect.

[0196] In this case, the firing temperature in the reducing atmosphere may be preferably 1000°C to 1300°C, and more preferably 1150°C to 1200°C.

[0197] The baking can be carried out for 1 to 3 hours, and more preferably for 2 hours.

[0198] Thereafter, a re-oxidation step of performing a re-oxidation heat treatment at a temperature lower than the firing temperature may be further included.

[0199] This suppresses further firing of the dielectric layers and internal electrodes and prevents the formation of structurally weak dielectric layers, thereby improving the reliability of the multilayer electronic component.

[0200] More specifically, the reoxidation step may be performed in a N2 reducing atmosphere at a temperature lower than the calcination temperature, 900°C to 1100°C, more preferably 1000°C, and the reoxidation time may be 2 hours to 4 hours, more preferably 3 hours.

[0201] Next, the method may include forming external electrodes on the body (S6). The external electrodes 131 and 132 may be formed by applying an external electrode paste to the outside of the body 110. For example, the external electrodes 131 and 132 may be formed to be electrically connected to the internal electrodes 121 and 122 exposed on one surface of the body 110. More specifically, the external electrodes 131 and 132 may be disposed on the third and fourth surfaces 3 and 4, which are both end surfaces in the second direction of the body 110. The external electrodes 131 and 132 may be formed of a single layer or multiple layers, and the formation method, components, and structure thereof are the same as those described above, so further description will be omitted.

[0202] The present invention will be described in more detail below by way of experimental examples. However, these examples are intended to aid in the specific understanding of the present invention, and the scope of the present invention is not limited to these examples.

[0203] (Experimental example) BaTiO powder with an average particle size of 150 nm was used as the main component base material. Using zirconia beads as a mixing / dispersing medium, the raw material powder containing the minor components corresponding to the compositions listed in Tables 1, 3, and 5 and the main component BaTiO powder were mixed with an ethanol / toluene solvent and a dispersant and milled in batches for 2 to 30 hours. After adding a binder, the mixture was milled for an additional 5 hours. The resulting slurry was used to produce molded sheets with thicknesses of 3.0 μm and 10.0 μm using a sheet-making molding machine. Ni internal electrodes were printed on the molded sheets. Top and bottom covers were fabricated by stacking 25 layers of cover sheets (10 to 13 μm thick), and 21 layers of printed active sheets were pressed and stacked to produce bars. The crimped bar was cut into chips of size 3216 (3.2 mm x 1.6 mm) using a cutting machine.

[0204] The completed 3216 size MLCC chip was pre-fired, then fired for 2 hours in a reducing atmosphere of 0.1%-0.5% H2 / 99.5%-99.9% N2 (H2O / H2 / N2 atmosphere) while maintaining a temperature of 1150°C-1200°C, and then heat-treated for re-oxidation in an N2 atmosphere at 1000°C for 3 hours.

[0205] Here, a hydrogen concentration of 0.1% corresponds to an electromotive force of 680mV on an oxygen partial pressure meter, and a hydrogen concentration of 0.5% corresponds to an electromotive force of 760mV. The fired chip was then subjected to a termination process using Cu paste and electrode firing to complete the external electrodes.

[0206] As a result, an MLCC chip of 3.2 mm x 1.6 mm size was fabricated, with a dielectric thickness of approximately 2.0 μm after firing and 20 dielectric layers.

[0207] The prototype MLCC chip was evaluated for its room temperature dielectric constant, DF (Dissipation factor), RC value, TCC (Temperature Coefficient of Capacitance), HALT MTTF, etc.

[0208] The room-temperature capacitance and dielectric loss of the MLCC chips were measured using an LCR meter at 1 kHz and AC 0.5 V / μm. The dielectric constant of the MLCC chip dielectric was calculated from the capacitance, the MLCC chip's dielectric thickness, the internal electrode area, and the number of layers. The room-temperature insulation resistance (IR) was measured for 10 sample chips each after applying a DC voltage of 10 V / μm for 60 seconds. The change in capacitance due to temperature was measured over a temperature range from -55°C to 125°C. A highly accelerated life test (HALT) was performed on 40 test specimens of each type, applying a voltage equivalent to an electric field of 42 V / μm at a temperature of 150°C. The time to failure was measured and the mean time to failure (MTTF) was calculated. Tables 2, 4, and 6 show the characteristics of prototype MLCC chips corresponding to the examples shown in Tables 1, 3, and 5.

[0209] In this example, the goal is to realize a dielectric that can achieve all of the following characteristics under firing conditions in a reducing atmosphere where Ni internal electrodes can be used: high capacitance, X7R or X7S capacitance-temperature characteristics, and high high-temperature reliability, as well as an MLCC chip that uses this dielectric.

[0210] To achieve this, the target characteristics are set as the criteria for determining characteristics, with a dielectric constant of 2000 or more, and in accelerated life testing (HALT) in which an electric field of 42 V / μm is applied at a temperature of 150°C, MTTF of 100 hours or more, RC value of 1000 ΩF or more, and TCC of ±22% or less in the temperature range of -55°C to 125°C. Examples that can achieve the above characteristics are described below.

[0211] The RC value is the product of the room temperature capacitance value measured at AC 0.2V / μm and 1kHz and the insulation resistance value measured at DC 10V / μm.

[0212] [Table 1]

[0213] [Table 2]

[0214] Examples 1-1 to 1-6 in Table 1 show examples according to the mixing milling time of the batch process when, relative to 100 mol of the main component BaTiO3 matrix of 150 nm size, the sum of the variable valence elements (Mn, V) of the first subcomponent is 0.3 mol, the content of the second subcomponent Mg is 1.0 mol, the content of the third subcomponent Dy2O3 is 0.5 mol (1.0 mol based on the Dy element), the content of the fourth subcomponent Ba or Ca is 0.8 mol, and the content of the fifth subcomponent SiO2 is 1.65 mol.

[0215] 1-1 to 1-6 in Table 2 show the characteristics of the prototype MLCC chips corresponding to these examples.

[0216] At the shortest batch milling time of 2 hours (Example 1-1), no grains with a dislocation length of 150 nm or more were observed, and no grain boundaries with 3.0 at% or more of Si dissolved in the BT lattice were observed. In a HALT evaluation at a temperature of 150°C and an electric field of 42 V / μm, the MTTF value was 52 hours, demonstrating poor performance of less than 100 hours. When the batch milling time was increased to 4 hours (Example 1-2), no grain boundaries with 3.0 at% or more of Si dissolved were observed, but grains with a dislocation length of 150 nm or more began to appear. At this time, the MTTF significantly improved to over 105 hours, confirming the realization of all of the target characteristics of the present invention. When the batch milling time was increased to 6 hours (Example 1-3), crystal grains with a sum of dislocation lengths of 150 nm or more within a single crystal grain were present, and grain boundaries with 3.0 at% or more of Si dissolved in the BT lattice were observed, with the MTTF being 156 hours, which was even higher than in Examples 1-1 and 1-2. When the batch milling time was further increased to 8 hours and 10 hours (Examples 1-4 and 1-5), crystal grains with a sum of dislocation lengths of 150 nm or more within a single crystal grain and grain boundaries with 3.0 at% or more of Si dissolved in the BT lattice were more easily observed, and the MTTF was further increased to 185 hours and 205 hours, respectively. When the batch milling time was extremely long, at 30 hours (Examples 1-6), crystal grains in which the sum of the dislocation lengths within a single crystal grain was 150 nm or more and grain boundaries in which 3.0 at% or more of Si was dissolved in the BT lattice were more readily observed simultaneously, and the MTTF further increased to 224 hours, but the dielectric constant decreased to less than 2000. Therefore, if a microstructure in which the sum of the dislocation lengths within a crystal grain was 150 nm or more and grain boundaries in which 3.0 at% or more of Si was dissolved in the BT lattice were simultaneously present within a range in which the dielectric constant was 2000 or more could be realized, all of the following properties could be achieved: dielectric constant ≥ 2000, HALT MTTF ≥ 100 hours at a temperature of 150°C and an electric field of DC 42 V / μm, RC value ≥ 1000 ΩF, and TCC ≤ ±22% in the temperature range of -55°C to 125°C.

[0217] Example 2-1 uses the same batch milling time and auxiliary ingredients as Examples 1-4, but is fired in a firing atmosphere with an EMF of 680 mV (hydrogen concentration of 0.1%), lower than the EMF of 760 mV (hydrogen concentration of 0.5%). Table 2 shows the characteristics of a prototype MLCC chip under these conditions. That is, Example 2-1 uses the same composition and batch milling time as Examples 1-4, but under conditions of a low hydrogen concentration in the firing atmosphere, the sum of dislocation lengths within the crystal grains is 150 nm or more, and the MTTF is 103 hours, showing good characteristics. However, there are no grain boundaries where Si is dissolved in the BT lattice at 3.0 at% or more, and the MTTF is lower than the 185 hours of Example 1-4. Example 2-2 uses the same conditions as Examples 1-4, but the SiO2 content is reduced to 0.8 mol. In this case, the same batch milling time and firing atmosphere as in Examples 1-4 were used. However, when the SiO2 content was low, the sum of dislocation lengths within the crystal grains was 150 nm or more, and the MTTF was 112 hours. Although the properties were good, there were no grain boundaries with 3.0 at% or more of Si dissolved in the BT lattice, which was lower than the MTTF of 185 hours in Examples 1-4. Example 2-3 shows an example in which the SiO2 content of Example 1-1 was increased to 3.0 mol. However, when the batch milling time was short (2 hours) and the SiO2 content was high, there were grain boundaries with 3.0 at% or more of Si dissolved in the BT lattice, but there were no crystal grains with a sum of dislocation lengths within the crystal grains of 150 nm or more. In this case, the MTTF was 46 hours, which does not meet the target characteristic of the present invention, MTTF ≥ 100 hours.

[0218] Therefore, to achieve the target characteristic of the present invention, MTTF ≥ 100 hours, it is necessary to have crystal grains containing dislocations whose sum of lengths is 150 nm or more. Furthermore, it is clear that the MTTF can be further improved if there are grain boundaries in which Si is dissolved in the BT lattice at a concentration of 3.0 at% or more.

[0219] [Table 3]

[0220] [Table 4]

[0221] Examples 3-1 to 5-6 in Table 3 show examples where the contents of the third, second, and first subcomponents are changed relative to 100 mol of BaTiO3 base material with a main component size of 150 nm, and Table 4 shows the characteristics of prototype MLCC chips corresponding to these examples.

[0222] Examples 3-1 to 3-5 correspond to examples in which the content of the third subcomponent, Dy2O3, was changed.

[0223] When the content of the third minor component Dy2O3 is as low as 0.2 mol or 0.4 at% in element ratio (Example 3-1), the MTTF is degraded to 55 hours, which falls under the target of less than 100 hours of the present invention, and the target characteristics are not achieved.When the content of Dy2O3 is excessively high as 2.0 mol or 4.0 at% in element ratio (Example 3-5), the MTTF is degraded to 83 hours, which falls under the target of less than 100 hours of the present invention, and the TCC characteristics also deviate by more than ±22%, and the target characteristics of the present invention are not achieved. When the Dy2O3 content is 0.3 to 1.5 mol or the Dy element ratio is in the range of 0.6 to 3.0 at % (Examples 3-2 to 3-4), all of the following properties can be satisfied: dielectric constant ≥ 2000, HALT evaluation MTTF ≥ 100 hours under temperature conditions of 150°C and electric field conditions of DC 42 V / μm, RC ≥ 1000 ΩF, and TCC ≤ ±22% in the temperature range of -55°C to 125°C.

[0224] Examples 4-1 to 4-4 correspond to examples in which the content of the second minor component, MgCO3, is changed. When the second minor component, Mg, is added, the effect of increasing the RC value can be achieved.

[0225] When the content of the second subcomponent MgCO3 is excessively high at 2.5 mol or 2.5 at% (Example 4-4), the MTTF is 55 hours, which falls within the range of less than 100 hours targeted by the present invention, and the characteristics are not realized. Therefore, when the MgCO3 content is 0 to 2.0 mol or the Mg element ratio is within the range of 0 to 2.0 at% (Examples 4-1 to 4-3), all of the characteristics targeted by the present invention can be realized.

[0226] Examples 5-1 to 5-6 correspond to examples where the content of the first minor component, MnO2 or V2O5, is changed. The content of the first minor component may refer to the sum of the contents of MnO2 and V2O5, or may refer to the content of MnO2 or V2O5 when added alone.

[0227] When the sum of the contents of the first minor component transition metals Mn and V is excessively low at an elemental ratio of less than 0.1 at% (Example 5-1), the MTTF is 45 hours, which falls within the 100 hours or less target of the present invention, and the characteristics are not realized. When MnO2 or V2O5 is added with Mn alone or V alone at an elemental ratio of 0.5 at% (Examples 5-5 to 5-6), the target characteristics of the present invention can be realized in both cases. Therefore, when the content of the first minor component is within the range of 0.2 to 1.4 at% in elemental ratio (Examples 5-2 to 5-6), all of the characteristics targeted by the present invention can be realized.

[0228] [Table 5]

[0229] [Table 6]

[0230] Examples 6-1 to 10-2 in Table 5 show examples where the contents of the fourth and fifth subcomponents are changed relative to 100 mol of BaTiO3 base material with a size of 150 nm as the main component, and Table 6 shows the characteristics of the prototype MLCC chips corresponding to these examples.

[0231] When the content of the fifth subcomponent, SiO2, was as low as 0.5 ml (Examples 6-1 to 6-3), the sintered density was low regardless of the content of the fourth subcomponent, and the room-temperature dielectric constant and MTTF were below the target values ​​of the present invention, making it difficult to achieve the target characteristics of the present invention. When an appropriate amount of Ba was added at each SiO2 content, resulting in a (Ba + Ca) / Si ratio of 0.48 (Examples 7-2, 8-3, and 9-2), the room-temperature dielectric constant was improved while satisfying all the characteristics of the present invention, compared to when that ratio was zero or close to zero (Examples 7-1, 8-1, and 9-1). However, when excessive SiO2 was added, resulting in a (Ba + Ca) / Si ratio of 1.88 (Examples 7-4, 8-5, and 9-4), the room-temperature dielectric constant was less than 2000 or the MTTF was less than 100 hours, failing to meet the target characteristics of the present invention.

[0232] Therefore, it can be confirmed from Examples 6-1 to 9-4 that the target characteristics of the present invention are achieved when the ratio of the fourth and fifth subcomponents (Ba+Ca) / Si satisfies the range of 1.60 or less.

[0233] Examples 10-1 to 10-2 show examples in which the content of BaCO3 is changed when the content of the fifth subcomponent SiO2 is excessive at 4.0 mol or 4.0 at% in element ratio. In this case, even if the ratio of the fourth and fifth subcomponents (Ba+Ca) / Si satisfies the range of 1.60 or less, it can be confirmed that it may be difficult to achieve the target characteristics because the room temperature dielectric constant and MTTF are lower than the target values ​​of the present invention.

[0234] Therefore, to summarize examples of changes in the fourth and fifth minor components, when the content of the fourth minor component is 4.8 mol or less or 4.8 at % or less in element ratio, the content of the fifth minor component, SiO2, satisfies the range of 0.8 to 3.0 mol or 0.8 to 3.0 at % in element ratio, and the ratio of the fourth minor component to the fifth minor component (Ba + Ca) / Si satisfies the range of 1.60 or less, all of the characteristics of the present invention can be realized.

[0235] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications, and changes may be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention.

[0236] Furthermore, the expression "one embodiment" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe each unique feature that is different from the others. However, the above-described one embodiment does not exclude being realized in combination with features of another embodiment. For example, even if a feature described in a particular embodiment is not described in another embodiment, it can be understood as a description of another embodiment unless there is a description in the other embodiment that contradicts or contradicts that feature.

[0237] The terms used in the present invention are merely used to describe one embodiment and are not intended to limit the present invention. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0238] 10, 10': first dielectric crystal grain 11: Dislocation 12:First grain boundary 100: Multilayer electronic components 110:Main body 111: Dielectric layer 112, 113: Cover part 114, 115: Margin 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: first electrode layer 131b, 132b: Second electrode layer 131c, 132c: plating layer

Claims

1. BaTiO ３ a body including a dielectric layer containing a system main component and an internal electrode; an external electrode disposed on the body; Including, The dielectric layer includes first dielectric crystal grains including at least one defect having a total length of 150 nm or more; the dielectric layer includes a first minor component including at least one of an oxide or a carbonate of a variable valence acceptor element, the variable valence acceptor element including at least one of Mn, V, Cr, Fe, Ni, Co, Cn, and Zn, and a content of the variable valence acceptor element included in the first minor component is 0.2 mol to 1.4 mol with respect to 100 mol of the main component; the dielectric layer includes a second minor component including at least one of an oxide or a carbonate of Mg, and the content of Mg element included in the second minor component is 0 mol to 2.0 mol with respect to 100 mol of the main component; the dielectric layer further includes a third minor component including at least one of an oxide and a carbonate of a rare earth element, the rare earth element including at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd, and Yb, and the content of the rare earth element included in the third minor component is 0.6 mol to 3.0 mol with respect to 100 mol of the main component; the dielectric layer includes a fourth minor component including at least one of an oxide and a carbonate of at least one element selected from Ba and Ca, and a total content of at least one element selected from Ba and Ca included in the fourth minor component is 0 mol to 4.8 mol relative to 100 mol of the main component; the dielectric layer includes a fifth minor component including at least one of an oxide of Si, a carbonate of Si, and a glass containing Si, and the content of the Si element included in the fifth minor component is 0.8 mol to 3.0 mol with respect to 100 mol of the main component; A multilayer electronic component, wherein a ratio (4s / 5s) of a content (4s) of one or more elements selected from Ba and Ca contained in the fourth subcomponent to a content (5s) of Si element contained in the fifth subcomponent satisfies 4s / 5s≦1.

60.

2. 2. The multilayer electronic component according to claim 1, wherein a sum of lengths of defects contained in the first dielectric crystal grains is equal to or greater than 158 nm and less than 843 nm.

3. the dielectric layer includes a plurality of dielectric crystal grains including the first dielectric crystal grains, and grain boundaries disposed between adjacent dielectric crystal grains; 2. The multilayer electronic component according to claim 1, wherein the grain boundaries include a first grain boundary that includes a region having a Si content of 3.0 at % or more within 2 nm from the grain boundaries in a direction perpendicular to the grain boundaries.

4. Solvent, dispersant, and BaTiO ３ providing and milling a dielectric composition comprising a dielectric powder base component; adding a binder to the dielectric composition and milling the mixture to form a slurry; forming a ceramic green sheet using the slurry; printing a conductive paste for an internal electrode on the ceramic green sheets and then laminating the printed ceramic green sheets to form a laminate; firing the laminate to form a body including dielectric layers and internal electrodes; forming an external electrode on the body; Including, In the step of milling the dielectric composition, the dielectric composition is milled for 4 hours or more; The dielectric composition further includes a first minor component including at least one of an oxide or a carbonate of a variable valence acceptor element, the variable valence acceptor element including at least one of Mn, V, Cr, Fe, Ni, Co, Cn, and Zn, and the content of the variable valence acceptor element included in the first minor component is 0.2 mol to 1.4 mol with respect to 100 mol of the main component; The dielectric composition includes a second minor component including at least one of an oxide or a carbonate of Mg, and the content of the Mg element included in the second minor component is 0 mol or more and 2.0 mol or less with respect to 100 mol of the main component; The dielectric composition further includes a third minor component including at least one of an oxide and a carbonate of a rare earth element, the rare earth element including at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd, and Yb, and the content of the rare earth element included in the third minor component is 0.6 mol or more and 3.0 mol or less with respect to 100 mol of the main component, The dielectric composition includes a fourth minor component including at least one of an oxide and a carbonate of at least one element selected from Ba and Ca, and a total content of at least one element selected from Ba and Ca included in the fourth minor component is 0 mol to 4.8 mol relative to 100 mol of the main component; The dielectric composition includes a fifth minor component including at least one of an oxide of Si, a carbonate of Si, and a glass containing Si, and the content of the Si element included in the fifth minor component is 0.8 mol to 3.0 mol with respect to 100 mol of the main component; a ratio (4s / 5s) of a content (5s) of one or more elements selected from Ba and Ca contained in the fourth subcomponent to a content (5s) of Si element contained in the fifth subcomponent satisfies 4s / 5s≦1.

60.

5. 5. The method for manufacturing a multilayer electronic component according to claim 4, wherein the dielectric layer includes first dielectric crystal grains including at least one defect whose total length is 150 nm or more.

6. 6. The method for producing a multilayer electronic component according to claim 5, wherein a sum of lengths of defects contained in the first dielectric crystal grains is equal to or greater than 158 nm and less than 843 nm.

7. the dielectric layer includes a plurality of dielectric crystal grains including the first dielectric crystal grains, and grain boundaries disposed between adjacent dielectric crystal grains; 6. The method for producing a multilayer electronic component according to claim 5, wherein the grain boundaries include a first grain boundary that includes a region having a Si content of 3.0 at % or more within 2 nm from the grain boundaries in a direction perpendicular to the grain boundaries.

8. The method for producing a multilayer electronic component according to claim 4 , wherein in the step of milling the dielectric composition, the dielectric composition is milled for 4 hours or more and less than 30 hours.

9. The method for manufacturing a multilayer electronic component according to claim 4 , wherein in the step of forming the body, the firing is performed in an atmosphere of EMF 760 mV or more.

10. 5. The method for manufacturing a multilayer electronic component according to claim 4, wherein in the step of forming the main body, the firing is carried out in an atmosphere with a hydrogen concentration of 0.5% or more.

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