Display device and method for manufacturing the same

Abstract

To provide a manufacturing method for a display device, in which decrease in reliability can be suppressed.SOLUTION: In one embodiment, a manufacturing method for a display device includes forming a lower electrode over a substrate, forming an insulating layer overlapping with the lower electrode, forming a first aluminum layer over the insulating layer, forming an intermediate layer on the first aluminum layer, forming a second aluminum layer on the intermediate layer, forming a thin film over the second aluminum layer, etching the first aluminum layer, the intermediate layer, the second aluminum layer, and the thin film, forming a partition wall including a lower part including the first aluminum layer, the intermediate layer, and the second aluminum layer, and including an upper part including the thin film and protruding from a side surface of the lower part, forming an organic layer existing on the lower electrode, and forming an upper electrode existing on the organic layer and in contact with the lower part of the partition wall.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a method for manufacturing the display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: A lower electrode is formed above a substrate, an insulating layer is formed overlapping the lower electrode, a first aluminum layer is formed above the insulating layer, an intermediate layer is formed on the first aluminum layer, a second aluminum layer is formed on the intermediate layer, a thin film is formed above the second aluminum layer, the first aluminum layer, the intermediate layer, the second aluminum layer, and the thin film are etched, a partition wall is formed having a lower portion including the first aluminum layer, the intermediate layer, and the second aluminum layer, and an upper portion including the thin film and protruding from a side surface of the lower portion, an organic layer is formed above the lower electrode, and an upper electrode is formed above the organic layer and in contact with the lower portion of the partition wall.

[0006] According to one embodiment, the display device comprises: The device comprises a substrate, a lower electrode disposed above the substrate, an insulating layer formed of an inorganic material and having an opening overlapping with the lower electrode, a partition having a lower portion disposed on the insulating layer and an upper portion protruding from a side surface of the lower portion, an organic layer disposed on the lower electrode and spaced apart from the lower portion of the partition, the organic layer including a light-emitting layer, and an upper electrode disposed on the organic layer, wherein the lower portion includes a first aluminum layer and a second aluminum layer disposed on the first aluminum layer, and the upper electrode is in contact with a side surface of the first aluminum layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. [Figure 5] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining the process of preparing the processing substrate SUB. [Figure 7] FIG. 7 is a diagram for explaining the step of preparing the processing substrate SUB. [Figure 8] FIG. 8 is a diagram for explaining the step of preparing the processing substrate SUB. [Figure 9] FIG. 9 is a diagram for explaining the step of preparing the processing substrate SUB. [Figure 10] FIG. 10 is a diagram for explaining another step of preparing the processing substrate SUB. [Figure 11] FIG. 11 is a diagram for explaining another step of preparing the processing substrate SUB. [Figure 12] FIG. 12 is a cross-sectional view of the processing substrate SUB prepared through step ST1. [Figure 13] FIG. 13 is a diagram illustrating the step of forming the first thin film 31. As shown in FIG. [Figure 14] FIG. 14 is a diagram for explaining the step of forming the resist 41. As shown in FIG. [Figure 15] FIG. 15 is a diagram for explaining a step of etching using the resist 41 as a mask. [Figure 16] FIG. 16 is a diagram illustrating the step of removing the resist 41. As shown in FIG. [Figure 17] FIG. 17 is an enlarged cross-sectional view of the partition wall 6 between the subpixels SPα and SPβ. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, both of which are disposed on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display elements 20 are organic light-emitting diodes (OLEDs) that function as light-emitting elements and may be referred to as organic EL elements. For example, the subpixel SP1 includes a display element 20 that emits light in the red wavelength range, the subpixel SP2 includes a display element 20 that emits light in the green wavelength range, and the subpixel SP3 includes a display element 20 that emits light in the blue wavelength range.

[0018] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, the subpixels SP1 and SP2 are aligned in the first direction X with the subpixel SP3.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0021] In the display area DA, ribs 5 and partition walls 6 are arranged. The ribs 5 have openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, opening AP2 is larger than opening AP1, and opening AP3 is larger than opening AP2.

[0022] The partitions 6 overlap the ribs 5 in a plan view. The partitions 6 have a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The plurality of first partitions 6x are respectively arranged between the openings AP1 and AP2 adjacent to each other in the second direction Y and between two openings AP3 adjacent to each other in the second direction Y. The second partitions 6y are respectively arranged between the openings AP1 and AP3 adjacent to each other in the first direction X and between the openings AP2 and AP3 adjacent to each other in the first direction X.

[0023] 2, the first partition 6x and the second partition 6y are connected to each other. As a result, the partition 6 as a whole is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib 5.

[0024] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with aperture AP3.

[0025] In the example of FIG. 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. The peripheral edges of the lower electrodes LE1, LE2, and LE3 overlap the ribs 5. The outline of the upper electrode UE1 roughly matches the outline of the organic layer OR1, and the peripheral edges of the upper electrode UE1 and the organic layer OR1 overlap the partition walls 6. The outline of the upper electrode UE2 roughly matches the outline of the organic layer OR2, and the peripheral edges of the upper electrode UE2 and the organic layer OR2 overlap the partition walls 6. The outline of the upper electrode UE3 roughly matches the outline of the organic layer OR3, and the peripheral edges of the upper electrode UE3 and the organic layer OR3 overlap the partition walls 6.

[0026] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 20 of the subpixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to, for example, the cathode of the display element 20, or a common electrode.

[0027] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0028] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on an insulating layer (organic insulating layer) 12. An insulating layer (inorganic insulating layer) 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered with ribs 5.

[0030] The partition 6 includes a lower portion (stem) 61 disposed on the rib 5, and an upper portion (cap) 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61 in FIG. 3. Such a shape of the partition 6 can also be said to be overhanging.

[0031] 2 includes a first portion OR1a and a second portion OR1b spaced apart from each other, as shown in FIG. 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a part of the rib 5. The second portion OR1b is located on the upper portion 62. 2 includes a first portion UE1a and a second portion UE1b spaced apart from each other, as shown in FIG. 3. The first portion UE1a faces the lower electrode LE1 and is located on the first portion OR1a. The first portion UE1a contacts a side surface of the lower portion 61. The second portion UE1b is located above the partition wall 6 and on the second portion OR1b.

[0032] 2 includes a first portion OR2a and a second portion OR2b spaced apart from each other, as shown in Fig. 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a part of the rib 5. The second portion OR2b is located on the upper portion 62. 2 includes a first portion UE2a and a second portion UE2b spaced apart from each other, as shown in FIG. 3. The first portion UE2a faces the lower electrode LE2 and is located on the first portion OR2a. The first portion UE2a contacts a side surface of the lower portion 61. The second portion UE2b is located above the partition wall 6 and on the second portion OR2b.

[0033] 2 includes a first portion OR3a and a second portion OR3b spaced apart from each other, as shown in FIG. 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a part of the rib 5. The second portion OR3b is located on the upper portion 62. 2 includes a first portion UE3a and a second portion UE3b spaced apart from each other, as shown in FIG. 3. The first portion UE3a faces the lower electrode LE3 and is located on the first portion OR3a. The first portion UE3a contacts a side surface of the lower portion 61. The second portion UE3b is located above the partition wall 6 and on the second portion OR3b.

[0034] In the example shown in FIG. 3, the subpixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0035] The cap layer CP1 includes a first portion CP1a and a second portion CP1b spaced apart from each other. The first portion CP1a is located in the opening AP1 and above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and above the second portion UE1b.

[0036] The cap layer CP2 includes a first portion CP2a and a second portion CP2b spaced apart from each other. The first portion CP2a is located in the opening AP2 and above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and above the second portion UE2b.

[0037] The cap layer CP3 includes a first portion CP3a and a second portion CP3b spaced apart from each other. The first portion CP3a is located in the opening AP3 and above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and above the second portion UE3b.

[0038] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the components of the subpixel SP1, including the first portion CP1a, the partition wall 6, and the second portion CP1b. The sealing layer SE2 continuously covers the components of the subpixel SP2, including the first portion CP2a, the partition wall 6, and the second portion CP2b. The sealing layer SE3 continuously covers the components of the subpixel SP3, including the first portion CP3a, the partition wall 6, and the second portion CP3b.

[0039] 3, the second portion OR1b, the second portion UE1b, the second portion CP1b, and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the second portion OR3b, the second portion UE3b, the second portion CP3b, and the sealing layer SE3 on the partition wall 6. In addition, the second portion OR2b, the second portion UE2b, the second portion CP2b, and the sealing layer SE2 on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart from the second portion OR3b, the second portion UE3b, the second portion CP3b, and the sealing layer SE3 on the partition wall 6.

[0040] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. Furthermore, the sealing layer 14 is covered with a resin layer 15.

[0041] The insulating layer 12 is made of an organic material. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are made of an inorganic material such as silicon nitride (SiNx). The thickness of the rib 5 made of an inorganic material is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the rib 5 is 200 nm or more and 400 nm or less.

[0042] The lower portion 61 of the partition wall 6 is made of a conductive material. Both the lower portion 61 and the upper portion 62 of the partition wall 6 may be conductive.

[0043] The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or may have a laminated structure of a metal material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 may be formed of a transparent conductive material such as ITO.

[0044] When the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, UE3, the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes. Also, when the potential of the upper electrodes UE1, UE2, UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3 correspond to anodes and the lower electrodes LE1, LE2, LE3 correspond to cathodes.

[0045] The organic layers OR1, OR2, and OR3 each include a plurality of functional layers. The first portion OR1a and the second portion OR1b of the organic layer OR1 each include an emitting layer EM1 formed of the same material. The first portion OR2a and the second portion OR2b of the organic layer OR2 each include an emitting layer EM2 formed of the same material. The first portion OR3a and the second portion OR3b of the organic layer OR3 each include an emitting layer EM3 formed of the same material. The emitting layers EM1, EM2, and EM3 are formed of materials that emit light in different wavelength ranges.

[0046] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These thin films have different refractive indices. The material of the thin films constituting the multilayer structure is different from the material of the upper electrodes UE1, UE2, and UE3 and also different from the material of the sealing layers SE1, SE2, and SE3. The cap layers CP1, CP2, and CP3 may be omitted.

[0047] A common voltage is supplied to the partition 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of the upper electrodes in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in the subpixels SP1, SP2, and SP3, respectively.

[0048] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 in the first portion OR1a of the organic layer OR1 emits light in the red wavelength range. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 in the first portion OR2a of the organic layer OR2 emits light in the green wavelength range. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 in the first portion OR3a of the organic layer OR3 emits light in the blue wavelength range.

[0049] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0050] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. The lower electrode LE shown in Fig. 4 corresponds to each of the lower electrodes LE1, LE2, and LE3 in Fig. 3. The organic layer OR shown in Fig. 4 corresponds to each of the organic layers OR1, OR2, and OR3 in Fig. 3. The upper electrode UE shown in Fig. 4 corresponds to each of the upper electrodes UE1, UE2, and UE3 in Fig. 3.

[0051] The organic layer OR includes a carrier adjustment layer CA1, an emitting layer EM, and a carrier adjustment layer CA2. The carrier adjustment layer CA1 is located between the lower electrode LE and the emitting layer EM, and the carrier adjustment layer CA2 is located between the emitting layer EM and the upper electrode UE. The carrier adjustment layers CA1 and CA2 each include multiple functional layers. The following description will be given taking as an example a case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode.

[0052] The carrier adjustment layer CA1 includes, as functional layers, a hole injection layer F11, a hole transport layer F12, an electron blocking layer F13, etc. The hole injection layer F11 is disposed on the lower electrode LE, the hole transport layer F12 is disposed on the hole injection layer F11, the electron blocking layer F13 is disposed on the hole transport layer F12, and the light-emitting layer EM is disposed on the electron blocking layer F13.

[0053] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, an electron injection layer F23, etc. The hole blocking layer F21 is disposed on the light-emitting layer EM, the electron transport layer F22 is disposed on the hole blocking layer F21, the electron injection layer F23 is disposed on the electron transport layer F22, and the upper electrode UE is disposed on the electron injection layer F23.

[0054] In addition to the above-mentioned functional layers, the carrier adjustment layers CA1 and CA2 may include other functional layers such as a carrier generation layer as necessary, or at least one of the above-mentioned functional layers may be omitted.

[0055] Next, an example of a method for manufacturing the display device DSP will be described.

[0056] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. The manufacturing method shown here roughly includes a step of preparing a processing substrate SUB that serves as a base for the subpixels SPα, SPβ, and SPγ (step ST1), and a step of forming the subpixels SPα (step ST2). After step ST2, a step of forming the subpixel SPβ, which is similar to the step of forming the subpixel SPα, is performed, and then a step of forming the subpixel SPγ is performed. Note that the subpixels SPα, SPβ, and SPγ here are any of the subpixels SP1, SP2, and SP3 described above.

[0057] In step ST1, first, a processing substrate SUB is prepared on which lower electrodes LEα, LEβ, LEγ, ribs 5, and partition walls 6 are formed on a substrate 10. Details will be described later.

[0058] In step ST2, first, a first thin film 31 including an emitting layer EMα is formed on a processing substrate SUB (step ST21). Then, a resist 41 patterned into a predetermined shape is formed on the first thin film 31 (step ST22). Then, a part of the first thin film 31 is removed by etching using the resist 41 as a mask (step ST23). Then, the resist 41 is removed (step ST24). This forms a subpixel SPα. The subpixel SPα includes a display element 21 having a first thin film 31 of a predetermined shape.

[0059] The process of forming the subpixel SPβ includes steps similar to steps ST21 to ST24, but in step ST21, a second thin film 32 including an emitting layer EMβ is formed instead of the first thin film 31. The second thin film 32 is then patterned to form the subpixel SPβ. The subpixel SPβ includes a display element 22 having the second thin film 32 in a predetermined shape.

[0060] The process of forming the subpixel SPγ includes steps similar to steps ST21 to ST24, but in step ST21, a third thin film 33 including an emitting layer EMγ is formed instead of the first thin film 31. The subpixel SPγ is formed by patterning the third thin film 33. The subpixel SPγ includes a display element 23 having the third thin film 33 in a predetermined shape.

[0061] The light-emitting layers EMα, EMβ, and EMγ are formed of materials that emit light in different wavelength ranges.

[0062] 6 to 11 are diagrams illustrating the process of preparing the processing substrate SUB. Each diagram shows an enlarged view of the portion of the processing substrate SUB where the partition wall 6 between the subpixels SPα and SPβ is to be formed. 6, lower electrodes LEα and LEβ are formed above the substrate 10. The circuit layer 11 and the insulating layer 12 are interposed between the substrate 10 and the lower electrodes LEα and LEβ. The lower electrodes LEα and LEβ are located on the insulating layer 12. 6, ribs 5 are formed so as to overlap the lower electrodes LEα and LEβ. The ribs 5 are insulating layers made of an inorganic material. The ribs 5 overlap the insulating layer 12 between the lower electrodes LEα and LEβ. 6, a metal layer 601 is formed on the ribs 5. The metal layer 601 is thinner than the ribs 5.

[0063] Next, as shown in the upper part of FIG. 7, a first aluminum layer 611 is formed above the rib 5 and on the metal layer 601. Such a first aluminum layer 611 is formed by performing continuous sputtering until the thickness thereof becomes 500 nm or less. The first aluminum layer 611 is thicker than the metal layer 601. The thickness of the first aluminum layer 611 is, for example, greater than the thickness of the rib 5, and is 200 nm or more and 500 nm or less, and preferably 400 nm or less. The first aluminum layer 611 is formed, for example, from pure aluminum.

[0064] When forming an aluminum layer, if the sputtering time is long, aluminum crystal grains are likely to grow due to the influence of heat from plasma, etc. According to the inventor's research, it was confirmed that crystal grains begin to appear when continuous sputtering is performed until the aluminum layer reaches a thickness of 400 nm or more. If continuous sputtering is performed until the aluminum layer reaches a thickness of more than 500 nm, the crystal grains may grow, potentially causing defects. For example, if crystal grains grow locally, the flatness of the surface of the first aluminum layer 611 may be impaired. Furthermore, if crystal grains adhere to undesired locations, defects may occur in subsequent processes.

[0065] As shown in the lower part of FIG. 7, an intermediate layer 61M is formed on the first aluminum layer 611. The intermediate layer 61M is a metal layer formed by sputtering a material different from the material of the first aluminum layer 611. For example, the intermediate layer 61M is formed from molybdenum or an aluminum alloy. By forming such an intermediate layer 61M, the growth of aluminum crystal grains when the first aluminum layer 611 is formed is suppressed.

[0066] 7, the thickness T1 of the first aluminum layer 611 shown in the upper part is equal to the thickness T2 of the first aluminum layer 611 shown in the lower part. The thickness T3 of the intermediate layer 61M is smaller than the thickness T2.

[0067] Next, as shown in the upper part of FIG. 8, a second aluminum layer 612 is formed on the intermediate layer 61M. Such second aluminum layer 612 is formed by continuous sputtering until it has a thickness of 500 nm or less. The thickness of the second aluminum layer 612 is the same as that of the first aluminum layer 611, and is, for example, 200 nm or more and 500 nm or less, and preferably 400 nm or less. The second aluminum layer 612 is formed, for example, from pure aluminum.

[0068] The total thickness of the first aluminum layer 611 and the second aluminum layer 612 is greater than 500 nm, for example, even greater than or equal to 700 nm.

[0069] The step of forming second aluminum layer 612 may be performed using the same manufacturing equipment as that used in the step of forming first aluminum layer 611, or may be performed using a different manufacturing equipment. Here, an example has been described in which a laminate of a first aluminum layer 611 and a second aluminum layer 612 is formed as the aluminum layer, but three or more aluminum layers may be formed by repeating a similar sputtering process.

[0070] Next, as shown in the lower part of FIG. 8, a thin film 620 is formed above the second aluminum layer 612. In the example shown in FIG. 8, the thin film 620 is formed by forming a first layer 621 on the second aluminum layer 612, and then forming a second layer 622 on the first layer 621. The thin film 620 is thinner than the second aluminum layer 612 and the rib 5. The second layer 622 is thinner than the first layer 621. The thin film 620 may be a single layer, or may be a laminate of three or more layers.

[0071] Next, as shown in FIG. 9, the metal layer 601, the first aluminum layer 611, the intermediate layer 61M, the second aluminum layer 612, and the thin film 620 are etched. This forms the partition wall 6 having a lower portion 61 and an upper portion 62. The lower portion 61 includes the metal layer 601, the first aluminum layer 611, the intermediate layer 61M, and the second aluminum layer 612. The upper portion 62 includes the thin film 620. The first layer 621 and the second layer 622 constituting the upper portion 62 protrude beyond the respective side surfaces 601S, 611S, 61MS, and 612S of the metal layer 601, the first aluminum layer 611, the intermediate layer 61M, and the second aluminum layer 612 constituting the lower portion 61. In the example shown in FIG. 9, the ends of the lower electrodes LEα and LEβ are located directly below the lower portion 61.

[0072] Through the above steps, a processing substrate SUB having partition walls 6 is prepared.

[0073] The method for forming the intermediate layer 61M is not limited to the above example. Other manufacturing methods will be described below.

[0074] 10, the process is the same as the above example up to the step of forming the first aluminum layer 611. The first aluminum layer 611 is formed by continuous sputtering until it has a thickness of 500 nm or less. The first aluminum layer 611 is formed of, for example, pure aluminum.

[0075] 10, the processed substrate SUB on which the first aluminum layer 611 has been formed by sputtering in the chamber is then removed from the chamber, and the first aluminum layer 611 is exposed to air. As a result, an upper layer 611T of the first aluminum layer 611 is oxidized. That is, an intermediate layer 61M of aluminum oxide is formed on the first aluminum layer 611 formed of pure aluminum. In this way, by exposing the first aluminum layer 611 to air after its formation, the growth of aluminum crystal grains when the first aluminum layer 611 is formed is suppressed.

[0076] 10, the thickness T1 of the first aluminum layer 611 shown in the upper part is greater than the thickness T2 of the first aluminum layer 611 shown in the lower part. The thickness T3 of the intermediate layer 61M is smaller than the thickness T2. The sum of the thicknesses T2 and T3 is equal to the thickness T1.

[0077] 11, a second aluminum layer 612 is formed on the intermediate layer 61M by continuous sputtering until the second aluminum layer 612 has a thickness of 500 nm or less. The second aluminum layer 612 is formed of, for example, pure aluminum. 11, a thin film 620 is formed above the second aluminum layer 612. In the example shown in FIG. 11, the thin film 620 is formed by forming a first layer 621 on the second aluminum layer 612, and then forming a second layer 622 on the first layer 621. Thereafter, etching is performed on the metal layer 601, the first aluminum layer 611, the intermediate layer 61M, the second aluminum layer 612, and the thin film 620. As a result, the partition wall 6 having a lower portion 61 and an upper portion 62 is formed.

[0078] Details of the step of forming the second aluminum layer 612, the step of forming the thin film 620, and the step of etching are as described with reference to FIGS.

[0079] The processed substrate SUB prepared through the above steps is shown in FIG. The processing substrate SUB includes, above a substrate 10, a lower electrode LEα of the subpixel SPα, a lower electrode LEβ of the subpixel SPβ, a lower electrode LEγ of the subpixel SPγ, a rib 5 having openings APα, APβ, and APγ overlapping with the lower electrodes LEα, LEβ, and LEγ, respectively, and a partition wall 6 arranged on the rib 5. Note that in Figures 13 to 16, the substrate 10 and the circuit layer 11 below the insulating layer 12 are not shown.

[0080] The step of forming the subpixel SPα shown in FIG. 5 (step ST2) will be described below.

[0081] 13, the first thin film 31 is formed over the subpixels SPα, SPβ, and SPγ. The process of forming the first thin film 31 includes the steps of forming an organic layer OR10 including an emitting layer EMα on a processing substrate SUB, forming an upper electrode UE10 on the organic layer OR10, forming a cap layer CP10 on the upper electrode UE10, and forming a sealing layer SE10 on the cap layer CP10. The sealing layer SE10 here is made of an inorganic material. That is, in the illustrated example, the first thin film 31 includes the organic layer OR10, the upper electrode UE10, the cap layer CP10, and the sealing layer SE10.

[0082] The organic layer OR10 includes a first organic layer OR11, a second organic layer OR12, a third organic layer OR13, a fourth organic layer OR14, and a fifth organic layer OR15. Each of the first organic layer OR11, the second organic layer OR12, the third organic layer OR13, the fourth organic layer OR14, and the fifth organic layer OR15 includes an emitting layer EMα. The first organic layer OR11 is formed so as to cover the lower electrode LEα. The second organic layer OR12 is spaced apart from the first organic layer OR11 and is located on an upper portion 62 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ. The third organic layer OR13 is spaced apart from the second organic layer OR12 and is formed so as to cover the lower electrode LEβ. The fourth organic layer OR14 is spaced apart from the third organic layer OR13 and is located on an upper portion 62 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ. The fifth organic layer OR15 is spaced apart from the fourth organic layer OR14 and is formed so as to cover the lower electrode LEγ.

[0083] The upper electrode UE10 includes a first upper electrode UE11, a second upper electrode UE12, a third upper electrode UE13, a fourth upper electrode UE14, and a fifth upper electrode UE15. The first upper electrode UE11 is located on the first organic layer OR11 and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ. The second upper electrode UE12 is spaced apart from the first upper electrode UE11 and is located on the second organic layer OR12 between the lower electrode LEα and the lower electrode LEβ. The third upper electrode UE13 is spaced apart from the second upper electrode UE12 and is located on the third organic layer OR13. In the illustrated example, the third upper electrode UE13 is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ, but may be in contact with either of the lower portions 61. The fourth upper electrode UE14 is spaced apart from the third upper electrode UE13 and is located on the fourth organic layer OR14 between the lower electrode LEβ and the lower electrode LEγ. The fifth upper electrode UE15 is spaced apart from the fourth upper electrode UE14, is located on the fifth organic layer OR15, and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ.

[0084] The cap layer CP10 includes a first cap layer CP11, a second cap layer CP12, a third cap layer CP13, a fourth cap layer CP14, and a fifth cap layer CP15. The first cap layer CP11 is located on the first upper electrode UE11. The second cap layer CP12 is spaced apart from the first cap layer CP11 and located on the second upper electrode UE12. The third cap layer CP13 is spaced apart from the second cap layer CP12 and located on the third upper electrode UE13. The fourth cap layer CP14 is spaced apart from the third cap layer CP13 and located on the fourth upper electrode UE14. The fifth cap layer CP15 is spaced apart from the fourth cap layer CP14 and located on the fifth upper electrode UE15.

[0085] The sealing layer SE10 is formed to cover the first cap layer CP11, the second cap layer CP12, the third cap layer CP13, the fourth cap layer CP14, the fifth cap layer CP15, and the partition wall 6.

[0086] 14, a resist 41 is formed on the sealing layer SE10. The resist 41 covers the subpixel SPα. That is, the resist 41 is disposed directly on the lower electrode LEα, the first organic layer OR11, the first upper electrode UE11, and the first cap layer CP11. The resist 41 also extends above the partition wall 6 from the subpixel SPα. Between the subpixels SPα and SPβ, the resist 41 is disposed on the subpixel SPα side (the left side of the figure) and exposes the sealing layer SE10 on the subpixel SPβ side (the right side of the figure). In the example shown, the resist 41 exposes the sealing layer SE10 in the subpixels SPβ and SPγ.

[0087] 15, etching is performed using the resist 41 as a mask to remove the first thin film 31 exposed from the resist 41. In the illustrated example, a portion of the second organic layer OR12, the entire third organic layer OR13, the entire fourth organic layer OR14, the entire fifth organic layer OR15, a portion of the second upper electrode UE12, the entire third upper electrode UE13, the entire fourth upper electrode UE14, the entire fifth upper electrode UE15, a portion of the second cap layer CP12, the entire third cap layer CP13, the entire fourth cap layer CP14, the entire fifth cap layer CP15, and a portion of the sealing layer SE10 are removed. As a result, the lower electrode LEβ is exposed in the subpixel SPβ, and the lower electrode LEγ is exposed in the subpixel SPγ.

[0088] With respect to the partition wall 6 between the subpixels SPα and SPβ, the second organic layer OR12, the second upper electrode UE12, the second cap layer CP12, and the sealing layer SE10 remain on the subpixel SPα side directly above the upper portion 62, while the second organic layer OR12, the second upper electrode UE12, the second cap layer CP12, and the sealing layer SE10 are removed on the subpixel SPβ side, thereby exposing the subpixel SPβ side of the partition wall 6. In addition, the partition wall 6 between the subpixels SPβ and SPγ is also exposed.

[0089] Then, in step ST24, the resist 41 is removed, as shown in FIG. 16. This exposes the sealing layer SE10 of the subpixel SPα. Through steps ST21 to ST24, the display element 21 is formed in the subpixel SPα. The display element 21 is composed of a lower electrode LEα, a first organic layer OR11 including an emitting layer EMα, a first upper electrode UE11, and a first cap layer CP11. The display element 21 is also covered with the sealing layer SE10.

[0090] A stacked body of a second organic layer OR12 including an emitting layer EMα, a second upper electrode UE12, and a second cap layer CP12 is formed on the partition wall 6 between the subpixels SPα and SPβ, and this stacked body is covered with a sealing layer SE10. In addition, a portion of the partition wall 6 on the side of the subpixel SPα is covered with the stacked body SE10.

[0091] 17 is an enlarged cross-sectional view of the partition wall 6 between the subpixels SPα and SPβ. Note that the first cap layer and the sealing layer are not shown in FIG. The partition wall 6 is disposed on the rib 5. A lower portion 61 of the partition wall 6 includes a metal layer 601, a first aluminum layer 611 disposed on the metal layer 601, an intermediate layer 61M disposed on the first aluminum layer 611, and a second aluminum layer 612 disposed on the intermediate layer 61M. An upper portion 62 of the partition wall 6 includes a first layer 621 and a second layer 622 formed of a material different from that of the lower portion 61. The intermediate layer 61M may be formed of a metal material such as molybdenum or an aluminum alloy, or may be formed of aluminum oxide. The first organic layer OR11 is in contact with the lower electrode LEα, extends over the rib 5, and is spaced apart from the partition wall 6. The first upper electrode UE11 covers the first organic layer OR11, is in contact with the rib 5 between the first organic layer OR11 and the partition wall 6, and is in contact with a side surface 601S of the metal layer 601 and a side surface 611S of the first aluminum layer 611.

[0092] According to this embodiment, after forming a first aluminum layer 611 having a thickness of 500 nm or less by continuous sputtering, an intermediate layer 61M is formed on the surface of the first aluminum layer 611, thereby suppressing the growth of aluminum crystal grains.

[0093] Similarly, by forming the second aluminum layer 612 having a thickness of 500 nm or less by successive sputtering, an aluminum layer with a total thickness exceeding 500 nm can be formed. Such an aluminum layer constitutes the lower portion 61 of the partition wall 6. Therefore, the partition wall 6 can be easily formed with a relatively high height. Furthermore, by controlling the thickness of each aluminum layer and adjusting the number of aluminum layers, the partition wall 6 can be easily formed with a desired height.

[0094] Furthermore, the growth of aluminum crystal grains is suppressed during the process of forming the second aluminum layer 612. This results in a flat surface of the second aluminum layer 612. Furthermore, cracks in the thin film 620 formed on the second aluminum layer 612 are suppressed.

[0095] Furthermore, adhesion of crystal grains to undesired positions such as alignment marks on the process substrate SUB is suppressed. Therefore, for example, when patterning the resist 41, the alignment marks can be read reliably, and misalignment of the resist 41 is suppressed.

[0096] Therefore, the deterioration of reliability can be suppressed.

[0097] The subpixel SPα in the above example is any one of the subpixels SP1, SP2, and SP3 shown in Fig. 2. For example, when the subpixel SPα corresponds to the subpixel SP1, the lower electrode LEα corresponds to the lower electrode LE1, the first organic layer OR11 corresponds to the first portion OR1a, the second organic layer OR12 corresponds to the second portion OR1b, the emitting layer EMα corresponds to the first emitting layer EM1, the first upper electrode UE11 corresponds to the first portion CP1a, the second upper electrode UE12 corresponds to the second portion UE1b, the first cap layer CP11 corresponds to the first portion CP1a, the second cap layer CP12 corresponds to the second portion CP1b, and the sealing layer SE10 corresponds to the sealing layer SE1.

[0098] As described above, according to this embodiment, it is possible to provide a display device and a manufacturing method thereof that can suppress a decrease in reliability and improve manufacturing yield.

[0099] Based on the display device and manufacturing method thereof described above as an embodiment of the present invention, all display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications also fall within the scope of the present invention as long as they include the gist of the present invention.

[0100] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0101] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0102] DSP…display device 10...Substrate 12...Insulating layer 5...Rib (insulating layer) 6...Partition wall 61...Lower portion 62...Upper portion SP1, SP2, SP3, SPα, SPβ, SPγ...subpixels 20, 21, 22, 23...Display element (organic EL element) LE, LE1, LE2, LE3, LEα, LEβ, LEγ...lower electrode (anode) UE, UE1, UE2, UE3, UE10...Upper electrode (cathode) OR,OR1,OR2,OR3,OR10…Organic layer CP, CP1, CP2, CP3, CP10...cap layer SE, SE1, SE2, SE3, SE10…Sealing layer

Claims

1. forming a lower electrode above the substrate; forming an insulating layer overlapping the lower electrode; forming a first aluminum layer above the insulating layer; forming an intermediate layer on the first aluminum layer; forming a second aluminum layer on the intermediate layer; forming a thin film over the second aluminum layer; etching the first aluminum layer, the intermediate layer, the second aluminum layer, and the thin film to form a partition wall having a lower portion including the first aluminum layer, the intermediate layer, and the second aluminum layer, and an upper portion including the thin film and protruding from a side surface of the lower portion; forming an organic layer overlying the lower electrode; forming an upper electrode located on the organic layer and in contact with the lower portion of the partition wall;

2. 2. The method of claim 1, wherein each of the first and second aluminum layers is formed by successive sputtering to a thickness of 500 nm or less.

3. 2. The method for manufacturing a display device according to claim 1, wherein each of the first aluminum layer and the second aluminum layer is formed of pure aluminum.

4. 2. The method for manufacturing a display device according to claim 1, wherein the intermediate layer is made of molybdenum or an aluminum alloy.

5. The method for manufacturing a display device according to claim 1 , wherein the intermediate layer is made of aluminum oxide.

6. forming a metal layer on the insulating layer before forming the first aluminum layer; the first aluminum layer is formed on the metal layer; the etching of the metal layer is performed simultaneously with the etching of the first aluminum layer; The method for manufacturing a display device according to claim 1 , wherein the upper electrode contacts each of the side surfaces of the metal layer and the first aluminum layer.

7. The method for manufacturing a display device according to claim 1 , wherein the insulating layer is made of an inorganic material.

8. The method for manufacturing a display device according to claim 1 , wherein a total thickness of the first aluminum layer and the second aluminum layer is greater than 500 nm.

9. A substrate; a lower electrode disposed above the substrate; an insulating layer formed of an inorganic material and having an opening overlapping the lower electrode; a partition wall having a lower portion disposed on the insulating layer and an upper portion protruding from a side surface of the lower portion; an organic layer disposed on the lower electrode and spaced apart from the lower portion of the partition wall, the organic layer including a light-emitting layer; an upper electrode disposed on the organic layer; the lower portion of the partition wall includes a first aluminum layer and a second aluminum layer disposed on the first aluminum layer; the upper electrode is in contact with a side surface of the first aluminum layer, The display device, wherein the lower portion of the partition wall includes an intermediate layer between the first aluminum layer and the second aluminum layer.

10. The display device according to claim 9 , wherein each of the first aluminum layer and the second aluminum layer is made of pure aluminum.

11. The display device of claim 10 , wherein the total thickness of the first aluminum layer and the second aluminum layer is greater than 500 nm.

12. 10. The display device according to claim 9, wherein the intermediate layer is made of molybdenum or an aluminum alloy.

13. The display device according to claim 9 , wherein the intermediate layer is made of aluminum oxide.

14. the lower portion of the partition wall includes a metal layer between the insulating layer and the first aluminum layer; The display device according to claim 9 , wherein the upper electrode contacts each of the side surfaces of the metal layer and the first aluminum layer.

15. The display device according to claim 9 , wherein the upper portion of the partition wall includes a thin film formed of a material different from that of the lower portion.

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