MEMORY ARRAY CIRCUIT INCLUDING WORD LINE CIRCUIT FOR IMPROVING WORD LINE SIGNAL TIMING AND ASSOCIATED METHODS - Patent application

Abstract

A memory array circuit is disclosed that includes a word line circuit that provides word line signal stability. In a memory access operation, a state of a word line signal on a word line of a memory row of the memory array can be based on a state of a word line latch during a first clock state of a latch clock signal. The word line latch receives an address decode signal generated from a decoded memory address. An inverting delay clock circuit generates clock pulses from the latch clock signal. The word line latch stores the address decode signal during the clock pulse and generates the word line signal based on the stored address decode signal. The memory address is received from an address bus. The pass-through address capture latch maximizes the time available for a decoder to decode the memory address, and the word line latch reduces fluctuations in the address signal propagated to the word line signal.

Description

[Technical Field]

[0001] The techniques of this disclosure relate to memory array circuits that store digital data, and more particularly to memory array circuits that are configured to improve timing margins and avoid word line drift. [Background technology]

[0002] Memory arrays are used in electronic devices to store large amounts of digital data for rapid access by a processing unit. A memory array is typically a two-dimensional (2D) array of memory bit cell circuits (“memory bit cells”) organized into memory rows and memory columns. A memory array is configured so that digital data bits are written to and read from the memory bit cells of a memory row. A memory row of memory bit cells in a memory array can store a data word, which may be, for example, 64, 128, or 256 bits of data, and may include additional bits for error detection and correction. In a memory read operation, a processing circuit sends an address of the data to be read to the memory array and also provides instructions for the read operation. Some bits of the address are used to determine which memory row to read. These address bits may be provided to a decoding circuit in the memory array. The memory array includes a word line corresponding to each memory row and a bit line corresponding to each memory column. A read operation involves activating the word lines coupled to all memory bit cells in a memory row.

[0003] The decoding circuitry activates a word line corresponding to the memory row containing the data word to be read. Each memory bit cell is also coupled to a bit line of a corresponding memory column. In response to the word line of the memory row being activated, stored data bits of the data word from the memory row are produced on the bit lines of the memory column. The data bits produced on the bit lines are provided to the output of the memory array and sent back to processing circuitry and / or other circuitry. Fluctuations in the word line signal activating a word line during a read operation can cause the read operation to return erroneous data.

[0004] The operation of the processing circuitry and memory array circuitry is synchronized by a periodic system clock signal. The system clock signal is typically in a first clock state for part of the clock period and in a second clock state for the remainder of the clock period based on a clock duty cycle. Signals are triggered to propagate from a source to a destination by an edge (e.g., a rising or falling voltage level) of the system clock signal and can be captured on another clock edge. The state of the signal can be captured and stored in sequential storage circuits such as latches, flip-flops, registers, bit cells, or other memory circuits. The captured signals can be, for example, stored in sequential storage circuits such as latches, flip-flops, registers, bit cells, or other memory circuits, e.g., in sequential storage circuits (e.g., V SS or V DD ) can be a binary value (e.g., "0" or "1") indicated by the received signal. If the received signal remains stable, the voltage level of the signal can be captured accurately and reliably. Furthermore, fluctuations in the signals controlling the read or write operations can cause errors in the data written to and read from the memory array circuitry. As the speed of processing circuits increases, the period of the system clock signal decreases, shortening the time it takes for the signal to stabilize. Memory arrays must receive and decode memory addresses within shorter clock periods to improve timing robustness. Summary of the Invention

[0005] Exemplary embodiments disclosed herein include memory array circuits including word line circuits for improving word line signal timing. Related methods for providing stable word line signals within a memory array are also disclosed. In a memory access operation of the exemplary embodiment, a state of a word line signal on a word line of a memory row of the memory array can be generated based on a word line latch during a first clock state of a latch clock signal. The word line latch receives an address decode signal generated from a decoded memory address. An inverting delay clock circuit is configured to generate a self-time pulse from the latch clock signal during the first clock state. The word line latch stores the address decode signal during the self-time pulse and generates the word line signal based on the stored address decode signal to isolate the word line from fluctuations in the memory address. In some examples, the memory address can be received from an address capture circuit coupled to an address bus. The address capture circuit can include a pass-through latch to maximize the time for a decoder to decode the memory address. However, fluctuations in the memory address can propagate to the address decode signal via the pass-through latch. The word line latches hold the word lines stable during memory access operations, maximizing the time to generate a more stable word line signal for accessing a memory row and reducing word line signal fluctuations during memory access operations.

[0006] An exemplary aspect disclosed herein includes a memory array circuit including a plurality of memory rows, each memory row including a plurality of memory bitcell circuits; and a word line coupled to each of the plurality of memory bitcell circuits. The memory array circuit includes an inverted delay clock circuit configured to receive a latch clock signal constituting one of a first clock state and a second clock state, to generate an inverted delayed clock signal constituting the second clock state in response to receiving the latch clock signal constituting the first clock state, and to generate an inverted delayed clock signal constituting the first clock state in response to receiving the latch clock signal constituting the second clock state. The memory array circuit also includes a plurality of word line latch circuits, each word line latch circuit coupled to a word line of one of the plurality of memory rows, to receive the latch clock signal and the inverted delayed clock signal, and to receive an address decode signal including a decode state constituting one of an active state and an inactive state. Each of the plurality of word line latches is further configured to store a decoded state of the received address decoded signal in response to the latch clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and to generate a word line signal including the stored decoded state of the address decoded signal on a word line of one of the plurality of memory rows. Each of the plurality of word line latch circuits is further configured to hold a word line signal of the stored decoded state of the address decoded signal on a word line of one of the plurality of memory rows in response to the latch clock signal constituting the first clock state and the inverted delayed clock signal constituting the second clock state, and to generate a word line signal on a word line of one of the plurality of memory rows in response to the latch clock signal constituting the second clock state,

[0007] In an exemplary aspect, an integrated circuit (IC) is disclosed that includes a memory array circuit. The memory array circuit includes a plurality of memory rows, each memory row including a plurality of memory bitcell circuits; and a word line coupled to each of the plurality of memory bitcell circuits. The memory array circuit includes an inverted delay clock circuit configured to receive a latch clock signal constituting one of a first clock state and a second clock state, generate an inverted delayed clock signal constituting the second clock state in response to receiving the latch clock signal constituting the first clock state, and generate an inverted delayed clock signal constituting the first clock state in response to receiving the latch clock signal constituting the second clock state. The memory array circuit also includes a plurality of word line latch circuits, each word line latch circuit coupled to a word line of one of the plurality of memory rows, receive the latch clock signal and the inverted delayed clock signal, and receive an address decode signal having a decode state constituting one of an active state and an inactive state. Each of the plurality of word line latch circuits is further configured to store a decoded state of the received address decoded signal in response to the latch clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and to generate a word line signal including the stored decoded state of the address decoded signal on a word line of one of the plurality of memory rows. Each of the plurality of word line latch circuits is configured to hold a word line signal of the stored decoded state of the address decoded signal on a word line of one of the plurality of memory rows in response to the latch clock signal constituting the first clock state and the inverted delayed clock signal constituting the second clock state, and to generate a word line signal of the one of the plurality of memory rows that constitutes an inactive state of the address decoded signal in response to the latch clock signal constituting the second clock state.

[0008] In another exemplary aspect, a method is disclosed for a memory array circuit including a plurality of memory rows, each memory row including memory bit cell circuits coupled to a word line. The method includes receiving a latch clock signal constituting one of a first clock state and a second clock state; generating an inverted delayed clock signal constituting the first clock state in response to the latch clock signal constituting the second clock state; and generating an inverted delayed clock signal constituting the second clock state in response to the latch clock signal constituting the first clock state. The method includes receiving, at one of the plurality of memory rows, an address decode signal including a decode state constituting one of an active state and an inactive state; and storing the decode state of the received address decode signal in response to the latch clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and generating the stored decode state of the address decode signal on a word line of the one of the plurality of memory rows. The method further includes generating a stored decoded state of the address decode signal on a word line of one of the plurality of memory rows in response to a latched clock signal constituting a first clock state and an inverted delayed clock signal constituting a second clock state, and generating an inactive state of the address decode signal on a word line of the one of the plurality of memory rows in response to a latched clock signal constituting a second clock state. [Brief explanation of the drawings]

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1]1 is a schematic diagram of a memory array circuit including an inverting delay clock circuit configured to generate a self-timed pulse in a first clock state of a latch clock signal and a word line latch configured to capture an address decode signal during the self-timed pulse, the memory array circuit generating a word line signal on a word line during the first clock state based on the word line latch. [Figure 2] 2 is a schematic diagram of an exemplary inverting delay clock circuit and word line latch of the memory array circuit of FIG. 1 configured to reduce word line signal swing. [Figure 3] 1 is a schematic diagram of word line circuitry used in a conventional memory array, where fluctuations on the address bus propagate and cause fluctuations on the word lines and hold time violations. [Figure 4] 4 is a timing diagram illustrating the signal states of a conventional memory array circuit using the word line latches of FIG. 3 and the signal states of the exemplary memory array circuit of FIG. 1 using the exemplary inverting delay clock circuit and word line latches of FIG. 2. [Figure 5A] 10 is a flow chart illustrating a method for capturing address decode signals in memory array circuitry in response to a self-timed pulse to reduce word line signal errors due to address bus fluctuations. [Figure 5B] 10 is a flow chart illustrating a method for capturing address decode signals in memory array circuitry in response to a self-timed pulse to reduce word line signal errors due to address bus fluctuations. [Figure 6] 1 is a block diagram of an exemplary processor-based system including a plurality of devices coupled to a system bus, the processor-based system including an inverting delay clock circuit configured to generate a self-timed pulse in a first clock state of a latch clock, and a word line latch configured to capture an address decode signal during the self-timed pulse and generate a word line latch based on the word line latch during the first clock state, similar to the memory array circuit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Exemplary embodiments disclosed herein include memory array circuits including word line circuits for improving word line signal timing. Related methods for providing stable word line signals within a memory array are also disclosed. In a memory access operation of the exemplary embodiment, a state of a word line signal on a word line of a memory row of the memory array can be generated based on a word line latch during a first clock state of a latch clock signal. The word line latch receives an address decode signal generated from a decoded memory address. An inverting delay clock circuit is configured to generate a self-timed pulse from the latch clock signal during the first clock state. The word line latch stores the address decode signal during the self-timed pulse and generates the word line signal based on the stored address decode signal to isolate the word line from fluctuations in the memory address. In some examples, the memory address can be received from an address capture circuit coupled to an address bus. The address capture circuit can include a pass-through latch to maximize the time for a decoder to decode the memory address. However, fluctuations in the memory address can propagate to the address decode signal through the pass-through latch. The word line latch holds the word line stable during the memory access operation. In this regard, the time to generate a more stable word line signal for accessing a memory row is maximized, reducing word line signal fluctuations during memory access operations.

[0011] 1 is a schematic diagram of an exemplary memory array circuit 100 including an inverting delayed clock circuit 102 and a plurality of word line latch circuits (“word line latches”) 104 configured to generate stable word line signals 106 on word lines 108. The memory array circuit 100 may be coupled to processing circuitry (not shown) configured to execute memory access instructions. The memory array circuit 100 includes a memory row 110 including a plurality of memory bit cell circuits (“memory bit cells”) 112. Each of the memory bit cells 112 stores a data bit 114 of a data word 116. The data words 116 may be accessed (e.g., read or written) in memory access operations in response to memory instructions executed within the processing circuitry.

[0012] The memory array circuit 100 determines the memory row 110 containing the data word 116 to be accessed in a memory access operation based on address signals 118 received on an address bus 120. The address signals 118 are received by an address capture circuit 122. The address signals 118 are synchronized with a system clock signal CLK SYS ("System Clock CLK SYS While the system clock CLK is in the first clock state, it is captured and stored in the address capture circuit 122 and held on the internal address bus 124. SYS After the system clock CLK transitions from the first clock state to the second clock state, the address signal 118 provided on the address bus 120 may propagate through the address capture circuit 122 to the internal address bus 124. In this regard, the address capture circuit 122 may propagate in response to the system clock CLK SYS When is not in the first clock state, it may be referred to as a pass-through circuit.

[0013] System clock CLK SYSIt should be noted that the states of a signal, such as first and second clock states, refer to the electrical state of the signal on a line or conductor. For example, a clock state or signal state may refer to the voltage level of a signal that is generated at a first voltage level in the first state and at a second voltage level in the second state. In this regard, the voltage levels may correspond to binary values, with a ground voltage (e.g., V ) indicating a first binary state ("0" or "1"). SS or 0 volts) and a supply voltage (e.g., V DD ) and the power supply voltage is a positive or negative voltage.

[0014] From the internal address bus 124, the address signals 118 are provided to a decode circuit 126, which decodes the address signals 118 to identify the memory row 110 to be accessed. The decode circuit 126 generates address decode signals 128 corresponding to each of the memory rows 110. Each of the address decode signals 128 is in a decode state (i.e., active or inactive) based on the address signals 118. For example, if the memory array circuit 100 includes 256 memory rows 110, the address signals 118 may include 8 bits and the decode circuit 126 may decode up to 256 memory rows 110. 8 256 address decode signals 128 can be generated, with each address decode signal 128 corresponding to one of the memory rows 110. One of the address decode signals 128 corresponds to an address signal 118, and that one memory row is driven to an active state for a memory access operation while the address decode signals 128 for the other memory rows 110 are in an inactive state. The address decode signals 128 are received by a word line latch 104, from which a word line signal 106 is generated. The word line latch 104 is driven in response to a system clock CLK SYS The latch clock signal CLK can be synchronized with the rising edge of LAT It operates in response to CLK. LAT and CLK SYSThe initiation of the second clock states may or may not be synchronized with each other in different implementations.

[0015] Further referring to the address capture circuit 122, the system clock CLK SYS While the system clock CLK is in the first clock state, the address signal 118 is captured and held stable. During this state, the address signal 118 is held constant on the internal address bus 124 and on the decoding circuitry 126, providing a non-fluctuating address decode signal 128 to the word line latch 104. SYS is in the second clock state, the address signal 118 passes through the address capture circuit 122 and enters the decode circuit 126. A fluctuation in the address signal 118 on the address bus 120 can cause a state change in the address decode signal 128. In this context, the term "fluctuation" with respect to the address signal 118 refers to a binary bit on the address bus 120 changing from "0" to "1" or from "1" to "0," or other instability in the signal on the address bus 120 that can change the decoded address indicated by the address signal 118. Fluctuations or instabilities, such as voltage fluctuations in the word line signal 106 on the word line 108 during a memory access operation, can cause errors in the memory access operation. For example, in a memory read operation, a fluctuation in the word line signal 106 on the memory row 110 being read can produce incorrect data on the bit lines in the memory array circuit 100, resulting in a memory read error.

[0016] As previously mentioned, the word line latch 104 is driven by the system clock CLK SYS The latch clock signal CLK rises in synchronization with LAT Specifically, it operates in response to the system clock CLK SYS transitioning from the second clock state to the first clock state (e.g., a rising edge of the clock), the latched clock signal CLK LAT The word line signal 106 also transitions from the second clock state to the first clock state. LATis in a first state. The word line signal 106 is generated in an active state on the word line 108 only when the latch clock signal CLK is in a second clock state. LAT The system clock CLK is generated in the inactive state in response to SYS may not remain in the first clock state throughout the entire memory access operation. Thus, to keep the word line signal 106 active long enough to perform the memory access operation, the latched clock signal CLK LAT In other words, the latched clock signal CLK cannot return to the second clock state in response to the system clock transitioning to the second clock state. LAT The duty cycle of the system clock CLK SYS The duty cycle of the system clock CLK may be longer than that of the SYS is in the second clock state, the address decode signal 128 is provided to the word line latch 104 through combinational logic, and the latch clock signal CLK LAT It is possible for the word line signal 106 to become unstable while the latched clock signal CLK is still in the first clock state. LAT Rather than passing the unstable address decode signal 128 through the word line latch 104 while the address decode signal 128 is in a first clock state, the word line latch 104 is configured to store the decode state of the address decode signal 128 and generate the word line signal 106 based on the stored decode state. More specifically, the inverting delayed clock circuit 102 is configured to latch the latched clock signal CLK LAT a latched clock signal CLK in a first clock state; LAT In response to receiving the inverted delayed clock signal CLK at the second clock state, the inverted delayed clock circuit 102 generates the inverted delayed clock signal CLK at the second clock state. DLY However, the inverting delayed clock circuit 102 is further configured to generate the latched clock signal CLK LAT After a delay period, which is the time it takes for the inverted delayed clock signal CLK to propagate through the inverted delayed clock circuit 102, DLY Generate.

[0017] The word line latch 104 receives the inverted delayed clock signal CLK DLY , and receives the address decode signal 128 in one of two decode states, active or inactive. The word line latch 104 latches the clock signal CLK in a first clock state. LAT and similarly the inverted delayed clock signal CLK of the first clock state. DLY In response to the latch clock signal CLK, the decoded state of the address decode signal 128 is stored. LAT In response to the transition from the second clock state to the first clock state, the inverted delayed clock signal CLK DLY Before transitioning from the first clock state to the second clock state, the latched clock signal CLK LAT and the inverted delayed clock signal CLK DLY Both CLK and CLK are in the first clock state. SYS is still in the first clock state and the address decode signal 128 is held stable by the address capture circuit 122. In this state, the word line latch 104 captures the address decode signal 128 and generates the word line signal 106 on the word lines 108 based on the stored decode state of the address decode signal 128. One of the word lines 108 for the target memory row 110 of the memory access operation receives the word line signal 106 in an active state based on the address signal 118. The word lines 108 of the other memory rows 110 (e.g., 255 of the 256) receive the word line signal 106 in an inactive state.

[0018] As mentioned above, the latch clock signal CLK LAT The transition to the first clock state of propagates through the inverted delayed clock circuit 102 and, at the end of the delay period, generates the inverted delayed clock signal CLK DLY to the second clock state. LAT and the inverted delayed clock signal CLK of the second clock state DLYIn response, the word line latch 104 holds the word line signal 106 on the word line 108 at the stored decoded state of the address decode signal 128. The latch clock signal CLK LAT transitions to the second clock state and back, latching the clock signal CLK in the second clock state. LAT In response, the word line latch 104 generates an inactive word line signal 106 on the word line 108 .

[0019] 2 is a schematic diagram provided for reference in the detailed description of one example of an inverting delay clock circuit 102 and word line latch 104 of FIG. 1, configured to reduce fluctuations in the word line signal 106. The latch clock signal CLK LAT is inverted and a delay period or "self-timed pulse" is generated by the inverting delay clock circuit 102, which in turn inverts the latched clock signal CLK LAT and an inverter circuit 204. The inverter circuit 204 includes an input coupled to the delay circuit 202. The inverted delay clock circuit 102 receives the latched clock signal CLK. LAT The propagation delay of the clock pulses CLK generates a self-timed pulse to the word line latch 104 during which the clock pulses CLK SYS The decoded state of the address decode signal 128 is expected to be stable while the latch clock signal CLK is in the first clock state. The word line signal 106 is generated by the stored address decode signal 128 and is not affected by the fluctuations in the address signal 118 after the self-timed pulse. The self-timed pulse is generated by the latch clock signal CLK. LAT transitions from the second clock state to the first clock state, and the inverted delayed clock signal CLK DLY is still in the first clock state. The duration of the self-timed pulse is the time when the latched clock signal CLK passes through the inverting delayed clock circuit 102. LAT The self-timed pulse is determined by the propagation delay time of the inverted delayed clock signal CLK (i.e., by the time the delay period ends). DLYIt ends when it transitions to the second clock state.

[0020] 2 shows that the word line latch 104 includes a pull-up circuit 206 coupled to an internal node 208 and a pull-down circuit 210 coupled to the internal node 208. The word line latch 104 also includes an inverter circuit 212 coupled to the internal node 208 and the word line 108. The pull-up circuit 206 is coupled to a latch clock signal CLK LAT is in the second clock state, DD ), the active state generated on the internal node 208 is inverted by the inverter circuit 212 to generate an inactive word line signal 106 on the word line 108.

[0021] The first transistor circuit 214 includes a pull-up transistor 215, which is connected to a power supply voltage V DD The pull-up transistor 215 further includes a first terminal 216 coupled to a power supply voltage node 218 that provides a second clock state of the latched clock signal CLK. The pull-up transistor 215 includes a second terminal 220 coupled to the internal node 208. The pull-up transistor 215 is configured to latch the second clock state of the latched clock signal CLK. LAT , and also includes a gate terminal 222 configured to control the coupling between the power supply voltage node 218 and the internal node 208 in response to the voltage.

[0022] The pull-up circuit 206 also includes a keep-up circuit 224 configured to maintain the stored inactive state of the word line signal 106. In response to the word line signal 106 being inactive, the keep-up circuit 224 pulls the internal node 208 (i.e., its voltage level) above the power supply voltage V under either of two conditions: DDFirst, under the condition that the address decode signal 128 provided to the word line latch 104 is in an inactive state and the word line signal 106 is in an inactive state, the internal node 208 can be held in an active state by the pull-up circuit 206. Second, the inverted delayed clock signal CLK DLY is in the second clock state and the word line signal 106 is in the inactive state, the internal node 208 may be held in an active state by the pull-up circuit 206. In either of these conditions, the active state generated on the internal node 208 is inverted by the inverter circuit 212 to continue to generate the inactive word line signal 106 on the word line 108.

[0023] In particular, the keep-up circuit 224 includes a second transistor 226, a third transistor 228, and a fourth transistor 230. The pull-up transistor 215, the second transistor 226, the third transistor 228, and the fourth transistor 230 may be, but are not limited to, P-type metal-oxide-semiconductor (PMOS) transistors. An example of a P-type transistor is a silicon transistor doped with a pentavalent dopant, such as aluminum, indium, or gallium. The second transistor 226 includes a first terminal 232 coupled to a pull-up node 234, a second terminal 236 coupled to the internal node 208, and a gate terminal 238. The gate terminal 238 is configured to control the coupling between the pull-up node 234 and the internal node 208 in response to the address decode signal 128 being inactive. The third transistor 228 includes a first terminal 240 coupled to the power supply voltage node 218, a second terminal 242 coupled to a pull-up node 234, and a gate terminal 244 configured to control the coupling between the power supply voltage node 218 and the pull-up node in response to the word line signal 106 being in an inactive state. The fourth transistor 230 includes a first terminal 246 coupled to the pull-up node 234, a second terminal 248 coupled to the internal node 208, and a gate terminal 250. The gate terminal 250 is configured to couple the inverted delayed clock signal CLK in the second clock state. DLY , configured to control the coupling between the pull-up node 234 and the internal node 208 .

[0024] The pull-down circuit 210 latches the clock signal CLK LAT is in the first clock, and if one of two additional conditions exists, the pull-down circuit 210 is configured to pull down the internal node 208 (i.e., its voltage level) to a second supply voltage, such as ground. LAT is in a first clock state and the word line signal 106 on the word line 108 is in an active state, the internal node 208 can be held (suppressed). LATis in a first clock state, the address decode signal 128 is in an active state, and the inverted delayed clock signal CLK DLY is in the first clock state, the pull-down circuit 210 can pull down the internal node 208.

[0025] In particular, the pull-down circuit 210 includes a fifth transistor 252, a sixth transistor 254, a seventh transistor 256, and an eighth transistor 258. The fifth transistor 252, the sixth transistor 254, the seventh transistor 256, and the eighth transistor 258 may be, but are not limited to, N-type metal-oxide-semiconductor (NMOS) transistors. An example of an N-type transistor is a silicon transistor doped with a trivalent dopant, such as arsenic, antimony, or bismuth. The fifth transistor 252 includes a first terminal 260 coupled to the internal node 208, a second terminal 262 coupled to a pull-down node 264, and a gate terminal 266. The gate terminal 266 is coupled to a latch clock signal CLK at a first clock state. LAT , to control coupling between the internal node 208 and a pull-down node 264. The sixth transistor 254 includes a first terminal 268 coupled to the pull-down node 264, a second terminal 270, and a gate terminal 272. The gate terminal 272 is configured to control coupling between the pull-down node 264 and the second terminal 270 in response to the address decode signal 128 being active. The seventh transistor 256 of the pull-down circuit 210 has a first terminal 274 coupled to the second terminal 270 of the sixth transistor 254 and a second power supply voltage (e.g., V SS and a second terminal 276 coupled to a second power supply voltage node 278 that supplies a first power supply voltage (or ground). A gate 279 supplies an inverted delayed clock signal CLK at the first clock state. DLY, controls the coupling between the second power supply voltage node 278 and the first terminal 274 of the seventh transistor 256. The eighth transistor 258 includes a first terminal 280 coupled to the pull-down node 264, a second terminal 282 coupled to the second power supply voltage node 278, and a gate terminal 284. The gate terminal 284 is configured to control the coupling between the second power supply voltage node 278 and the pull-down node 264 in response to the word line signal 106 being active.

[0026] Referring back to FIG. 1 , a detailed description of the decode circuit 126 and the address capture circuit 122 will be provided. The decode circuit 126 includes an input 130 coupled to the internal address bus 124 and multiple outputs 132, with each output 132 coupled to one of the multiple word line latches 104. The decode circuit 126 is configured to receive the address signals 118 on the internal address bus 124, decode the address signals 118, and generate decoded states of the address decode signals 128 on the outputs 132. In particular, on one output 132 corresponding to the address signal 118, the decode circuit 126 is configured to generate the address decode signal 128 in an active state. On the other output 132 (i.e., not corresponding to the address signal 118), the decode circuit 126 is configured to generate the address decode signal 128 in an inactive state. The memory array circuit 100 may be included in an integrated circuit (IC) 134, which may further include processing circuitry (not shown), for example.

[0027] An active pass-through address capture circuit 122 in a second clock state is coupled to an internal address bus 124 and is also coupled to the address bus 120. The address capture circuit 122 receives the address signals 118 on the address bus 120 and is coupled to the system clock CLK SYS The active system clock CLK is configured to receive the SYS In response to this, the address capture circuit 122 stores the address signal 118 and holds the address signal 118 stored in the address capture circuit 122 on the internal address bus 124. The system clock CLK in an inactive state SYSIn response to the system clock CLK, the address capture circuit 122 generates the address signals 118 received on the address bus 120 onto the internal address bus 124. SYS While is in an inactive state, the address capture circuit 122 is in a pass-through state to maximize the time available for decoding the address.

[0028] 3 is a diagram of a word line circuit 300 used in a conventional memory array where fluctuations on the address bus propagate and can result in fluctuations on the word lines and timing margin violations. An internal node 302 is connected to a latched clock signal CLK LAT is in the second clock state and whenever the address decode signal 304 is in the inactive state. LAT is in a first clock state and address decode signal 304 is in an active state. Inverter 306 generates word line signal 308 that is the inverse of the state of internal node 302. Thus, word line circuit 300 does not store address decode signal 304, but instead combines and generates word line signal 308 based on address decode signal 304, which may contain variations or timing variations that could potentially cause errors in memory access operations.

[0029] FIG. 4 is a timing diagram illustrating the states of signals in a conventional memory array circuit using the word line circuit 300 of FIG. 3 and the exemplary memory array circuit 100 of FIG. 1 using the exemplary inverting delay clock circuit 102 and word line latch 104 of FIGS. 1 and 2. The signals in FIG. 4 are referenced using the same labels as in FIGS. 1-3. The signals are described below in descending order, starting with the first signal (address signal 118) at the top of the timing diagram in FIG. 4. As shown, the first signal in FIG. 4 is address signal 118 arriving on address bus 120. Before time T0, address signal 118 transitions from a second clock state (e.g., low) to a first clock state (e.g., high) based on a memory address provided by processing circuitry. The second signal in FIG. 4 is the system clock CLK SYS At time T0, the system clock CLK SYS transitions from the second clock state to the first clock state, remains in the first clock state for a time based on the clock duty cycle, and returns to the second clock state at time T2. SYS is in a first clock state from time T0 to time T2. SYS returns to the second clock state, holds the captured state of address signal 118 on internal address bus 124 from time T0 to time T2.

[0030] 4 is an internal address bus 124 that carries address signal 118. Before time T0 and after time T2, address signal 118 propagates from address bus 120 through address capture circuit 122 to internal address bus 124. Thus, fluctuations that may occur on address bus 120 before time T0 and after time T2 will cause fluctuations in address signal 118 on internal address bus 124.

[0031] 4 is an address decode signal 128 that corresponds to the address signal 118 on the internal address bus 124. Before time T3, the address signal 118 transitions from an inactive state to an active state, and after time T3, it returns to an inactive state as an example of a transition of the address signal 118. The system clock CLK SYS When the address capture circuit 122 is in the second clock state, the address decode signal 128 transitions from an inactive state to an active state and back to an inactive state because the address capture circuit is a pass-through latch. Thus, any fluctuations in the address signal 118 on the address bus 120 are propagated through the address capture circuit 122 and the decode circuit 126.

[0032] The fifth signal in Figure 4 is the system clock CLK SYS The latch clock signal CLK rises in synchronization with LAT The latch clock signal CLK LAT The amount of time that the latched clock signal CLK remains in the first clock state may be determined by a self-timer circuit or in another manner. LAT is the system clock CLK at time T0 SYS , transitions from the second clock state to the first clock state (e.g., rising), but the latched clock signal CLK LAT is the system clock CLK SYS has a longer duty cycle than

[0033] 4 is a word line signal 308 generated by the word line circuit 300 of a conventional memory array circuit. For comparison, the word line signal 308 is an example of a problem with the conventional method. As shown in FIG. 4, the system clock CLK SYS When is in the second clock state, a transition in the address signal 118 on the address bus 120 (eg, at time T3) propagates through the word line circuit 300 and causes a transition in the word line signal 308.

[0034] The seventh signal in FIG. 4 is the inverted delayed clock signal CLK DLYAs shown, the inverted delayed clock signal CLK DLY The state of the latch clock signal CLK LAT The word line latch 104 of FIG. LAT and the inverted delayed clock signal CLK DLY and are both in a first clock state (e.g., high). This state exists from time T0 to time T1 and is referred to herein as a self-timed pulse. The word line signal 106 is coupled to the latch clock signal CLK. LAT The latched clock signal CLK is held in a state determined by the captured address decode signal 128 until it transitions to a second clock state (e.g., falls to a low state). LAT After transitioning back to the second clock state, the word line signal 106 is pulled down to an inactive state.

[0035] 4 is internal node 208 of FIG. 2, which is inverted to generate word line signal 106. The final signal in FIG. 4 is word line signal 106 on word line 108. One of the word line signals 106 in memory array circuit 100 is activated corresponding to the address specified by address signal 118. Word line signal 106 does not change in response to fluctuations in address signal 118 on address bus 120 because those fluctuations do not propagate through word line latch 104.

[0036] 5A and 5B are flow charts illustrating a method 500 in the memory array circuit 100 of FIG. 1 for capturing address decode signals 128 in response to clock pulses to reduce errors due to fluctuations in address signals 118 on an address bus 120. The method 500 is in a memory array circuit 100 that includes a plurality of memory rows 110, each memory row including a memory bit cell circuit 112 coupled to a word line 108. The method 500 begins in FIG. 5A with latching a clock signal CLK in one of a first clock state and a second clock state.LAT The method includes receiving (block 502) a latched clock signal CLK constituting a second clock state. LAT , an inverted delayed clock signal CLK constituting a first clock state DLY (block 504), and generating a latched clock signal CLK constituting a first clock state. LAT , an inverted delayed clock signal CLK constituting a second clock state DLY (block 506). The method further includes receiving, at a memory row of the plurality of memory rows 110, an address decode signal 128 comprising a decode state constituting one of an active state and an inactive state (block 508). The method 500 further includes receiving a latched clock signal CLK constituting a first clock state. LAT and an inverted delayed clock signal CLK constituting the first clock state. DLY 5B, the method includes storing a decoded state of the received address decode signal 128 in response to the received address decode signal 128 and generating the stored decoded state of the address decode signal 128 on a word line 108 of one of the plurality of memory rows 110 (block 510). The method continues with FIG. 5B, where the latched clock signal CLK constituting the first clock state is generated. LAT and a delayed clock signal CLK constituting the second clock state. DLY and latching the stored decoded state of the address decode signal 128 on the word line 108 of one of the plurality of memory rows 110 (block 512). The method also includes latching a clock signal CLK constituting a second clock state. LAT generating an inactive state of the address decode signal 128 on the word line 108 of one of the plurality of memory rows 110 in response to the signal (block 514).

[0037] FIG. 6 is a block diagram of an exemplary processor-based system 600 including a processor 602 (e.g., a microprocessor) that includes instruction processing circuitry 604. The processor-based system 600 may be one or more circuits included on an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 600 includes a processor 602. The processor 602 represents one or more general-purpose processing circuits, such as a microprocessor or a central processing unit. More specifically, the processor 602 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports explicit consumer naming for communicating a product value resulting from the execution of a producer instruction. The processor 602 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, the processor 602 includes an instruction cache 606 for temporarily storing instructions in fast-access memory accessible by the instruction processing circuitry 604. Instructions fetched or prefetched from memory, such as main memory 608, via system bus 610 are stored in instruction cache 606. Data may be stored in cache memory 612, coupled to system bus 610, for low-latency access by processor 602. Instruction processing circuitry 604 is configured to process instructions fetched into instruction cache 606 and to process the instructions for execution.

[0038] The processor 602 and main memory 608 are coupled to a system bus 610, which may interconnect peripheral devices included in the processor-based system 600. As is well known, the processor 602 communicates with these other devices by exchanging address, control, and data information via the system bus 610. For example, the processor 602 may communicate bus transaction requests to a memory controller 614 in the main memory 608, which serves as an example of a slave device. Although not shown in FIG. 6, multiple system buses 610 may be provided, each comprising a different fabric. In this example, the memory controller 614 is configured to provide memory access requests to a memory array 616 in the main memory 608. The memory array 616 comprises an array of storage bit cells for storing data. The main memory 608 may be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as a synchronous DRAM (SDRAM), and a static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0039] Other devices may be connected to the system bus 610. As shown in FIG. 6, these devices may include, by way of example, a main memory 608, one or more input devices 618, one or more output devices 620, a modem 622, and one or more display controllers 624. The input device(s) 618 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output device(s) 620 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 622 may be any device configured to enable the exchange of data with a network 626. The network 626 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The modem 622 may be configured to support any type of communication protocol desired. The processor 602 may also be configured to access a display controller 624 via the system bus 610 to control information sent to one or more displays 628. The displays 628 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0040] 6 may include an instruction set 630 that is executed by the processor 602 for any desired application in accordance with the instructions. The instructions 630 may be stored in the main memory 608, the processor 602, and / or the instruction cache 606, as examples of non-transitory computer-readable media 632. The instructions 630 may also reside, completely or at least partially, within the main memory 608 and / or within the processor 602 during execution. The instructions 630 may also be transmitted or received over the network 626 via the modem 622, such that the network 626 includes the computer-readable medium 632.

[0041] Although the computer-readable medium 632 is shown to be a single medium in the exemplary embodiment, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) on which one or more sets of instructions are stored. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Accordingly, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0042] As shown in FIGS. 1 and 2, the processor 602 of the processor-based system 600 may include, in any of its devices, memory array circuitry that uses inverting delay clock circuits and word line latches to generate more stable word line signals on the word lines of the memory rows.

[0043] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0044] Embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (such as a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0045] Unless otherwise specifically stated, and as is apparent from the foregoing, throughout the specification, discussions using terms such as "processing," "calculating," "determining," or "displaying" refer to the operations and processes of a computer system or similar electronic computing device that manipulate and convert data and memory represented as physical (electronic) quantities in the registers of the computer system into other data similarly represented as physical quantities in the memory or registers within the computer system, or in other such information storage, transmission, or display devices.

[0046] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Further, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0047] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware and / or by instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device. The components of the distributed antenna system described herein may be used in, by way of example, any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented will depend on the particular application, design choices, and design constraints imposed on the overall system. Those skilled in the art may realize the described functionality for each particular application in various ways, but such implementation decisions should not be interpreted as a departure from the scope of the present embodiments.

[0048] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0049] The embodiments disclosed herein may be embodied in hardware and instructions stored in the hardware, which may reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as separate components in a remote station, base station, or server. Also, it should be noted that the operational steps described in any of the exemplary embodiments herein are set forth for the purpose of example and discussion. The described operations may be performed in many different sequences other than the sequence illustrated. Furthermore, an operation described as a single operational step may actually be performed in many different steps.

[0050] Furthermore, one or more of the operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0051] Unless otherwise expressly stated, the methods described herein are in no way intended to be construed as requiring that its steps be performed in a particular order. Thus, where a method claim does not actually recite the order in which its steps must be followed, or where the claims or specification do not specifically state that the steps are limited to a particular order, no particular order is intended to be inferred.

[0052] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

Claims

1. A memory array circuit, the memory array circuit comprising: A plurality of memory rows, each memory row including: a plurality of memory bitcell circuits; a plurality of memory rows including a word line coupled to each of the plurality of memory bit cell circuits; 1. An inverting delay clock circuit, comprising: receiving a latch clock signal constituting one of a first clock state and a second clock state; generating an inverted delayed clock signal constituting the second clock state in response to receiving the latched clock signal constituting the first clock state; and an inverted delayed clock circuit configured to generate the inverted delayed clock signal constituting the first clock state in response to receiving the latched clock signal constituting the second clock state; a plurality of word line latch circuits, each word line latch circuit coupled to a word line of one of the plurality of memory rows; receiving the latch clock signal and the inverted delayed clock signal; receiving an address decode signal having a decode state constituting one of an active state and an inactive state; storing the decoded state of the received address decoded signal in response to the latched clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and generating a word line signal on the word line of one of the plurality of memory rows that includes the stored decoded state of the address decoded signal; latching the word line signal, including the stored decoded state of the address decode signal, on a word line of one of the plurality of memory rows in response to the latched clock signal constituting the first clock state and the inverted delayed clock signal constituting the second clock state; and a plurality of word line latch circuits configured to generate, in response to the latch clock signal constituting the second clock state, the word line signal constituting the inactive state of the address decode signal on a word line of one of the plurality of memory rows; Memory array circuitry.

2. 2. The memory array circuit of claim 1, wherein the inverted delayed clock circuit is further configured to generate the inverted delayed clock signal in response to expiration of a delay period after receiving the latched clock signal.

3. The inverting delay clock circuit a delay circuit configured to receive the latch clock signal; an inverter circuit having an input coupled to the delay circuit; 3. The memory array circuit of claim 2, wherein said inverted delayed clock signal is generated at the output of said inverter circuit.

4. Each word line latch circuit a pull-up circuit coupled to the internal node; a pull-down circuit coupled to the internal node; 2. The memory array circuit of claim 1, further comprising: an inverter circuit coupled from said internal node to said word line.

5. The pull-up circuit a first transistor circuit configured to pull up the internal node to a first power supply voltage corresponding to the active state in response to the latched clock signal constituting the second clock state; a second transistor circuit configured to pull up the internal node to the first power supply voltage in response to the word line signal constituting the inactive state, in response to the address decode signal constituting the inactive state, and in response to the inverted delayed clock signal constituting the second clock state.

6. The first transistor circuit includes a first transistor, the first transistor comprising: a first terminal coupled to a first power supply voltage node; a second terminal coupled to the internal node; a gate terminal configured to control coupling between said first power supply voltage node and said internal node in response to said latched clock signal constituting said second clock state.

7. the second transistor circuit includes a second transistor, a third transistor, and a fourth transistor; The second transistor is a first terminal coupled to the pull-up node; a second terminal coupled to the internal node; a gate terminal configured to control coupling between the pull-up node and the internal node in response to the address decode signal configuring the inactive state; The third transistor is a first terminal coupled to a first power supply voltage node; a second terminal coupled to the pull-up node; a gate terminal configured to control coupling between the first power supply voltage node and the pull-up node in response to the word line signal configuring the inactive state; The fourth transistor is a first terminal coupled to the pull-up node; a second terminal coupled to the internal node; a gate terminal configured to control coupling of said pull-up node to said internal node in response to said inverted delayed clock signal constituting said second clock state.

8. The pull-down circuit responds to the latched clock signal constituting the first clock state by: In response to the word line configuring the active state, holding the internal node at a second power supply voltage corresponding to the inactive state; 5. The memory array circuit of claim 4, further configured to pull down the internal node to the second power supply voltage in response to the address decode signal constituting the active state and the inverted delayed clock signal constituting the first clock state.

9. the pull-down circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The fifth transistor is a first terminal coupled to the internal node; a second terminal coupled to the pull-down node; a gate terminal configured to control coupling of the internal node to the pull-down node in response to the latch clock signal constituting the first clock state; The sixth transistor is a first terminal coupled to the pull-down node; a second terminal; and a gate terminal configured to control coupling of the pull-down node and the second terminal of the sixth transistor in response to the address decode signal configuring the active state; The seventh transistor is a first terminal coupled to the second terminal of the sixth transistor; a second terminal coupled to a second power supply voltage node; a gate terminal configured to control coupling of the second terminal of the sixth transistor to the second power supply voltage node in response to the inverted delayed clock signal constituting the first clock state; The eighth transistor is a first terminal coupled to the pull-down node; a second terminal coupled to the second power supply voltage node; a gate terminal configured to control coupling of said pull-down node to said second power supply voltage node in response to said word line configuring said active state.

10. Further comprising a decoding circuit, the decoding circuit comprising: an input coupled to the first address bus; a plurality of outputs, each coupled to one of the plurality of word line latch circuits; receiving a first address signal on the first address bus; decoding the first address signal; generating the address decode signal on one of the plurality of outputs corresponding to the decoded first address signal, the address decode signal configuring an active state; and 2. The memory array circuit of claim 1, further configured to generate the address decode signal constituting an inactive state on outputs of the plurality of outputs that do not correspond to the decoded first address signal.

11. further comprising an address capture circuit coupled to the first address bus and the second address bus, the address capture circuit comprising: receiving a second address signal on the second address bus; receiving a system clock signal constituting one of a system clock active state and a system clock inactive state; storing the second address signal in response to the system clock signal constituting the system clock active state, and holding the first address signal on the first address bus based on the second address signal stored in the address capture circuit; and 11. The memory array circuit of claim 10, further configured to generate the first address signal on the first address bus based on the second address signal received on the second address bus in response to the system clock signal configuring the system clock inactive state.

12. 8. The memory array circuit of claim 7, wherein the first, second, third, and fourth transistors comprise P-type metal-oxide-semiconductor (PMOS) transistors.

13. 10. The memory array circuit of claim 9, wherein the fifth, sixth, seventh, and eighth transistors comprise N-type metal-oxide-semiconductor (NMOS) transistors.

14. 1. An integrated circuit (IC) including a memory array circuit, the memory array circuit comprising: A plurality of memory rows, each memory row including: a plurality of memory bitcell circuits; a plurality of memory rows including a word line coupled to each of the plurality of memory bit cell circuits; 1. An inverting delay clock circuit, comprising: receiving a latch clock signal constituting one of the second clock state and the first clock state; generating an inverted delayed clock signal constituting the first clock state in response to the latched clock signal constituting the second clock state; and an inverted delayed clock circuit configured to generate the inverted delayed clock signal constituting the second clock state in response to the latched clock signal constituting the first clock state; a plurality of word line latch circuits, each word line latch circuit coupled to a word line of one of the plurality of memory rows; receiving the latch clock signal; receiving the inverted delayed clock signal; receiving an address decode signal having a decode state constituting one of an active state and an inactive state; storing the decoded state of the received address decoded signal in response to the latched clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and generating a word line signal on the word line of the one memory row of the plurality of memory rows that includes the stored decoded state of the address decoded signal; maintaining the word line signal including the stored decoded state of the address decode signal on a word line of the one of the plurality of memory rows in response to the latched clock signal constituting the first clock state and an inverted delayed clock signal constituting the second clock state; and a plurality of word line latch circuits configured to generate the word line signal constituting the inactive state of the address decode signal on the word line of the one memory row of the plurality of memory rows in response to the latch clock signal constituting the second clock state; Integrated circuit.

15. 1. A method in a memory array circuit including a plurality of memory rows, each memory row including memory bit cell circuits coupled to a word line, the method comprising: receiving a latch clock signal constituting one of a first clock state and a second clock state; generating an inverted delayed clock signal constituting the first clock state in response to the latched clock signal constituting the second clock state; generating the inverted delayed clock signal constituting the second clock state in response to the latched clock signal constituting the first clock state; receiving an address decode signal at a memory row of the plurality of memory rows, the address decode signal including a decode state constituting one of an active state and an inactive state; storing the decoded state of the received address decoded signal in response to a latched clock signal constituting the first clock state and the inverted delayed clock signal constituting the first clock state, and generating the stored decoded state of the address decoded signal on the word line of the one memory row of the plurality of memory rows; generating the stored decoded state of the address decode signal on the word line of the one memory row of the plurality of memory rows in response to the latched clock signal constituting the first clock state and the inverted delayed clock signal constituting the second clock state; generating the inactive state of the address decode signal on the word line of the one memory row of the plurality of memory rows in response to the latch clock signal constituting the second clock state; method.

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