Semiconductor device

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] A semiconductor device having an integrated circuit configured with thin film transistors (hereinafter referred to as TFTs) and For example, the present invention relates to an electronic device incorporating a semiconductor integrated circuit as a component, and a manufacturing method thereof. do.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Electro-optical devices, semiconductor circuits, electronic components, and electronic equipment are all considered semiconductor devices. is. [Background technology]

[0003] In recent years, semiconductor devices have been developed and are used as LSIs, CPUs, and memories. A CPU is a semiconductor integrated circuit (at least transistors and It is a collection of semiconductor elements that have a memory and on which electrodes that serve as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, e.g., printed circuit boards. It is mounted on a wiring board and used as one of the components in various electronic devices.

[0005] Furthermore, the development of semiconductor devices capable of transmitting and receiving data is progressing. The devices are called wireless tags or RFID tags. Many of them have a semiconductor circuit (IC chip) formed using a conductive substrate.

[0006] Silicon-based semiconductor materials are known as semiconductor thin films that can be used in thin film transistors. However, oxide semiconductors are attracting attention as other materials. , zinc oxide or zinc oxide-based materials are known. 10 18 / cm 3 A thin film formed of amorphous oxide (oxide semiconductor) with a thickness of less than Transistors have been disclosed in Patent Documents 1 to 3. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165527 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention [Problem to be solved by the invention]

[0008] For electronic devices, not only the power consumption during operation but also the power consumption during standby is considered important. In particular, portable electrical devices are battery-powered and can be used with limited power. In addition, if the leakage current of in-vehicle electrical equipment is large during standby, This may shorten the life of the battery, and in the case of electric vehicles, Leakage current reduces the driving distance per unit charge.

[0009] In order to reduce power consumption, it is necessary to reduce not only the power consumption during operation but also the leakage current during standby. It is effective to reduce the leakage current of each transistor. LSIs have millions of transistors, and the leakage currents of these transistors are added together. Such leakage current increases the consumption of semiconductor devices during standby. There are various causes of leakage current, but the main cause is the increase in power consumption during standby. If the leakage current can be reduced, it will be possible to reduce the power consumption of the drive circuits used in electrical equipment. This can be achieved.

[0010] Therefore, the challenge is to reduce the leakage current of transistors used in LSIs, CPUs, and memories. This is one of the topics.

[0011] Reducing parasitic capacitance is also effective in reducing power consumption during operation. One of the challenges is to reduce the amount of power consumed by the device.

[0012] Also, the channel length of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories By shortening L, the operating speed of the circuit can be increased and power consumption can be reduced. Both of these are also issues to be addressed. [Means for solving the problem]

[0013] By removing impurities that act as electron donors (donors) in the oxide semiconductor, it is possible to obtain intrinsic or substantially oxide semiconductors, which are fully intrinsic semiconductors and have a larger energy gap than silicon semiconductors Thin film transistors, in which the channel region is formed in the body, are used for LSIs, CPUs, memory, etc. A semiconductor integrated circuit is fabricated.

[0014] Impurities such as hydrogen or OH groups contained in the oxide semiconductor are removed, specifically, the oxide semiconductor The hydrogen concentration in the conductor is 5×10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3The hydrogen concentration is sufficiently reduced to a high level. The use of a purified oxide semiconductor layer reduces the off-state current of a thin film transistor. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This is done using standard ion mass spectroscopy (NMS).

[0015] In the region where the gate voltage Vg is positive, the drain current Id is large enough and the gate voltage Vg is less than 0. Under this condition, the drain current Id is preferably 0, and the hydrogen concentration is sufficiently reduced to provide a highly pure Thin film transistors using a modified oxide semiconductor layer have a drain voltage Vd of +1V or When the gate voltage Vg is in the range of -5V to -20V, the off-state current is 1. x10 -13 It can be less than [A].

[0016] A thin film transistor using an oxide semiconductor layer that has been highly purified by sufficiently reducing the hydrogen concentration is This makes it possible to realize a semiconductor device with low power consumption due to leakage current.

[0017] In addition, a thin-film transistor using an oxide semiconductor layer with a sufficiently reduced hydrogen concentration and high purification is also available. The sintered body can be formed on a glass substrate, and LSI, CPU, and memory can be mounted on the glass substrate. By using a large-area glass substrate, manufacturing costs can be reduced. In addition, the substrate is not limited to a glass substrate, and the substrate can be formed on a silicon substrate where the hydrogen concentration is sufficiently reduced. It is also possible to form a thin film transistor using an oxide semiconductor layer having high thermal conductivity. It is preferable to use a silicon substrate for heat dissipation of semiconductor circuits. The hydrogen concentration is sufficiently reduced even on flexible substrates, such as plastic films. Thin film transistors can be formed using a compound semiconductor layer, and flexible wireless tags can be manufactured. can be produced.

[0018] One of the configurations of the invention disclosed in this specification is a method for forming a compound on an insulating surface that is detected by secondary ion mass spectrometry. The hydrogen concentration is 5×10 19 / cm 3 and the carrier concentration is 5×10 14 / cm 3 Below an oxide semiconductor layer below the oxide semiconductor layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, and an oxide semiconductor layer over the oxide semiconductor layer. a gate insulating layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a semiconductor integrated circuit having a plurality of thin film transistors each having a gate electrode layer thereon; It is a device.

[0019] The above configuration solves at least one of the above problems.

[0020] In addition, a conductive layer may be formed below the oxide semiconductor layer. A conductive layer on the surface, an insulating layer on the conductive layer, and a layer detected by secondary ion mass spectrometry on the insulating layer. Hydrogen concentration is 5×10 19 / cm 3 and the carrier concentration is 5×10 14 / cm 3 below an oxide semiconductor layer, a source electrode layer and a drain electrode layer on the oxide semiconductor layer, and an oxide semiconductor layer a gate insulating layer on the semiconductor layer, the source electrode layer, and the drain electrode layer; a gate electrode layer; and a conductive layer formed on the front surface of the insulating layer. The semiconductor device is characterized in that the insulating film overlaps with the oxide semiconductor layer.

[0021] In each of the above configurations, in order to reduce parasitic capacitance, a source electrode layer or a drain electrode layer may be further provided. The source electrode layer or the drain electrode layer has an insulating layer in contact with the gate insulating layer. The source electrode layer or the drain electrode layer overlaps with a part of the gate electrode layer with an insulating layer interposed therebetween. By providing an insulating layer in contact with the gate electrode layer and the source electrode layer, The parasitic capacitance between the electrode layer and the drain electrode layer can be reduced.

[0022] In addition, in order to reduce parasitic capacitance at the wiring intersections, A gate insulating layer and an insulating layer are laminated between the gate wiring layer and the source wiring layer. Wider spacing between layers reduces power consumption due to parasitic capacitance and prevents short circuits between wires Prevention is also possible.

[0023] In addition, a plurality of thin film transistors using an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced are assembled. It is also possible to form an EDMOS circuit in combination, which is configured by forming a first oxide layer on an insulating surface. a first thin film transistor having a semiconductor layer and a second thin film transistor having a second oxide semiconductor layer; a first oxide semiconductor layer and a second oxide semiconductor layer; The semiconductor layer has a hydrogen concentration of 5×10 detected by secondary ion mass spectrometry. 19 / cm 3 Below and the carrier concentration is 5×10 14 / cm 3 The following is the result.

[0024] In addition, a resistor, a capacitor, an inductor, and a semiconductor device can be fabricated using an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced. For example, resistors can be formed on the same substrate by reducing the hydrogen concentration sufficiently. The oxide semiconductor layer can be formed by sandwiching the oxide semiconductor layer between upper and lower electrode layers. In addition, an oxide semiconductor layer serving as a resistor is formed on the same substrate, and the first conductive layer and the first It is provided between the conductive layer and an overlying second conductive layer.

[0025] In addition to LSI, CPU, and memory, amplifiers for power supply circuits, transmission / reception circuits, and audio processing circuits are also included. The hydrogen concentration is measured by the amplifier, the display drive circuit, the controller, or the converter of the sound processing circuit. It may also be configured using a thin film transistor that uses a sufficiently reduced oxide semiconductor layer. do.

[0026] Also, a semiconductor device that has multiple semiconductor integrated circuits mounted in one package to increase integration. A so-called MCP (Multi Chip Package) may also be used.

[0027] When mounting a semiconductor integrated circuit on a circuit board, it may be mounted face up. Alternatively, a flip chip configuration (face down configuration) may be used. [Effects of the Invention]

[0028] A thin film transistor using an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced can reduce leakage current. The thin film transistor can be made extremely small, and by using it in a semiconductor integrated circuit, A semiconductor device with low power consumption can be realized. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] FIG. 1 is an equivalent circuit diagram illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 5]FIG. 1 is a block diagram illustrating one embodiment of the present invention. [Figure 6] FIG. 2 is a diagram illustrating a block diagram. [Figure 7] 1A to 1C illustrate a semiconductor device. [Figure 8] 1A to 1C illustrate a semiconductor device. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] FIG. 1 is an equivalent circuit diagram illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a diagram showing a band structure between the source and drain of a MOS transistor using an oxide semiconductor. [Figure 13] 13 is a diagram showing a state in which a positive voltage is applied to the drain side in FIG. 12. [Figure 14] 1A and 1B are energy band diagrams of the MOS structure of a MOS transistor using an oxide semiconductor, showing (A) the case where the gate voltage is positive, and (B) the case where the gate voltage is negative. [Figure 15] A comparative diagram showing the source-drain band structure of a silicon MOS transistor. [Figure 16] FIG. 1 is an equivalent circuit diagram illustrating one embodiment of the present invention. [Figure 17] FIG. 1 is an equivalent circuit diagram illustrating one embodiment of the present invention. [Figure 18] FIG. 1 illustrates an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0031] (Embodiment 1) In this embodiment, an example of a cross-sectional structure of a semiconductor integrated circuit will be described.

[0032] In this embodiment mode, one embodiment of a semiconductor integrated circuit and a manufacturing method thereof will be described with reference to FIGS. 2, 3 and 4.

[0033] 1(A) and 1(B) show an example of a cross-sectional structure of a semiconductor integrated circuit. The thin film transistor 440 is one of the thin film transistors with a top gate structure.

[0034] The thin film transistor 440 includes a first insulating layer 447a, a second insulating layer 447b, a third insulating layer 447c, a fourth insulating layer 447d, a fourth insulating layer 447e, a fourth insulating layer 447f, a fifth insulating layer 447g, a sixth insulating layer 447h, a sixth insulating layer 447i, a sixth insulating layer 447j ... The second insulating layer 443, the third insulating layer 447b, the oxide semiconductor layer 442, and the first source electrode layer 445a, a second source electrode layer 448a, a first drain electrode layer 445b, a second drain The gate electrode layer 448b, the gate insulating layer 444, and the gate electrode layer 441 are included.

[0035] A part of the oxide semiconductor layer 442 overlapping with the gate electrode layer 441 is a channel formation region. The lower end of the first source electrode layer 445a and the first drain electrode layer 445b adjacent to each other on the nitride semiconductor layer 442 are The channel length L1 is determined by the gap width between the lower end of the electrode layer 445b.

[0036] The thin film transistor 440 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0037] In addition, a thin film transistor 47 having reduced parasitic capacitance is formed on the same substrate as the thin film transistor 440. 0 can also be formed in the same process.

[0038] 1A, a thin film transistor 440 and a thin film transistor 441 are formed on a substrate 430. The process for producing 470 will be described.

[0039] There is no significant limitation on the substrate that can be used for the substrate 430 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0040] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide (B2O3), Therefore, glass containing more BaO than B2O3 is preferred. It is preferable to use a glass substrate.

[0041] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, a crystallized glass substrate or the like may also be used. In addition, a semiconductor substrate having an insulating layer on its surface, a plastic substrate, or the like can also be used as appropriate. do.

[0042] First, a conductive film is formed on a substrate 430 having an insulating surface, and then a first photolithography is performed. Electrode layers 479a, 479b, and 479c are formed by the process. , 479c, the material is an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, Alternatively, an alloy containing the above elements or an alloy combining the above elements may be used. In this embodiment, the electrode layers 479a, 479b, and 479c are made of tungsten nitride. The structure is a laminate of a silicon layer and a tungsten layer.

[0043] Next, a first insulating layer 447a is formed to cover the electrode layers 479a, 479b, and 479c. The first insulating layer 447a is formed by depositing a silicon oxide layer, a nitride layer, or the like by plasma CVD or sputtering. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed as a single layer or a stacked layer.

[0044] Next, a spacer insulating layer is formed on the first insulating layer 447a, and then a second photolithography is performed. The spacer insulating layer is selectively removed by a film process to form a second insulating layer 443. A silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride layer is formed by using a plasma CVD method or a sputtering method. The spacer insulating layer is formed of a silicon nitride oxide layer in a single layer or a multilayer structure. In the same process, a fifth insulating layer 473 that will become a spacer insulating layer is formed. The electrode layer 479c is formed in a position where it overlaps with the electrode layer 479c. In order to reduce parasitic capacitance, a spacer insulating layer is formed in the region where the film thickness is to be thick. The fourth insulating layer and the first insulating layer are laminated to form a thin film to form a storage capacitor, etc. A first insulating layer is provided in the region where the thickness is to be increased.

[0045] Next, a third insulating layer 447a is formed to cover the first insulating layer 447b, the second insulating layer 443, and the fifth insulating layer 473. The third insulating layer 447b in contact with the oxide semiconductor layer is formed of silicon oxide. silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, or aluminum oxynitride layer The third insulating layer 447b is preferably an oxide insulating layer. The CVD method, the sputtering method, or the like can be used. In order to prevent a large amount of silicon from being contained, the third insulating layer 447b is formed by sputtering. It is preferable to form a film.

[0046] In this embodiment, the third insulating layer 447b is formed by a silicon oxide film deposited by a sputtering method. The substrate 430 is transferred to a processing chamber, and a high-purity oxygen gas containing hydrogen and moisture is used. A sputtering gas containing silicon is introduced and a silicon target is used to form a third insulating layer 44 on the substrate 430. As 7b, a silicon oxide layer is formed. The substrate 430 may be at room temperature or heated. It's fine.

[0047] For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the distance between the substrate and the target is 108° C. The distance between the two (TS distance) was 60 mm, the pressure was 0.4 Pa, the high frequency power supply was 1.5 kW, and oxygen and RF sputtering was performed under an atmosphere of oxygen and argon (oxygen flow rate 25 sccm, argon flow rate 25 sccm). A silicon oxide layer is formed by deposition. The film thickness is 100 nm. Preferably, a silicon target is used instead of a synthetic quartz target for forming a silicon oxide layer. It can be used as a get. The sputtering gas is oxygen or oxygen and argon. This is done using a mixed gas of ethanol.

[0048] In this case, the third insulating layer 447b is formed while removing the remaining moisture in the processing chamber. In order to prevent hydrogen, hydroxyl groups, or moisture from being contained in the third insulating layer 447b, This is the case.

[0049] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The concentration of impurities contained in 447b can be reduced.

[0050] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and DC sputtering. DC sputtering using a power supply, and pulsed DC sputtering using a pulsed bias. The RF sputtering method is mainly used to form insulating films, and The C sputtering method is mainly used to form metal films.

[0051] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0052] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0053] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0054] The third insulating layer 447b may have a laminated structure, for example, a silicon nitride layer from the substrate 430 side. a nitride insulating layer such as a silicon layer, a silicon nitride oxide layer, or an aluminum nitride layer, and the oxide A laminated structure with an insulating layer may also be used.

[0055] For example, a spat containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A silicon nitride layer is formed by introducing a target gas and using a silicon target. Even if the silicon nitride layer is formed, the remaining moisture in the processing chamber is removed, just like the silicon oxide layer. It is preferable to coat the surface.

[0056] When forming a silicon nitride layer, the substrate may also be heated during film formation.

[0057] When a silicon nitride layer and a silicon oxide layer are stacked as the third insulating layer 447b, the silicon nitride layer The silicon layer and silicon oxide layer are formed in the same processing chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced to the chamber. A silicon nitride layer is formed using a silicon target, and then a sputtering gas containing oxygen is used. The gas is switched to nitriding gas and a silicon oxide layer is formed using the same silicon target. The silicon layer and the silicon oxide layer can be formed successively without exposure to the atmosphere. This can prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the silicon nitride layer.

[0058] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the third insulating layer 447b. Form.

[0059] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, a third insulating layer 447b is formed in a preheating chamber of a sputtering device. The substrate 430 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 430. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. This preheating process may be omitted.

[0060] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the metal attached to the surface of the third insulating layer 447b is removed. It is preferable to remove aluminum. Reverse sputtering is a method of removing aluminum without applying voltage to the target side. In a gas atmosphere, a voltage is applied to the substrate side using a high frequency power supply to form plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of argon atmosphere. may also be used.

[0061] The oxide semiconductor film is formed by sputtering. nO series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor films are used. In this embodiment, an oxide semiconductor film is formed using a tube for forming an In—Ga—Zn—O-based oxide semiconductor. The oxide semiconductor film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, under an oxygen atmosphere, or under a rare gas atmosphere (typically, argon) and It can be formed by sputtering in an oxygen-mixed atmosphere. When using the targeting method, a target containing 2% to 10% by weight of SiO2 is used. The film may be formed by the above method.

[0062] The oxide semiconductor film was prepared by sputtering using a target containing zinc oxide as the main component. A metal oxide target can be used. Another example is a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: As a result, In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] can be used. In addition, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, 2O3:Ga2O3:ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3 A target having a composition ratio of ZnO=1:1:4 [molar ratio] can also be used. The filling rate of the oxide semiconductor film formation target is 90% or more and 100% or less, preferably 95% By using a target for oxide semiconductor film formation with a high filling rate, As a result, the formed oxide semiconductor film becomes a dense film.

[0063] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the metal oxide as a target. An oxide semiconductor film is formed over the substrate 430. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump It is preferable to use a pump or a titanium sublimation pump. A turbo pump with a cold trap may also be used. The evacuated film formation chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor film formed in the film forming chamber is exhausted, the oxide semiconductor film is preferably exhausted. The concentration of impurities contained in the conductive film can be reduced. You may do so.

[0064] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, and the pressure is 1000 kJ / cm. Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 sccm The conditions are as follows: an atmosphere of argon (30 sccm) and pulsed direct current (DC) By using a power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm to 30 nm thick. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately.

[0065] Next, the oxide semiconductor film is subjected to a third photolithography process to form an island-shaped oxide semiconductor layer 4 The oxide semiconductor layers 442 and 472 are processed into island-shaped oxide semiconductor layers 442 and 472 (see FIG. 1A). The resist mask for forming 72 may be formed by an ink jet method. When the mask is formed using the inkjet method, no photomask is required, reducing manufacturing costs. can.

[0066] The etching of the oxide semiconductor film here can be performed by either dry etching or wet etching. Either one or both may be used.

[0067] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0068] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0069] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0070] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0071] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0072] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0073] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into island-shaped oxide semiconductor layers 442 and 472 by etching. .

[0074] In this embodiment, first heat treatment is performed on the oxide semiconductor layers 442 and 472. The temperature of the heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, This prevents water and hydrogen from re-entering the oxide semiconductor layer, thereby obtaining the oxide semiconductor layer. The oxide semiconductor layers 442 and 472 can be dehydrated or dehydrogenated by the heat treatment. do.

[0075] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0076] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0077] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0078] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the crystallinity is high. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. In some cases, it becomes a conductive film. In addition, microcrystalline parts (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where an oxide semiconductor film having a thickness of 20 nm or less (typically, 2 nm or more and 4 nm or less) is formed, There are also cases where this is the case.

[0079] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0080] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the film formation, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, and then the source electrode and After forming the gate insulating layer on the drain electrode, the insulating layer may be formed.

[0081] However, hydrogen and moisture must be sufficiently reduced during film formation to obtain a highly purified oxide semiconductor layer. If this can be achieved, the first heat treatment does not have to be performed. In order to obtain a highly purified oxide semiconductor layer, a substrate is placed in a treatment chamber maintained in a reduced pressure state. The substrate is heated to a temperature above room temperature but below 400° C., and the remaining moisture in the processing chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the metal oxide as a target. The deposition chamber was evacuated using a cryopump to form an oxide semiconductor layer on a substrate. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since the exhaust gas contains the oxide semiconductor layer formed in the deposition chamber, The concentration of impurities can be reduced. The cryopump removes the moisture remaining in the processing chamber. By performing sputtering from the substrate, the substrate temperature during the deposition of the oxide semiconductor layer can be increased from room temperature to 400 °C or less.

[0082] Next, a resist mask is formed on the third insulating layer 447b by a fourth photolithography process. is formed, and selectively etched to form an opening reaching the electrode layer 479a.

[0083] Next, a conductive film is formed over the third insulating layer 447b and the oxide semiconductor layers 442 and 472. The conductive film may be formed by sputtering or vacuum deposition. Elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above elements are included Examples of the alloy include an alloy of manganese, manganese alloy, and the like. One or more of magnesium, zirconium, beryllium, and thorium are selected. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, A two-layer structure in which a Ti film is laminated and an aluminum film is laminated on top of the Ti film. A three-layer structure is also possible, where a titanium (Ti) film is formed on top of Al. , Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neo A film made of a single or multiple combinations of elements selected from neodymium (Nd) and scandium (Sc). In this embodiment, a titanium film ( Film thickness: 10 nm to 100 nm) and aluminum film (film thickness: 20 nm to 500 nm) ) to form a laminated film.

[0084] Next, a silicon oxide layer, a silicon nitride layer, and the like are formed by plasma CVD or sputtering. A silicon layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed on the conductive film in a single layer or a stacked layer. An insulating film having a thickness of 200 nm or more and 2000 nm or less is formed.

[0085] Next, a resist mask is formed on the insulating film by a fifth photolithography process. The fourth insulating layer 446, the first source electrode layer 445a, and the second source electrode layer 445b are selectively etched. A source electrode layer 448a, a first drain electrode layer 445b, and a second drain electrode layer 448b are formed. After the formation, the resist mask is removed. The fourth insulating layer 446 is then removed to form a gate insulating film. The source electrode layer is provided to reduce the parasitic capacitance between the source electrode layer and the When the ends of the gate electrode layer and the drain electrode layer are tapered, the coverage of the gate insulating layer to be laminated thereon is improved. This is preferable because it improves the

[0086] Note that when the conductive film is etched, the oxide semiconductor layers 442 and 472 are removed, and the underlying oxide semiconductor layers 442 and 472 are removed. The materials and etching conditions are appropriately adjusted so that the third insulating layer 447b is not exposed. To reduce.

[0087] In this embodiment, the first source electrode layer 445a and the first drain electrode layer 445b are The second source electrode layer 448a and the second drain electrode layer 448b were formed using a Ti film. An aluminum film is used for the oxide semiconductor layer 442, and an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 442. The etchant is a mixture of ammonia water, water, and hydrogen peroxide. is used.

[0088] Note that in the fifth photolithography step, only a part of the oxide semiconductor layer 442 is etched. In some cases, the first source electrode is formed on the oxide semiconductor layer, and the oxide semiconductor layer has a groove (a recess). A resist mask for forming the first drain electrode layer 445a and the first drain electrode layer 445b is then applied. If the resist mask is formed by the inkjet method, the photoresist mask can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0089] The fifth photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer adjacent to each other on the oxide semiconductor layer 442 is formed by laser light or ArF laser light. The width of the gap between the end of the thin film transistor 44 and the lower end of the drain electrode layer is In addition, when exposure is performed with a channel length L1 of less than 25 nm, In this case, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. Violet) for exposure during resist mask formation in the fifth photolithography process Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length L1 of the thin film transistor 440 is set to 10 nm or more and 1000 nm or less. This allows for faster circuit operation, and the extremely small off-state current allows for low It is also possible to reduce power consumption.

[0090] Next, the fourth insulating layer 446, the oxide semiconductor layers 442 and 472, and the first source electrode layer 44 5a, the second source electrode layer 448a, the first drain electrode layer 445b, and the second drain electrode layer 448c. The gate insulating layer 444 is formed on the gate electrode layer 448b.

[0091] The gate insulating layer 444 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 444 can be formed as a single layer or a stacked layer. In order to prevent a large amount of the oxide from being contained, the gate insulating layer 444 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen or The process is carried out using a mixed gas of oxygen and argon.

[0092] The gate insulating layer 444 is formed between the second source electrode layer 448a and the second drain electrode layer 448b. Alternatively, a silicon oxide layer and a silicon nitride layer may be stacked from the first side. The gate insulating layer of the first electrode is a silicon oxide layer (SiO x (x >0)) and forming a second gate insulating layer on the first gate insulating layer by sputtering. The silicon nitride layer (SiN y (y>0)) In this embodiment, the pressure is 0.4 Pa. , high frequency power supply 1.5kW, oxygen and argon (oxygen flow rate 25sccm, argon flow rate 25 A silicon oxide layer with a thickness of 100 nm was formed by RF sputtering in a 1000 nm atmosphere. Complete.

[0093] Next, a resist mask is formed by a sixth photolithography process and selectively etched. 4. A thin film transistor is formed by removing a portion of the gate insulating layer 444 and the fourth insulating layer 446. An opening reaching the source electrode layer or the drain electrode layer of the transistor 470 is formed.

[0094] Next, a conductive film is formed on the gate insulating layer 444 and the opening, and then a seventh photolithography step is performed. The gate electrode layers 441 and 471 and the wiring layers 474a and 474b are formed by a deposition process. Alternatively, the resist mask may be formed by an ink-jet method. When the film is formed by the photolithography method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0095] The gate electrode layers 441 and 471 and the wiring layers 474a and 474b are made of molybdenum, Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium The metal material or the alloy material mainly composed of these is used to form a single layer or a laminated layer. It is possible.

[0096] For example, a two-layer stack structure of gate electrode layers 441 and 471 and wiring layers 474a and 474b is used. The two-layer structure consists of a molybdenum layer on an aluminum layer, or a molybdenum layer on a copper layer. Two-layer structure with laminated layer of ribdenum, or titanium nitride or tantalum nitride layer on copper layer Preferably, the titanium nitride layer and the molybdenum layer are laminated together, or the titanium nitride layer and the molybdenum layer are laminated together. The three-layer structure is a tungsten layer or tungsten nitride layer and an aluminum layer. and silicon alloy or aluminum and titanium alloy with titanium nitride or titanium layer. It is preferable that the gate electrode layer be a stack of layers. As the light-transmitting conductive film, a light-transmitting conductive oxide or the like can be formed. Examples include:

[0097] In this embodiment, gate electrode layers 441 and 471 and wiring layers 474a and 474b are formed by sputtering. A tungsten film with a thickness of 150 nm is formed by the deposition method.

[0098] Next, a second heat treatment (preferably 2 In this embodiment, the temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can be done after forming a protective insulating layer or a planarizing insulating layer on the thin film transistors 440 and 470. good.

[0099] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling it down to room temperature several times. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0100] Through the above steps, the oxide semiconductor layer 44 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2, 472 can be formed (FIG. 1(B)). )reference.).

[0101] The thin film transistor 4 in which the parasitic capacitance with the electrode layer 479c is reduced by the fifth insulating layer 473 70 includes a third source electrode layer 475a, a fourth source electrode layer 478a, a third drain electrode layer 478b, and a The fifth insulating layer 475b is a first insulating layer, and the fourth drain electrode layer 478b is a second insulating layer. The electrode layer 479c overlapping with the fourth drain electrode layer 478b is a gate signal line. The third source electrode layer 475a is connected to the electrode layer 479. The fourth source electrode layer 478a is electrically connected to the wiring layer 474a. The channel length L2 of the thin film transistor 470 is The channel length L1 of the transistor 440 is longer than that of the transistor 440, and the OFF current value is small.

[0102] In addition, a protective insulating layer and a planarizing insulating layer for planarization are formed on the thin film transistors 440 and 470. For example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer may be provided as the protective insulating layer. A silicon layer, a silicon nitride oxide layer, or an aluminum oxide layer is formed as a single layer or a stacked layer. It is possible.

[0103] The planarization insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphor glass), BP SG (phosphorus boron glass) can be used. A planarizing insulating layer may be formed by stacking a plurality of insulating films.

[0104] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0105] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, an SOG method, or the like depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0106] In addition, the electrode layer 4 is provided below the oxide semiconductor layer 472 of the thin film transistor 470. 79b can function as a back gate. The potential of the back gate is a fixed potential For example, the potential may be 0 V or a ground potential, and may be determined appropriately by the practitioner. By providing gate electrodes above and below the semiconductor layer, the reliability of thin film transistors can be investigated. In the bias-thermal stress test (hereinafter referred to as BT test) for The amount of change in the threshold voltage of the thin film transistor can be reduced. By providing gate electrodes above and below the semiconductor layer, reliability can be improved.

[0107] In addition, the threshold voltage can be controlled by controlling the gate voltage applied to the electrode layer 479b. In addition, the threshold voltage can be set to a positive value to form an enhancement transistor. In addition, the threshold voltage can be set to negative to function as a depletion type transistor. It can also function as a

[0108] For example, a combination of enhancement and depletion type transistors An inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured using this and used in a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. It is preferable to use a thin film transistor that can pass a large amount of ON current for the layer. A recessed type transistor or a thin film transistor having gate electrodes above and below an oxide semiconductor layer A transistor is used.

[0109] Fabricating thin-film transistors with different structures on the same substrate without significantly increasing the number of processes For example, in an integrated circuit that operates at high speed, gate electrodes are provided above and below the oxide semiconductor layer. An EDMOS circuit is constructed using thin film transistors with electrodes, and a gate electrode is formed on the oxide semiconductor layer. Thin film transistors having gate electrodes can also be formed in other regions.

[0110] If the threshold voltage of the n-channel TFT is positive, it is called an enhancement type transistor. When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition will be followed throughout the specification.

[0111] The thin film transistor 470 and the thin film transistor 440 are formed by a gate insulating layer 444 and a second insulating layer 446. When a silicon nitride film is used for both the oxide semiconductor layers 442 and 47 and the insulating layer 447a, The top and bottom of the silicon nitride film can be sandwiched between the two layers, effectively blocking the penetration of hydrogen and moisture. With this structure, the oxide semiconductor layers 442 and 472 can be The water and hydrogen contained in the material can be reduced to an extremely low concentration, preventing them from re-entering the atmosphere.

[0112] (Embodiment 2) In the first embodiment, a thin film transistor 470 having a wiring intersection and an oxide semiconductor layer 44 2. The thin film transistor 440 having the gate electrode layer 441 only above the thin film transistor 440 has been described. Below, two n-channel thin film transistors are used to form an integrated circuit inverter circuit. Note that the manufacturing process of the thin film transistor is almost the same as that in Embodiment Mode 1. Therefore, only the differences will be explained in detail.

[0113] In addition, since the integrated circuit is configured using an inverter circuit, capacitance, resistance, etc., In addition to the circuit, we will also explain the process of forming a capacitor and two types of resistors on the same substrate.

[0114] In addition, when two n-channel TFTs are combined to form an inverter circuit, E formed by combining an excitation type transistor and a depletion type transistor When forming a DMOS circuit and an enhancement-type TFT (hereinafter referred to as an EMOS circuit) There is a saying.

[0115] In this embodiment, an EDMOS circuit is used as an example. The equivalent circuit of the EDMOS circuit is shown in FIG. The cross-sectional structure of the inverter circuit is shown in Figure 3.

[0116] The circuit connection shown in FIG. 3 corresponds to FIG. 2, and the first thin film transistor 480 is connected to the enhancement The second thin film transistor 490 is a depletion type n-channel transistor. This is an example of an n-channel transistor.

[0117] In FIG. 3, electrode layers 479d, 479e, 479f, 479g, and 479h are disposed on a substrate 430. Electrode layers 479d, 479e, 479f, 479g, and 479h are embodiments of the present invention. The electrode layers 479a, 479b, and 479c can be formed by the same process and using the same materials. .

[0118] A voltage is applied to the electrode layer 479d, and the threshold voltage is set to a positive value to form an enhancement type transistor. A voltage is also applied to the electrode layer 479e, and the threshold voltage is set to a negative value. It functions as a depletion-type transistor.

[0119] The electrode layer 479f is one of the electrodes that form a capacitance. The electrode layer 479h is one of the electrodes connected to the first resistor. The electrode is

[0120] In addition, the first insulating layer 4 covers the electrode layers 479d, 479e, 479f, 479g, and 479h. 87a and a third insulating layer 487b are formed. In the region where the second insulating layer is to be formed, a second insulating layer that will become a spacer insulating layer is provided as in the first embodiment. In the capacitance section, the first insulating layer 487a overlapping the electrode layer 479f and the electrode layer 479f are The third insulating layer 487b overlapping with 9f serves as a dielectric.

[0121] In this embodiment, unlike in Embodiment 1, the thickness of the second oxide semiconductor layer 482b is The oxide semiconductor layer 482a is thicker than the oxide semiconductor layer 482b. In addition, by increasing the film thickness, a depletion-type transistor can be obtained. In particular, the electrode layer 479e can be made to function as a negative voltage. Since it is not necessary to apply a voltage, the electrode layer 479e can be omitted.

[0122] The third oxide semiconductor layer 43 is formed to have the same thickness as the first oxide semiconductor layer 482a. 2b functions as a first resistor. A first insulating layer 487a overlaps the electrode layer 479h. and the third insulating layer 487b, and an opening is formed in the third insulating layer 487a. The second oxide semiconductor layer 482 is electrically connected to the electrode layer 479h. The fourth oxide semiconductor layer 432a formed to the same thickness as the fourth oxide semiconductor layer 432b functions as a second resistor. The first insulating layer 487 overlapping the electrode layer 479g has a different resistance value from the first resistor. Openings are formed in the third insulating layer 487a and the third insulating layer 487b, and the fourth oxide semiconductor Body layer 432a and electrode layer 479g are electrically connected to each other.

[0123] The thin film transistor 480 includes a first gate electrode layer 481 and a gate insulating layer 492. The oxide semiconductor layer 482a overlaps with the first gate electrode layer 481. The first source electrode layer 485b in contact with a part of the first wiring 484b is electrically connected to the first wiring 484b. The first wiring 484b is a power supply line (negative power supply line) to which a negative voltage VDL is applied. The power supply line may be a power supply line of ground potential (ground power supply line).

[0124] The first source electrode layer 48 is made of the same material as the first source electrode layer 445a in the first embodiment. The second source electrode layer 488b formed on and in contact with the first embodiment is also The insulating layer is formed of the same material as the second source electrode layer 448a. In the example shown, the insulating film is patterned using the same mask as the insulating film. After patterning the layer, an insulating film is formed. The insulating layer 486 is then removed to form an insulating layer 486, and the conductive layer is selectively etched using the insulating layer 486 as a mask. The first source electrode layer 485b, the second source electrode layer 488b, the first drain electrode A layer 485a and a second drain electrode layer 488a are formed. An insulating layer 486 is formed later. A parasitic capacitance formed between the second gate electrode layer 491 and the fourth drain electrode layer 498b This is provided to reduce the amount of

[0125] In the capacitance section, the first source electrode layer 485b is formed in the same process and with the same material. The capacitor electrode layer 433 is formed by the same process and material as the second source electrode layer 488b. The second capacitor electrode layer 434 is formed by the first capacitor electrode layer 433 and the second capacitor electrode layer 434 overlaps electrode layer 479f.

[0126] The first electrode layer 477 is formed in the same process and with the same material as the first source electrode layer 485b. The second oxide semiconductor layer 432b is formed on and in contact with the third oxide semiconductor layer 432b, which is a resistor. The second electrode layer 438 is formed by the same process as the first electrode layer 47 and using the same material as the base electrode layer 488b. 7 is formed on top of it.

[0127] The second thin film transistor 490 has a second gate electrode layer 4 91 and a second oxide semiconductor layer overlapping the second gate electrode layer 491 via a gate insulating layer 492. The third wiring 484a is a power supply line (positive power line).

[0128] In addition, a third source electrode layer 495a partially overlapping with and in contact with the second oxide semiconductor layer 482b, The fourth source electrode layer 498a is in contact with a part of the second oxide semiconductor layer 482b. The third drain electrode layer 495b and the fourth drain electrode layer 498b overlap each other. The third source electrode layer 495a is formed using the same process and material as the first source electrode layer 485b. , and the third drain electrode layer 495b are formed. In addition, the second source electrode layer 488b The fourth source electrode layer 498a and the fourth drain electrode layer 498b are formed by the same process and using the same material. 98b is formed.

[0129] The insulating layer 486 has an opening that reaches the second drain electrode layer 488a. The drain electrode layer 488a is electrically connected to the second gate electrode layer 491 which functions as a second wiring. to connect the first thin film transistor 480 and the second thin film transistor 490; Construct an EDMOS circuit.

[0130] The gate insulating layer 492 has an opening in a region overlapping with the electrode layer 479f, and the second capacitor electrode The fourth wiring 431 connected to the layer 434 functions as a capacitance wiring.

[0131] The fifth wiring 435 has an opening in the gate insulating layer 492 in the region where it overlaps with the electrode layer 479g. The second oxide semiconductor layer 432a is in contact with the fourth oxide semiconductor layer 432a functioning as a second resistor.

[0132] In this embodiment, an EDMOS circuit, a capacitance section, a first resistor, and a second resistor are formed on the same substrate. However, the present invention is not limited to this. They can be formed on the same substrate.

[0133] In addition, the cross-sectional structure of the terminal portion of the wiring that can be formed on the same substrate in this embodiment is shown in FIG. FIG. 4(A) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 4(B).

[0134] In FIG. 4A, a conductive layer 486 is formed on a stack of an insulating layer 486 and a gate insulating layer 492. 37 is a terminal electrode for connection that functions as an input terminal. The terminals are made of the same material as the electrode layers 479d, 479e, 479f, 479g, and 479h. The electrode layer 479i is electrically connected to the first source electrode layer 485b. The first insulating layer 487a and the third insulating layer 487b are placed under the electrode layer 439. The electrode layer 479i is not electrically connected to the first terminal electrode layer 439, and 9i to a potential different from that of the first terminal electrode layer 439, for example, floating, GND, 0V, etc. If you set it to , you can create a capacitance for noise countermeasures or static electricity countermeasures. The first terminal electrode layer 439 has a second terminal electrode layer 489 provided thereon. , and is electrically connected to the conductive layer 437 via the insulating layer 486 and the gate insulating layer 492. There are.

[0135] The first terminal electrode layer 439 is formed of the same material and in the same process as the first source electrode layer 485b. The second terminal electrode layer 489 can be formed using the same material as the second source electrode layer 488b. The conductive layer 437 can be formed using the same material and process as the first gate electrode layer 4. It can be formed using the same material and process as 81.

[0136] This embodiment mode can be freely combined with Embodiment Mode 1.

[0137] (Embodiment 3) In this embodiment, the EDMOS circuit shown in the second embodiment is used to implement a CPU (central processing unit). Here is an example of creating a path.

[0138] An example of a block diagram of a CPU is shown in FIG. 5. The CPU 1001 shown in FIG. A control circuit 1002, an instruction analysis decoder 1003, a register array 1004, Address logic buffer circuit 1005, data bus interface 1006, ALU1 007, instruction register 1008, etc.

[0139] These circuits are made of thin film transistors, inverters, etc., as shown in the first or second embodiment. The thin film shown in Embodiment 1 or 2 is manufactured using a capacitor circuit, a resistor, a capacitor, etc. The transistor uses an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced. The off-state current of the transistor can be made extremely small, and at least a part of the CPU 1001 a thin film transistor having an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced; This allows for low power consumption.

[0140] Here, we will briefly explain each circuit. Timing control circuit 1002 receives external commands, converts them into internal information, and sends them out to other blocks. It also issues instructions to the outside, such as reading and writing memory data, depending on the internal operation. The command analysis decoder 1003 has the role of converting external commands into internal commands. The register array 1004 is a volatile memory that temporarily stores data. The data buffer circuit 1005 is a circuit that specifies an address in the external memory. The interface 1006 is used to input and output data to and from external devices such as memory or a printer. The ALU 1007 is a circuit that performs arithmetic operations. The instruction register 1008 is a circuit that stores instructions. It is a circuit that temporarily stores information. A CPU is made up of a combination of such circuits. It is being done.

[0141] At least a part of the CPU 1001 is made of the thin film transistor shown in the first or second embodiment. By using a resistor, leakage current during standby is reduced, and the driving circuits used in electrical equipment This can reduce power consumption.

[0142] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0143] (Fourth embodiment) In this embodiment mode, an example of usage of the semiconductor device described in the above embodiment mode will be described. Specifically, regarding an application example of a semiconductor device that can input and output data without contact, The following will explain the use of semiconductor devices that can input and output data without contact. Depending on the state, it may be called an RFID tag, ID tag, IC tag, RF tag, wireless tag, electronic tag or It is also called a wireless chip.

[0144] An example of a top surface structure of a semiconductor device described in this embodiment mode will be described with reference to FIG. The semiconductor device shown in FIG. 8A is provided with an antenna (also referred to as an on-chip antenna). The semiconductor integrated circuit chip 400 and the antenna 405 (also referred to as a booster antenna) The semiconductor integrated circuit chip 400 includes a support substrate 406 provided thereon. 06 and the antenna 405. The insulating layer 410 holds the semiconductor integrated circuit chip 40 on the support substrate 406 and the antenna 405. It can be fixed to 0.

[0145] The surface of the semiconductor integrated circuit chip 400 is protected from electrostatic damage (malfunction of the circuit) caused by electrostatic discharge. A conductive shield is provided to prevent damage to the semiconductor element and the device. If the resistance of the antenna 405 is high and the pattern of the antenna 405 is not electrically connected, The conductive shield provided on the surface of the semiconductor integrated circuit chip 400 may be provided in contact with the conductive shield. .

[0146] The semiconductor integrated circuit provided in the semiconductor integrated circuit chip 400 includes a memory section and a logic section. A plurality of thin film transistors and other elements that constitute the memory section and logic section are provided. As a thin film transistor, a highly purified oxide semiconductor layer with a sufficiently reduced hydrogen concentration is used. The semiconductor device according to the present embodiment uses a thin film transistor that uses a This allows not only field-effect transistors but also memory elements that use semiconductor layers to be applied. Therefore, it is possible to manufacture and provide semiconductor devices that satisfy the functions required for a wide range of uses. .

[0147] FIG. 7A shows the antenna and semiconductor included in the semiconductor integrated circuit chip 400 shown in FIG. 8A. 7A shows an enlarged view of a conductor integrated circuit. In FIG. 7A, the antenna 101 has one turn. The loop antenna is rectangular, but is not limited to this configuration. The shape is not limited to a curved shape, but may be a circular shape. The number of turns is not limited to one, and may be more than one. However, when the number of turns of the antenna 101 is one, In this case, the parasitic capacitance occurring between the semiconductor integrated circuit 100 and the antenna 101 can be reduced. do.

[0148] 8(A) and 7(A), the antenna 101 is disposed around the semiconductor integrated circuit 100. The antenna is arranged to surround the enclosure, and the antenna is not connected to the antenna except for the area corresponding to the power supply point 408 shown by the dashed line. The antenna 101 is arranged in a different area from the semiconductor integrated circuit 100. As shown in FIG. 7(B), the power supply 408 may be connected to the power supply 408 in addition to the power supply 408 shown by the broken line. In the semiconductor integrated circuit, the antenna is arranged so as to overlap at least a part of the semiconductor integrated circuit. However, as shown in FIG. 8(A) and FIG. 7(A), the antenna 101 may be a semiconductor. By arranging the antenna in a different area from the integrated circuit 100, the semiconductor integrated circuit 100 and the antenna This can reduce the parasitic capacitance occurring between the capacitors 101.

[0149] In FIG. 8A, the antenna 405 is mainly located in the loop-shaped portion surrounded by the dashed line 407. By electromagnetic induction with the antenna 101, signals can be transmitted and received or power can be supplied. The antenna 405 is mainly sensitive to radio waves in the area other than the area surrounded by the dashed line 407. This allows signals to be exchanged with the interrogator or power to be supplied. During this period, the frequency of the radio waves used as the carrier (carrier wave) is 30MHz or higher. Hz or less is desirable, and for example, frequency bands such as 950 MHz and 2.45 GHz can be used. That's fine.

[0150] The antenna 405 has a rectangular loop shape with one turn in the area surrounded by the dashed line 407. However, the loop portion is not limited to having a rectangular shape. The number of turns is limited to one, and the shape may be curved, for example, circular. It may be plural.

[0151] The semiconductor device described in this embodiment mode is an electromagnetic induction type, an electromagnetic coupling type, or a microwave type. In the case of microwave systems, the antenna 1 is used depending on the wavelength of the electromagnetic waves used. 01. The shape of the antenna 405 can be determined appropriately.

[0152] For example, as a signal transmission method in semiconductor devices, a microwave method (e.g., UHF band When applying the signal The length and shape of the antenna can be set appropriately taking into consideration the wavelength of the electromagnetic waves used to transmit the signal. For example, the antenna can be made into a linear shape (e.g., a dipole antenna), a flat shape (e.g., a pad antenna), The antenna can be formed into various shapes such as a chip antenna or ribbon antenna. It is not limited to a straight line, but can be a curved or meandering shape or a combination of these, taking into account the wavelength of the electromagnetic wave. It may also be provided in a shape similar to the above.

[0153] In FIG. 9, the antenna 101 and the antenna 405 are arranged in a coil shape, and the antenna is connected by electromagnetic induction or electromagnetic coupling. An example of applying the method is shown below.

[0154] In FIG. 9, a support on which a coil-shaped antenna 405 is provided as a booster antenna is shown. A semiconductor integrated circuit chip 400 having a coil-shaped antenna 101 provided thereon is provided on a substrate 406. The antenna 405, which is a booster antenna, is provided with a support substrate 406 sandwiched therebetween. And so, capacitance is formed.

[0155] Next, the structure and arrangement of the semiconductor integrated circuit chip 400 and the booster antenna will be described. FIG. 8B shows the semiconductor integrated circuit chip 400 and the support substrate 40 shown in FIG. 6 corresponds to a perspective view of a semiconductor device in which an antenna 405 formed on the semiconductor device 100 is stacked. 8(C) corresponds to a cross-sectional view taken along dashed line XY in FIG. 8(B).

[0156] The semiconductor integrated circuit chip 400 shown in FIG. 8C is the same as that shown in the first or second embodiment. In this case, the semiconductor device is divided into individual chips. The semiconductor integrated circuit chip shown in FIG. 1 is used as an example, but this embodiment can also be applied to other embodiments. It is not limited to the structure.

[0157] The semiconductor integrated circuit 100 shown in FIG. 8C is made up of a first insulator 112 and a second insulator 102. In this embodiment, a plurality of semiconductor integrated circuits are sandwiched between the substrate and the side surfaces of the substrate. After bonding the first insulator and the second insulator together, the laminate for each semiconductor integrated circuit is A conductive shield is formed on the cut laminate to produce a semiconductor integrated circuit chip 400. The dividing means is not particularly limited as long as it can be physically divided. In this state, the separation is achieved by irradiating the film with laser light.

[0158] In FIG. 8C, the semiconductor integrated circuit 100 is closer to the antenna 405 than the antenna 101. However, the antenna 101 is not limited to this configuration. It may be located closer to the antenna 405 than the circuit 100. The integrated circuit 100 and the antenna 101 are directly connected to the first insulator 112 and the second insulator 102. They may be fixed by themselves or by an adhesive layer that functions as an adhesive.

[0159] Next, the operation of the semiconductor device according to this embodiment will be described. 6 is a block diagram showing an example of the configuration of such a semiconductor device. The booster antenna includes an antenna 422, a semiconductor integrated circuit 423, and an on-chip amplifier. When an electromagnetic wave is transmitted from the interrogator 421, the antenna 424 When the antenna 422 receives the electromagnetic waves, an alternating current is generated in the antenna 422. A magnetic field is generated around the antenna 422. Then, the loop-shaped portion of the antenna 422 Electromagnetic coupling with the loop-shaped antenna 424 results in induction to the antenna 424. The semiconductor integrated circuit 423 uses the induced electromotive force to generate a signal or The interrogator 421 receives power from the interrogator 421. Conversely, the interrogator 421 receives power from the interrogator 421. Therefore, by passing a current through the antenna 424 and generating an induced electromotive force in the antenna 422, , and transmits a signal to the interrogator 421 on the reflected wave of the radio wave transmitted from the interrogator 421. It is possible.

[0160] The antenna 422 has a loop-shaped portion that is electromagnetically coupled mainly to the antenna 424. The part that receives the radio waves from the interrogator 421 is divided into two parts. The shape of the antenna 422 in the part that mainly receives radio waves is any shape that can receive radio waves. For example, a dipole antenna, a folded dipole antenna, a slot antenna, , meander line antenna, microstrip antenna, etc. may be used.

[0161] In addition, although the configuration of the semiconductor integrated circuit having only one antenna has been described with reference to FIG. This configuration is not limited to this. It may have two antennas. Two antennas provide power. It is possible to use different radio wave frequencies for transmitting signals.

[0162] The semiconductor device according to this embodiment uses an on-chip antenna and Signals or power are transmitted and received contactlessly between the star antenna and the on-chip antenna. Therefore, unlike when an external antenna is connected to a semiconductor integrated circuit, This makes it difficult for the connection between the semiconductor integrated circuit and the antenna to be severed, and prevents initial defects in the connection. Furthermore, in this embodiment, a booster antenna is used, Unlike the case of only an on-chip antenna, the dimensions or shape of the on-chip antenna It is less subject to the area constraints of semiconductor integrated circuits, and the frequency band of radio waves that can be received is not limited. Enjoy the benefits of an external antenna, such as the ability to extend signal distance. can be done.

[0163] The semiconductor integrated circuit can also be formed directly on a flexible substrate. The semiconductor integrated circuit may be transferred from a substrate (such as a glass substrate) to another substrate (such as a plastic substrate). .

[0164] In addition, when transferring a semiconductor integrated circuit from a substrate to another substrate, various methods are available without particular limitation. For example, a peeling layer may be formed between the substrate and the semiconductor integrated circuit. That's fine.

[0165] For example, when a metal oxide film is formed as a peeling layer, the metal oxide film is brittle due to crystallization. The weakening allows the element layer including the semiconductor integrated circuit, which is the layer to be peeled, to be peeled off from the formation substrate. After the metal oxide film is weakened by crystallization, a part of the peeling layer can be further dissolved in a solution or Etching is performed using halogen fluoride gases such as NF3, BrF3, and ClF3 to remove the brittle The metal oxide film may be peeled off.

[0166] Also, as a peeling layer, a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, The substrate used is a transparent substrate. In this case, the separation layer is irradiated with laser light from the preparation substrate to remove nitrogen and oxygen contained in the separation layer. A method of vaporizing oxygen or hydrogen to separate the formation substrate from the separation layer can be used.

[0167] Alternatively, the peeling layer may be removed by etching, so that the layer to be peeled off can be peeled off from the formation substrate. .

[0168] In addition, there are methods for removing the substrate by mechanical polishing, and methods for removing the substrate by NF3, BrF3, ClF It is possible to use a method of removing the fluorine-containing compound by etching with halogen fluoride gas such as 3 or HF. In this case, the release layer does not need to be used.

[0169] In addition, laser irradiation, etching with gas or solution, or sharp knives or scalpels may cause A groove is formed to expose the peeling layer, and the layer to be peeled is created from the peeling layer using the groove as a starting point. It can also be peeled off from the substrate.

[0170] The peeling method may involve, for example, applying mechanical force (pulling off with a human hand or a gripping tool). The separation can be carried out by using a method such as a separation process using a rotating roller. Alternatively, the layer to be peeled may be peeled off from the peeling layer by dropping the liquid onto the peeling layer and allowing the liquid to penetrate into the interface with the peeling layer. In addition, fluoride gas such as NF3, BrF3, or ClF3 is introduced into the groove, and the peeling layer is etched with the fluoride gas. Alternatively, a method of etching and removing the layer to be peeled off from the substrate may be used. When peeling, a liquid such as water may be poured on the film.

[0171] As for other peeling methods, when the peeling layer is made of tungsten, ammonia water and peroxide are used. The peeling can be performed while etching the peeling layer with a mixed solution of hydrogen oxide and water.

[0172] A thin film transistor using an oxide semiconductor layer that has been highly purified by sufficiently reducing the hydrogen concentration is The off-state current is small, and low power consumption can be achieved. This can lead to electrostatic breakdown of semiconductor integrated circuits due to electrostatic discharge (causing malfunction of circuits and damage to semiconductor elements). In addition, a pair of insulators sandwiching the semiconductor integrated circuit can prevent damage. It is possible to provide a semiconductor device that is highly reliable and has durability while achieving size reduction and miniaturization. Cut.

[0173] (Embodiment 5) In this embodiment, a non-contact data storage device formed using the device of the fourth embodiment is used. An application example of a semiconductor device capable of inputting and outputting non-contact signals will be described below with reference to the drawings. Depending on the type of use, semiconductor devices that can input and output data by touch are RFID tags, Also known as D tag, IC tag, IC chip, RF tag, wireless tag, electronic tag or wireless chip. Be found out.

[0174] The semiconductor device 800 has a function of contactlessly exchanging data, and includes a high-frequency circuit 810, a power supply circuit a circuit 820, a reset circuit 830, a clock generating circuit 840, a data demodulating circuit 850, and a data a data modulation circuit 860, a control circuit 870 for controlling other circuits, a memory circuit 880, and an antenna. The high frequency circuit 810 has an antenna 890 (see FIG. 10(A)). The signal is received by the data modulation circuit 860 and output from the antenna 890. The power supply circuit 820 is a circuit that generates a power supply potential from a received signal, and the reset circuit The circuit 830 is a circuit for generating a reset signal, and the clock generating circuit 840 is a circuit for generating a reset signal. It is a circuit that generates various clock signals based on the received signal input from 0, and The circuit 850 demodulates the received signal and outputs it to the control circuit 870. 60 is a circuit that modulates the signal received from the control circuit 870. For example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and The code extraction circuit 910 is provided with a control circuit and an output unit circuit 940. It is a circuit that extracts each of the multiple codes contained in the instructions sent to 870. The code determination circuit 920 compares the extracted code with the code corresponding to the reference and determines the code. The CRC determination circuit 930 is a circuit that determines the contents of the transmitted This is a circuit that detects whether or not there is an error.

[0175] Next, an example of the operation of the semiconductor device described above will be described. A radio signal is received. The radio signal is sent to the power supply circuit 820 via the high frequency circuit 810. A high power supply potential (hereinafter referred to as VDD) is generated. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is also supplied to the The signal is demodulated (hereinafter referred to as the demodulated signal). The signal passing through the clock generating circuit 840 and the demodulated signal are sent to the control circuit 870. The signal sent to the control circuit 870 is transmitted to the chord extraction circuit 910, the chord determination circuit 920, and and analyzed by the CRC determination circuit 930. The information about the semiconductor device stored in the memory circuit 880 is output. The device information is encoded through the output unit circuit 940. The information of the device 800 passes through a data modulation circuit 860 and is converted into a radio signal by an antenna 890. In addition, in the plurality of circuits constituting the semiconductor device 800, a low power supply voltage The potential (hereinafter referred to as VSS) is common, and VSS can be set to GND.

[0176] In this way, a signal is sent from the communication device to the semiconductor device 800, and the signal is transmitted from the semiconductor device 800. The data of the semiconductor device is read by receiving the transmitted signal with a communication device. This becomes possible.

[0177] In addition, the semiconductor device 800 does not have a power source (battery) for supplying power voltage to each circuit. It can be a type that uses electromagnetic waves, or it can be equipped with a power source (battery) and uses electromagnetic waves and a power source ( It may also be a type in which the power supply voltage is supplied to each circuit by a power supply (battery).

[0178] Next, an example of a usage form of a semiconductor device capable of contactless data input / output will be described. A communication device 3200 is provided on the side of the mobile terminal including the display unit 3210, and an item 3220 The semiconductor device 3230 is provided on the side of the article 3220 (FIG. 10(B)). When the communication device 3200 is held over the body device 3230, the raw materials and origin of the product are displayed on the display unit 3210. , inspection results for each production process, distribution history, and product information such as product descriptions. When the product 3260 is transported by the belt conveyor, the communication device 324 0 and a semiconductor device 3250 provided on the product 3260, and inspecting the product 3260. In this way, the semiconductor device can be used in the system. This makes it easy to obtain information, achieving high functionality and added value.

[0179] As described above, the range of application of semiconductor devices is extremely wide, and they can be used in a wide range of electronic devices. It is Noh.

[0180] (Embodiment 6) The thin film transistor obtained in the first or second embodiment is a highly purified oxide. It is a thin film transistor that uses semiconductors, and by configuring a circuit with this thin film transistor, This makes it possible to realize low power consumption and stabilize the operation of the memory circuit.

[0181] In this embodiment mode, a memory that can be configured using the thin film transistor of Embodiment 1 will be described. An example of a relay circuit is shown below.

[0182] FIG. 11A shows an equivalent circuit diagram of an example of a memory circuit. The memory circuitry includes a row decoder, a write circuit and a refresh circuit, a column decoder, The memory element 1100 is arranged in a matrix. The signal lines connected to 1100 are routed through the write and refresh circuits to the row decoder. The scanning lines connected to the memory elements 1100 arranged in a matrix are called column data lines. The row decoder receives the bit signal. The read enable signal / write enable signal (RE / WE) is provided to the refresh circuit. A data signal (DATA) and an output signal (OUT) are input.

[0183] Each memory element 1100 has a capacitor and a thin film transistor. One of the source and drain of the thin film transistor is connected to a signal line. The other terminal of the input is connected to one electrode of the capacitance element, and the other electrode of the capacitance element is connected to the low potential side (preferably Preferably, it is connected to a reference potential (Vss).

[0184] FIG. 11B shows the write circuit and refresh circuit shown in FIG. A specific example of the configuration of the refresh circuit will be shown below.

[0185] The write circuit and refresh circuit shown in FIG. 11(B) are implemented by AND circuits. ) and a sense amplifier. A signal from the row decoder is input to one input of the third AND circuit 1103. The PRC signal is input to the other input of the first AND circuit 1101, and the second AND circuit 11 A write enable signal (WE) is input to the other input of the third AND circuit 11 The other input of the first AND circuit 103 receives a read enable signal (RE). The output of 101 controls the on / off of the first switch 1104 and the second AND circuit 11 The output of 02 controls the on / off of the second switch 1105 and the third AND circuit 110 The output of 3 controls the on / off of the third switch 1106. Precharge signal line Vp rc is connected to the signal line via the first switch 1104, and the data signal line data is connected to the second The signal line is connected via the switch 1105.

[0186] The signal line connected via the first switch 1104 and the second switch 1105 is The sense amplifier is connected to the output terminal 1103 via a switch 1106. A signal is output to the output signal line (OUT).

[0187] The AND circuit described above may have a general configuration and may have a simple configuration. It is preferable.

[0188] Note that a sense amplifier refers to a circuit having a function of amplifying an input signal.

[0189] The signal used here may be, for example, an analog signal using voltage, current, resistance, or frequency. For example, the potential may be set to at least a first potential. and the second potential, and the first potential is set to high level (high potential, V H It is also written as potential, and a low level (low potential, V L (also written as By doing so, it is possible to set a binary digital signal. H and V L is a constant value However, taking into consideration the influence of noise, H and V L It is also possible to give some width to the

[0190] In addition, terms with ordinal numbers such as 1st and 2nd are used to avoid confusion between elements. This is added for convenience and does not limit the number.

[0191] As described above, the thin film transistor described in the first embodiment is used, and the capacitor described in the second embodiment is used. A memory circuit can be fabricated using the above.

[0192] The refresh timing of the memory circuit is determined based on the leakage current of the storage element 1100 evaluated in advance. This is determined at the design stage at a fixed time interval based on the It is set taking into consideration the temperature dependency of the clock current and the variations in the manufacturing process.

[0193] In the thin film transistor described in Embodiment 1 or 2, the hydrogen concentration is sufficiently reduced. The off-state current of the thin film transistor can be made extremely small by using an oxide semiconductor layer. The temperature characteristics of the off-state current change very little from -30°C to 120°C. can be kept small.

[0194] Therefore, if the thin film transistor shown in the first or second embodiment is used, silicon The refresh interval can be set to a longer time interval compared to transistors using Power consumption during standby can be reduced.

[0195] In addition, since the off-state current has almost no temperature dependency, the memory of this embodiment can be easily used in electronic devices mounted on a vehicle. The leakage current during standby is extremely small, making it suitable for use in electric vehicles. Even during long periods of standby, the driving distance per unit charge remains almost constant. .

[0196] The transistor described in Embodiment 1 or 2 has a structure in which carriers are separated from each other in an oxide semiconductor. Remove impurities that can act as donors or acceptors to an extremely low level, An intrinsic or substantially intrinsic semiconductor is used.

[0197] FIG. 12 shows a source-drain region of the transistor shown in the first or second embodiment. The Fermi level of a highly purified oxide semiconductor is higher than that of an ideal oxide semiconductor. In an oxide semiconductor with a sufficiently reduced hydrogen concentration, In this case, the number of minority carriers (holes in this case) is zero or very close to zero.

[0198] If the work function is φm and the electron affinity of the oxide semiconductor is χ, then the work function φm is the electron affinity χ If it is smaller, it will be an ohmic contact for electrons.

[0199] Here, if φm=χ, the Fermi level of the electrode metal and the oxide semiconductor at the junction surface The conduction band edge levels of the two materials match. Band gap 3.05 eV, electron affinity 4.3 eV, Intrinsic state (carrier density approx. 1×10 -7 / cm 3 ) and the source and drain electrodes When titanium (Ti) with a work function of 4.3 eV is used as the dopant electrode, as shown in FIG. Thus, no barrier is formed for the electrons.

[0200] Figure 13 shows a schematic diagram of the energy band structure. When a positive voltage (V D >0) The dashed line shows the case where no voltage is applied to the gate (V G =0), the solid line indicates a positive Voltage (V G When no voltage is applied to the gate, a high potential is applied. Because of the barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, and current does not flow. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, This indicates the ON state where current flows.

[0201] Here, the barrier height affects the carrier mobility. As the voltage increases, the barrier height (h b ) becomes smaller and the mobility becomes larger. If the work function φm of the base electrode is similar to the electron affinity of the oxide semiconductor, h b is even smaller However, when such an electrode material is in contact with an oxide semiconductor, It is necessary not to make contact with insulating materials.

[0202] In such a case, in a bottom gate type (inverted staggered type) transistor, the source-drain The barrier between the electrons becomes smaller, making it easier for parasitic channels to form. In this case, a top-gate transistor is considered to be suitable.

[0203] Figure 14(A) shows the energy band diagram of the MOS structure when the gate voltage is positive. The figure shows a transistor using an oxide semiconductor. In oxide semiconductors, there are almost no thermally excited carriers, and even if a positive gate voltage is applied, Carriers are not accumulated near the gate insulating film. However, as shown in Figure 13, Carriers injected from the

[0204] FIG. 14(B) is an energy band diagram of the MOS structure when the gate voltage is made negative. , a transistor using an oxide semiconductor is shown. Since there are almost no carriers (positive holes), carriers are not accumulated near the gate insulating film. This means that the off-state current is small.

[0205] FIG. 15 shows the band diagram of a transistor using silicon semiconductor. The intrinsic carrier density of silicon semiconductors is 1.45 x 10 10 / cm 3 (300K) In practice, impurities such as phosphorus or boron are added. Since a silicon wafer is used, the actual size is 1×10 14 / cm 3 More than a career exists in the silicon semiconductor, which contributes to the conduction between the source and drain. The band gap of silicon semiconductor is 1.12 eV, so The off-state current of a transistor varies greatly depending on the temperature.

[0206] In this way, simply applying a wide bandgap oxide semiconductor to a transistor Instead, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration is reduced to 1×10 14 / cm 3 Less than 1 × 10 12 / cm 3 By making it so that The carriers thermally excited at the operating temperature are eliminated, and only the carriers injected from the source side are included. This allows the transistor to operate, reducing the off-state current to 1×10 -13 A, and the off-state current is extremely stable with almost no change due to temperature changes. Therefore, a transistor that operates smoothly can be obtained.

[0207] (Embodiment 7) This embodiment is configured using the thin film transistor of the first embodiment or the second embodiment. 1 shows an example of a shift register that can be implemented.

[0208] FIG. 16(A) shows an equivalent circuit diagram of an example of a shift register. The shift register shown has two clock signal lines and a The flip-flops are electrically connected to each other in two stages. Alternatively, flip-flops may be provided in more stages.

[0209] In the two clock signal lines, each of the input clock signals is The signal line is high level (V H ), the other is set to low level (V L ) and operate it.

[0210] In the shift register shown in FIG. 16(A), the first clock signal line CLK is electrically connected to The flip-flops in the first stage are electrically connected to the second clock signal line CLKB in order. The connected second-stage flip-flops, followed by the n-1th-stage flip-flops, and An example having an n-th stage flip-flop will be described. However, the present invention is not limited to this. It is sufficient to have at least a first flip-flop and a second flip-flop. .

[0211] The clock signal line CLK is a wiring to which the clock signal CK is input.

[0212] The clock signal line CLKB is a wiring through which the clock signal CKB is input.

[0213] The clock signals CK and CKB are respectively connected to a NOT circuit (an inverter circuit).

[0214] The first flip-flop receives the start signal SP and the start signal SPB. The clock signal CK is input as a clock signal, and the input signals SP and SPB are The output signal OUT is output according to the state of the signal and the state of the clock signal CK. Here, the state of the signal refers to, for example, the potential, current, or frequency of the signal.

[0215] The start signals SP and SPB are each generated by, for example, a NOT circuit (inverter circuit).

[0216] In addition, the signal here may be, for example, an analog signal using voltage, current, resistance, or frequency. For example, the potential may be set to at least a first potential. and the second potential, and the first potential is set to high level (high potential, V H It is also written as potential, and a low level (low potential, V L (also written as By doing so, it is possible to set a binary digital signal. H and V L is a constant value However, taking into consideration the influence of noise, H and V L It is also possible to give some width to the

[0217] In addition, terms with ordinal numbers such as 1st and 2nd are used to avoid confusion between elements. This is added for convenience and does not limit the number.

[0218] The second flip-flop receives the output signal of the first flip-flop as the start signal SP. The clock signal OUT is input, and the clock signal CK2 is input as a clock signal. The output signal FF1out and the signal FF2out whose state is set according to the clock signal CK2 as an output signal.

[0219] The second flip-flop receives the start signal SP and the start signal SPB. The clock signal CK2 is input as a lock signal, and the input signals SP and SPB The output signal OUTB is output in accordance with the state of this signal and the state of the clock signal CK2.

[0220] FIG. 16B shows a specific example of the configuration of the first flip-flop shown in FIG. 16A. vinegar.

[0221] The start signal SP is applied to one of the source and drain of the first thin film transistor 1111. is input to one of the source and drain of the fourth thin film transistor 1114.

[0222] The start signal SPB is applied to one of the source and drain of the second thin film transistor 1112. On the other hand, the signal is input to one of the source and drain of the third thin film transistor 1113 .

[0223] The clock signal CLK is applied to the first thin film transistor 1111 and the second thin film transistor 1112. 112, the gates of the third thin film transistor 1113 and the fourth thin film transistor 1114 The data is entered into the

[0224] The other of the source and drain of the first thin film transistor 1111 is connected to the fifth thin film transistor The gate of the transistor 1115 is connected to one electrode of the first capacitor 1119 .

[0225] The other of the source and drain of the second thin film transistor 1112 is connected to the sixth thin film transistor The gate of the transistor 1116 is connected to one electrode of the second capacitor 1120 .

[0226] The other of the source and drain of the third thin film transistor 1113 is connected to the seventh thin film transistor The gate of the transistor 1117 is connected to one electrode of the third capacitor element 1121 .

[0227] The other of the source and drain of the fourth thin film transistor 1114 is connected to the eighth thin film transistor The gate of the transistor 1118 is connected to one electrode of the fourth capacitor 1122 .

[0228] The drain of the fifth thin film transistor 1115 is connected to a high potential side (preferably the power supply potential Vdd). The source of the fifth thin film transistor 1115 is connected to the first capacitor element 111. The other electrode of the transistor 9 is connected to the drain of the sixth thin film transistor 1116, and the output signal O The other electrode of the second capacitor element 1120 and the sixth thin film transistor 11 The source of 16 is connected to the low potential side (preferably the reference potential Vss).

[0229] The drain of the seventh thin film transistor 1117 is connected to a high potential side (preferably the power supply potential Vdd). The source of the seventh thin film transistor 1117 is connected to the third capacitor element 112. The other electrode of the first thin film transistor 1111 is connected to the drain of the eighth thin film transistor 1118, and the output signal O The other electrode of the fourth capacitor 1122 and the eighth thin film transistor 1123 are connected to each other. The source of 118 is connected to the low potential side (preferably the reference potential Vss).

[0230] A first capacitance element 1119, a second capacitance element 1120, a third capacitance element 1121, and a fourth capacitance element 1122 The capacitor 1122 is formed on the same substrate as the thin film transistor using the capacitor described in Embodiment 2. It can be made on a plate.

[0231] As described above, the purified oxide semiconductor layer described in Embodiment 1 or 2 is used. A flip-flop circuit is formed by using the thin film transistor and the capacitor described in the second embodiment. It can be made.

[0232] (Embodiment 8) This embodiment is configured using the thin film transistor of the first embodiment or the second embodiment. An example of a boost circuit (charge pump circuit) that can achieve this is shown below.

[0233] Fig. 17 shows an example of a specific configuration of a booster circuit. The booster circuit shown in Fig. 17 has two clocks. A lock signal line, a plurality of forward diode-connected transistors 1123, and A plurality of capacitance elements 1 each having one electrode connected between the source and drain of a plurality of transistors 124, and one electrode is connected to the end of the plurality of transistors, and the other electrode is connected to the The other electrodes of the plurality of capacitor elements are connected to the capacitor elements. , is electrically connected to one of the two clock signal lines.

[0234] It should be noted that a clock signal line may be further provided.

[0235] There are more transistors and capacitors depending on the voltage you want to output. Good too.

[0236] In the two clock signal lines, each of the input clock signals is The signal line is high level (V H ), the other is set to low level (V L ) and operate it.

[0237] The clock signals CLK and CLKB are each generated by, for example, a NOT circuit (inverter). The NOT circuit can be generated using the EDM circuit shown in the second embodiment. It can be manufactured using an OS circuit.

[0238] By using the boost circuit shown in Figure 17, the voltage input from Vin can be increased to Vout. For example, when the power supply potential Vdd is input from Vin, the voltage from Vout is It is possible to output a voltage higher than Vdd and boost it to the desired voltage. The signal whose potential has been boosted to a desired potential is input to, for example, a power supply line, and is then fed to a booster circuit. It is used for each circuit mounted on the same board as the circuit.

[0239] Here, the constant potential held at the other electrode of the storage capacitor element is, for example, the power supply potential V dd or the reference potential Vss.

[0240] In addition, the signal here may be, for example, an analog signal using voltage, current, resistance, or frequency. For example, the potential may be set to at least a first potential. and the second potential, and the first potential is set to high level (high potential, V H It is also written as potential, and a low level (low potential, V L (also written as By doing so, it is possible to set a binary digital signal. H and V L is a constant value However, taking into consideration the influence of noise, H and V L It is also possible to give some width to the

[0241] In addition, terms with ordinal numbers such as 1st and 2nd are used to avoid confusion between elements. This is added for convenience and does not limit the number.

[0242] As described above, the thin film transistor described in the first embodiment and the capacitor described in the second embodiment are used. A booster circuit can be fabricated using this.

[0243] (Embodiment 9) In this embodiment, a semiconductor integrated circuit obtained in any one of the first to eighth embodiments is mounted. An example of such an electronic device will be described with reference to FIG. A semiconductor integrated circuit is transferred from a plastic substrate to another substrate by a method of transferring the semiconductor integrated circuit. By mounting it on a plastic film, thin or flexible electronic devices can be manufactured. Semiconductor integrated circuits are mounted on circuit boards and installed inside the main body of each electronic device. It is being done.

[0244] The motherboard includes a semiconductor including the thin film transistor of the first or second embodiment. The integrated circuit is implemented. The semiconductor integrated circuit is a logic circuit, a flash memory, The circuit is fabricated by implementing a ry circuit, an SRAM circuit, a DRAM circuit shown in the sixth embodiment, etc. The CPU shown in the third embodiment can also be implemented. The circuit may be mounted by wire bonding. It is possible to mount an integrated circuit film of any shape.

[0245] In addition, an FPC is attached to the circuit board, and via the FPC, it can be connected to, for example, a display device. The display driver and controller can be configured. As the driver, the shift register shown in the seventh embodiment or the E shown in the second embodiment may be used. It has a DMOS circuit.

[0246] FIG. 18(A) shows a notebook-type device manufactured by mounting at least a semiconductor integrated circuit as a component. The personal computer includes a main body 3001, a housing 3002, a display unit 3003, and a keyboard. The CPU and the board 3004 shown in the third embodiment are also included. A notebook personal computer has the DRAM circuit shown in form 6.

[0247] FIG. 18(B) shows a portable information device manufactured by mounting at least a semiconductor integrated circuit as a component. The main body 3021 is a terminal (PDA) having a display unit 3023 and an external interface 30 25 and operation buttons 3024. A stylus is also provided as an accessory for operation. There is 3022.

[0248] FIG. 18(C) shows an electronic paper manufactured by mounting at least a semiconductor integrated circuit as a component. Electronic paper is used in all kinds of electronic devices that display information. For example, electronic books, posters, etc. can be displayed using electronic paper. Suitable for in-car advertising on trains and other vehicles, and for display on various cards such as credit cards. FIG. 18(C) shows an example of an electronic book 2700. For example, The electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703 . The housing 2701 and the housing 2703 are integrated by a shaft 2711. The opening and closing operation can be performed around the axis 11. With this configuration, It becomes possible to perform the operation.

[0249] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 18C), and An image can be displayed on the display portion (the display portion 2707 in FIG. 18C).

[0250] 18C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The back of the housing may be provided with a keyboard, a pointing device, etc. External connection terminals (earphone terminal, USB terminal, AC adapter and USB) on the front or side It is equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. It may also be possible to use the following.

[0251] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0252] FIG. 18(D) shows a mobile phone manufactured by mounting at least a semiconductor integrated circuit as one component. It is composed of two housings, housing 2800 and housing 2801. Housing 2801 The display panel 2802, the speaker 2803, the microphone 2804, the pointing device The device 2806, the camera lens 2807, the external connection terminal 2808, etc. The housing 2800 also includes a solar cell 2810 for charging the portable information terminal, an external memory The antenna is built into the housing 2801. are.

[0253] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. A booster circuit (such as the booster circuit shown in the eighth embodiment) for boosting the voltage to be supplied to each circuit to a voltage required for each circuit. circuit) is implemented.

[0254] In addition to the above configuration, the non-contact IC chip shown in the fourth or fifth embodiment may be used. , and may also have a built-in small recording device.

[0255] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the lens 2802, allowing video calls. The speaker 2803 and microphone 2804 are not limited to voice calls, but can also be used for video calls. Furthermore, the housing 2800 and the housing 2801 can be slid apart, As shown in Figure 18(D), it can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0256] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0257] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0258] FIG. 18(E) shows a digital card manufactured by mounting at least a semiconductor integrated circuit as a component. The camera includes a main body 3051, a display unit (A) 3057, an eyepiece 3053, and an operation switch 30 54, a display unit (B) 3055, a battery 3056, etc.

[0259] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 8. [Explanation of symbols]

[0260] 100 Semiconductor Integrated Circuit 101 Antenna 102 Second Insulator 112 First Insulator 400 Semiconductor Integrated Circuit Chips 405 Antenna 406 Support substrate 407 dashed line 408 Power Supply Point 410 Insulating layer 420 Semiconductor devices 421 Interrogator 422 Antenna 423 Semiconductor Integrated Circuits 424 Antenna 430 board 431 Wiring 432a Oxide semiconductor layer 432b Oxide semiconductor layer 433 First Capacitive Electrode Layer 434 Second Capacitive Electrode Layer 435 5th wiring 437 Conductive Layer 438 Second electrode layer 439 First terminal electrode layer 440 Thin Film Transistor 441 Gate electrode layer 442 Oxide semiconductor layer 443 Second insulating layer 444 Gate insulating layer 445a Source electrode layer 445b Drain electrode layer 446 Fourth insulating layer 447a Insulating layer 447b Insulating layer 448a Source electrode layer 448b Drain electrode layer 470 Thin Film Transistors 471 First gate electrode layer 472 Oxide semiconductor layer 473 Fifth Insulating Layer 474a Wiring layer 474b wiring layer 475a Source electrode layer 475b Drain electrode layer 477 First electrode layer 478a Source electrode layer 478b Drain electrode layer 479a~479i Electrode layer 480 First Thin Film Transistor 481 First gate electrode layer 482a Oxide semiconductor layer 482b Oxide semiconductor layer 484a Wiring 484b wiring 485a Drain electrode layer 485b Source electrode layer 486 Insulating Layer 487a Insulating layer 487b Insulating layer 488a Drain electrode layer 488b Source electrode layer 489 Terminal electrode layer 490 Second Thin Film Transistor 491 Second gate electrode layer 492 Gate insulating layer 495a Source electrode layer 495b Drain electrode layer 498a Source electrode layer 498b Drain electrode layer 800 Semiconductor devices 810 High Frequency Circuit 820 Power supply circuit 830 Reset Circuit 840 Clock Generation Circuit 850 Data demodulation circuit 860 Data Modulation Circuit 870 Control circuit 880 Memory circuit 890 Antenna 910 Code Extraction Circuit 920 Code Judgment Circuit 930 CRC judgement circuit 940 Output unit circuit 1001 CPU 1002 Timing control circuit 1003 Instruction Analysis Decoder 1004 Register Array 1005 Address logic buffer circuit 1006 Data Bus Interface 1007 ALU 1008 Instruction Register 1100 memory element 1101 First AND circuit 1102 Second AND circuit 1103 Third AND Circuit 1104 Switch 1105 Switch 1106 Switch 1111 Thin-film transistor 1112 Thin-film transistor 1113 Thin-film transistor 1114 Thin-film transistor 1115 Thin-film transistor 1116 Thin-film transistor 1117 Thin-film transistor 1118 Thin-film transistor 1119 Capacitor element 1120 Capacitor element 1121 Capacitor element 1122 Capacitor element 1123 Transistor 1124 Capacitor element 3200 Communication Equipment 3210 Display section 3220 items 3230 Semiconductor devices 3240 communication device 3250 Semiconductor Equipment 3260 items

Claims

[Claim 1] The hydrogen concentration on the insulating surface is 5×10 １９ / cm ３ and the carrier concentration is 5×10 １４ / cm ３ an oxide semiconductor layer having the following structure: a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate electrode layer formed on the gate insulating layer;

Images