MEMORY SYSTEM AND ASSOCIATED METHODS INCLUDE A MEMORY ARRAY USING COLUMN READ CIRCUITRY TO CONTROL THE FLOATING OF COLUMN READ BIT LINES - Patent application

Abstract

The memory system includes a column circuit that generates a logic state of data stored in one of the memory bitcell circuits in a column during a read operation. The column circuit includes a read control circuit that causes a float control circuit to couple a read bitline to a charged evaluate output line during a read operation and causes the float control circuit to decouple the read bitline from the evaluate output line during an idle phase. Decoupling the read bitline from the charged evaluate output line reduces power loss between read operations due to current leakage through read port circuitry in the memory bitcell circuit to which the read bitline is coupled. The memory system may include at least one read bitline, each read bitline coupled to a respective float control circuit and to a respective plurality of memory bitcell circuits in the column.

Description

[Technical Field]

[0001] The techniques of this disclosure relate generally to memory arrays, and more particularly to circuits for controlling read lines in columns of memory bit cell circuits in a memory array. [Background technology]

[0002] Integrated circuits (ICs) enable electronic devices to perform a wide variety of applications with high speed and accuracy. An IC may contain one or more processing circuits that execute application instructions and rapidly process information. Instructions and other information may be stored in memory arrays of a memory system. Information stored in memory arrays also includes data that may be used and generated by the instructions. Examples of such data include photographs, video games, databases, and application user data.

[0003] To accommodate the large amount of data stored in an IC, a memory array can occupy a significant percentage of the area of ​​the IC. The memory array can also consume a significant percentage of the power consumed by the IC. Power consumption in an IC can generate heat and reduce the battery life of a mobile device. A memory array can consume power at a higher rate when addressed memory bitcell circuits are being accessed to read or write information during instruction processing. A memory array can also be powered when not being accessed, in an inactive mode when it is not being accessed to retain data. Leakage currents can exist that cause memory arrays to consume power in the inactive mode. Therefore, IC manufacturers seek ways to reduce power consumption by reducing leakage currents in memory arrays during active and inactive modes. Summary of the Invention

[0004] Exemplary aspects disclosed herein include a memory system including a memory array that uses a column readout circuit to control the floating of column readout bitlines. Related methods for performing read operations in a memory array that uses a column readout circuit to control the floating of column readout bitlines are also disclosed. The memory system includes one or more bitcell columns, each including a plurality of memory bitcells (e.g., static random access memory (SRAM) bitcells), each storing a logic state. The logic state stored in a selected one of the memory bitcells can control a read port circuit in the memory bitcell to determine the logic state generated on the read bitline. The read port circuit includes a read port output, and the read port outputs of multiple memory bitcells in the same column are coupled to the read bitline. The memory system includes a column readout circuit for evaluating the logic state at the read port output of a selected memory bitcell. The column readout circuit includes an evaluate output line coupled to the readout port circuit by the read bitline in a dynamic readout circuit configuration. The column readout circuit also includes a precharge circuit that is activated to precharge the evaluate output line during an idle phase and a precharge phase of a read operation. The column readout circuit includes a float control circuit coupled in-line between the evaluate output line and the read bit line. The memory system includes a read control circuit for controlling activation and deactivation of the float control circuit. During an idle phase between read operations, while the evaluate output line is precharged by the precharge circuit, the float control circuit is deactivated to decouple the evaluate output line from the read bit line and the read port circuit. In other words, since the read bit line and the read port output of the read port circuit are kept floating during the idle phase, the precharge circuit precharges only the evaluate output line, which reduces power consumption caused by leakage current through the read port circuit.Because there are multiple memory bitcells in a column, each containing a read port circuit, if the evaluate output line were coupled to the read bitline during the idle phase, power loss due to leakage would be much higher. During the precharge phase of a read operation, prior to the evaluate phase of the read operation, a float control circuit is activated to couple the evaluate output line to the read bitline and the read port circuit, briefly precharging the dynamic read circuit for evaluation. A voltage drop across the float control circuit pulls the read bitline and read port output to a voltage lower than the power supply voltage, which saves power and reduces charging time. The precharge circuit is deactivated during the evaluate phase of the read operation, and the read port circuit of the selected memory bitcell is activated to provide an evaluation of the stored logic state to the evaluate output line. The read word line (RWL) coupled to the selected memory bitcell activates the read port circuit during the evaluate phase, and the stored logic state controls the read port circuit to indicate the stored logic state on the evaluate output line. The read port circuit can be two stacked transistors controlled by RWL and the stored logic state, respectively, to precharge or discharge the read bit line based on the logic state stored in the memory bit cell. After the read operation, the float control circuit is deactivated in the idle phase.

[0005] The performance of a memory system during a memory read operation can be improved by reducing the number of memory bit cells to which a read bit line is coupled in a column. In this way, both the length of the read bit line and the number of capacitive loads can be reduced. To this end, the memory bit cells in each column may be divided into multiple (e.g., two or more) read bit lines, each coupled to an evaluate output line via a corresponding float control circuit. During a read operation, since only one memory bit cell in a column can be read, only the float control circuit of the read bit line coupled to the selected memory bit cell is activated, while all other float control circuits remain inactive to reduce power dissipation.

[0006] In an exemplary aspect disclosed herein, a memory system is disclosed. The memory system includes at least one bitcell column circuit, each bitcell column circuit including a plurality of memory bitcell circuits, a read bitline coupled to a first plurality of memory bitcell circuits in a bitcell column circuit in the at least one bitcell column circuit, and a column readout circuit. The column readout circuit includes an evaluate output line, a precharge circuit configured to precharge the evaluate output line during an idle phase and a precharge phase of a read operation, and a float control circuit coupled between the read bitline and the evaluation output line. The float control circuit is configured to couple the read bitline to the evaluate output line during the precharge and evaluation phases of the read operation and to decouple the read bitline from the evaluation output line during the idle phase. The column readout circuit is configured to evaluate a stored logic state of a selected one of the first plurality of memory bitcell circuits on the evaluate output line during the evaluation phase. The at least one bit cell column circuit also includes a read control circuit coupled to the float control circuit, the read control circuit configured to cause the float control circuit to couple the evaluation output lines to the read bit lines in response to the precharge phase and in response to an evaluation phase of the read operation, and to cause the float control circuit to decouple the evaluation output lines from the read bit lines in response to an idle phase.

[0007] In another exemplary aspect, a memory system includes at least one bitcell column circuit, each bitcell column circuit including a plurality of memory bitcell circuits, a read bitline coupled to a first plurality of memory bitcell circuits in a bitcell column circuit of the at least one bitcell column circuit, and a column readout circuit. The column readout circuit includes an evaluate output line, a precharge circuit configured to precharge the evaluate output line during an idle phase and a precharge phase of a read operation, and a float control circuit coupled between the read bitline and the evaluate output line. The float control circuit is configured to couple the read bitline to the evaluate output line during the precharge and evaluate phases of the read operation and to decouple the read bitline from the evaluation output line during the idle phase. The column readout circuit also includes a column output circuit coupled to the evaluate output line, the column output circuit configured to generate a column output signal based on the evaluate output signal, the column output circuit including an inverter circuit configured to generate the column output signal having a logic state complementary to that of the evaluate output line. The column readout circuit is configured to evaluate the stored logic state of a selected one of the first plurality of memory bit cell circuits on an evaluation output line during an evaluation phase.

[0008] In another exemplary aspect, a method of read operation in a memory system is disclosed. The method includes receiving, at a read control circuit in a bitcell column circuit in the memory system, an indication indicating one of an idle phase, a precharge phase of a read operation, or an evaluation phase of a read operation to read a logic state of data stored in a memory bitcell circuit of a plurality of memory bitcell circuits in the bitcell column circuit, the bitcell column circuit further including an evaluation output line, a float control circuit, and a first read bit line coupled to a read port circuit in each of a first plurality of memory bitcell circuits in the bitcell column circuit. The method includes controlling, by the read control circuit, the precharge circuit to couple the evaluation output line to a supply voltage rail and charge the evaluation output line to a first precharge state corresponding to a first voltage in response to the indication indicating the idle phase, to couple the evaluation output line to the supply voltage rail and charge the evaluation output line to the first precharge state in response to the indication indicating the precharge phase of the read operation, and to isolate the evaluation output line from the supply voltage rail in response to the indication indicating the evaluation phase of the read operation. The method further includes controlling, by the read control circuit, the float control circuit to couple the first read bit line to the evaluation output line in response to an indication indicating a precharge phase of the read operation, to couple the first read bit line to the evaluation output line in response to an indication indicating an evaluation phase of the read operation, and to decouple the read bit line from the evaluation output line in response to an indication indicating an idle phase.The method further includes coupling, by a read port circuit in a selected one of the first plurality of memory bitcell circuits, a first read bitline to a ground voltage rail and discharging an evaluation output line to a discharged state based on a first logic state of data stored in the selected one of the first plurality of memory bitcell circuits; isolating, by the read port circuit in the one of the first plurality of memory bitcell circuits, the first read bitline from the ground voltage rail and maintaining the evaluation output line in a first precharge state based on a second logic state of data stored in the one of the first plurality of memory bitcell circuits; and generating, in response to an indication of an evaluation phase of the read operation, a column output signal at a first output logic state based on the evaluation output line including the first precharge state and a second output logic state based on the evaluation output line including the discharged state, at a column output circuit. [Brief explanation of the drawings]

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] [Figure 1] FIG. 1 is a schematic diagram of a memory array circuit including a bit cell column circuit including a plurality of memory bit cell circuits, each bit cell circuit column including a column read circuit configured to generate a column output signal indicative of a logic state stored in one of the memory bit cell circuits during a read operation. [Figure 2] FIG. 1 is a schematic diagram illustrating features of a column of bit cell circuits in a conventional memory array circuit, including a column read circuit coupled to a first read bit line coupled to the read port circuits of memory bit cell circuits in a first plurality of memory bit cell circuits and a second read bit line coupled to the read port circuits of memory bit cell circuits in a second plurality of memory bit cell circuits. [Figure 3]3 is a timing diagram illustrating control and data signals within the conventional memory array circuit of FIG. 2 during a read operation. [Figure 4A] FIG. 1 is a schematic diagram illustrating an exemplary memory system including features of a bit cell column circuit, including a read control circuit configured to selectively couple a first read bit line to a column read circuit during a read operation for one of a first plurality of memory bit cell circuits. [Figure 4B] FIG. 4B is a schematic diagram illustrating the example memory system of FIG. 4A including a bit cell column circuit including a read control circuit configured to selectively couple one of a first read bit line and a second read bit line to the column read circuit in a read operation in response to a read address. [Figure 5A] 4B is a flowchart illustrating a method of a read operation in the example memory array circuit of FIG. 4A. [Figure 5B] 4B is a flowchart illustrating a method of a read operation in the example memory array circuit of FIG. 4A. [Figure 5C] 4B is a flowchart illustrating a method of a read operation in the example memory array circuit of FIG. 4A. [Figure 6] 4B is a timing diagram illustrating control and data signals within the exemplary memory array circuit of FIG. 4A during a read operation. [Figure 7] FIG. 4B is a block diagram of an exemplary processor-based system including a plurality of devices coupled to a system bus, where the processor-based system includes a memory array system including a bit cell column circuit feature including a read control circuit configured to selectively couple a first read bit line to a column read circuit in a read operation for one of a first plurality of memory bit cell circuits, as shown in FIGS. 4A and 4B. DETAILED DESCRIPTION OF THE INVENTION

[0011] Exemplary aspects disclosed herein include a memory system including a memory array that uses a column readout circuit to control the floating of column readout bitlines. Related methods for performing read operations in memory arrays that use a column readout circuit to control the floating of column readout bitlines are also disclosed. The memory system includes one or more bitcell columns, each bitcell column including a plurality of memory bitcells (e.g., static random access memory (SRAM) bitcells), each storing a logic state. The logic state stored in a selected one of the memory bitcells can control a read port circuit within the memory bitcell to determine the logic state generated on the read bitline. The read port circuit includes a read port output, and the read port outputs of multiple memory bitcells in the same column are coupled to the read bitline. The memory system includes a column readout circuit for evaluating the logic state at the read port output of a selected memory bitcell. The column readout circuit includes an evaluate output line coupled to the readout port circuit by the read bitline in a dynamic readout circuit configuration. The column readout circuit also includes a precharge circuit that is activated to precharge the evaluate output line during an idle phase and a precharge phase of a read operation. The column read circuit includes a float control circuit coupled in-line between the evaluation output line and the read bit line. The memory system includes a read control circuit for controlling activation and deactivation of the float control circuit. During idle phases between read operations, the float control circuit is deactivated to decouple the evaluation output line from the read bit line and the read port circuit while the evaluation output line is precharged by the precharge circuit. In other words, the read bit line and the read port output of the read port circuit are kept floating during the idle phase, so that the precharge circuit precharges only the evaluation output line, which reduces power consumption caused by leakage current by the read port circuit.Because there are multiple memory bitcells in a column, each containing a read port circuit, power loss due to leakage would be much higher if the evaluate output line were coupled to the read bitline during the idle phase. During the precharge phase of a read operation, prior to the evaluate phase of the read operation, a float control circuit is activated to couple the evaluate output line to the read bitline and the read port circuit, briefly precharging the dynamic read circuit for evaluation. A voltage drop across the float control circuit pulls the read bitline and read port output to a voltage lower than the power supply voltage, saving power and reducing charging time. The precharge circuit is deactivated during the evaluate phase of the read operation, and the read port circuit of the selected memory bitcell is activated to provide an evaluation of the stored logic state to the evaluate output line. The read wordline (RWL) coupled to the selected memory bitcell activates the read port circuit during the evaluate phase, and the stored logic state controls the read port circuit to indicate the stored logic state on the evaluate output line. The read port circuit can be two stacked transistors controlled by RWL and the stored logic state, respectively, to precharge or discharge the read bit line based on the logic state stored in the memory bit cell. After the read operation, the float control circuit is deactivated in the idle phase.

[0012] The performance of a memory system during a memory read operation can be improved by reducing the number of memory bit cells to which a read bit line is coupled in a column. In this way, both the length of the read bit line and the number of capacitive loads can be reduced. To this end, the memory bit cells in each column can be divided into multiple (e.g., two or more) read bit lines, each coupled to an evaluate output line via a corresponding float control circuit. During a read operation, since only one memory bit cell in a column can be read, only the float control circuit of the read bit line coupled to the selected memory bit cell is activated, while all other float control circuits remain inactive to reduce power dissipation.

[0013] FIG. 1 is a schematic diagram of a memory array circuit 100 including bit cell column circuits (“column circuits”) 102, each including a plurality of memory bit cell circuits 104. Each of the column circuits 102 includes a column readout circuit 106 configured to generate a column output signal 108 corresponding to a logic state stored in one of the memory bit cell circuits 104 during a read operation. A first read bit line 110 is coupled to each of a first plurality of memory bit cell circuits 112 of the plurality of memory bit cell circuits 104. A second read bit line 114 is coupled to each of a second plurality of memory bit cell circuits 116 of the plurality of memory bit cell circuits 104. The column readout circuit 106 is coupled to both the first read bit line 110 and the second read bit line 114. A read word line RWL for each row (not shown) of the memory array circuit 100 is coupled to each of the memory bit cell circuits 104 of the corresponding row. The read word line RWL is activated in a selected one of the rows to be read during a read operation. In each column circuit 102, the column read circuit 106 is configured to read the logic state of a selected one of the plurality of memory bitcell circuits 116, which may be one of the first plurality of memory bitcell circuits 112 and the second plurality of memory bitcell circuits 104, depending on the selected row. Read word lines RWL(0) through RWL(M) are coupled to the first plurality of memory bitcell circuits 112, and read word lines RWL(M+1) through RWL(N) are coupled to the second plurality of memory bitcell circuits 116. Each column circuit 102 may include, for example, 64 memory bitcell circuits 104, with each of the first plurality of memory bitcell circuits 112 and the second plurality of memory bitcell circuits 116 including 32 of the plurality of memory bitcell circuits 104 (e.g., M=31 and N=63). The plurality of memory bit cells 104 may be divided into a first plurality of memory bit cells 112 and a second plurality of memory bit cells 116 to improve performance of read operations in the memory array circuit 100 .In this regard, the first read bit line 110 and the second read bit line 114 may have lower capacitance than a single read bit line due to their shorter length and fewer loads. In other examples, the memory array circuit 100 may include any number of column circuits 102. Each of the column circuits 102 may include one or more read bit lines coupled to any number of memory bit cell circuits 104. The memory array circuit 100 of FIG. 1 may be a conventional memory circuit including conventional column circuits such as those shown in FIG. 2. Alternatively, the memory array circuit 100 of FIG. 1 may be an exemplary memory array circuit including exemplary column circuits such as those shown in FIGS. 4A and 4B and disclosed herein.

[0014] 2 is a schematic diagram illustrating features of a bit cell column circuit ("column circuit") 200 used in a conventional memory array circuit 202 corresponding to the memory array circuit 100 of FIG. 1. The conventional memory array circuit 202 including the conventional bit cell column circuit 200 is first presented to provide a background for understanding the exemplary aspects disclosed herein. The illustrated features of the column circuit 200 are used to perform a read operation of memory bit cell circuits 204 in any row (not shown) of the memory array circuit 202 in the column circuit 200. Before describing the read operation, the illustrated features will first be described.

[0015] Column circuit 200 includes a column read circuit 206 coupled to a first read bit line 208 and a second read bit line 210. The first read bit line 208 is further coupled to a first read port circuit 212 in each of a first plurality of memory bit cell circuits 214, as shown in FIG. 1. The second read bit line 210 may be coupled to a second read port circuit 216 of a second plurality of memory bit cell circuits 218 of column circuit 200.

[0016] The column readout circuit 206 includes pull-up circuits 224(1) and 224(2) coupled to the first read bit line 208 and the second read bit line 210, respectively. The column circuit 200 also includes a read control circuit 222 coupled to the pull-up circuits 224(1) and 224(2). The read control circuit 222 generates pull-up signals 220(1) and 220(2) that control the pull-up circuits 224(1) and 224(2), respectively, in the column readout circuit 206. The pull-up signals 220(1) and 220(2) turn on the pull-up circuits 224(1) and 224(2) to pull the first read bit line 208 and the second read bit line 210 to a supply voltage rail 226 (e.g., V DD ), and the periods between read operations are sometimes referred to as idle phases. Pull-up circuits 224(1) and 224(2) are conductive when turned on. When pull-up circuits 224(1) and 224(2) are turned on, supply voltage rail 226 is electrically coupled to supply voltage V SUP Based on this, the first read bit line 208 and the second read bit line 210 are set to a voltage V CHG The column readout circuit 206 also includes keep-up circuits 228(1) and 228(2) configured to selectively couple the first read bit line 208 and the second read bit line 210, respectively, to the supply voltage rail 226 during a read operation.

[0017] Each of the memory bitcell circuits 204 stores a logic state of data (e.g., a "bit" of binary data) as either a high or low voltage level on a data node. Each of the memory bitcell circuits 204 also stores the logical complement of the logic state on the data node on a complement data node. For example, a binary "0" is represented by a logic "0" at ground voltage V SS and a binary "1" is a first logic state that can be stored as a low voltage level corresponding to a supply voltage V DD A logic state "1" on a data node in one of the memory bit cell circuits 204 corresponds to a complement logic state "0" on the complementary data node. A logic state "0" stored on a data node corresponds to a complement logic state "1" on the complementary data node.

[0018] Read port circuits 212 and 216 are used within memory bit cell circuit 204 to generate the logic state of the data stored on read bit lines 208 and 210. In one example, read port circuits 212 and 216 are "stacked" or connected to a first read bit line 208 and a ground voltage (e.g., V SS ) and a ground voltage rail 234 that supplies a voltage on the first read bit line 208. Transistors 230(1) and 232(1) can be "turned on" to allow current to flow in response to voltages on their gates 236 and 238, respectively. When both transistors 230(1) and 232(1) are turned on, charge on the first read bit line 208 can be discharged to the ground voltage rail 234. The gate 236 of transistor 230(1) is controlled by a read word line signal RWL. The gate 238 of transistor 232(1) is coupled to a complementary data node (not shown) of the memory bit cell circuit.

[0019] The column read circuit 206 drives both the first read bit line 208 and the second read bit line 210 to a high voltage level (e.g., supply voltage V DD ) only when the SS 224(1) and 224(2) . Column output signal 242 is generated at a high voltage state when either input of first read bit line 208 or second read bit line 210 is in a low voltage state and the other input remains precharged (e.g., in a high voltage state). Column output signal 242 is thus based on one of first read bit line 208 or second read bit line 210 being pulled up by a corresponding one of pull-up circuits 224(1) and 224(2) and the voltage state of the other of first read bit line 208 or second read bit line 210 (based on the logic state stored thereon).

[0020] The column read circuit 206, read control circuit 222, and first and second read bit lines 208 and 210 are inactive during an idle phase between read operations. During the idle phase, the read control circuit 222 controls the pull-up circuits 224(1) and 224(2) to keep the first and second read bit lines 208 and 210 charged to a precharged state, keeping the column circuit 200 ready for a read operation, as described below. During the idle phase, the keep-up circuits 228(1) and 228(2) are turned off.

[0021] A read operation of one of the memory bitcell circuits 204 in the first plurality of memory bitcell circuits 214 in the column circuit 200 will be described as an example. A read operation in the memory array circuit 202 reads data stored in the memory bitcell circuits 204 in a selected row (not shown) of the memory array circuit 202. Thus, the read operation reads data stored in one of the memory bitcell circuits 204 in the column circuit 200. As shown in the timing diagram of FIG. 3 below, the read enable signal RDEN received by the read control circuit 222 transitions to an active state to indicate a read operation. While the read enable signal RDEN is in an active state, the system clock signal CLK (see FIG. 3) transitions to a first clock state, triggering the read control circuit 222 to shut off the pull-up circuits 224(1) and 224(2). Disconnecting pull-up circuits 224(1) and 224(2) isolates first read bit line 208 and second read bit line 210 from supply voltage rail 226 while first read bit line 208 and second read bit line 210 are in a precharged state. First read bit line 208 and second read bit line 210 can be discharged by leakage current in first read port circuit 212 and second read port circuit 216 within first plurality of memory bit cell circuits 214 and second plurality of memory bit cell circuits 218. Keep-up circuits 228(1) and 228(2) are turned on during read operations to selectively prevent first read bit line 208 and second read bit line 210 from being discharged by leakage current.

[0022] The transition of system clock signal CLK to the first clock state also activates the read word line signal RWL for the selected row (e.g., to a high voltage), turning on transistor 232(1) in first read port circuit 212 and preparing to generate the logic state of the stored data on column output signal 242. As an example, if the binary data state stored in the selected one of the first plurality of memory bit cell circuits 214 corresponds to a high voltage (e.g., "1"), the complementary data node is at a low voltage. Thus, in this example, transistor 230(1) coupled to the complementary data node is not turned on, and first read bit line 208 is not discharged from its precharge state. Alternatively, if the logic state of the data stored in the selected one of the first plurality of memory bit cell circuits 214 corresponds to a low voltage state (e.g., "0") and the complementary data node is at a high voltage, as shown in FIG. 3, transistor 230(1) is turned on, and first read bit line 208 is discharged to the ground voltage (e.g., V SS ) to discharge state.

[0023] In other words, in an example where the logic state of the data stored in a selected one of the first plurality of memory bit cell circuits 214 is low (“0”), the first read bit line 208 is driven to the supply voltage of the supply voltage rail 226 (e.g., V DD ), the second read bit line 210 is in a precharged state based on the second read bit line 210 being pulled up to a high voltage state by pull-up circuit 224(2), so that the NAND function of column output circuit 240 (described above) generates column output signal 242 in a low voltage state (“0”), which in this example corresponds to the logic state of the data stored in the selected one of the first plurality of memory bit cell circuits 214.

[0024] In another example, if the logic state of the data stored in the selected one of the first plurality of memory bit cell circuits 214 is high (“1”), the first read bit line 208 is discharged to a low voltage (“0”) state and the NAND function of the column output circuit 240 (described above) transitions the column output signal 242 to a high state (“1”). In this manner, the logic state of the column output signal 242 corresponds to the logic state of the data stored in the selected one of the first plurality of memory bit cell circuits 214.

[0025] Keep-up circuits 228(1) and 228(2) are turned on during a read operation to prevent the first read bit line 208 and the second read bit line 210 from slowly discharging due to leakage current in the first read port circuit 212 and the second read port circuit 216, respectively. Allowing the first read bit line 208 and the second read bit line 210 to discharge changes the column output signal 242. Keep-up circuit 228(1) includes transistors 244(1) and 246(1), and keep-up circuit 228(2) includes transistors 244(2) and 246(2). Transistors 244(1), 244(2), 246(1), and 246(2) in this example are turned on and become conductive by signals in a low voltage state. The read control circuit 222, which turns on the keep-up circuits 228(1) and 228(2), includes providing a control signal 248 at a low voltage to transistors 246(1) and 246(2). The column output signal 242 is coupled to transistors 244(1) and 244(2) and is therefore controlled by the voltage state of the column output signal 242. At the start of a read operation, the pull-up circuits 224(1), 224(2) are cut off and the first and second read bit lines 208, 210 are fully charged before the read word line signal RWL is activated. Providing a high voltage to the column output circuit 240 generates a low voltage on the column output signal 242 based on the NAND function of the column output circuit 240. The low voltage state of column output signal 242 turns on transistors 244(1) and 244(2) in keep-up circuits 228(1) and 228(2), which keeps first and second read bit lines 208 and 210 coupled to supply voltage rail 226. With transistors 244(1) and 244(2) turned on, first read bit line 208 remains charged in a precharged (high voltage) state. Second read bit line 210 likewise remains charged.

[0026] As described above, in a read operation, the logic state of the data stored in the plurality of memory bitcell circuits 204 is generated in column output signal 242 in response to read word line signal RWL. If the logic state of the stored data corresponds to a low voltage state, column output signal 242 remains at a low voltage in response to read word line signal RWL, which keeps transistors 244(1) and 244(2) in keep-up circuits 228(1) and 228(2) turned on and continues to charge first and second read bitlines 208 and 210. On the other hand, if the logic state of the data stored in a selected one of the first plurality of memory bitcell circuits 214 is high, the first read bitline 208 is discharged and the state of column output signal 242 becomes high, which turns off transistors 244(1) and 244(2). Therefore, keep-up circuits 228(1) and 228(2) do not continue to supply charge to first and second read bit lines 208 and 210, which are discharged by first and second read port circuits 212 and 216. Column output signal 242 remains in a low voltage state until the read operation is complete. System clock signal CLK transitions back to the second clock state, indicating the end of the read operation and indicating an idle phase. Regardless of the logic state of the data stored in the selected one of the first plurality of memory bit cell circuits 214, once the read operation is complete, keep-up circuits 228(1) and 228(2) are turned off (i.e., transistors 246(1) and 246(2) are turned off) and pull-up circuits 224(1) and 224(2) are turned on, preparing column circuit 200 for another read operation. In response to the idle phase indication, pull-up circuits 224(1) and 224(2) are turned on again to precharge the first and second read bit lines 208 and 210 in preparation for the next read operation.

[0027] FIG. 3 is a timing diagram illustrating signals in the conventional memory array circuit 202 of FIG. 2 during a read operation, as described above. The start of a read operation is indicated by the transition of the read enable signal RDEN to an active state at time T1. The read enable signal RDEN may be provided to the column circuit 200 by, for example, a memory controller or processor. When the read enable signal RDEN is active, pull-up circuits 224(1) and 224(2) are turned off in response to a transition of the system clock signal CLK to a first clock state, as shown at time T2. In FIG. 3, the first clock state corresponds to a high voltage state, but could alternatively correspond to a low voltage state. At time T3, in response to the transition of the system clock signal CLK to the first clock state at time T2, the read word line signal RWL is activated, turning on transistor 232(1) of the first read port circuit 212 of the selected row of the first plurality of memory bitcell circuits 214. Pull-up circuits 224(1) and 224(2) are turned off and keep-up circuits 228(1) and 228(2) are turned on at time T3 in Figure 3. The signals of keep-up circuits 228(1) and 228(2) are not shown in Figure 3.

[0028] 3 illustrates an example of a read operation in which the logic state of the complementary data stored in the memory bit cell circuit corresponds to a high voltage state. With the complementary data node coupled to gate 236, the high voltage state stored on the complementary data node turns on transistor 230(1), discharging the first read bit line 208 to a discharged state (low voltage state). Because the memory bit cell circuit being read is not coupled to the second read bit line 210, the second read bit line 210 remains pulled up to a high voltage state. A low voltage state on the first read bit line 208, coupled to column output circuit 240, transitions column output signal 242 to a high voltage state at time T4. In response to the system clock signal CLK transitioning to the second clock state at time T5, the read word line signal RWL is deactivated and pull-up circuits 224(1) and 224(2) are again turned on and begin providing charge to the first and second read bit lines 208 and 210 at time T6 in preparation for another read operation.

[0029] FIG. 4A is a schematic diagram illustrating features of a memory system 400 including one or more bitcell column circuits 402 (“column circuit 402”), each including a plurality of memory bitcell circuits 404 (“memory bitcells 404”) (e.g., SRAM bitcells), each storing a logic state of data. The logic state stored in a selected one of the memory bitcells 404 can control a read port circuit 408 in that memory bitcell 404 to determine the logic state generated on a read bit line 406. The read port circuit 408 includes a read port output 410, and the read port outputs 410 of multiple memory bitcells 404 in the same column 412 are coupled to the read bit line 406. The memory system 400 includes a column read circuit 414 for evaluating the logic state on the read port output 410 of the selected memory bitcell 404. The column read circuit 414 includes an evaluation output line 416 that is coupled to the read port circuit 408 by the read bit line 406 in a dynamic read circuit configuration. The column read circuit 414 also includes a precharge circuit 418 that is activated to precharge the evaluation output line 416 during idle phases between read operations and during a precharge phase of a read operation. The column read circuit 414 includes a float control circuit 420 that is coupled in-line between the evaluation output line 416 and the read bit line 406. The memory system 400 includes a read control circuit 422 for controlling the activation and deactivation of the float control circuit 420. During idle phases between read operations, while the evaluation output line 416 is precharged by the precharge circuit 418, the float control circuit 420 is deactivated, decoupling the evaluation output line 416 from the read bit line 406 and the read port circuit 408.

[0030] In other words, the read bit lines 406 and the read port outputs 410 of the read port circuitry 408 are kept floating during the idle phase so that the precharge circuitry 418 precharges only the evaluate output lines 416, which reduces power consumption that may be caused by leakage current through the read port circuitry 408. As used herein, the terms "floating" or "floating state" refer to the state in which the read bit lines 406 and the read port outputs 410 are kept floating above a supply voltage (e.g., V DD ), ground voltage (e.g., V SS ) or any intermediate voltage between the supply voltage and ground. Thus, a node that is floating will not charge or will discharge quickly, but leakage current can slowly discharge a node that is charged when floating. Because there are multiple memory bit cells 404 in a column 412, and each memory bit cell 404 includes a read port circuit 408, power loss due to leakage will be much higher if the evaluate output line 416 is coupled to the read bit line 406 during the idle phase. During the precharge phase of a read operation, before the evaluate phase of the read operation, a float control circuit 420 is activated to couple the evaluate output line 416 to the read bit line 406 and the read port circuit 408, briefly precharging the dynamic read circuit for evaluation. The voltage drop across the float control circuit 420 causes the read bit line 406 and the read port output 410 to be pulled to the power supply voltage (e.g., V DD ) lower voltage V CHGThe read bit line 406 is pulled up (“charged”) to the logic high potential, which conserves power and reduces the time required to charge the read bit line 406. During the evaluation phase of a read operation, the precharge circuit 418 is deactivated and the read port circuit 408 of the selected memory bit cell 404 is activated to provide an evaluation of the stored logic state on the evaluation output line 416. A read word line 424 coupled to the selected memory bit cell 404 provides a read word line signal RWL that activates the read port circuit 408 during the evaluation phase. The stored logic state in the selected memory bit cell 404 controls the read port circuit 408 to indicate the stored logic state on the evaluation output line 416. The read port circuit may be two stacked transistors 426 and 428 controlled by the read word line signal RWL and the stored logic state, respectively, to precharge or discharge the read bit line 406 based on the logic state stored in the memory bit cell 404. After the read operation, the float control circuit 420 is deactivated during the idle phase.

[0031] The column readout circuit 414 includes a column output circuit 430 configured to generate a column output signal 432 based on the logic state (i.e., voltage level) of the evaluation output line 416. The column output circuit 430 generates the column output signal 432 based on whether the evaluation output line 416 is in a first precharge state or a discharge state. The column output circuit 430 may be an inverter circuit that generates the column output signal 432 having a logic state complementary to the logic state of the evaluation output line 416. In another example, the column output circuit 430 may be a buffer circuit that passes the same logic state from the evaluation output line 416 to the column output signal 432. The column output circuit 430 may be determined based on the desired polarity of the logic state on the column output signal 432 compared to the logic state of the data stored in the selected one of the memory bit cell circuits 404.

[0032] The memory system 400 includes at least one column circuit 402, with each column 412 including a plurality of memory bit cell circuits 404. The memory system 400 may be, for example, a memory array circuit or a register file circuit. A read bit line 406 is coupled to a first plurality 434 of the memory bit cell circuits 404. A column read circuit 414 and a read control circuit 422 are included in each of the at least one column circuit 402 and are used in a read operation to read the logic state of data stored in a selected row (not shown) of the first plurality 434 of memory bit cell circuits 404 in the memory system 400.

[0033] The column readout circuit 414 includes a precharge circuit 418 configured to precharge the evaluate output line 416 at the beginning of a readout operation. Precharging the evaluate output line 416 may involve, for example, precharging the evaluate output line 416 with a supply voltage V DD The evaluation output line 416 may include coupling the evaluation output line 416 to a supply voltage rail 436 that provides a supply voltage V DD Based on the voltage V PRE The voltage drop across the precharge circuit 418 causes the voltage V PRE is the supply voltage V DD The precharge circuit 418 may be a transistor such as a P-type field effect transistor (FET) (PFET). In this regard, the precharge circuit 418 may be "turned on" and become conductive in response to receiving a precharge signal 438 in an active state that is a low voltage state (e.g., 0 volts) to turn on the PFET. If the precharge circuit 418 includes an N-type FET (NFET), the active state of the precharge signal 438 may be a high voltage state (e.g., V DD A PFET is a transistor in which the semiconductor (e.g., silicon) is doped with trivalent impurities, while an NFET contains a semiconductor doped with pentavalent impurities.

[0034] The read control circuit 422 is configured to generate a precharge signal 438 in an active state in response to receiving an indication of an idle phase in the memory system 400. The read control circuit 422 is also configured to generate a precharge signal 438 in an active state in response to receiving an indication of a precharge phase of a read operation in the memory system 400. The read control circuit 422 is configured to generate a precharge signal 438 (e.g., a high voltage signal for the precharge circuit 418, which includes a PFET) in an inactive state in response to receiving an indication of an evaluate phase of a read operation in the memory system 400. The precharge phase, evaluate phase, and idle phase are described below.

[0035] At the end of a read operation, an indication of the idle phase is received at the read control circuit 422, and the memory system 400 remains in the idle phase until the read control circuit 422 receives an indication of the precharge phase of another read operation. The indication of the precharge phase, the evaluate phase, and the idle phase is based on receiving the read enable signal RDEN and the system clock signal CLK. The indication of the precharge phase may include receiving a transition of the read enable signal RDEN from an inactive state to an active state, indicating that the memory system 400 is enabled for a read operation.

[0036] In response to receiving the precharge phase indication, the read control circuit generates a float control signal 440 in an active state to turn on the float control circuit 420. The float control circuit 420 is coupled between the read bit line 406 and the evaluate output line 416. The float control circuit 420 is configured to couple the read bit line 406 to the evaluate output line 416 during the precharge phase. During the precharge phase, the precharge circuit 418 charges the read bit line 406 during the precharge phase prior to the evaluate phase, since the evaluate output line 416 is coupled to the read bit line 406 through the float control circuit 420. The read bit line 406 is driven to the voltage V PRE Based on the voltage V CHG The voltage V of the read bit line 406 in the second precharge state CHG is the voltage V on the evaluation output line 416 in the first precharge state due to the voltage drop across the float control circuit 420. PRE The read bit line 406 is connected to a low voltage V CHG Because the read bit line 406 is charged to V, it can charge more quickly than if it were directly connected to the evaluate output line 416 without the float control circuit 420. Additionally, in the first precharge state, the voltage V of the evaluate output line 416 PRE Instead, for a read operation, the read bit line 406 is driven to a low voltage V CHG The read bit lines 406 are coupled to the read port outputs 410 of all of the first plurality 434 of memory bit cell circuits 404. Thus, the read port outputs 410 are also coupled to the low voltage V during the precharge phase. CHGThe read port circuit 408 includes transistors 426 and 428. The read port circuit 408 in a selected one of the first plurality 434 of memory bit cell circuits 404 can be activated by a corresponding read word line signal RWL. The read word line signal RWL remains inactive during the precharge phase, preventing the read port circuit 408 from turning on. The read bit line 406 is charged during the precharge phase regardless of any leakage current that may flow through the read port circuit 408.

[0037] The precharge phase ends when the read control circuit 422 receives an indication of an evaluate phase. Receiving an indication of an evaluate phase of a read operation in the read control circuit 422 includes receiving a read enable signal RDEN in an active state and receiving a transition of the system clock signal CLK from the second clock state to the first clock state. The read control circuit 422 causes the float control circuit 420 to couple the evaluate output line 416 to the read bit line 406 during the precharge and evaluate phases of the read operation. The column read circuit 414 is configured to evaluate the stored logic state of a selected one of the first plurality 434 of memory bit cell circuits 404 on the evaluate output line 416 during the evaluate phase. The evaluate phase of the read operation begins when the read bit line 406 is coupled to a voltage V CHGThe evaluation phase begins after the precharge phase in which the evaluation output lines 416 are precharged to a second precharge state at 0 V. The read control circuit 422 is further configured, in response to receiving an indication of the evaluation phase, to generate a precharge signal 438 in an inactive state to turn off the precharge circuit 418 and isolate the evaluation output lines 416 from the supply voltage rail 436. Additionally, in response to receiving an indication of the evaluation phase, the read control circuit 422 continues to generate a float control signal 440 in an active state to keep the float control circuit 420 turned on and continue to couple the evaluation output lines 416 to the read bit lines 406. Thus, during the evaluation phase, the precharge circuit 418 is no longer charging the evaluation output lines 416 and the read bit lines 406. The column read circuit also includes keep-up circuits 442 to prevent the evaluation output lines 416 and the read bit lines 406 from slowly discharging due to leakage current through the read port circuits 408 of the first plurality 434 of memory bit cell circuits 404. The keep-up circuit 442 continues to charge the evaluation output line 416 as long as the column output signal 432 is in a low voltage state. That is, during the precharge phase, the evaluation output line 416 is charged to a first precharge state, causing the column output circuit 430 to generate the column output signal 432 in a low voltage state. The keep-up circuit 442 continues to charge the evaluation output line 416 faster than it can be discharged by the read output circuit 408 within the first plurality 434 of memory bitcell circuits 404. During the evaluation phase, the read bitline 406 may remain charged or may be discharged by the read port circuit 408 depending on the logic state of the data stored in a selected one of the first plurality 434 of memory bitcell circuits 404.

[0038] The read port circuitry 408 includes transistors 426 and 428, which are connected between the read bit line 406 and a ground voltage rail 444, e.g., a low voltage or ground voltage V SS(e.g., 0 volts). When both transistors 426 and 428 are turned on, the read bit line 406 may be coupled to a ground voltage rail 444. During the evaluation phase, coupling the read bit line 406 to the ground voltage rail 444 discharges the read bit line 406 to a discharged state based on the ground voltage, as follows:

[0039] Transistor 426 is coupled between the read port output 410 (which is coupled to the read bit line 406) and transistor 428. Transistor 426 is also coupled to a read word line 424 and is controlled by a read word line signal RWL. The read word line signal RWL is received by an active read port circuit 408 in a selected one of the first plurality 434 of memory bit cell circuits 404. The selected one of the memory bit cell circuits 404 is in a row of the memory system 400 targeted by a read address to be read in a read operation. Transistor 428 is coupled between transistor 426 and a ground voltage rail 444. Transistor 428 is coupled to a data node (not shown) of the memory bit cell circuit 404. The transistor is controlled by the logic state of the stored data, which is indicated by the voltage level of the data node. The data node coupled to transistor 428 can be a data node that stores a “true” logic state or a complementary data node that stores a “complementary” logic state. In some examples, transistor 428 may be an NFET that is activated by a first logic state corresponding to a high voltage level. Thus, when a read word line signal RWL is received in an active state and a high voltage state is stored on the data node coupled to transistor 428, read port circuitry 408 is turned on and becomes conductive, allowing read bit line 406 to discharge to the ground voltage rail 444. In response to receiving read word line signal RWL in an active state and corresponding to a high voltage, read port circuitry 408 is activated. In other words, in response to receiving read word line signal RWL in an active state and the logic state of the data stored on the data node comprising a first logic state (e.g., corresponding to a high voltage on the data node), read port circuitry 408 couples read bit line 406 to the ground voltage rail 444 and discharges evaluate output line 416 to a discharged state.Alternatively, in response to the read word line signal RWL in an active state and the logic state of the data stored on the data node including a second logic state (e.g., corresponding to a low voltage stored on the data node), the read port circuit 408 isolates the read bit line 406 from the ground voltage rail 444 and maintains the evaluate output line 416 in a first precharge state. In this situation, when the read port circuit 408 discharges the read bit line 406 and the evaluate output line 416, the evaluate output line 416 is discharged faster than it is charged by the keep-up circuit 442. As a result, the column output signal 432 transitions to a high voltage state based on the evaluate output line 416 being in the discharged state, and the keep-up circuit 442 is turned off, isolating the evaluate output line 416 from the supply voltage rail. In another example, the transistor 428 can be implemented by a PFET that responds to a logic state corresponding to a low voltage level. In this example, the voltage levels corresponding to the first and second logic states are reversed.

[0040] The logic state stored in a selected one of the memory bit cell circuits 404 is generated as a column output signal 432 during a read operation. The read operation ends when the read control circuit 422 receives an idle phase indication. The read control circuit 422 causes the float control circuit 420 to isolate the evaluate output line 416 from the read bit line 406 during the idle phase. Receiving the idle phase indication also includes the read control circuit 422 receiving a read enable signal RDEN in an inactive state and receiving a transition of the system clock signal CLK to a second clock state. The first and second clock states of the system clock signal CLK may correspond, for example, to high and low voltage states, respectively, or to low and high voltage states, respectively.

[0041] In response to receiving the idle phase indication, the read control circuit 422 generates a float control signal 440 in an inactive state, which turns off the float control circuit 420 and, in the idle phase, decouples the evaluate output line 416 from the read bit line 406. Additionally, in response to receiving the idle phase indication, the read control circuit 422 generates a precharge signal 438 to precharge the evaluate output line 416 to a first precharge state in preparation for the next read operation.

[0042] 4B is a schematic diagram illustrating the example memory system 400 of FIG. 4A including a bit cell column circuit 402 that includes a column read circuit 414 coupled to the first read bit line 406 shown in FIG. 4A and also coupled to a second read bit line 446. The first read bit line 406 is coupled to a first plurality 434 of memory bit cell circuits 404. The second read bit line 446 is coupled to a second plurality 448 of the memory bit cell circuits 404 in the memory system 400.

[0043] The performance of the memory system 400 during memory read operations may be improved by reducing the number of memory bit cells 404 to which read bit lines 406 are coupled in the column circuits 402. The length of the read bit lines 406 and the number of capacitive loads (e.g., read port outputs 410) may be reduced compared to coupling all memory bit cell circuits 404 in a column 412 to a first read bit line 406. To this end, the memory bit cell circuits 404 in each column 412 may be divided into multiple (e.g., two or more) read bit lines, such as a first read bit line 406 and a second read bit line 446. The first read bit line 406 is coupled to an evaluate output line 416 via a float control circuit 420, and the second read bit line 446 is coupled to the evaluate output line 416 via a second float control circuit 450. In a read operation, only one of the memory bit cell circuits 404 in the column 412 can be read, so only one of the float control circuits 420 and 450 is activated at a time, while the other float control circuit remains inactive to reduce power dissipation.

[0044] The memory system 400 may include a memory array circuit including a first bank and a second bank (not shown). In some examples, the memory system 400 may include a plurality of column circuits 402, each including, for example, 64 memory bitcell circuits 404 (0:63), where a first plurality 434 of memory bitcell circuits 404 may include memory bitcell circuits (0:31) in the column circuit 402 and a second plurality 448 of memory bitcell circuits 404 may include memory bitcell circuits (32:63). The column circuit 402 may include any number of memory bitcell circuits 404, and the first plurality 434 of memory bitcell circuits 404 may include a different number of memory bitcell circuits 404 than the second plurality 448 of memory bitcell circuits 404. The memory bitcell circuit 404 may be an SRAM bitcell circuit, such as a six-transistor (6T), eight-transistor (8T), and / or ten-transistor (10T) SRAM bitcell circuit, although the exemplary column circuit 402 may be used in a memory array circuit 402 that includes any type of memory bitcell circuit that stores the logic state of a "bit" of binary data corresponding to either a high voltage state or a low voltage state. For example, a binary "0" is represented by a "0" at a ground voltage V SS and a binary "1" may be stored on a data node configured to store data as a low voltage state corresponding to a supply voltage V DD In some examples, a binary "0" is represented by a high voltage and a binary "1" is represented by a low voltage. Stored data having a logic state "1" on a data node corresponds to a complementary logic state "0" on the complementary data node, and a stored logic state "0" on a data node corresponds to a complementary logic state "1" on the complementary data node.

[0045] In some examples, the first plurality 434 of memory bitcell circuits 404 may be in a first bank (not shown) of the memory system 400, and the second plurality 448 of memory bitcell circuits 404 may be in a second bank (not shown) of the memory system 400. Alternatively, the first plurality 434 and the second plurality 448 of memory bitcell circuits 404 may both be in the same column 412 in the first bank of the memory system, and at least one additional read bitline (not shown) may be coupled to the evaluate output line 416 and to a third plurality of memory bitcell circuits 404 of the memory system 400 in the second bank. The read control circuit 422 of FIG. 4B is configured to control the column read circuit 414 to selectively couple one of the first read bitline 406 and the second read bitline 446 to the evaluate output line 416 during a read operation based on indications of a read address. The read control circuit 422 may be configured to control any number of float control circuits, each corresponding to a read bit line coupled to a plurality of memory bit cell circuits 404 in the column 412. The read control circuit 422 couples the first read bit line 406 to the evaluation output line 416 when the row selected for the read operation based on the read address includes one of the first plurality 434 of memory bit cell circuits 404. The read control circuit 422 is configured to couple the second read bit line 446 to the evaluation output line 416 when the row selected for the read operation based on the read address includes one of the second plurality 338 of memory bit cell circuits 404. One of the first read bit line 406 and the second read bit line 446 is coupled to the evaluation output line 416, while the other of the first read bit line 406 and the second read bit line 444 (and others, if any) remains electrically isolated from the evaluation output line 416. Thus, the evaluation output line 416 is charged or discharged based on only one of the first read bit line 406 and the second read bit line 446, and the column output circuit 430 is electrically coupled to only one of the first read bit line 406 and the second read bit line 446 at a time.

[0046] A second read bit line 446 coupled to a second plurality 448 of memory bit cells 404 in memory system 400 performs a read operation in a manner corresponding to the above description of a read operation of one of the first plurality 434 of memory bit cell circuits 404 on first read bit line 406. Any additional read bit lines coupled to memory bit cell circuits 404 in column 412 are also controlled by read control circuit 422 in a read operation as described above with respect to first read bit line 406.

[0047] 4B , the memory system 400 includes a first read bit line 406 coupled to a float control circuit 420. The memory system 400 includes a second read bit line 446 coupled to a second plurality 448 of memory bit cell circuits 404 in the bit cell column circuit 402. The column read circuit 414 further includes a second float control circuit 450 coupled between the evaluate output line 416 and the second read bit line 446. The read control circuit 422 is configured to, in response to an indication that a read operation is directed to one of the first plurality 434 of memory bit cells 404, cause the column read circuit 414 to couple the first read bit line 406 to the evaluate output line 416 during a precharge phase and to couple the first read bit line 406 to the evaluate output line 416 during an evaluation phase of the read operation. The read control circuit 422 is also configured to, in response to an indication that a read operation is directed to one of the second plurality 448 of memory bit cells 404, cause the column read circuit to couple the second read bit line 446 to the evaluation output line 416 during a precharge phase and to couple the second read bit line 446 to the evaluation output line 416 during an evaluation phase of the read operation. In response to the float control circuit 420 coupling the first read bit line 406 to the evaluation output line 416, the column output signal 432 is based on the first read bit line 406 including one of a discharged state and a second precharge state. In response to the float control circuit 420 coupling the second read bit line 446 to the evaluation output line 416, the column output signal 432 is based on the second read bit line 446 including one of a discharged state and a second precharge state.

[0048] The read control circuit 422 is also configured to isolate the first read bit line 406 and the second read bit line 446 (and other read bit lines, if any) from the evaluate output line 416 during idle phases (i.e., between read operations). The read control circuit 422 controls the precharge circuit 418 to recharge the evaluate output line 416 during idle phases in preparation for the next read operation.

[0049] 5A-5C are flowcharts illustrating a method 500 of a read operation in the exemplary memory system of FIG. 4A. The method 500 includes receiving, at a read control circuit 422 in a bitcell column circuit 402 in the memory system 400, an indication of one of an idle phase, a precharge phase of a read operation, and an evaluate phase of a read operation to read the logic state of data stored in a memory bitcell circuit 404 of a plurality of memory bitcell circuits 404 in the bitcell column circuit 402, the bitcell column circuit 402 further including an evaluate output line 416, a float control circuit 420, and a first read bit line 406 coupled to a read port circuit 408 in each of a first plurality 434 of the memory bitcell circuits 404 in the bitcell column circuit 402 (block 502). The method includes controlling, by the read control circuitry 422, the precharge circuitry 418 (block 504), to couple the evaluation output line 416 to the supply voltage rail 436 and charge the evaluation output line 416 to a first precharge state (block 506) in response to an instruction indicating an idle phase, to couple the evaluation output line 416 to the supply voltage rail 436 and charge the evaluation output line 416 to the first precharge state (block 508) in response to an instruction indicating a precharge state of a read operation, and to decouple the evaluation output line 416 from the supply voltage rail 436 in response to an instruction indicating an evaluation phase of a read operation (block 510). The method includes controlling the float control circuit 420 by the read control circuit 422 (block 512) to couple the first read bit line 406 to the evaluation output line 416 in response to an instruction indicating a precharge phase of the read operation (block 514), to couple the first read bit line 406 to the evaluation output line 416 in response to an instruction indicating an evaluation phase of the read operation (block 516), and to decouple the first read bit line 406 from the evaluation output line 416 in response to an instruction indicating an idle phase (block 518).The method includes, in response to an instruction indicating an evaluation phase of the read operation, coupling, by a read port circuit 408 in a selected one of the first plurality 434 of memory bitcell circuits 404, a first read bitline 406 to a ground voltage rail 444 and discharging an evaluation output line 416 to a discharged state based on a first logic state of data stored in the selected one of the first plurality 434 of memory bitcell circuits 404 (block 520). The method includes, in response to an instruction indicating the evaluation phase of the read operation, decoupling, by a read port circuit 408 in one of the first plurality 434 of memory bitcell circuits 404, the first read bitline 406 from the ground voltage rail 444 and maintaining the evaluation output line 416 in a first precharged state based on a second logic state of data stored in one of the first plurality 434 of memory bitcell circuits 404 (block 522). The method includes generating, in response to an indication of an evaluation phase of the read operation, a column output signal 432 in a column output circuit 430 at a first output logic state based on the evaluation output line 416 that includes a first precharge state and at a second output logic state based on the evaluation output line 416 that includes a discharge state (block 524).

[0050] 6 is a timing diagram illustrating control and data signals within the exemplary memory system 400 of FIGS. 4A and 4B during a read operation. Prior to a read operation, the evaluation output line 416 is pulled up to a first precharge state. The first read bit line 406 is floating and may discharge due to leakage current. The read operation begins at time T1 in response to the read enable signal RDEN and the read address ADDR. In response to the read address ADDR and the read enable signal RDEN, the first read bit line 406 is coupled to the evaluation output line 416 and begins charging to the precharge state. The second read bit line 446 continues to float. At time T2, the system clock signal CLK transitions (e.g., rising), which, at time T3, triggers the read control circuit 422 to turn off the precharge circuit 418, stopping charging the evaluate output line 416, and activate the read word line signal RWL, which turns on the transistor 426 on the read port circuit 408. In the read operation of FIG. 6, because the data stored in the memory bit cell circuit 404 is in a high state, the first read bit line 406 is discharged and the evaluate output line 416 transitions to a low state. In response to the evaluate output line 416 transitioning to a low state, the column output signal 432 transitions to a high state at time T4. At time T5, the system clock signal CLK transitions again (e.g., falling edge), causing the read control circuit 422 to begin charging the evaluate output line 416 and turn off the read word line signal RWL. At time T6, the read address ADDR indication may change, which decouples the first read bit line 406 from the evaluate output line 416, leaving the first read bit line 406 floating.

[0051] 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 (e.g., a microprocessor) that includes instruction processing circuitry 704. The processor-based system 700 may be one or more circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 700 includes a processor 702. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. More specifically, the processor 702 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports explicit consumer naming for communicating product values ​​resulting from the execution of producer instructions. The processor 702 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 706 for temporary, fast-access memory storage of instructions accessible by instruction processing circuits 704. Instructions fetched or prefetched from memory, such as main memory 708, via a system bus 710 are stored in instruction cache 706. Data may be stored in a cache memory 712 coupled to system bus 710 for low-latency access by processor 702. Instruction processing circuits 704 are configured to process instructions fetched into instruction cache 706 and to process the instructions for execution.

[0052] The processor 702 and main memory 708 are coupled to a system bus 710, which may interconnect peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information via the system bus 710. For example, the processor 702 may communicate bus transaction requests to a memory controller 714 in the main memory 708, acting as an example of a slave device. Although not shown in FIG. 7, multiple system buses 710 may be provided, each comprising a different fabric. In this example, the memory controller 714 is configured to provide memory access requests to a memory array 716 in the main memory 708. The memory array 716 comprises an array of storage bit cells for storing data. The main memory 708 may be, by way of non-limiting example, a dynamic random access memory (DRAM) such as a read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, SRAM, etc.).

[0053] Other devices may be connected to the system bus 710. As shown in FIG. 7, these devices may include, by way of example, a main memory 708, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input devices 718 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 720 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 722 may be any device configured to enable the exchange of data with a network 726. The network 726 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The modem 722 may be configured to support any type of communication protocol desired. The processor 702 may also be configured to access a display controller 724 via the system bus 710 to control information sent to one or more displays 728. The display 728 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0054] 7 may include a set of instructions 730 that are executed by processor 702 for any desired application in accordance with the instructions. The instructions 730 may be stored in main memory 708, processor 702, and / or instruction cache 706, as examples of non-transitory computer-readable medium 732. The instructions 730 may also reside, completely or at least partially, within main memory 708 and / or processor 702 during execution thereof. The instructions 730 may also be transmitted or received over network 726 via modem 722, such that network 726 includes computer-readable medium 732.

[0055] While the computer-readable medium 732 is shown to be a single medium in the exemplary embodiment, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0056] The processor 702 in the processor-based system 700 may include, in any device therein, an exemplary memory array system including features of a bit cell column circuit including read control circuitry configured to selectively couple a first read bit line to the column read circuitry in a read operation to one of a first plurality of memory bit cell circuits, as illustrated in FIGS. 4A and 4B.

[0057] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0058] Embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), etc.

[0059] Unless otherwise stated, and as is apparent from the foregoing description, throughout the description, descriptions utilizing terms such as "processing," "calculating," "determining," "displaying," etc. will be understood to refer to the operations and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers, or other such information storage, transmission, or display device.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0061] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be implemented in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0062] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0063] The embodiments disclosed herein may be implemented with hardware and instructions stored on the hardware, such as RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0064] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for purposes of example and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in an exemplary embodiment may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0065] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps should be followed, or unless it is specifically stated in the claim or specification that the steps should be limited to a particular order, no particular order is intended to be inferred.

[0066] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

Claims

1. At least one bit cell column circuit, each bit cell column circuit comprising: a plurality of memory bitcell circuits; a read bit line coupled to a first plurality of memory bit cell circuits of the plurality of memory bit cell circuits in a bit cell column circuit of the at least one bit cell column circuit; a column readout circuit, an evaluation output line; a precharge circuit configured to precharge the evaluation output line during an idle phase and a precharge phase of a read operation by coupling the evaluation output line to a supply voltage rail in response to receiving a precharge signal in an active state from a read control circuit; a float control circuit coupled between the read bit line and the evaluation output line, the float control circuit comprising: coupling the read bit line to the evaluation output line during the precharge and evaluation phases of the read operation; disconnecting the read bit lines from the evaluate output lines during the idle phase; The float control circuit is configured as follows: the column readout circuitry being configured to evaluate a stored logic state of a selected one of the first plurality of memory bit cell circuits on the evaluation output line during the evaluation stage; the read control circuit coupled to the float control circuit, generating a float control signal in an active state to turn on the float control circuit in response to receiving an indication of the precharge phase of the read operation and in response to receiving an indication of the evaluate phase of the read operation, thereby causing the float control circuit to couple the evaluate output line to the read bit line in response to the precharge phase and in response to the evaluate phase of the read operation; generating the float control signal in an inactive state to turn off the float control circuit in response to receiving an indication of the idle phase, thereby causing the float control circuit to isolate the evaluate output line from the read bit line in response to the idle phase; generating the precharge signal in the active state in response to receiving an indication of the idle phase and in response to receiving an indication of the precharge phase of the read operation; generating the precharge signal in an inactive state in response to receiving an indication of the evaluation phase of the read operation; the read control circuit configured as follows; a memory system comprising the at least one bit cell column circuit,

2. The precharge circuit being configured to couple the evaluation output line to the supply voltage rail means that the precharge circuit is charging the evaluation output line to a first precharge state including a first voltage; charging the read bit line to a second precharge state including a second voltage lower than the first voltage based on the evaluation output line being charged to the first voltage; 10. The memory system of claim 1, wherein the memory system is configured as follows:

3. Each of the plurality of memory bit cell circuits comprises: a data node configured to store a logical state of the data; a read port circuit including a read port output coupled to the read bit line; wherein the read port circuitry, in response to receiving a read word line (RWL) signal in an active state: in response to the logic state of the data stored at a first data node comprising a first logic state, coupling the read bit line to a ground voltage rail and discharging the evaluate output line to a discharged state; in response to the logic state of the data stored on the first data node comprising a second logic state, isolating the read bit line from the ground voltage rail and maintaining the evaluate output line in a first precharge state; 3. The memory system of claim 2, configured as follows:

4. the column readout circuitry further comprising a column output circuit configured to generate a column output signal based on an evaluation output signal on the evaluation output line, the evaluation output signal being based on whether the evaluation output line is in the first precharge state or the discharge state; 4. The memory system of claim 3.

5. The column readout circuitry further comprises a keep-up circuit coupled to the evaluation output line, the keep-up circuitry during the evaluation phase: coupling the evaluation output line to the supply voltage rail in response to the column output signal indicating that the evaluation output line includes the first precharge state; decoupling the evaluation output line from the supply voltage rail in response to the column output signal indicating that the evaluation output line includes a discharge state; 5. The memory system of claim 4, configured as follows:

6. the read bit lines include a first read bit line; the float control circuit includes a first float control circuit; the memory system further includes a second read bit line coupled to a second plurality of memory bit cell circuits in the bit cell column circuit; the column readout circuit further includes a second float control circuit; The read control circuit is configured to cause the float control circuit to couple the evaluate output line to the read bit line in response to the precharge step and in response to the evaluate step, whereby the read control circuit is configured to: in response to an indication that a read operation is directed to one of the first plurality of memory bit cell circuits, causing the column read circuit to couple the first read bit line to the evaluate output line and decouple the second read bit line from the evaluate output line during the precharge and evaluate phases of the read operation; in response to an indication that a read operation is directed to a memory bit cell in the second plurality of memory bit cell circuits, causing the column read circuit to couple the second read bit line to the evaluation output line and decouple the first read bit line from the evaluation output line during the second precharge state and the evaluation phase of the read operation; During the idle phase, the first read bit line and the second read bit line are isolated from the evaluation output line. The memory system of claim 5 , further configured to:

7. In response to coupling the first read bit line to the evaluation output line, the column output circuit generates the column output signal based on the first read bit line including one of the discharged state and the second precharged state; In response to coupling the second read bit line to the evaluation output line, the column output circuit generates the column output signal based on the second read bit line including one of the discharged state and the second precharged state.

7. The memory system of claim 6.

8. At least one bit cell column circuit, each bit cell column circuit comprising: a plurality of memory bitcell circuits; a read bit line coupled to a first plurality of memory bit cell circuits of the plurality of memory bit cell circuits in a bit cell column circuit of the at least one bit cell column circuit; a column readout circuit, an evaluation output line; a precharge circuit configured to precharge the evaluation output line during an idle phase and a precharge phase of a read operation by coupling the evaluation output line to a supply voltage rail in response to receiving a precharge signal in an active state from a read control circuit; a float control circuit coupled between the read bit line and the evaluation output line, the float control circuit comprising: coupling the read bit line to the evaluation output line during the precharge phase and the evaluation phase of the read operation; disconnecting the read bit lines from the evaluate output lines during the idle phase; The float control circuit is configured as follows: a column output circuit coupled to the evaluation output line, the column output circuit configured to generate a column output signal based on the evaluation output signal, the column output circuit including an inverter circuit configured to generate the column output signal having a logic state complementary to a logic state of the evaluation output line; the column readout circuitry being configured to evaluate a stored logic state of a selected one of the first plurality of memory bit cell circuits on the evaluation output line during the evaluation stage; the read control circuit coupled to the float control circuit, generating a float control signal in an active state to turn on the float control circuit in response to receiving an indication of the precharge phase of the read operation and in response to receiving an indication of the evaluate phase of the read operation, thereby causing the float control circuit to couple the evaluate output line to the read bit line in response to the precharge phase and in response to the evaluate phase of the read operation; generating the float control signal in an inactive state to turn off the float control circuit in response to receiving an indication of the idle phase, thereby causing the float control circuit to isolate the evaluate output line from the read bit line in response to the idle phase; generating the precharge signal in the active state in response to receiving an indication of the idle phase and in response to receiving an indication of the precharge phase of the read operation; generating the precharge signal in an inactive state in response to receiving an indication of the evaluation phase of the read operation; the read control circuit configured as follows; a memory system including:

9. The read control circuitry further coupled to the precharge circuitry, the read control circuitry configured to control the float control circuitry and the precharge circuitry.

9. The memory system of claim 8.

10. The precharge circuit being configured to couple the evaluation output line to the supply voltage rail means that the precharge circuit is charging the evaluation output line to a first precharge state including a first voltage; charging the read bit line to a second precharge state including a second voltage lower than the first voltage based on the evaluation output line being charged to the first voltage; 10. The memory system of claim 9, further configured to:

11. Each of the plurality of memory bit cell circuits comprises: a data node configured to store a logical state of the data; a read port circuit including a read port output coupled to the read bit line; wherein the read port circuitry, in response to receiving a read word line (RWL) signal in an active state: in response to the logic state of the data stored at a first data node comprising a first logic state, coupling the read bit line to a ground voltage rail and discharging the evaluate output line to a discharged state; in response to the logic state of the data stored on the first data node comprising a second logic state, isolating the read bit line from the ground voltage rail and maintaining the evaluate output line in a first precharge state; 11. The memory system of claim 10 configured as follows:

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