Image display device manufacturing method and image display device

Abstract

According to one embodiment, this method for producing an image display device comprises: a step for forming a graphene layer on a first surface of a substrate; a step for forming a semiconductor layer on the graphene layer; a step for machining the semiconductor layer to form a light-emitting element which includes a light-emitting surface on the graphene layer and an upper surface on the reverse side from the light-emitting surface; a step for forming a first insulating film which covers the first surface, the graphene layer and the light-emitting element; a step for forming a circuit element on the first insulating film; a step for forming a second insulating film which covers the first insulating film and the circuit element; a step for forming a first via which passes through the first insulating film and the second insulating film; and a step for forming a first wiring layer on the second insulating film. The first via is provided between the first wiring layer and the upper surface and electrically connects the first wiring layer and the upper surface.

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device. [Background technology]

[0002] There is a demand for thin image display devices that have high brightness, a wide viewing angle, high contrast, and low power consumption. To meet these market demands, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is anticipated as a self-emitting element. A method of manufacturing display devices using micro LEDs has been introduced in which individually formed micro LEDs are sequentially transferred to a driving circuit. However, as the number of micro LED elements increases with the trend toward higher image quality, such as full HD, 4K, and 8K, the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and then sequentially transferred to a substrate on which a driving circuit, etc., is formed. Furthermore, there is a risk of poor connections between the micro LEDs and the driving circuit, etc., resulting in reduced yields.

[0004] A technique is known in which a semiconductor layer including a light-emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-141492 [Non-patent literature]

[0006] [Non-Patent Document 1] H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils", SCIENTIFIC REPORTS, 7:2112, 18 May 2017 [Non-patent document 2] JW Shon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes on amorphous substrates by pulsed sputtering", SCIENTIFIC REPORTS, 4:5325, 23 June 2014 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0008] A method for manufacturing an image display device according to one embodiment of the present invention includes the steps of: forming a graphene-containing layer on a first surface of a substrate; forming a semiconductor layer including a light-emitting layer on the graphene-containing layer; processing the semiconductor layer to form a light-emitting element including a light-emitting surface on the graphene-containing layer and an upper surface opposite to the light-emitting surface; forming a first insulating film covering the first surface, the graphene-containing layer, and the light-emitting element; forming circuit elements on the first insulating film; forming a second insulating film covering the first insulating film and the circuit elements; forming a first via that penetrates the first insulating film and the second insulating film; and forming a first wiring layer on the second insulating film. The first via is provided between the first wiring layer and the upper surface and electrically connects the first wiring layer to the upper surface.

[0009] An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a light-emitting element including a light-emitting surface on the first surface and an upper surface opposite to the light-emitting surface, a first insulating film covering the first surface and the light-emitting element, a circuit element provided on the first insulating film, a second insulating film covering the first insulating film and the circuit element, a first via provided to penetrate the first insulating film and the second insulating film, and a first wiring layer provided on the second insulating film. The first via is provided between the first wiring layer and the upper surface and electrically connects the first wiring layer to the upper surface.

[0010] An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a first semiconductor layer including a light-emitting surface on the first surface on which multiple light-emitting regions can be formed, multiple light-emitting layers spaced apart from one another on the first semiconductor layer, multiple second semiconductor layers each having a different conductivity type from the first semiconductor layer, a first insulating film covering the first surface, the first semiconductor layer, the multiple light-emitting layers, and the multiple second semiconductor layers, multiple transistors spaced apart from one another on the first insulating film, a second insulating film covering the first insulating film and the multiple transistors, multiple first vias penetrating the first insulating film and the second insulating film, and a first wiring layer on the second insulating film. The multiple second semiconductor layers and the multiple light-emitting layers are separated by the first insulating film. The multiple first vias are respectively provided between the first wiring layer and the multiple second semiconductor layers, and electrically connect the first wiring layer and the multiple second semiconductor layers.

[0011] An image display device according to one embodiment of the present invention includes a light-transmitting member having a first surface, a plurality of light-emitting elements each having a light-emitting surface on the first surface and an upper surface opposite the light-emitting surface, a first insulating film covering the first surface and the plurality of light-emitting elements, a circuit element provided on the first insulating film, a second insulating film covering the first insulating film and the circuit element, a plurality of first vias provided to penetrate the first insulating film and the second insulating film, and a first wiring layer provided on the second insulating film. The plurality of first vias are provided between the first wiring layer and the upper surface and electrically connect the first wiring layer to the upper surface, respectively. [Effects of the Invention]

[0012] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer step of light emitting elements and improves yield.

[0013] According to one embodiment of the present invention, it is possible to reduce the size of the light emitting element, and a high-definition image display device is realized. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic cross-sectional view illustrating a part of an image display device according to a first embodiment. [Figure 2] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 3] FIG. 1 is a schematic plan view illustrating a part of an image display device according to a first embodiment. [Figure 4A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 4B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 5A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 5B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 6B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7A] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7B] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7C] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 7D] 3A to 3C are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device according to the first embodiment. [Figure 8] 5A to 5C are schematic cross-sectional views illustrating a part of a modified example of the manufacturing method of the image display device of the first embodiment. [Figure 9] FIG. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 10]FIG. 10 is a schematic perspective view illustrating an image display device according to a modified example of the first embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a second embodiment. [Figure 12] FIG. 10 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 13A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 13B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 14A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 14B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 15A] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 15B] 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a second embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment. [Figure 17A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 17B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 18A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 18B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a third embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment. [Figure 20A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 20B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 21A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 21B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 22A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 22B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fourth embodiment. [Figure 23] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fifth embodiment. [Figure 24A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 24B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 25A] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 25B] 10A to 10C are schematic cross-sectional views illustrating a part of a method for manufacturing an image display device according to a fifth embodiment. [Figure 26] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 27] FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a sixth embodiment. [Figure 28] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a seventh embodiment. [Figure 29] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a seventh embodiment. [Figure 30] FIG. 13 is a block diagram illustrating an image display device according to an eighth embodiment. [Figure 31] FIG. 13 is a block diagram illustrating an image display device according to a modified example of the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0016] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. FIG. 1 shows a schematic configuration of a sub-pixel 20 of the image display device of this embodiment. In the following, the description may be made using an XYZ three-dimensional coordinate system. The light-emitting elements 150 are arranged on a two-dimensional plane, as shown in Figs. 9 and 10 described later. A light-emitting element 150 is provided for each sub-pixel 20. The two-dimensional plane on which the sub-pixels 20 are arranged is referred to as an XY plane. The sub-pixels 20 are arranged along the X-axis direction and the Y-axis direction.

[0017] Fig. 1 shows a cross section taken along line AA' in Fig. 3, which will be described later, and is a cross section obtained by connecting cross sections in multiple planes perpendicular to the XY plane onto a single plane. In other figures, as in Fig. 1, cross sections in multiple planes perpendicular to the XY plane do not show the X and Y axes, but show only the Z axis perpendicular to the XY plane. In other words, in these figures, the plane perpendicular to the Z axis is the XY plane.

[0018] In the following, the positive direction of the Z axis may be referred to as "up" or "above," and the negative direction of the Z axis may be referred to as "down" or "below," but the direction along the Z axis is not necessarily limited to the direction in which gravity acts. The length along the Z axis may be referred to as height.

[0019] The subpixel 20 has a light-emitting surface 151S that is substantially parallel to the XY plane. The light-emitting surface 151S is a surface that emits light mainly in the negative direction of the Z axis, which is perpendicular to the XY plane. In this embodiment, its modifications, and all embodiments and modifications thereof described below, the light-emitting surface emits light mainly in the negative direction of the Z axis.

[0020] 1, a subpixel 20 of the image display device includes a substrate (light-transmitting member) 102, a graphene layer 140, a light-emitting element 150, a first interlayer insulating film (first insulating film) 156, a transistor (circuit element) 103, a second interlayer insulating film (second insulating film) 108, a via (first via) 161a, and a first wiring layer 110. In this embodiment, the subpixel 20 further includes a color filter 180.

[0021] The substrate 102 has two surfaces 102a and 102b. The surface 102b is the surface opposite the surface 102a, and both surfaces 102a and 102b are substantially parallel to the XY plane. The light-emitting element 150 is provided on one surface (first surface) 102a. The color filter 180 is provided on the other surface 102b. The substrate 102 is a light-transmitting substrate, such as a glass substrate.

[0022] In this embodiment, a graphene layer 140 is provided between the substrate 102 and the light emitting element 150. The graphene layer 140 is provided on one surface 102a of the substrate 102, and the light emitting element 150 is provided on the graphene layer 140. The graphene layer 140 is used in the process of forming the light emitting element 150, as will be described later with reference to FIGS. 4A to 6B. The graphene layer 140 is thin enough to transmit light.

[0023] The light emitting element 150 is provided on the color filter 180 via the graphene layer 140 and the substrate 102. The surface of the light emitting element 150 on the color filter 180 is a light emitting surface 151S.

[0024] The light emitting element 150 is driven by a transistor 103 provided on the first interlayer insulating film 156. The transistor 103 is a thin film transistor (TFT).

[0025] The configuration of the sub-pixel 20 will be described in detail below. The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly below the light-emitting surface 151S of the light-emitting element 150 in accordance with the shape of the light-emitting surface 151S. In the color filter 180, the portion other than the color conversion portion 182 is made into a light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a sharp image.

[0026] The color conversion section 182 may have one layer or two or more layers. FIG. 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., wavelength, of the light emitted by the subpixel 20. When the emission color of the subpixel 20 is red, the color conversion section 182 preferably has two layers, made up of a color conversion layer 183 and a filter layer 184 that transmits red light. When the emission color of the subpixel 20 is green, the color conversion section 182 preferably has two layers, made up of a color conversion layer 183 and a filter layer 184 that transmits green light. When the emission color of the subpixel 20 is blue, the color conversion section 182 preferably has one layer.

[0027] When color conversion section 182 has two layers, one layer is color conversion layer 183 and the other layer is filter layer 184. Color conversion layer 183 is stacked on filter layer 184, and is provided at a position closer to light emitting element 150 than filter layer 184.

[0028] Color conversion layer 183 converts the wavelength of light emitted by light emitting element 150 to a desired wavelength. In the case of a subpixel 20 that emits red light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 630 nm±20 nm. In the case of a subpixel 20 that emits green light, color conversion layer 183 converts light of 467 nm±30 nm, which is the wavelength of light emitting element 150, to light of a wavelength of, for example, approximately 532 nm±20 nm.

[0029] Filter layer 184 blocks the wavelength component of blue light emission that remains without being color converted by color conversion layer 183 .

[0030] When the color of light emitted by subpixel 20 is blue, the light may be output via color conversion layer 183, or may be output directly without going through color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is approximately 467 nm±30 nm, the light may be output without going through color conversion layer 183. When the wavelength of light emitted by light emitting element 150 is 410 nm±30 nm, it is preferable to provide color conversion layer 183 in order to convert the wavelength of the output light to approximately 467 nm±30 nm.

[0031] Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with a filter layer 184 that transmits blue light, minute reflections of external light other than blue light that occur on the surface of the light-emitting element 150 are suppressed.

[0032] The substrate 102 is provided on a color filter 180. The graphene layer 140 is provided on one surface 102a of the substrate 102.

[0033] The graphene layer 140 includes a plurality of graphene sheets 140a. The graphene sheet 140a is provided for each light emitting element 150. The outer periphery of the graphene sheet 140a in the XY plane view substantially coincides with the outer periphery of the light emitting element 150 in the XY plane view.

[0034] The light emitting element 150 includes a light emitting surface 151S provided on a graphene sheet (layer including graphene) 140a. The light emitting element 150 includes an upper surface 153U provided on the opposite side of the light emitting surface 151S. In this example, the outer peripheral shapes of the light emitting surface 151S and the upper surface 153U in the XY plane view are square or rectangular, and the light emitting element 150 is a prismatic element having the light emitting surface 151S on the surface 102a. The cross section of the prismatic element may be a polygon with five or more sides. The light emitting element 150 is not limited to a prismatic element, and may be a cylindrical element.

[0035] The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from a light-emitting surface 151S toward an upper surface 153U. The light-emitting surface 151S, which is the n-type semiconductor layer 151, is provided in contact with the graphene sheet 140a. The light-emitting element 150 emits light mainly in the negative direction of the Z axis through the light-emitting surface 151S, the graphene sheet 140a, the substrate 102, and the color filter 180.

[0036] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided on one surface 102a of the substrate 102 so as to protrude in one direction from the n-type semiconductor layer 151. The height of the connection portion 151a from the surface 102a is the same as or lower than the height of the n-type semiconductor layer 151 from the surface 102a. The connection portion 151a is part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of a via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0037] When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane is, for example, approximately square or rectangular. When the shape of the light emitting element 150 in the XY plane is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane is cylindrical, the shape of the light emitting element 150 in the XY plane is not limited to a circle and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element in the planar view, the degree of freedom in the wiring layout, etc. is improved.

[0038] The light emitting element 150 may include, for example, In X Al Y Ga 1-X-Y A gallium nitride compound semiconductor including a light emitting layer such as N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, approximately 467 nm±30 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of approximately 410 nm±30 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned values ​​and can be any appropriate wavelength.

[0039] The first interlayer insulating film (first insulating film) 156 covers the surface 102a, the graphene layer 140 including the graphene sheet 140a, and the light-emitting element 150. The first interlayer insulating film 156 electrically isolates adjacent light-emitting elements 150 from each other. The first interlayer insulating film 156 electrically isolates the light-emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming the circuit 101 including circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from thermal stress and the like that occurs when the transistor 103 and the like are formed.

[0040] The first interlayer insulating film 156 is preferably formed of an organic insulating material. The organic insulating material used for the first interlayer insulating film 156 has optical reflectivity and is preferably a white resin. By using a white resin for the first interlayer insulating film 156, returned light resulting from light emitted laterally from the light-emitting element 150 is reflected. Since returned light emitted from the light-emitting element 150 can also occur at the interface between the light-emitting element 150 and the graphene sheet 140a or the boundary between the light-emitting element 150 and the substrate 102, this returned light can also be reflected. In this way, by using a white resin for the first interlayer insulating film 156, the light-emitting efficiency of the light-emitting element 150 is substantially improved. Furthermore, the optical reflectivity of the first interlayer insulating film 156 can reflect scattered light, etc., upward from the light-emitting element 150, thereby preventing the light from reaching the transistor 103 and preventing malfunction of the transistor 103.

[0041] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin, such as SOG (Spin On Glass), or a novolac-type phenolic resin. The scattering particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light emitting element 150. The scattering particles preferably have a diameter of about 1 / 2 the wavelength of the light. Examples of such scattering particles include TiO2, Al2O3, and ZnO.

[0042] In addition to the above, the white resin can also be formed by utilizing a large number of minute pores dispersed in the transparent resin. When the first interlayer insulating film 156 is whitened, an SiO2 film or the like may be used by overlaying it on the SOG or the like. In this case, the SiO2 film or the like is formed by using, for example, ALD (Atomic-Layer-Deposition) or CVD.

[0043] The first interlayer insulating film 156 may be made of a black resin. By using a black resin for the first interlayer insulating film 156, scattering of light within the subpixels 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display sharper images.

[0044] A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided to ensure flatness when forming the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is an insulating film made of, for example, SiO2 or the like.

[0045] The transistor 103 is formed on a TFT lower layer film 106. In addition to the transistor 103, other circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and a circuit 101 is formed with wiring and the like. For example, in FIG. 2, which will be described later, the transistor 103 corresponds to the drive transistor 26. In FIG. 2, other circuit elements include the selection transistor 24 and the capacitor 28. The circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a first wiring layer 110.

[0046] In this example, the transistor 103 is a p-channel TFT. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous silicon region formed on the TFT underlayer film 106. For example, laser annealing using a laser is used to polycrystallize and activate the amorphous silicon region. A TFT formed by the LTPS process has sufficiently high mobility.

[0047] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the regions 104s and 104d. The regions 104s and 104d are activated by doping with p-type impurities such as boron (B) or boron fluoride (BF), and function as p-type semiconductor regions. The regions 104s and 104d are ohmically connected to the vias 111s and 111d, respectively.

[0048] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate it from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, thereby controlling the current flowing between the regions 104s and 104d.

[0049] The insulating layer 105 is made of, for example, SiO2. The insulating layer 105 may be a multi-layer insulating layer containing SiO2, Si3N4, or the like.

[0050] The gate 107 may be formed of, for example, polycrystalline Si, or may be formed of a high-melting point metal such as W or Mo. When the gate 107 is formed of a polycrystalline Si film, it is formed by, for example, CVD or the like.

[0051] The second interlayer insulating film 108 is provided on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of, for example, a white resin or an inorganic film such as SiO2. The second interlayer insulating film 108 also functions as a planarizing film for forming the first wiring layer 110.

[0052] The vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108 and the insulating layer 105. The first wiring layer 110 is formed on the second interlayer insulating film 108. The first wiring layer 110 includes a plurality of wirings that may have different potentials. In this example, the first wiring layer 110 includes wirings 110s, 110d, and 110k. These wirings 110s, 110d, and 110k are formed separately.

[0053] A portion of the wiring 110s is provided above the region 104s. Another portion of the wiring 110s is connected to, for example, a power supply line 3 shown in FIG. 2, which will be described later. A portion of the wiring 110d is provided above the region 104d. Another portion of the wiring 110d is provided above the upper surface 153U. A portion of the wiring 110k is provided above the connection portion 151a. Another portion of the wiring 110k is connected to, for example, a ground line 4 shown in the circuit shown in FIG. 2, which will be described later.

[0054] In the cross-sectional views from Fig. 1 onwards, unless otherwise specified, the reference numerals representing the wiring layers are shown next to the wires that make up the wiring layers. In the example of Fig. 1, the reference numeral for the first wiring layer 110 is shown next to the wire 110s.

[0055] The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0056] The wiring 110s is connected to the region 104s through the via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to, for example, a power supply line 3 shown in the circuit of FIG. 2 (described later) through the via 111s and the wiring 110s.

[0057] The wiring 110d is connected to the region 104d through a via 111d. The region 104d is the drain region of the transistor 103.

[0058] The via (first via) 161a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the upper surface 153U. The via 161a is provided between the wiring (first wiring) 110d and the upper surface 153U, and electrically connects the wiring 110d and the p-type semiconductor layer 153. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the via 161a, the wiring 110d, and the via 111d.

[0059] The via (second via) 161k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connecting portion 151a. The via 161k is provided between the wiring (second wiring) 110k and the connecting portion 151a, and electrically connects the wiring 110k and the connecting portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 2 via the connecting portion 151a, the via 161k, and the wiring 110k.

[0060] The first wiring layer 110 and the vias 111s, 111d, 161a, and 161k are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0061] A protective layer may be provided over the second interlayer insulating film 108 and the first wiring layer 110 to protect them from the external environment.

[0062] FIG. 2 is a schematic block diagram illustrating the image display device according to this embodiment. As shown in Fig. 2, the image display device 1 of this embodiment includes a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged, for example, in a lattice pattern. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

[0063] The image display device 1 further includes power lines 3 and ground lines 4. The power lines 3 and ground lines 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power lines 3 and ground lines 4 are electrically connected to each subpixel 20, and supply power to each subpixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and the GND terminal 4a are provided at the ends of the power lines 3 and the ground lines 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power terminal 3a with respect to the GND terminal 4a.

[0064] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction of the sub-pixels 20.

[0065] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 in each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0066] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0067] The subpixel 20 includes a light-emitting element 22, a select transistor 24, a drive transistor 26, and a capacitor 28. In Figure 2 and Figure 3 described below, the select transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0068] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness that corresponds to the current flowing through the light-emitting element 22.

[0069] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a power line 3.

[0070] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current that has passed through it.

[0071] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. In other words, the row selection circuit 5 scans the rows in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned subpixels 20, causing them to emit light. The brightness of the subpixels 20 is determined by the current flowing through the light-emitting elements 22. The subpixels 20 emit light at a gradation based on the determined brightness, and an image is displayed in the display area 2.

[0072] FIG. 3 is a schematic plan view illustrating a part of the image display device of this embodiment. In FIG. 3, line AA′ represents a cutting line in the cross-sectional view of FIG. In this embodiment, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction with a first interlayer insulating film 156 interposed therebetween. The light-emitting element 150 corresponds to the light-emitting element 22 in FIG. 2. The driving transistor 103 corresponds to the driving transistor 26 in FIG. 2 and is also denoted as T2.

[0073] 3, the cathode electrode of the light-emitting element 150 is provided by a connection portion 151a. The connection portion 151a is provided in a layer lower than the transistor 103 and the first wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k through a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k through a contact hole 161k1.

[0074] The anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in FIG. 1. An upper surface 153U of the p-type semiconductor layer 153 is connected to the wiring 110d through a via 161a. More specifically, one end of the via 161a is connected to the upper surface 153U. The other end of the via 161a is connected to the wiring 110d through a contact hole 161a1.

[0075] The other end of the wiring 110d is connected to the drain electrode of the transistor 103 through the via 111d shown in FIG. 1. The drain electrode of the transistor 103 is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through the via 111s shown in FIG. 1. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the first wiring layer 110 includes a power line 3, and the wiring 110s is connected to the power line 3.

[0076] In this example, the ground line 4 is provided in a layer even higher than the first wiring layer 110. Although not shown in FIG. 1, an interlayer insulating film is further provided on the first wiring layer 110. The ground line 4 is provided on the uppermost interlayer insulating film and is insulated from the power line 3.

[0077] In this way, the light emitting element 150 can be electrically connected to the first wiring layer 110 provided above the light emitting element 150 by using the vias 161k and 161a.

[0078] A method for manufacturing the image display device 1 of this embodiment will be described. 4A to 6B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. As shown in FIG. 4A, in the manufacturing method of the image display device of this embodiment, a substrate 102 is prepared. The substrate 102 is a light-transmitting substrate, for example, a substantially rectangular glass substrate measuring approximately 1500 mm × 1800 mm. A graphene layer (graphene layer) 1140 is formed on one surface (first surface) 102a of the substrate. The graphene layer 1140 is a layer containing graphene, and is preferably formed by stacking several to approximately ten monolayer graphene layers. The graphene layer 1140, cut to an appropriate size and shape, is placed at a predetermined position on the surface 102a and adsorbed to the substrate 102 due to the flatness of the surface 102a. The graphene layer 1140 may be adhered to the surface 102a, for example, with an adhesive or the like.

[0079] The periphery of the cut graphene layer 1140 in the XY plane view is determined according to the periphery of the semiconductor layer 1150 in the XY plane view shown in Fig. 4B described later. The periphery of the graphene layer 1140 in the XY plane view and the periphery of the semiconductor layer 1150 in the XY plane view are set so as to sufficiently include the periphery of the light-emitting element 150 in the XY plane view shown in Fig. 5A described later. In other words, the periphery of the light-emitting element 150 is disposed within the periphery of the graphene layer 1140 and the periphery of the semiconductor layer 1150 in the XY plane view.

[0080] 4B, the semiconductor layer 1150 is formed over the graphene layer 1140. The semiconductor layer 1150 is formed in the following order from the graphene layer 1140 side toward the positive direction of the Z axis: an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153. The semiconductor layer 1150 includes, for example, GaN, and more specifically, In X Al Y Ga 1-X-Y N (0≦X, 0≦Y, X+Y<1), etc. Crystal defects due to mismatch of crystal lattices are likely to occur in the early stages of growth of the semiconductor layer 1150, and crystals containing GaN as the main component generally exhibit n-type semiconductor characteristics. Therefore, by growing the n-type semiconductor layer 1151 on the graphene layer 1140, it is possible to improve the yield.

[0081] The semiconductor layer 1150 can be formed by physical vapor deposition methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering, with low-temperature sputtering being preferred. Low-temperature sputtering is preferably performed using light or plasma assistance during film formation, since this allows for lower temperatures. Epitaxial growth by MOCVD can sometimes exceed 1000°C. In contrast, it is known that low-temperature sputtering can epitaxially grow GaN crystals, including a light-emitting layer, on the graphene layer 1140 at low temperatures of approximately 400°C to 700°C (see Non-Patent Documents 1 and 2, etc.). Such low-temperature sputtering is suitable for forming the semiconductor layer 1150 on a glass substrate.

[0082] By growing a GaN semiconductor layer 1150 on the graphene layer 1140 using an appropriate deposition technique, a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 is formed on the graphene layer 1140. The semiconductor layer 1150 is formed within the region indicated by the two-dot chain line in FIG. 4B.

[0083] During the growth process of the semiconductor layer 1150, amorphous deposits 1162 containing Ga and other growth seed materials may be deposited on the surface 102a where the graphene layer 1140 is not present. In this example, the deposits 1162 are stacked in the order of deposits 1162a, 1162b, and 1162c from the surface 102a toward the positive direction of the Z axis. The deposit 1162a is deposited when the n-type semiconductor layer 1151 is formed, the deposit 1162b is deposited when the light-emitting layer 1152 is formed, and the deposit 1162c is deposited when the p-type semiconductor layer 1153 is formed, but this is not limitative.

[0084] The semiconductor layer 1150 may not only be formed directly on the graphene layer 1140, but also be formed on a buffer layer formed on the graphene layer 1140. Providing a buffer layer may promote GaN crystal growth. The buffer layer can be formed thin enough not to impair light transparency, and may be made of any material that promotes GaN crystal growth, such as an insulating material or a metal material.

[0085] As shown in FIG. 5A, the semiconductor layer 1150 shown in FIG. 4B is processed into a desired shape by etching, and the light emitting element 150 is formed.

[0086] In the process of forming the light emitting element 150, the connection portion 151a is formed, and then other portions are formed by further etching. OneIt is possible to form the light emitting element 150 having the connection portion 151a protruding in the direction of the light emitting element 150. The light emitting element 150 is formed by, for example, a dry etching process, and preferably by anisotropic plasma etching (Reactive Ion Etching, RIE).

[0087] 4B is over-etched and formed into a graphene sheet 140a when the light emitting device 150 is formed. Therefore, the outer periphery of the graphene sheet 140a in the XY plane view substantially coincides with the outer periphery of the light emitting device 150 in the XY plane view.

[0088] A first interlayer insulating film (first insulating film) 156 is formed to cover the surface 102a, the graphene sheet 140a, and the light emitting element.

[0089] 5B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156 by, for example, CVD. A Si layer 1104 is formed on the formed TFT lower layer film 106. The Si layer 1104 is an amorphous Si layer when formed, and after formation, the Si layer 1104 is polycrystallized by, for example, scanning with an excimer laser pulse multiple times to form the Si layer 1104.

[0090] As shown in FIG. 6A, the polycrystallized Si layer 1104 shown in FIG. 5B is processed into an island shape to form the TFT channel 104. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104 with the insulating layer 105 interposed therebetween. The gate 107 is selectively doped with impurities such as B and thermally activated to form the transistor (circuit element) 103. Regions 104s and 104d are p-type active regions and function as the source region and drain region of the transistor 103, respectively. Region 104i is an n-type active region and functions as the channel.

[0091] When the LTPS process is used, the transistor 103 is formed in the desired position on the TFT underlayer film 106 in this manner.

[0092] 6B, a second interlayer insulating film (second insulating film) 108 is provided so as to cover the insulating layer 105 and the gate 107. An appropriate manufacturing method is applied to form the second interlayer insulating film 108 depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is made of SiO2, a technique such as ALD or CVD is used.

[0093] The flatness of the second interlayer insulating film 108 only needs to be such that the first wiring layer 110 can be formed thereon, and a planarization step does not necessarily have to be performed. If the planarization step is not performed on the second interlayer insulating film 108, the number of steps can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 is thin, the depth of the via holes for the vias 161a and 161k can be made shallower, ensuring a sufficient opening diameter. This makes it easier to ensure electrical connection through the vias, and reduces yield losses due to poor electrical characteristics.

[0094] Vias 161a and 161k are formed penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via (first via) 161a is formed by filling a conductive material into a via hole formed to reach the upper surface 153U, and is electrically connected to the upper surface 153U. The via (second via) 161k is formed by filling a conductive material into a via hole formed to reach the connecting portion 151a, and is electrically connected to the connecting portion 151a.

[0095] Vias 111s and 111d are formed to penetrate the second interlayer insulating film 108 and the insulating layer 105. The via 111s is formed to reach the region 104s. The via 111d is formed to reach the region 104d. RIE, for example, is used to form via holes to form the vias 161a, 161k, 111s, and 111d.

[0096] The first wiring layer 110 including the wirings 110k, 110d, and 110s is formed on the second interlayer insulating film 108. The wiring 110k is connected to one end of the via 161k. The wiring 110d is connected to one end of the via 161a and one end of the via 111d. The wiring 110s is connected to one end of the via 111s. In forming the first wiring layer 110, the wirings 110k, 110d, and 110s may be formed simultaneously with the formation of the vias 161a, 161k, 111d, and 111s.

[0097] Thereafter, a protective film may be formed to cover the second interlayer insulating film 108 and the first wiring layer 110 to protect them from the external environment.

[0098] The process of forming the color filter 180 shown in FIG. 1 will be described. 7A to 7D are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. 7A to 7D show a method for forming a color filter by an inkjet method.

[0099] As shown in FIG. 7A, a structure 1192 is prepared. A color filter is formed on the exposed surface (second surface) 102b of the substrate 102. The structure 1192 is formed up to the step shown in FIG. 6B described above. In addition to the substrate 102 and the light-emitting element 150, the structure 1192 includes the graphene sheet 140a, the first interlayer insulating film 156, the TFT lower film 106, the TFT channel, the insulating layer 105, the gate 107, the vias 111s, 111d, 161a, 161k, the first wiring layer 110, and the like shown in FIG. 6B.

[0100] 7B, light-shielding portion 181 is formed in an area on surface 102b that does not include light-emitting surface 151S. Light-shielding portion 181 is formed using, for example, screen printing or photolithography technology.

[0101] As shown in FIG. 7C, a phosphor corresponding to the emitted color is ejected from an inkjet nozzle to form a color conversion layer 183. The phosphor colors the areas on surface 102b where light-shielding portion 181 is not formed. For example, fluorescent paint using a general phosphor material, perovskite phosphor material, or quantum dot phosphor material is used as the phosphor. The use of perovskite phosphor material or quantum dot phosphor material is preferable because it allows each emitted color to be realized, while also providing high monochromaticity and color reproducibility. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of light-shielding portion 181.

[0102] As already explained, if no color conversion unit is formed for a blue-emitting subpixel, then color conversion layer 183 is not formed. Furthermore, if a single layer of color conversion unit is sufficient when forming a blue color conversion layer for a blue-emitting subpixel, then the thickness of the blue phosphor coating is preferably the thickness of filter layer 184 laminated on color conversion layer 183, and is approximately the same as the thickness of light-shielding unit 181.

[0103] As shown in Figure 7D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coating is approximately the same as the thickness of the light-shielding portion 181. In this way, the color filter 180 is formed.

[0104] A process for forming a film-type color filter 180a will be described below instead of the inkjet-type color filter formation process. FIG. 8 is a schematic cross-sectional view illustrating a part of a modified example of the manufacturing method of the image display device of this embodiment. In FIG. 8, the diagram above the arrow indicates a structure 1192. In addition to the substrate 102 and the light-emitting element 150, the structure 1192 includes the graphene sheet 140a, the first interlayer insulating film 156, the TFT lower layer film 106, the TFT channel, the insulating layer 105, the gate 107, the vias 111s, 111d, 161a, and 161k, and the first wiring layer 110 shown in FIG. 6B. The diagram below the arrow indicates a glass substrate 186, a color filter 180a bonded to the glass substrate 186, and a transparent thin-film adhesive layer 189 that bonds the color filter 180a to the structure 1192. The arrow indicates the state in which the color filter 180a is attached to the structure 1192 together with the glass substrate 186 and the transparent thin-film adhesive layer 189.

[0105] 8, to avoid complexity of the illustration, the reference numerals and the components themselves including the reference numerals are omitted for some of the components of the structure 1192. The components in the structure 1192 that are not shown are the circuit 101 including the transistor 103 and the vias 161a and 161k shown in FIG.

[0106] As shown in Figure 8, color filter (wavelength conversion member) 180a includes light-shielding portion 181a, color conversion layers 183R, 183G, and 183B, and filter layer 184a. Light-shielding portion 181a has the same function as in the inkjet system. Color conversion layers 183R, 183G, and 183B have the same function and are made of the same material as in the inkjet system. Filter layer 184a also has the same function as in the inkjet system.

[0107] One surface of the color filter 180a is bonded to the structure 1192. The other surface of the color filter 180a is bonded to the glass substrate 186. A transparent thin film adhesive layer 189 is provided on one surface of the color filter 180a, and the color filter 180a is bonded to the exposed surface (second surface) 102b of the structure 1192 via the transparent thin film adhesive layer 189.

[0108] In this example, the color filter 180a has color conversion sections arranged in the positive direction of the X axis in the order of red, green, and blue. For the red color conversion section, a red color conversion layer 183R is provided on the transparent thin film adhesive layer 189 side. For the green color conversion section, a green color conversion layer 183G is provided on the transparent thin film adhesive layer 189 side. For the red and green color conversion sections, a filter layer 184a is provided on the glass substrate 186 side. For the blue color conversion section, in this example, a single-layer color conversion layer 183B is provided from the glass substrate 186 side to the transparent thin film adhesive layer 189 side. However, this is not limiting; similarly to the case of other colors, a filter layer 184a may be provided on the glass substrate 186 side. The frequency characteristics of the filter layer 184 may be the same for all colors of the color conversion section, or may differ for each color of the color conversion section. A light-shielding section 181a is provided between each color conversion section.

[0109] As shown by the arrows in FIG. 8, the positions of the color conversion layers 183R, 183G, and 183B of each color are aligned with the positions of the light emitting elements 150, and the color filter 180a is attached to the structure 1192 via a transparent thin film adhesive layer 189.

[0110] In this way, color filters 180, 180a are formed on structure 1192 including light-emitting element 150 and circuit 101, thereby forming subpixels. An appropriate method for forming color filters is selected from inkjet methods, film methods, and other methods that can equally form color filters. Forming color filter 180 using the inkjet method can omit processes such as attaching a film, making it possible to manufacture the image display device 1 shown in FIG. 2 at lower cost.

[0111] Whether the color filter 180 is formed by an inkjet method or the film-type color filter 180a, it is desirable for the color conversion layer 183 to be as thick as possible to improve color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light will approximate Lambertian, while the emission angle of the unconverted blue light will be limited by the light-shielding portions 181 and 181a. This causes a problem of viewing-angle dependency in the display color of the displayed image. To match the light distribution of the unconverted blue light with the light distribution of the subpixels provided with the color conversion layer 183, it is desirable for the thickness of the color conversion layer 183 to be approximately half the opening size of the light-shielding portions 181 and 181a.

[0112] For example, in the case of a high-resolution image display device with a resolution of about 250 ppi (pitch per inch), the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, if the color conversion material is made of spherical phosphor particles, it is preferable that they be stacked in a close-packed structure to suppress light leakage from the light emitting element 150. To achieve this, at least three particle layers are required. Therefore, the particle size of the phosphor material that makes up the color conversion layer 183 is preferably about 5 μm or less, and more preferably about 3 μm or less.

[0113] After the color filters 180 and 180a are formed, the structure 1192 shown in Fig. 7D etc. is diced together with the color filters 180 and 180a to form the image display device. Note that the step of forming the color filters 180 and 180a may be performed after the structure 1192 is diced.

[0114] FIG. 9 is a schematic perspective view illustrating the image display device according to this embodiment. 9, the image display device of this embodiment has a light-emitting circuit section 172 having a large number of light-emitting elements 150 on a color filter 180. In addition to the light-emitting elements 150, the light-emitting circuit section 172 includes a graphene sheet 140a and a first interlayer insulating film 156 formed on the substrate 102 shown in FIG. 1. A circuit 101 including a transistor 103 and the like is provided on the light-emitting circuit section 172 via the TFT lower layer film 106 shown in FIG. 1. The circuit 101 and the light-emitting circuit section 172 are electrically connected via vias 161a and 161k shown in FIG. 1.

[0115] (Variation) FIG. 10 is a schematic perspective view illustrating an image display device according to a modified example of this embodiment. In the image display device of the first embodiment described above, the color filter 180 is provided, but as shown in FIG. 10, the image display device may be configured to emit monochromatic light without providing a color filter.

[0116] The effects of the image display device of this embodiment will be described. In the manufacturing method of the image display device of this embodiment, light emitting elements 150 are formed by etching semiconductor layer 1150 formed by crystal growth on substrate 102. Thereafter, light emitting elements 150 are covered with first interlayer insulating film 156, and circuit 101 including circuit elements such as transistor 103 that drives light emitting elements 150 is fabricated on first interlayer insulating film 156. Therefore, the manufacturing process is significantly shortened compared to the case where individual light emitting elements are transferred to substrate 102.

[0117] In the manufacturing method of the image display device 1 of this embodiment, the graphene layer 1140 is formed on the substrate 102, and the formed graphene layer 1140 can be used as a seed for crystal growth of the semiconductor layer 1150. The graphene layer 1140 can be easily formed by attaching graphene cut into a predetermined shape onto one surface 102a of the substrate 102, and the process can be simplified.

[0118] An image display device with 4K resolution has more than 24 million subpixels, and an image display device with 8K resolution has more than 99 million subpixels. Individually forming such a large number of light-emitting elements and mounting them on a circuit board requires an enormous amount of time. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, mounting a large number of light-emitting elements individually reduces yield due to poor connections during mounting, and further increases in costs are unavoidable. However, the manufacturing method for the image display device of this embodiment provides the following advantages.

[0119] In the manufacturing method of the image display device of this embodiment, the light emitting element 150 is formed after the entire semiconductor layer 1150 is formed on the graphene layer 1140 formed on the substrate 102, which makes it possible to eliminate the transfer step of the light emitting element 150. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time required for the transfer step can be shortened and the number of steps can be reduced compared to conventional manufacturing methods.

[0120] Since the semiconductor layer 1150 having a uniform crystal structure is grown on the graphene layer 1140, the light-emitting element 150 can be arranged in a self-aligned manner by cutting the graphene into an appropriate shape and attaching it. Therefore, there is no need to align the light-emitting element on the substrate 102, and the light-emitting element 150 can be easily miniaturized, making it suitable for high-definition displays.

[0121] After forming the light-emitting element directly on the substrate 102 by etching or the like, the light-emitting element 150 and the circuit element formed on the upper layer of the light-emitting element 150 are electrically connected by forming a via, thereby realizing a uniform connection structure and suppressing a decrease in yield.

[0122] In this embodiment, for example, the light emitting elements 150 on the glass substrate formed as described above are covered with a first interlayer insulating film 156, and a driving circuit including a TFT and a scanning circuit can be formed on the planarized surface using an LTPS process or the like. The LTPS process has the advantage that it can utilize existing flat panel display manufacturing processes and plants, and can also reduce thermal stress on the underlying light emitting elements 150 and the like, thereby improving yield.

[0123] In this embodiment, the light-emitting element 150 formed below the transistor 103 and the like can be electrically connected to the power supply line, ground line, driving transistor, and the like formed above by forming vias that penetrate the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technically established multilayer wiring technology, a uniform connection structure can be easily realized, thereby improving yield. Therefore, a decrease in yield due to poor connection of the light-emitting element and the like is suppressed.

[0124] The graphene sheet 140a formed from the graphene layer 1140 is a laminate of several atoms to several tens of atoms, and is therefore sufficiently thin so as not to impair light transmittance. This makes it possible to omit the step of removing the substrate 102 on which the graphene layer 140 including the graphene sheet 140a is formed. This allows the image display device to be manufactured with fewer steps, thereby realizing a cost reduction for the image display device.

[0125] It is also possible to add a step of removing the substrate 102 before forming the color filter 180. In this case, it is possible to realize a thinner image display device.

[0126] (Second embodiment) FIG. 11 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. 11 , the subpixel 220 of the image display device of this embodiment differs from the other embodiments described above in the configurations of the light-emitting element 250 and the transistor 203. Specifically, the light-emitting surface 253S of the light-emitting element 250 is provided by a p-type semiconductor layer 253, and the transistor 203 is an n-channel transistor, which differs from the other embodiments described above. The subpixel 220 also differs from the other embodiments described above in that it includes a second wiring layer 230 including a wiring 230a, and the wiring 230a connects the p-type semiconductor layer 253 and the via 261a. The same components as those in the other embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0127] The image display device of this embodiment includes a subpixel 220. The subpixel 220 includes a substrate 102, a second wiring layer 230, a graphene layer 140, a light-emitting element 250, a first interlayer insulating film 156, a transistor (circuit element) 203, a second interlayer insulating film 108, a via (first via) 261k, and a first wiring layer 110. The subpixel 220 further includes a color filter 180.

[0128] As in the other embodiments described above, the light emitting element 250 is provided on one surface 102a of the substrate 102. The color filter 180 is provided on the other surface 102b of the substrate 102.

[0129] The second wiring layer 230 is provided on the surface 102a. The second wiring layer 230 includes a plurality of wirings 230a. The wirings 230a are provided for each light-emitting element 250. The second wiring layer 230 including the wirings 230a is formed of a conductive film having optical transparency. The conductive film is formed of a transparent conductive film such as ITO or ZnO, or is formed of a metal thin film formed to be sufficiently thin so as to transmit light.

[0130] The graphene layer 140 including a plurality of graphene sheets 140a is provided on the second wiring layer 230. The graphene sheet 140a is provided on the wiring 230a, and the light emitting element 250 is electrically connected to the wiring 230a via the graphene sheet 140a.

[0131] The light-emitting element 250 includes a light-emitting surface 253S and an upper surface 251U opposite to the light-emitting surface 253S. The light-emitting surface 253S is in contact with the graphene sheet 140a. Therefore, the light-emitting element 250 emits light in the negative direction of the Z axis through the light-emitting surface 253S, the graphene sheet 140a, the wiring 230a, the substrate 102, and the color filter 180.

[0132] The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are stacked in this order from the light emitting surface 253S toward the upper surface 251U.

[0133] The light emitting element 250 has the same shape in the XY plane as the light emitting element 150 of the other embodiments described above. An appropriate shape is selected depending on the layout of the circuit elements and the like.

[0134] Light emitting element 250 is a light emitting diode similar to light emitting element 150 shown in FIG. 1 above.

[0135] The periphery of the wiring 230a is set to include the periphery of the light-emitting element 250 when the light-emitting element 250 is projected onto the wiring 230a in the XY plane. In other words, the periphery of the light-emitting element 250 is disposed within the periphery of the wiring 230a in the XY plane. The wiring 230a is provided on the surface 102a so as to protrude in one direction from directly below the light-emitting surface 253S. One end of the via 261a is connected to the protruding region of the wiring 230a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power line 3 of the circuit in FIG. 12 described below via the graphene sheet 140a, the wiring 230a, the via 261a, and the wiring 210a.

[0136] The outer periphery of the graphene sheet 140a in the XY plane view substantially coincides with the outer periphery of the light emitting element 250 in the XY plane view, as in the other embodiments described above.

[0137] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the second interlayer insulating film 108, the vias 111s and 111d, and the wiring layer 110.

[0138] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with impurities such as phosphorus (P) and activated to form n-type semiconductor regions. The region 204s is in ohmic contact with the via 111s. The region 204d is in ohmic contact with the via 111d.

[0139] The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0140] In transistor 203, when a voltage higher than that of region 204s is applied to gate 107, a channel is formed in region 204i. The current flowing between regions 204s and 204d is controlled by the voltage applied to region 204s by gate 107. The TFT channel 204 and gate 107 are formed using the same materials and methods as the TFT channel 104 and gate 107 in the other embodiments described above.

[0141] The first wiring layer 110 includes wirings 110s, 110d, and 210a. A part of the wiring 210a is provided above the wiring 230a. The other part of the wiring 210a is connected to, for example, a power supply line 3 shown in FIG. 12, which will be described later.

[0142] The vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108. The via 111s is provided between the wiring 110s and the region 204s. The via 111s electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d. The via 111d electrically connects the wiring 110d and the region 204d. The vias 111s and 111d are formed using the same materials and manufacturing methods as in the other embodiments described above.

[0143] The via (first via) 261k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the upper surface 251U. The via 261k is provided between the wiring (third wiring) 110d and the upper surface 251U, and electrically connects the wiring 110d and the upper surface 251U. Therefore, the n-type semiconductor layer 251 is electrically connected to the region 204d that forms the drain electrode of the transistor 203 via the via 261k, the wiring 110d, and the via 111d.

[0144] The via (second via) 261a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the wiring 230a. The via 261a is provided between the wiring (fourth wiring) 210a and the wiring 230a, and electrically connects the wiring 210a and the wiring 230a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power supply line 3 of the circuit in FIG. 12 via the wiring 230a, the via 261a, and the wiring 210a.

[0145] FIG. 12 is a schematic block diagram illustrating an image display device according to this embodiment. 12, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, subpixels 220 are arranged in a lattice pattern on the XY plane.

[0146] As in the other embodiments described above, pixel 10 includes multiple subpixels 220 that emit light of different colors. Subpixel 220R emits red light. Subpixel 220G emits green light. Subpixel 220B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 220R, 220G, and 220B emitting light at desired brightnesses.

[0147] One pixel 10 includes three subpixels 220R, 220G, and 220B, which are arranged linearly on the X axis, as in this example. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, may have subpixels of different colors arranged in different columns.

[0148] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 12, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0149] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the ground line 4 side. In other words, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0150] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power line 3.

[0151] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

[0152] In this embodiment, the polarity of the drive transistor 226 is n-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of subpixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each subpixel 220 in the selected row. The drive transistor 226 of the subpixel 220 in the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the current that has passed through it.

[0153] The manufacturing method of this embodiment will be described. 13A to 15B are schematic cross-sectional views illustrating a part of the method for manufacturing the image display device of this embodiment. 13A, a substrate 102 is prepared. The substrate 102 is a light-transmitting substrate such as a glass substrate, as in the other embodiments described above. A light-transmitting conductive film 1130 is formed on one surface 102a of the prepared substrate 102. A graphene layer 1140 is formed on the light-transmitting conductive film 1130.

[0154] As shown in FIG. 13B , the semiconductor layer 1150 is formed over the graphene layer 1140. The semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151 formed in this order from the graphene layer 1140 side toward the positive direction of the Z axis. The semiconductor layer 1150 is formed over the graphene layer 1140 as shown within the two-dot chain line in FIG. 13B . As in the other embodiments described above, amorphous deposits 1162 containing Ga, which is a growth seed material, may be deposited on the surface 102a where the graphene layer 1140 is not present. In this example, the deposits 1162 are stacked in this order from the surface 102a toward the positive direction of the Z axis: deposits 1162d, 1162e, and 1162f. Deposit 1162d is shown as being deposited during the formation of p-type semiconductor layer 1153, deposit 1162e is shown as being deposited during the formation of light-emitting layer 1152, and deposit 1162f is shown as being deposited during the formation of n-type semiconductor layer 1151, but this is not limited to this.

[0155] As shown in FIG. 14A, the transparent conductive film 1130 shown in FIG. 13B is processed by etching to form a second wiring layer 230 including wirings 230a.

[0156] 13B is processed by etching to form the light emitting element 250 on the wiring 230a. The graphene layer 1140 shown in FIG. 13B is over-etched during the formation of the light emitting element 250 and formed into a graphene sheet 140a.

[0157] The first interlayer insulating film 156 is formed to cover the surface 102 a, the second wiring layer 230 including the wiring 230 a, the graphene layer 140 including the graphene sheet 140 a, and the light emitting element 250 .

[0158] As shown in FIG. 14B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the Si layer 1104 is formed on the TFT lower layer film 106 and polycrystallized.

[0159] As shown in FIG. 15A, the polycrystalline Si layer 1104 shown in FIG. 14B is processed into an island shape to form a TFT channel 204. An insulating layer 105 is formed to cover the TFT underlayer film 106 and the TFT channel 204. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. The transistor 203 is formed by selectively doping the gate 107 with impurities such as B and thermally activating it. Regions 204s and 204d are n-type active regions and function as the source region and drain region of the transistor 203, respectively. Region 204i is a p-type active region and functions as the channel.

[0160] As shown in FIG. 15B, the second interlayer insulating film 108 is formed to cover the insulating layer 105 and the transistor 203. Vias 111s and 111d are formed to penetrate the second interlayer insulating film 108 and the insulating layer 105. A via hole is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the upper surface 251U, and is filled with a conductive material to form a via (first via) 261k. The via 261k is electrically connected to the upper surface 251U. A via hole is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the wiring 230a, and is filled with a conductive material to form a via (first via) 261a. The via 261a is electrically connected to the wiring 230a. The wiring 110s is connected to the via 111s. The wiring 110d is connected to the via 111d and the via 261k. The wiring 210a is connected to the via 261a. The steps of forming the first wiring layer 110 and connecting it to the vias 111s, 111d, 261a, and 261k may be performed simultaneously with the steps of forming the vias 111s, 111d, 261a, and 261k.

[0161] 11 is formed on the other surface 102b of the substrate 102, thereby forming the subpixels 220. The color filter 180 is preferably formed by the inkjet method described in relation to FIGS. 7A to 7D, but may also be formed by the film attachment method described in relation to FIG. 8. Alternatively, a monochrome image display device may be formed without providing a color filter.

[0162] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 250 and reducing the number of processes. In addition, by setting the polarity of the TFT to p-channel, it becomes possible to use the light-emitting surface 253S as the p-type semiconductor layer 253. This has the advantage of improving the degree of freedom in arranging circuit elements and designing the circuit.

[0163] The second wiring layer 230 including the wiring 230a is formed of a light-transmitting conductive film, so it is easy to introduce into the manufacturing process and to process into a desired shape. In addition, since the second wiring layer 230 has sufficient light-transmittance, there is no need to add a step such as removing the substrate 102 after forming the subpixels 220, which has the advantage of simplifying and shortening the manufacturing process.

[0164] In this embodiment, by connecting the wiring 230a to the light emitting surface 253S via the graphene sheet 140a and connecting one end of the via 261a to the wiring 230a, the p-type semiconductor layer 253 can be electrically connected to an external circuit with low resistance. By adopting a vertical light emitting element structure as in this embodiment, the component of the current flowing in each layer of the light emitting element 250 along the XY plane can be suppressed and directed along the Z axis, and loss within the light emitting element 250 can be reduced.

[0165] In this embodiment, the p-type semiconductor layer 253 and the via 261a are connected by the wiring 230a of the second wiring layer 230, but this can also be applied to the first embodiment. That is, by providing the n-type semiconductor layer 151 on the wiring 230a via the graphene sheet 140a, the n-type semiconductor layer 151 and the via 161k can be connected via the graphene sheet 140a and the wiring 230a.

[0166] (Third embodiment) FIG. 16 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that the light-emitting element 150, whose light-emitting surface 151S is provided by an n-type semiconductor layer 151, is driven by an n-channel transistor 203. This embodiment differs from the other embodiments described above in that a light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 203. The light-emitting element 150 of this embodiment also differs from the other embodiments described above in that the graphene sheet 140a is removed and the light-emitting surface 151S is roughened. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0167] 16, the image display device of this embodiment includes a subpixel 320. The subpixel 320 includes a color filter (light-transmitting member) 180, a light-emitting element 150, a first interlayer insulating film 156, a light-shielding layer 330, a transistor 203, a second interlayer insulating film 108, a via (first via) 361a, and a first wiring layer 110.

[0168] In this embodiment, the light emitting element 150 is provided on the connection surface (first surface) 180S of the color filter 180 and has a roughened light emitting surface 151S. A transparent resin layer 188 is provided between the roughened light emitting surface 151S and the color filter 180. The transparent resin layer 188 is also provided on one surface 156S1 of the first interlayer insulating film 156, and the light emitting element 150 and the first interlayer insulating film 156 are provided on the connection surface 180S of the color filter 180 via the transparent resin layer 188. The transparent resin layer 188 is formed to cover the surface 156S1 and the light emitting surface 151S, and forms a relatively flat plane, making it easier to form the color filter 180.

[0169] The light emitting element 150 has an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153 laminated in this order from the light emitting surface 151S toward the upper surface 153U. The light emitting surface 151S, which is the n-type semiconductor layer 151, is provided on a connection surface 180S of the color filter 180. The connection surface 180S is a surface that contacts the transparent resin layer 188. The light emitting element 150 emits light in the negative direction of the Z axis via the transparent resin layer 188 and the color conversion unit 182 of the color filter 180.

[0170] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided so as to protrude in one direction from the n-type semiconductor layer 151 on the connection surface 180S. In this example, the connection portion 151a is provided so as to protrude in a direction different from that in the other embodiments described above. The shape and configuration of the connection portion 151a are the same as in the first embodiment, and the shape and configuration of the light-emitting element 150 are also the same as in the first embodiment. One end of a via 361k is connected to the connection portion 151a.

[0171] The light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. The TFT lower film 106 and the insulating layer 105 are provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. Therefore, more specifically, the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the TFT lower film 106. That is, the light-shielding layer 330 is provided over the other surface 156S2 of the first interlayer insulating film 156. The other surface 156S2 is the surface opposite to the one surface 156S1 of the first interlayer insulating film 156. The light-shielding layer 330 is provided over the entire surface, except for a portion, between the first interlayer insulating film 156 and the TFT lower film 106.

[0172] The light-shielding layer 330 is formed of a material having light-shielding properties. The material of the light-shielding layer 330 may be conductive or non-conductive as long as it has light-shielding properties, and may be formed of, for example, a metal material having light reflectivity as in this example. The light-shielding layer 330 includes through-holes 331a and 331k. The through-hole 331a is provided at a position through which the via 361a of the light-shielding layer 330 passes in the XY plane view. The diameter of the through-hole 331a is set larger than the diameter of the via 361a so that the light-shielding layer 330 does not come into contact with the via 361a when the via 361a passes through the through-hole 331a. The through-hole 331k is provided at a position through which the via 361k of the light-shielding layer 330 passes in the XY plane view. The diameter of the through hole 331k is set larger than the diameter of the via 361k so that the light blocking layer 330 does not come into contact with the via 361k when the via 361k is passed through the through hole 331k.

[0173] The via 361a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the upper surface 153U. The via 361k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the connection portion 151a.

[0174] In the above description, the light-shielding layer 330 is formed from a metal material, but the light-shielding layer 330 may be formed from a resin that does not have electrical conductivity. In this case, the resin is, for example, a black resin from the viewpoint of light-shielding properties. When the light-shielding layer 330 is formed from a black resin, the vias can be formed by forming via holes together with the first interlayer insulating film 156 and the like and filling them with a conductive material, without previously forming through holes 331k, 331a having diameters larger than those of the vias 361k, 361a.

[0175] The light-shielding layer 330 is provided to cover the TFT channel 204. The light-shielding layer 330 is formed so as to include the outer periphery of the TFT channel 204 when the TFT channel 204 is projected onto the light-shielding layer 330 in the XY plane view. In other words, the outer periphery of the TFT channel 204 is disposed within the outer periphery of the light-shielding layer 330 in the XY plane view. Even when scattered light or the like is emitted upward from the light-emitting element 150 provided below the TFT channel 204, the light-shielding layer 330 blocks the scattered light or the like, and the scattered light or the like is hardly able to reach the TFT channel, thereby suppressing malfunction of the transistor 203.

[0176] From the viewpoint of light-blocking properties, it is desirable that the light-blocking layer 330 be provided over the entire surface between the first interlayer insulating film 156 and the second interlayer insulating film 108, as in this example; however, the light-blocking layer 330 is not limited to being a single physical component. For example, the light-blocking layer 330 may be provided separately in a portion directly below the TFT channel 204 and a portion directly above the light-emitting element 150. In this example, the light-blocking layer 330 is not connected to any potential, but may be connected to a specific potential such as ground potential or power supply potential. When the light-blocking layer 330 has multiple separated portions, all of the portions may be connected to a common potential, or each portion may be connected to a different potential.

[0177] The first wiring layer 110 is provided on the second interlayer insulating film 108. The first wiring layer 110 includes wirings 110s, 110d, and 310a.

[0178] The via 111s is provided between the wiring 110s and the region 204s, and electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d, and electrically connects the wiring 110d and the region 204d.

[0179] The wiring 110s is connected to the region 204s through the via 111s. The region 204s is the source region of the transistor 203. Therefore, the source region of the transistor 203 is electrically connected to, for example, the ground line 4 shown in FIG. 12 through the via 111s and the wiring 110s.

[0180] The wiring 110d is connected to the region 204d through a via 111d. The region 204d is the drain region of the transistor 203. One end of the wiring 110d is provided above the connection portion 151a. One end of the wiring 310a is provided above the light emitting element 150. The wiring 310a is electrically connected to the power supply line 3 in FIG.

[0181] The via 361k is provided between the wiring 110d and the connection portion 151a and electrically connects the wiring 110d and the connection portion 151a. Therefore, the drain region of the transistor 203 is electrically connected to the n-type semiconductor layer 151 via the via 111d, the wiring 110d, the via 361k, and the connection portion 151a.

[0182] The via 361a is provided between the wiring 310a and the upper surface 153U, and electrically connects the wiring 310a and the upper surface 153U. Therefore, the p-type semiconductor layer 153 is electrically connected to the power supply line 3 through the via 361a and the wiring 310a.

[0183] A method for manufacturing the image display device of this embodiment will be described. 17A to 18B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. In this example, the steps up to the step described in relation to Fig. 5A are applied in the same manner as in the first embodiment. In the following description, the steps from Fig. 17A onwards are applied after the step of Fig. 5A. However, as described above, in this embodiment, the protruding direction of the connection portion 151a is different from that in Fig. 5A.

[0184] 17A, a light-shielding layer 330 is formed over the surface 156S2 of the first interlayer insulating film 156. Through-holes 331a and 331k are formed through the light-shielding layer 330 to expose the surface 156S2.

[0185] 17B, ​​the TFT lower layer film 106 is formed on the light-shielding layer 330 and the exposed surface 156S2. The through-holes 331a and 331k are filled with a material that forms the TFT lower layer film 106, and then the TFT lower layer film 106 is planarized. The TFT channel 204 is formed on the planarized TFT lower layer film 106. The insulating layer 105 is formed to cover the TFT channel 204, and the gate 107 is formed on the insulating layer 105 to form the transistor 203. These steps can be performed using the LTPS process in the same manner as in the second embodiment.

[0186] 18A, a second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107, and vias 111s, 111d, 361k, and 361a are formed therein. A first wiring layer 110 is formed on the second interlayer insulating film 108, and the via 111s is connected to the wiring 110s, the vias 111d and 361k are connected to the wiring 110d, and the via 361a is connected to the wiring 310a. These steps are the same as those in the other embodiments described above.

[0187] As shown in FIG. 18B, an adhesive layer 1170 is applied onto the second interlayer insulating film 108 and the first wiring layer 110, and a reinforcing substrate 1180 is adhered by the adhesive layer 1170.

[0188] Thereafter, the substrate 102 and the graphene sheet 140a shown in FIG. 18A are removed sequentially or simultaneously by wet etching or laser lift-off.

[0189] After removing the graphene sheet 140a, the exposed light-emitting surface 151S is roughened by, for example, wet etching.

[0190] Thereafter, a transparent resin layer 188 is provided to cover the surface 156S1 and the light-emitting surface 151S, thereby forming a substantially planar color filter forming surface 188S. The color filter 180 shown in FIG. 16 is formed on the color filter forming surface 188S, thereby forming subpixels. If a monochrome image display device is to be formed without providing a color filter, the substrate 102 shown in FIG. 18A is not removed. In this case, the light-emitting surface 151S is not roughened.

[0191] The effects of the image display device of this embodiment will be described. In the manufacturing method of the image display device of this embodiment, similar to the other embodiments described above, there are effects of shortening the time for the transfer step for forming light emitting element 150 and reducing the number of steps, and in addition, since light emitting surface 151S is made of n-type semiconductor layer 151, which has a lower resistance than p-type, n-type semiconductor layer 151 can be formed thick and light emitting surface 151S can be sufficiently roughened. In the image display device of this embodiment, roughening light emitting surface 151S diffuses the emitted light, so even small light emitting element 150 can be used as a light source with a sufficient light emitting area.

[0192] In this embodiment, the light emitting element 150, whose light emitting surface 151S is the n-type semiconductor layer 151, can be driven by the n-channel transistor 203. This increases the degree of freedom in circuit configuration, and improves design efficiency.

[0193] In the image display device of this embodiment, the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. That is, the light-shielding layer 330 is provided between the light-emitting element 150 and the transistor 203. Therefore, even if scattered light or the like is emitted upward from the light-emitting element 150, the emitted light is unlikely to reach the TFT channel 204, and malfunction of the transistor 203 can be prevented.

[0194] The light-shielding layer 330 can be formed of a conductive material such as metal, and can be connected to any potential. For example, by arranging a part of the light-shielding layer 330 directly under a switching element such as the transistor 203 and connecting it to a ground potential or a power supply potential, it can be used to suppress noise.

[0195] The light-shielding layer 330 is not limited to application in this embodiment, but can be commonly applied to the subpixels of the other embodiments described above and other embodiments to be described later. Even when applied to other embodiments, the same effects as those described above can be obtained.

[0196] In this embodiment, in order to roughen the light-emitting surface 151S, the substrate 102 and the graphene sheet 140a are removed and then the color filter 180 is formed. As described above, the roughened surface of the light-emitting surface 151S allows the light to efficiently emit light and allows the light to reach the color filter 180 without passing through the substrate 102, the graphene sheet 140a, or the like. Therefore, even with low-luminance emission, it is possible to display a high-resolution image, which can contribute to low power consumption.

[0197] In the above example, the configuration and manufacturing method of a light-emitting element having a roughened light-emitting surface have been described. A light-emitting element having a connection portion can have a roughened light-emitting surface, as in the present embodiment. Specifically, the configuration of a light-emitting element having a roughened light-emitting surface can be applied to the light-emitting element 150 in the first embodiment, the light-emitting element 250 in the second embodiment, and the light-emitting element 650 in the sixth embodiment. A roughened light-emitting surface can also be applied to the semiconductor layer 750 in the seventh embodiment, which will be described later. By roughening the light-emitting surfaces of the components of these light-emitting elements, the above-mentioned effects can be achieved.

[0198] (Fourth embodiment) FIG. 19 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment , release This embodiment differs from the other embodiments described above in that it includes a third wiring layer 470 on the optical element 150. In other respects, it is the same as the other embodiments described above, and the same components are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0199] 19 , a subpixel 420 of the image display device of this embodiment includes a substrate 102, a second wiring layer 230, a graphene layer 140, a light-emitting element 150, a third wiring layer 470, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 461a, and a first wiring layer 110. The subpixel 420 further includes a color filter 180.

[0200] As in the second embodiment, the second wiring layer 230 is provided on one surface 102a of the substrate 102. The second wiring layer 230 includes a plurality of wirings 230a. The plurality of wirings 230a is provided for each light-emitting element 150. A graphene sheet 140a is provided on the wirings 230a, and the light-emitting element 150 is provided on the wirings 230a via the graphene sheet 140a. The configurations and functions of the second wiring layer 230 including the wirings 230a and the graphene layer 140 including the graphene sheet 140a are the same as in the second embodiment, and detailed description thereof will be omitted.

[0201] A resin layer 457 is provided covering the surface 102a, the second wiring layer 230, the graphene layer 140, and the light-emitting element 150. The resin layer 457 is, for example, a transparent resin. A third wiring layer 470 is provided on the resin layer 457. The third wiring layer 470 may include a plurality of wirings. For example, some of the plurality of wirings may be physically separated and may be electrically at different potentials. Other parts of the plurality of wirings are physically connected. In this example, the third wiring layer 470 includes separated wirings 470a and 470b.

[0202] The wiring (first light-shielding electrode) 470a is provided over and to the sides of the light-emitting element 150, covering the upper surface 153U and side surfaces of the light-emitting element 150. The wiring 470a covers most of the light-emitting element 150 except for the light-emitting surface 151S, and thus the wiring 470a blocks scattered light and reflected light to the sides and above the light-emitting element 150. The connection electrode 462a is provided between the upper surface 153U and the wiring 470a, and electrically connects the upper surface 153U and the wiring 470a. The wiring 470a functions as a light-shielding electrode.

[0203] When resin layer 457 is made of a transparent resin, scattered light and the like emitted from above or the sides of light emitting element 150 is reflected by wiring 470a toward light emitting surface 151S, thereby improving the substantial light emitting efficiency of light emitting element 150. When resin layer 457 is made of a material with high light reflectivity, such as white resin, wiring 470a is further provided on resin layer 457, thereby achieving even higher light reflectivity.

[0204] The via (first via) 461a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the wiring (first light-shielding electrode) 470a. The via 461a is provided between the wiring 110d and the wiring 470a, and electrically connects the wiring 110d and the wiring 470a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection electrode 462a, the wiring 470a, the via 461a, the wiring 110d, and the via 111d.

[0205] The via 461k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the first interlayer insulating film 156, and the resin layer 457, and to reach the wiring 230a. The via 461k is provided between the wiring 110k and the wiring 230a, and electrically connects the wiring 110k and the wiring 230a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 of the circuit in FIG. 2 via the graphene sheet 140a, the wiring 230a, the via 461k, and the wiring 110k.

[0206] The first interlayer insulating film 156 is provided to cover the resin layer 457 and the third wiring layer 470. The configurations of the TFT lower layer film 106 and the circuit 101 provided on the first interlayer insulating film 156 are the same as those in the other embodiments described above, and detailed description thereof will be omitted.

[0207] A method for manufacturing the image display device of this embodiment will be described. 20A to 22B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. 13A and 13B are applied to the manufacturing method of the image display device of this embodiment, and the following description applies to the steps from FIG. 13B onward. However, in FIG. 13B , a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151 are stacked in this order on a graphene layer 1140 on a light-transmitting conductive film 1130, from the graphene layer 1140 side toward the positive direction of the Z axis. In this embodiment, the semiconductor layer 1150 is formed by stacking the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 in this order from the graphene layer 1140 side toward the positive direction of the Z axis. The techniques described in the first and second embodiments above are applied to the process of forming the semiconductor layer 1150.

[0208] As shown in Fig. 20A, the translucent conductive film 1130 shown in Fig. 13B is processed by etching to form a second wiring layer 230 including wiring 230a. The semiconductor layer 1150 shown in Fig. 13B is processed by etching to form the light emitting element 150. The graphene layer 1140 shown in Fig. 13B is over-etched during the formation of the light emitting element 150 and formed into a graphene sheet 140a.

[0209] The resin layer 457 is formed to cover the surface 102a, the wiring 230a, the graphene sheet 140a, and the light emitting element 150. An opening 463a is formed in the resin layer 457 so that a part of the upper surface 153U of the light emitting element 150 is exposed.

[0210] 20B, metal layer 1470 is formed to cover resin layer 457. When forming metal layer 1470, opening 463a shown in FIG. 20A may be filled at the same time to form connection electrode 462a, or opening 463a may be filled to form connection electrode 462a, and then metal layer 1470 may be formed.

[0211] 21A, the metal layer 1470 shown in FIG. 20B is processed by etching to form the third wiring layer 470. When the third wiring layer 470 is formed, wirings 470a and 470b are formed separately. The wiring 470a is formed so as to cover the upper surface 153U and side surfaces of the light emitting element 150. A first interlayer insulating film 156 is formed to cover the resin layer 457 and the third wiring layer 470.

[0212] As shown in FIG. 21B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and a polycrystallized Si layer 1104 is formed on the TFT lower layer film 106.

[0213] As shown in FIG. 22A, the TFT channel 104, the insulating layer 105, the gate 107, and the regions 104s, 104d, and 104i are formed using an LTPS process or the like.

[0214] 22B, vias 111s, 111d, 461a, and 461k are formed, and the first wiring layer 110 is formed on the second interlayer insulating film 108. The via 461k is formed by filling a via hole formed so as to reach the wiring 230a with a conductive material. The techniques described in the manufacturing methods for the image display devices of the other embodiments described above can be applied to the details of the manufacturing steps of FIGS. 21A to 22B.

[0215] Thereafter, a color filter 180 is formed on the other surface 102b of the substrate 102, thereby forming sub-pixels 420. As shown in Fig. 10, a monochrome image display device may be formed without providing a color filter.

[0216] The effects of the image display device of this embodiment will be described. As with the other embodiments described above, the image display device of this embodiment has the advantage of being able to shorten the time required for the transfer process to form the light emitting element 150 and reduce the number of processes. In addition, the image display device of this embodiment has the following advantages.

[0217] In the image display device of this embodiment, the subpixel 420 includes a third wiring layer 470. The third wiring layer 470 is electrically isolated from the light-emitting element 150 by a resin layer 457. The third wiring layer 470 includes a wiring 470a, which covers the upper surface 153U and side surfaces of the light-emitting element 150 via the resin layer 457. This allows for blocking of scattered light and the like above and to the sides of the light-emitting element 150. Even though the transistor 103 is provided above the light-emitting element 150, the wiring 470a blocks scattered light and the like above and to the sides of the light-emitting element 150, thereby preventing the scattered light and the like from reaching the transistor 103. This prevents malfunction of the transistor 103 due to scattered light and the like from the light-emitting element 150. Note that the wiring 470b, which is formed simultaneously with the wiring 470a, can be used for connection to other circuit elements and the like, thereby contributing to efficient wiring layout.

[0218] Additionally, in this embodiment, similarly to the second embodiment, a second wiring layer 230 formed by processing a translucent conductive film is provided, and wiring 230a is connected to the light emitting surface 151S. This facilitates processing, and enables simplification and shortening of the manufacturing process.

[0219] Furthermore, because of the vertical light emitting element structure, the current component flowing in the horizontal direction is suppressed, which has the advantage of reducing loss inside the light emitting element 150.

[0220] (Fifth embodiment) FIG. 23 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. This embodiment differs from the other embodiments described above in that a light-shielding electrode 560a is provided to cover the upper surface 153U of the light-emitting element 150, and the light-shielding electrode 560a is connected to wiring 510d formed on the wall surface of the through-hole 511a. In this example, a light-transmitting substrate such as a glass substrate is thinned, and a color filter 180 is provided on the thinned substrate 502. In other respects, this embodiment is the same as the other embodiments, and the same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0221] As shown in FIG. 23, the subpixel 520 of the image display device of this embodiment includes a substrate 502, a second wiring layer 230, a graphene layer 140, a light-emitting element 150, a light-shielding electrode 560a, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, and a first wiring layer 110.

[0222] The substrate 502 has two surfaces 502a and 502b. The surface 502b is the surface opposite to the surface 502a. The substrate 502 is a light-transmitting substrate, such as a glass substrate. The substrate 502 may be a glass substrate or a light-transmitting resin substrate. The light-emitting element 150 is provided on one surface (first surface) 502a of the substrate 502. A color filter 180 is provided on the other surface 502b of the substrate 502. The color filter 180 is the same as in the other embodiments described above.

[0223] The light-emitting element 150 is provided on the wiring 230a of the second wiring layer 230 via the graphene sheet 140a, and is electrically connected to the wiring 230a at the light-emitting surface 151S via the graphene sheet 140a. The configurations of the second wiring layer 230 including the wiring 230a, the graphene layer 140 including the graphene sheet 140a, the light-emitting element 150, and the first interlayer insulating film 156 are the same as those in the other embodiments described above. The via 461k is also the same as in the fourth embodiment described above in that it electrically connects the wiring 110k and the wiring 230a between them. The configuration of the transistor 103 on the TFT lower layer film 106 is also the same as those in the other embodiments described above. Detailed description of these elements will be omitted.

[0224] A through-hole 511a is provided above the light-emitting element 150. The through-hole 511a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the upper surface 153U. The inner periphery of the through-hole 511a in the XY plane view is the same as the outer periphery of the upper surface 153U in the XY plane view, or is provided to be slightly inside the outer periphery of the upper surface 153U in the XY plane view.

[0225] The light-shielding electrode (second light-shielding electrode) 560a is provided across the upper surface 153U. Since the light-shielding electrode 560a is provided at the bottom of the through-hole 511a, the outer periphery of the light-shielding electrode 560a in the XY plane view approximately matches the inner periphery of the through-hole 511a in the XY plane view. Therefore, the light-shielding electrode 560a is provided so as to cover all or most of the upper surface 153U.

[0226] The light-shielding electrode 560a blocks scattered light and other light emitted upward from the light-emitting element 150. This prevents the scattered light and other light emitted upward from reaching the transistor 103, thereby preventing the transistor 103 from malfunctioning. Light reflectivity can be improved by forming the light-shielding electrode 560a from a highly reflective material such as Ag or by providing an ITO film between the light-shielding electrode 560a and the upper surface 153U. By improving light reflectivity, scattered light and other light emitted toward the upper surface 153U can be reflected toward the light-emitting surface 151S, thereby improving the substantial light-emitting efficiency of the light-emitting element 150. The light-shielding electrode 560a can be integrally formed with the wiring 510d formed on the wall surface of the through-hole 511a. Therefore, the light-shielding electrode 560a and the wiring 510d function as the vias (first vias) 161a and the like that connect the first wiring layer 110 and the upper surface of the light-emitting element 150 in the other embodiments described above.

[0227] The first wiring layer 110 includes a wiring 510d. The wiring 510d is provided on the second interlayer insulating film 108, and is also provided on the wall surface of the through-hole 511a, and is connected to the light-shielding electrode 560a at the bottom of the through-hole 511a. The wiring 510d is connected to the drain region of the transistor 103 through the via 111d, and therefore the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 through the light-shielding electrode 560a, the wiring 510d, and the via 111d.

[0228] The other components, such as the transistor 103, are the same as those in the other embodiments described above, and detailed description thereof will be omitted.

[0229] A method for manufacturing the image display device of this embodiment will be described. 24A to 25B are schematic cross-sectional views illustrating a part of a method for manufacturing the image display device of this embodiment. 13A and 13B are applied to the manufacturing method of the image display device of this embodiment, and the following description applies to the steps from Fig. 13B onwards. Note that the polarity of the semiconductor layer 1150 shown in Fig. 13B is opposite to that in the second embodiment, as in the fourth embodiment.

[0230] As shown in Fig. 24A, the translucent conductive film 1130 shown in Fig. 13B is processed by etching to form the second wiring layer 230 including the wiring 230a. The semiconductor layer 1150 shown in Fig. 13B is processed by etching to form the light emitting element 150. The graphene layer 1140 shown in Fig. 13B is over-etched during the formation of the light emitting element 150 and is shaped into the graphene sheet 140a. The first interlayer insulating film 156 is formed to cover the surface 102a, the second wiring layer 230 including the wiring 230a, the graphene layer 140 including the graphene sheet 140a, and the light emitting element 150.

[0231] 24B, a through-hole 511a is formed so as to penetrate through the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 provided above the upper surface 153U of the light-emitting element 150, and reach the upper surface 153U. By forming the through-hole 511a, a part of the upper surface 153U is exposed from the opening 511.

[0232] It is preferable that the entire upper surface 153U is exposed by the opening 511 of the through hole 511a, but this is set according to the accuracy of forming the through hole 511a. For example, the inner circumference of the through hole 511a in the XY plane is set to be slightly smaller than the outer circumference of the upper surface 153U in the XY plane.

[0233] A via hole 462k is formed, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and reaching the wiring 230a. A via hole 112d is formed, penetrating the second interlayer insulating film 108 and the insulating layer 105, and reaching the region 104d. A via hole 112s is formed, penetrating the second interlayer insulating film 108 and the insulating layer 105, and reaching the region 104s. The via holes 462k, 112d, and 112s are formed, for example, simultaneously. The through hole 511a may be formed simultaneously with the via holes 462k, 112d, and 112s, or may be formed separately.

[0234] 25A, the via holes 462k, 112d, and 112s shown in FIG. 24B are filled with a conductive material to form vias 461k, 111d, and 111s. When the vias 461k, 111d, and 111s are formed, the bottoms of the through holes 511a, i.e., the upper surfaces 153U, may be covered with a conductive material.

[0235] The first wiring layer 110 is formed on the second interlayer insulating film 108. When forming the first wiring layer 110, a conductive layer that forms the first wiring layer 110 is formed on the second interlayer insulating film 108 and processed by etching to form the first wiring layer 110 including the wirings 110k, 510d, and 110s. The conductive layer is formed not only on the second interlayer insulating film 108 but also on the exposed upper surface 153U and the wall surfaces of the through holes 511a.

[0236] In this way, the wiring 110k connected to the via 461k is formed, the wiring 510d connected to the via 111d is formed, and the wiring 110s connected to the via 111s is formed. The wiring 510d is provided over the wall surface of the through-hole 511a, and is therefore also connected to the upper surface 153U.

[0237] An adhesive layer 1170 is provided on the second interlayer insulating film 108 and the first wiring layer 110, and a reinforcing substrate 1180 is bonded by the adhesive layer 1170. Thereafter, the substrate 102 shown in FIG. 24B is thinned by wet etching or the like and processed into a thin substrate 502.

[0238] As shown in FIG. 25B, a color filter 180 is formed on the other surface 502b of the substrate 502.

[0239] When the substrate 502 is a light-transmitting resin substrate, the substrate 502 may be, for example, a resin layer formed on a glass substrate. After light-emitting elements and the like are formed on the resin layer substrate 502, the glass substrate is removed by wet etching or the like, and then a color filter 180 is formed on the surface 502b from which the glass substrate has been removed. As shown in FIG. 10, a monochrome image display device may be formed without providing a color filter. In that case, the thinning process of the substrate 102 shown in FIG. 24B may be omitted.

[0240] In this way, sub-pixels 520 are formed.

[0241] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light emitting element 150 and reducing the number of processes. In addition, since the light-shielding electrode 560a is provided over the upper surface 153U, it is possible to block scattered light and the like emitted upward by the light emitting element 150. The light-shielding electrode 560a prevents light from reaching the transistor 103 provided above the light emitting element 150, thereby preventing malfunction.

[0242] In this embodiment, there is no need to add a step for forming the light-shielding electrode 560a because the light-shielding electrode 560a can be formed at the same time as the via formation and the first wiring layer 110. This reduces the manufacturing process and shortens the time from inputting materials to completing the product.

[0243] (Sixth embodiment) FIG. 26 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the configuration of the light-emitting element 650 differs from that of the other embodiments. The other components are the same as those of the other embodiments described above. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. 26, the image display device includes a subpixel 620. The subpixel 620 includes a color filter (light-transmitting member) 180, a second wiring layer 230, a graphene layer 140, a light-emitting element 650, a first interlayer insulating film 156, a light-shielding layer 330, a transistor 103, a second interlayer insulating film 108, and a first wiring layer 110.

[0244] The light emitting element 650 is provided on the connection surface (first surface) 180S of the color filter 180 via a transparent resin layer 188. As with the other embodiments described above, wiring 230a is provided on the transparent resin layer 188, and a graphene sheet 640a is provided on the wiring 230a. Also, as with the fourth and fifth embodiments described above, the light emitting element 650 is provided on the graphene sheet 640a. A surface 156S1 on the light emitting surface 651S side of the first interlayer insulating film 156 is also provided on the connection surface 180S of the color filter 180 via a transparent resin layer 188.

[0245] Light-emitting element 650 includes light-emitting surface 651S and top surface 653U, which is the surface opposite to light-emitting surface 651S. Light-emitting element 650 has n-type semiconductor layer 651, light-emitting layer 652, and p-type semiconductor layer 653 laminated in this order from light-emitting surface 651S toward top surface 653U. As will be described later with reference to FIG. 27 , light-emitting element 650 has a truncated pyramid or truncated cone shape formed so that the area in the XY plane view gradually decreases from light-emitting surface 651S toward top surface 653U.

[0246] In this embodiment, a light-shielding layer 330 is provided between the TFT lower film 106 and the first interlayer insulating film 156. The light-shielding layer 330 is the same as that described in the third embodiment with reference to FIG. 16. Therefore, the light-shielding layer 330 is provided so as to cover the TFT channel 104, and can block light emitted from the light-emitting element 650, thereby preventing malfunction of the transistor 103 including the TFT channel 104.

[0247] The via 461k is provided in the same manner as in the fourth embodiment. That is, the via 461k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156 and reach the wiring 230a. The via 461k is provided between the wiring 110k and the wiring 230a, and electrically connects the wiring 110k and the wiring 230a.

[0248] The via 661a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, the light-shielding layer 330, and the first interlayer insulating film 156, and to reach the upper surface 653U. The via 661a is provided between the wiring 110d and the upper surface 653U, and electrically connects the wiring 110d and the upper surface 653U. The other components are the same as those in the other embodiments described above, and detailed description thereof will be omitted.

[0249] FIG. 27 is an enlarged view of the light emitting element 650 in FIG. 26, showing in detail the relationship between the light emitting surface 651S and the side surface 655a. 27, the light-emitting surface 651S is a plane substantially parallel to the XY plane. The light-emitting element 650 is provided on the connection surface 180S of the color filter via the transparent resin layer 188, and the light-emitting surface 651S is a plane substantially parallel to the connection surface 180S.

[0250] In the following, for simplicity, the first interlayer insulating film 156 will be described as being made of a transparent resin, but even if the first interlayer insulating film 156 is made of a white resin, the effect of the scattering particles in the white resin on the refractive index is small and can be ignored.

[0251] The side surface 655a of the light-emitting element 650 is a surface between the upper surface 653U and the light-emitting surface 651S, and is a surface adjacent to the light-emitting surface 651S and the upper surface 653U. The interior angle θ between the side surface 655a and the light-emitting surface 651S is smaller than 90°. Preferably, the interior angle θ is approximately 70°. More preferably, the interior angle θ is smaller than a critical angle of the side surface 655a, which is determined based on the refractive index of the light-emitting element 650 and the refractive index of the first interlayer insulating film 156. The light-emitting element 650 is covered with the first interlayer insulating film 156, and the side surface 655a is in contact with the first interlayer insulating film 156.

[0252] The critical angle θc of the interior angle θ formed between the side surface 655a of the light emitting element 650 and the light emitting surface 651S is determined, for example, as follows. When the refractive index of light emitting element 650 is n0 and the refractive index of first interlayer insulating film 156 is n1, the critical angle θc of light emitted from light emitting element 650 to first interlayer insulating film 156 is found using the following equation (1).

[0253] θc=90°-sin -1 (n1 / n0) (1)

[0254] For example, it is known that the refractive index of a general transparent organic insulating material such as acrylic resin is approximately 1.4 to 1.5. Therefore, when the light emitting element 650 is made of GaN and the first interlayer insulating film 156 is made of a general transparent organic insulating material, the refractive index n0 of the light emitting element 650 is 2.5, and the refractive index n0 of the first interlayer insulating film 156 is 1.4 to 1.5. n1 = 1.4. By substituting these values ​​into equation (1), we obtain the critical angle θc = 56°.

[0255] This indicates that when the internal angle θ between light-emitting surface 651S and side surface 655a is θc = 56°, light emitted from light-emitting layer 652 that is parallel to light-emitting surface 651S is totally reflected by side surface 655a. It also indicates that light emitted from light-emitting layer 652 that has a component in the positive direction of the Z axis is totally reflected by side surface 655a.

[0256] On the other hand, of the light emitted from light-emitting layer 652, light having a component in the negative direction of the Z axis is emitted from side surface 655a at an emission angle according to the refractive index at side surface 655a. Light incident on first interlayer insulating film 156 is emitted from first interlayer insulating film 156 at an angle determined by the refractive index of first interlayer insulating film 156.

[0257] The light totally reflected by side surface 655a is reflected again by upper surface 653U, and the light having a component in the negative direction of the Z axis among the reflected light is emitted from light-emitting surface 651S and side surface 655a. The light parallel to light-emitting surface 651S and the light having a component in the positive direction of the Z axis are totally reflected by side surface 655a.

[0258] In this way, of the light emitted from light-emitting layer 652, light parallel to light-emitting surface 651S and light having a component in the positive direction of the Z axis are converted by side surface 655a into light having a component directed in the negative direction of the Z axis. Therefore, the proportion of light emitted from light-emitting element 650 that is directed toward light-emitting surface 651S increases, and the substantial luminous efficiency of light-emitting element 650 improves.

[0259] By setting θ<θc, most of the light having a component parallel to the light-emitting surface 651S can be totally reflected inside the light-emitting element 650. If the refractive index of the first interlayer insulating film 156 is n=1.4, the critical angle θc is approximately 56°, so it is more preferable to set the interior angle θ to 45°, 30°, or the like. Furthermore, the critical angle θc becomes smaller for materials with a larger refractive index n. However, even if the interior angle θ is set to approximately 70°, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis. Therefore, taking into account manufacturing variations and the like, the interior angle θ may be set to, for example, 80° or less.

[0260] A method for manufacturing the image display device of this embodiment will be described. In this embodiment, the manufacturing process of the light emitting device 650 is different from that of the other embodiments, and the other manufacturing processes can be applied to the other embodiments described above. The different parts of the manufacturing process will be described below. In this embodiment, in order to obtain the shape of the light emitting device 650 shown in FIG. 26, the following steps are performed for the steps shown in FIG. 13B and thereafter. The semiconductor layer 1150 shown in FIG. 13B is etched into the shape of the light-emitting element 650 shown in FIG. 26. To form the light-emitting element 650, an etching rate is selected so that the side surface 655a shown in FIG. 27 forms an interior angle θ with the light-emitting surface 651S. For example, a higher etching rate is selected closer to the top surface 653U. Preferably, the etching rate is set to increase linearly from the light-emitting surface 651S side toward the top surface 653U side.

[0261] Specifically, for example, the resist mask pattern for dry etching is designed to become gradually thinner toward its edge during exposure. This allows the resist to gradually recede from the thinner portion during dry etching, increasing the amount of etching from the light-emitting surface 651S toward the top surface 653U. As a result, the side surface 655a of the light-emitting element 650 is formed to form a certain angle with respect to the light-emitting surface 651S. Therefore, in the light-emitting element 650, the areas of the layers from the top surface 653U in an XY plane view are formed so that the areas increase in the order of p-type semiconductor layer 653, light-emitting layer 652, and n-type semiconductor layer 651.

[0262] Thereafter, subpixels 620 are formed in the same manner as in the other embodiments. As shown in Fig. 10, a monochrome image display device may be formed without providing a color filter. In that case, the process of removing the substrate can be omitted, as in the third embodiment.

[0263] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 650 and reducing the number of processes, as well as the following effects. In the image display device of this embodiment, light emitting element 650 is formed to have a side surface 655a that forms an interior angle θ with respect to light emitting surface 651S on which light emitting element 650 is provided. Interior angle θ is set to be smaller than 90° based on a critical angle θc that is determined by the refractive indexes of the materials of light emitting element 650 and first interlayer insulating film 156. Interior angle θ enables light emitted from light emitting layer 652 that is directed to the side or above light emitting element 650 to be converted into light directed toward light emitting surface 651S and then emitted. By making interior angle θ sufficiently small, the substantial light emitting efficiency of light emitting element 650 is improved.

[0264] In this embodiment, the light emitting element 650 is a vertical element, and is connected to the via 461k using the wiring 230a of the second wiring layer 230. However, as in the first embodiment, the light emitting element may be provided with a connection portion formed on the connection surface 180S, and connected to the via 461k through the connection portion.

[0265] (Seventh embodiment) FIG. 28 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. In this embodiment, the image display device differs from the other embodiments in that it includes a subpixel group 720 including a plurality of light-emitting regions on one light-emitting surface. The same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate. 28, the image display device of this embodiment includes a subpixel group 720. The subpixel group 720 includes a substrate (light-transmitting member) 102, a graphene layer 140, a semiconductor layer 750, a first interlayer insulating film (first insulating film) 156, a plurality of transistors 103-1 and 103-2, a second interlayer insulating film (second insulating film) 108, a plurality of vias (first vias) 761a1 and 761a2, and a first wiring layer 110. The subpixel group 720 further includes a color filter 180. The semiconductor layer 750 is provided on one surface (first surface) 102a of the substrate 102, and the color filter 180 is provided on the other surface of the substrate 102.

[0266] In this embodiment, turning on the p-channel transistors 103-1 and 103-2 injects holes from one side of the semiconductor layer 750 through the first wiring layer 110 and vias 761a1 and 761a2. Turning on the p-channel transistors 103-1 and 103-2 injects electrons from the other side of the semiconductor layer 750 through the first wiring layer 110 and vias 761k. Holes and electrons are injected into the semiconductor layer 750, and the recombination of the holes and electrons causes the separated light-emitting layers 752a1 and 752a2 to emit light. The drive circuit for driving the light-emitting layers 752a1 and 752a2 may have the circuit configuration shown in FIG. 2, for example. Using the example of the second embodiment, the n-type and p-type semiconductor layers of the semiconductor layers may be interchanged, and the semiconductor layers may be driven by n-channel transistors. In this case, the drive circuit may have the circuit configuration shown in FIG. 12.

[0267] The configuration of the sub-pixel group 720 will now be described in detail. The semiconductor layer 750 has a light emitting surface 751S. The light emitting surface 751S is provided on and in contact with one surface 102a of the substrate 102. The light emitting surface 751S is a surface of the n-type semiconductor layer 751. The light emitting surface 751S includes a plurality of light emitting regions 751R1 and 751R2.

[0268] The semiconductor layer 750 includes an n-type semiconductor layer (first semiconductor layer) 751, light emitting layers 752a1 and 752a2, and p-type semiconductor layers (second semiconductor layers) 753a1 and 753a2. The light emitting layer 752a1 is provided on the n-type semiconductor layer 751. The light emitting layer 752a1 is provided on the n-type semiconductor layer 751, separated from and spaced apart from the light emitting layer 752a2. The p-type semiconductor layer 753a1 is provided on the light emitting layer 752a1. The p-type semiconductor layer 753a2 is provided on the light emitting layer 752a2, separated from and spaced apart from the p-type semiconductor layer 753a1.

[0269] The p-type semiconductor layer 753a1 has an upper surface 753U1 provided on the side opposite to the surface on which the light emitting layer 752a1 is provided, and the p-type semiconductor layer 753a2 has an upper surface 753U2 provided on the side opposite to the surface on which the light emitting layer 752a2 is provided.

[0270] Light-emitting region 751R1 substantially coincides with the region of light-emitting surface 751S that faces upper surface 753U1. Light-emitting region 751R2 substantially coincides with the region of light-emitting surface 751S that faces upper surface 753U2.

[0271] The relationship between the semiconductor layer 750 and the light emitting regions 751R1 and 751R2 will be described. FIG. 29 is a schematic cross-sectional view illustrating a part of the image display device of this embodiment. FIG. 29 is a schematic diagram for explaining the light emitting regions 751R1 and 751R2 of the semiconductor layer 750. As shown in FIG. As shown in Fig. 29, light-emitting regions 751R1 and 751R2 are surfaces on light-emitting surface 751S. In Fig. 29, the portions of semiconductor layer 750 that include light-emitting regions 751R1 and 751R2 are referred to as light-emitting portions R1 and R2, respectively. Light-emitting portion R1 includes a portion of n-type semiconductor layer 751, light-emitting layer 752a1, and p-type semiconductor layer 753a1. Light-emitting portion R2 includes a portion of n-type semiconductor layer 751, light-emitting layer 752a2, and p-type semiconductor layer 753a2.

[0272] The semiconductor layer 750 includes a connection portion R0. The connection portion R0 is provided between the light emitting portion R1 and the light emitting portion R2, and is a part of the n-type semiconductor layer 751. One end of the via 761k shown in FIG. 28 is connected to the connection portion R0, and provides paths for current to the light emitting portions R1 and R2.

[0273] In the light-emitting portion R1, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 752a1. In the light-emitting portion R1, holes supplied from the upper surface 753U1 are supplied to the light-emitting layer 752a1. The electrons and holes supplied to the light-emitting layer 752a1 combine to emit light. The light emitted from the light-emitting layer 752a1 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R1. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R1, the light-emitting region 751R1 is the portion of the light-emitting surface 751S that emits light. Therefore, in this example, the light-emitting region 751R1 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 752a1 projected onto the light-emitting surface 751S in an XY planar view.

[0274] The light-emitting portion R2 is similar to the light-emitting portion R1. That is, in the light-emitting portion R2, electrons supplied via the connection portion R0 are supplied to the light-emitting layer 752a2. In the light-emitting portion R2, holes supplied from the upper surface 753U2 are supplied to the light-emitting layer 752a2. The electrons and holes supplied to the light-emitting layer 752a2 combine to emit light. The light emitted from the light-emitting layer 752a2 reaches the light-emitting surface 751S through the n-type semiconductor layer 751 of the light-emitting portion R2. Because the light travels approximately straight along the Z-axis direction within the light-emitting portion R2, the light-emitting portion 751R2 is the portion of the light-emitting surface 751S that emits light. Therefore, in this example, the light-emitting region 751R2 approximately coincides with the area surrounded by the outer periphery of the light-emitting layer 752a2 projected onto the light-emitting surface 751S in the XY plane view.

[0275] In this embodiment, the light emitting surface 751S is provided on the graphene sheet 740a, and therefore the light emitted from each of the light emitting regions 751R1 and 751R2 reaches the substrate 102 and the color filter 180 via the graphene sheet 740a.

[0276] In this way, in the semiconductor layer 750, the n-type semiconductor layer 751 can be shared to form a plurality of light emitting regions 751R1 and 751R2 on the light emitting surface 751S.

[0277] In this embodiment, the semiconductor layer 750 can be formed by using a part of the n-type semiconductor layer 751 as the connection portion R0 in the plurality of light-emitting layers 752a1, 752a2 and the plurality of p-type semiconductor layers 753a1, 753a2 of the semiconductor layer 750. Therefore, the semiconductor layer 750 can be formed in the same manner as the method for forming the light-emitting elements 150, 250 in the first embodiment, second embodiment, etc. described above.

[0278] Returning to FIG. 28, the explanation continues. The graphene layer 140 includes a plurality of graphene sheets 740a. The graphene sheets 740a are provided on the surface 102a, one for each semiconductor layer 750. The light emitting surface 751S is in contact with the graphene sheets 740a, and the semiconductor layers 750 are provided on the surface 102a of the substrate 102 via the graphene sheets 740a. The periphery of the graphene sheets 740a in the XY plane view substantially coincides with the periphery of the semiconductor layers 750 in the XY plane view.

[0279] The first interlayer insulating film 156 (first insulating film) is provided to cover the surface 102a of the substrate 102, the graphene sheet 740a, and the semiconductor layer 750.

[0280] The TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is planarized, and the TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

[0281] An insulating layer 105 covers the TFT lower film 106 and the TFT channels 104-1 and 104-2. A gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0282] A second interlayer insulating film (second insulating film) 108 is provided to cover the insulating layer 105 and the gates 107-1 and 107-2.

[0283] The TFT channel 104-1 includes p-type doped regions 104s1 and 104d1, which are the source and drain regions of the transistor 103-1. The region 104i1 is n-type doped and forms the channel of the transistor 103-1. The TFT channel 104-2 similarly includes p-type doped regions 104s2 and 104d2, which are the source and drain regions of the transistor 103-2. The region 104i2 is n-type doped and forms the channel of the transistor 103-2. In this embodiment, the circuit 101 includes the TFT channels 104-1 and 104-2, the insulating layer 105, the second interlayer insulating film 108, the vias 111s1, 111d1, 111s2, and 111d2, and the first wiring layer 110.

[0284] The first wiring layer 110 is provided on the second interlayer insulating film 108. The first wiring layer 110 includes wirings 710s1, 710d1, 710k, 710d2, and 710s2.

[0285] The wiring 710k is provided above the n-type semiconductor layer 751. The via 761k is provided between the wiring 710k and the n-type semiconductor layer 751, and electrically connects the wiring 710k to the n-type semiconductor layer 751. The wiring 710k is connected to, for example, the ground line 4 of the circuit in FIG.

[0286] The vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106. The via 111d1 is provided between the region 104d1 and the wiring 710d1, and electrically connects the region 104d1 and the wiring 710d1. The via 111s1 is provided between the region 104s1 and the wiring 710s1, and electrically connects the region 104s1 and the wiring 710s1. The via 111d2 is provided between the region 104d2 and the wiring 710d2, and electrically connects the region 104d2 and the wiring 710d2. The via 111s2 is provided between the region 104s2 and the wiring 710s2, and electrically connects the region 104s2 and the wiring 710s2. The wirings 710s1 and 710s2 are connected to the power supply line 3 of the circuit in FIG. 2, for example.

[0287] The wiring 710d1 is provided above the upper surface 753U1. The via 761a1 is provided between the wiring 710d1 and the upper surface 753U1 and electrically connects the wiring 710d1 and the upper surface 753U1. Therefore, the p-type semiconductor layer 753a1 is electrically connected to the drain region of the transistor 103-1 via the via 761a1, the wiring 710d1, and the via 111d1.

[0288] The wiring 710d2 is provided above the upper surface 753U2. The via 761a2 is provided between the wiring 710d2 and the upper surface 753U2 and electrically connects the wiring 710d2 and the upper surface 753U2. Therefore, the p-type semiconductor layer 753a2 is electrically connected to the drain region of the transistor 103-2 via the via 761a2, the wiring 710d2, and the via 111d2.

[0289] For example, transistors 103-1 and 103-2 are drive transistors for adjacent subpixels and are driven sequentially. When holes supplied from transistor 103-1 are injected into light-emitting layer 752a1 and electrons supplied from wiring 710k are injected into light-emitting layer 752a1, light-emitting layer 752a1 emits light and light is emitted from light-emitting region 751R1. When holes supplied from transistor 103-2 are injected into light-emitting layer 752a2 and electrons supplied from wiring 710k are injected into light-emitting layer 752a2, light-emitting layer 752a2 emits light and light is emitted from light-emitting region 751R2.

[0290] The effects of the image display device of this embodiment will be described. Like the image display devices of the other embodiments described above, the image display device of this embodiment has the advantage of shortening the time required for the transfer process for forming the semiconductor layer 750 and reducing the number of processes. Furthermore, since the connection portion R0 can be shared by multiple light-emitting portions R1 and R2, the number of vias 761k provided in the connection portion R0 can be reduced. Reducing the number of vias allows the pitch of the light-emitting portions R1 and R2 constituting the subpixel group 720 to be reduced, resulting in a compact, high-resolution image display device. While this example describes the case of two light-emitting regions, the number of light-emitting regions formed on the light-emitting surface is not limited to two and can be any number of three or more.

[0291] In the example of this embodiment, a case where a color filter is provided has been described, but as in the other embodiments, a monochrome image display device may be provided without providing a color filter.

[0292] The components of the above-described embodiments may be appropriately selected and applied in addition to the above-described forms. As described above, roughening the light-emitting surface can be applied to the first, second, sixth, and seventh embodiments. It is clear that the application of the light-shielding layer 330 can also be applied to the first, second, fourth, fifth, and seventh embodiments. By applying the light-shielding layer 330 to the embodiments in which the wiring 470a having a light-shielding function shown in FIG. 19 or the light-shielding electrode 560a shown in FIG. 23 is applied, further improvement in light-shielding performance can be expected.

[0293] In the second embodiment, an example in which the p-type semiconductor layer 253 is the light emitting surface 253S has been described, but the example of the second embodiment can be easily applied to light emitting devices of other embodiments and their manufacturing processes.

[0294] (Eighth embodiment) The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0295] FIG. 30 is a block diagram illustrating an image display device according to this embodiment. FIG. 30 shows the main components of a computer display. 30, an image display device 801 includes an image display module 802. The image display module 802 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 802 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0296] The image display device 801 further includes a controller 870. The controller 870 receives control signals separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each subpixel and to control the driving order.

[0297] (Variation) FIG. 31 is a block diagram illustrating an image display device according to a modified example of this embodiment. FIG. 31 shows the configuration of a high-definition flat-screen television. As shown in Fig. 31, an image display device 901 includes an image display module 902. The image display module 902 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 901 includes a controller 970 and a frame memory 980. The controller 970 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied via a bus 940. The frame memory 980 stores one frame's worth of display data and is used for processing such as smooth video playback.

[0298] The image display device 901 has an I / O circuit 910. The I / O circuit 910 is simply represented as "I / O" in Fig. 31. The I / O circuit 910 provides an interface circuit or the like for connecting to an external terminal, device, or the like. The I / O circuit 910 includes, for example, a USB interface for connecting an external hard disk drive, an audio interface, or the like.

[0299] The image display device 901 has a receiving unit 920 and a signal processing unit 930. An antenna 922 is connected to the receiving unit 920, which separates and generates necessary signals from radio waves received by the antenna 922. The signal processing unit 930 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by the receiving unit 920 are separated by the signal processing unit 930 into image data, audio data, etc., and generated.

[0300] By configuring the receiving unit 920 and the signal processing unit 930 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for Wi-Fi, a GPS receiver, etc., other image display devices can also be used. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be used as a mobile information terminal such as a smartphone or a car navigation system.

[0301] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified version thereof or a version of another embodiment. The image display module in this embodiment and the modified version includes a large number of sub-pixels, as shown in Figures 9 and 10.

[0302] According to the embodiment described above, it is possible to realize a method for manufacturing an image display device and an image display device that shortens the transfer step of light emitting elements and improves yield.

[0303] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0304] 1,201,801,901 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20,220,320,420,520,620 Subpixel, 22,222 Light emitting element, 24,224 Selection transistor, 26,226 Drive transistor, 28,228 Capacitor, 101 Circuit, 102,502 Substrate, 102a,102b Surface, 103,103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulating layer, 107,107-1,107-2 Gate, 108 Second interlayer insulating film, 110 First wiring layer, 110d, 110k, 210a, 230a Wiring, 140 Graphene layer, 140a, 740a Graphene sheet, 150, 250, 650 Light emitting element, 151a Connection portion, 151S, 253S, 651S, 751S Light emitting surface, 153U, 251U, 653U, 753U1, 753U2 Upper surface, 156 First interlayer insulating film, 161a, 161k, 261a, 261k, 361a, 361k, 461a, 461k, 661a, 761a1, 761a2, 761k Via, 172 Light emitting circuit portion, 180, 180a Color filter, 180S Connection surface, 188 Transparent resin layer, 230 Second wiring layer, 330 light-shielding layer, 470 third wiring layer, 470a, 560a light-shielding electrodes, 720 subpixel group, 1140 graphene layer, 1150 semiconductor layer, 1180 reinforcing substrate, 1192 structure

Claims

1. forming a second wiring layer having light-transmitting properties on the first surface of the substrate; forming a layer including graphene on the first surface after forming the second wiring layer; forming a semiconductor layer including a light-emitting layer on the graphene-containing layer; processing the semiconductor layer to form a light-emitting device including a light-emitting surface on the graphene-containing layer and a top surface opposite the light-emitting surface; forming a first insulating film covering the first surface, the graphene-containing layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; forming a first via that penetrates the first insulating film and the second insulating film; forming a second via that penetrates the first insulating film and the second insulating film; forming a first wiring layer on the second insulating film; Equipped with the first via is provided between the first wiring layer and the upper surface and electrically connects the first wiring layer and the upper surface; The method for manufacturing an image display device, wherein the second via is provided between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

2. The method for manufacturing an image display device according to claim 1 , wherein the substrate has light-transmitting properties.

3. The method for manufacturing an image display device according to claim 2, further comprising the step of forming a wavelength conversion member on the side of the light emitting surface.

4. 4. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a third wiring layer so as to cover the light emitting elements before the step of forming the first insulating film.

5. removing the substrate; roughening the light-emitting surface; The method for manufacturing an image display device according to claim 1, further comprising:

6. forming a wavelength conversion member in place of the substrate; The method for manufacturing an image display device according to claim 5, further comprising:

7. 7. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a light-shielding layer on the first insulating film.

8. 8. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer contains a gallium nitride compound semiconductor.

9. a light-transmitting member having a first surface; a second wiring layer having optical transparency and provided on the first surface; a light-emitting element including a light-emitting surface on the first surface and an upper surface opposite to the light-emitting surface; a third wiring layer including a first light-shielding electrode covering the upper surface and a side surface of the light-emitting element and electrically connected to the upper surface; a first insulating film covering the first surface and the light emitting element; a circuit element provided on the first insulating film; a second insulating film covering the first insulating film and the circuit element; a first via provided through the first insulating film and the second insulating film; a second via provided through the first insulating film and the second insulating film; a first wiring layer provided on the second insulating film; Equipped with the first wiring layer includes a third wiring and a fourth wiring separated from the third wiring, the first via is provided between the third wiring and the first light-shielding electrode, and electrically connects the third wiring and the first light-shielding electrode; The second via is provided between the fourth wiring and the second wiring layer, and electrically connects the fourth wiring and the second wiring layer.

10. 10. The image display device according to claim 9, wherein an internal angle formed between the first surface and a side surface of the light emitting element is smaller than 90 degrees.

11. The image display device according to claim 9 , further comprising a layer including graphene provided between the first surface and the light-emitting surface.

12. 12. The image display device according to claim 9, wherein the light-emitting surface is roughened.

13. 13. The image display device according to claim 9, further comprising a light-shielding layer provided between the first insulating film and the second insulating film.

14. 14. The image display device according to claim 9, wherein the first insulating film has light reflectivity.

15. 15. The image display device according to claim 9, wherein the light emitting element includes a gallium nitride compound semiconductor.

16. 16. The image display device according to claim 9, wherein the light-transmitting member includes a wavelength conversion member.

Images