Power Semiconductor Module

Abstract

To provide a power semiconductor module containing a semiconductor switch for switching at high speed while being connected in parallel.SOLUTION: A power semiconductor module comprises a plurality of semiconductor switches 4 arranged in groups 2 and 3 of at least two semiconductor switches. Each semiconductor switch 4 includes: a first terminal; a second terminal; and a control terminal (a gate terminal 10) in a controlled path. Each of the groups 2 and 3 includes: a first group contact (a source group contact 14) connected to a first terminal; a second group contact (a drain group contact 15) connected to a second terminal; and a control group contact (a gate group contact 13) connected to the control terminal. In addition, a mating connection bridge 6 for connecting at least two control group contacts and the first group contact is provided. The mating connection bridge has a layer structure in which a first conductive layer and a second conductive layer are separated by an insulation layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor module having a plurality of semiconductor switches arranged in at least two groups, each having a first terminal and a second terminal of a controlled path and a control terminal. [Background technology]

[0002] From EP 3 113 223 A1 a power semiconductor module is known in which several power semiconductor switches are connected together by means of separate substrate metallizations arranged in a stacked manner. Summary of the Invention [Problem to be solved by the invention]

[0003] To reduce switching losses in power modules, one option is to use wide-bandgap semiconductors, which in principle have fast switching behavior. However, the use of fast-switching semiconductors poses new challenges for module design. In addition, the area of ​​a typical wide-bandgap semiconductor device is significantly smaller than that of modern silicon devices, so more of them need to be connected in parallel to achieve the target rated current.

[0004] The object is to provide a power semiconductor module which is based on wide bandgap semiconductors and which comprises a number of semiconductor switches which are connected in parallel and which have fast switching behavior. [Means for solving the problem]

[0005] According to one embodiment, this object is achieved by the following power semiconductor module, the power semiconductor module comprising a plurality of semiconductor switches arranged in at least two groups, the semiconductor switches having first and second terminals of controlled paths and a control terminal, each group having a first group contact connected to the first terminal, a second group contact connected to the second terminal, and a control group contact connected to the control terminal, the power semiconductor module further comprising: Multiple Control Group Contact and connect multiple groups of at least two First Group Contact comrades The interconnect bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

[0006] The state of the semiconductor device is controlled by applying a voltage between the control group contacts and the first group contacts, i.e., this voltage switches the state between an open state and a closed state. Therefore, for low-loss operation, it is important to be able to change this voltage quickly and without significant oscillations. The above embodiment has an improved gate connection. Because both conductive layers are placed very close together in an interconnect bridge separated by only a very thin insulating layer, a substantial reduction in gate control loop inductance can be achieved compared to conventional wirebond connections between substrates.

[0007] The physical reason for the inductance reduction is that the inductive coupling increases significantly when two conductors are placed in close proximity. Current flowing through the gate connection layer of an interconnect bridge to the gate terminal of a switch in that group primarily charges the capacitance of the gate electrode. A related current flows in the opposite direction through the source connection layer of the interconnect bridge. Due to the antiparallel direction of the currents and the mutual inductive coupling, a substantial reduction in gate inductance can be achieved.

[0008] The proposed embodiment makes it possible to reduce the influence of the different lengths on the gate inductance of the different semiconductor switch groups, even in a power semiconductor module in which many semiconductor switches are connected in parallel and therefore the lengths of the connection paths to different semiconductor switch groups are significantly different, thereby achieving better synchronization of the switching behavior and less oscillation, thereby improving the switching behavior and reducing power loss during the switching period.

[0009] A further advantage of the proposed embodiment is that resistors, such as gate resistors located directly in the module and typically used to damp oscillations between the switches, can be omitted or at least reduced, which further improves the switching behavior. If resistors are omitted, a direct connection between the module gate contacts and the control terminals of the semiconductor switches can be achieved, which means that there are no electronic elements in between.

[0010] A sufficient reduction in vibration would at least make it possible to replace thick film resistors with more readily available semiconductor resistors, thereby facilitating and reducing the manufacturing costs of the module.

[0011] According to a more detailed embodiment, the layer structure is formed as a "normal" or flexible printed circuit board. In such an embodiment, both sides of a flexible insulating material are at least partially covered with a conductive material, such as a metal. The conductive material is advantageously copper, or aluminum, or an alloy of copper and aluminum.

[0012] According to another embodiment, the layer structure is formed of a ceramic substrate with two-sided metallization. The interconnect bridge advantageously has at least two legs on each side, and the legs are connected to both group contacts of the two groups by soldering, welding, or adhesive bonding. In the described embodiment, MOSFETs, MISFETs, or IGBTs are typically used as semiconductor switches. The semiconductor switches may be silicon-based or wide-bandgap material-based, typically SiC or GaN.

[0013] The present disclosure includes yet another aspect of improving gate connections by selectively increasing the inductance of some connections within a module. According to this aspect, a compensation structure is provided for shorter gate connection paths. While this approach increases the total gate inductance, it can reduce the difference between the inductances of different groups of gate connection paths within a module. This further reduces oscillations and thus improves switching behavior. The compensation structure according to this aspect can be used in combination with the inductance reduction described above. This may be necessary or beneficial because the physical possibilities for inductance reduction are limited and complete equalization cannot be achieved in all practical configurations. However, combining both aspects, i.e., reducing the inductance of long connection paths and increasing the inductance of short connection paths, can lead to complete equalization or at least a substantial reduction of the gate inductance difference.

[0014] Any feature described with respect to one of these aspects is also disclosed herein with respect to the other aspect, even if each feature is not explicitly mentioned in the context of the particular aspect.

[0015] The accompanying drawings are included for a better understanding. In the drawings, elements of identical structure and / or function may be referred to with the same reference numerals. It should be understood that the embodiments shown in the drawings serve for illustrative purposes and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a schematic diagram of a first embodiment of a power module. [Figure 2] FIG. 10 is a diagram illustrating the effect of the first embodiment on gate inductance. [Figure 3] 1 shows a more specific diagram of the first embodiment. [Figure 4] FIG. 1 illustrates an embodiment of an interconnection bridge. [Figure 5] FIG. 5 shows a detail of the drawing in FIG. 4. [Figure 6] 10A-10C show another embodiment of an interconnecting bridge with increased mechanical stability. [Figure 7] 10A-10C show another embodiment of an interconnecting bridge with increased mechanical stability. [Figure 8] FIG. 10 shows a second embodiment of a power module having an additional compensation structure. [Figure 9] 1A-1C illustrate several design options for the compensation structure. [Figure 10] 1A-1C illustrate several design options for the compensation structure. [Figure 11] 1A-1C illustrate several design options for the compensation structure. [Figure 12] 1A-1C illustrate several design options for the compensation structure. DETAILED DESCRIPTION OF THE INVENTION

[0017] 1 is a schematic diagram of a power module 1 including two groups 2 and 3 of semiconductor switches 4. Gate terminals 10 of the semiconductor switches 4 are connected to module gate contacts 5. The length of the conductive path between the module gate contacts 5 and the gate terminals 10 of the semiconductor switches 4 depends on the geometric arrangement of components within the module 1. For example, if more than two groups of semiconductor switches are provided, it may be difficult to ensure that the connection path lengths of each of the groups of semiconductor switches are equal.

[0018] Unequal gate connection lengths become a problem because the use of wide-bandgap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), has become more prevalent to overcome the limitations of silicon-based power semiconductor devices. Typically, wide-bandgap devices, such as silicon carbide and gallium nitride devices, are attractive due to their fast switching capabilities, which result in low switching losses. However, using multiple wide-bandgap semiconductors in a module has resulted in stronger oscillations observed within the module. To reduce such oscillations, resistors have been added to the gate connection paths. In many cases, a 5 Ω resistor is sufficient to suppress the oscillations. However, adding such resistors requires the use of thick-film technology, which means additional manufacturing steps are required. While this approach can suppress oscillations, it does not fully preserve the original advantage of wide-bandgap semiconductors, namely, their fast switching capabilities.

[0019] According to the present disclosure, the goal is not to suppress oscillations but to avoid them in the first place. The way to do this is not to minimize the total gate inductance of the power semiconductor module 1, but to equalize the gate inductances of the different groups of semiconductor switches. While the switching function of the power semiconductor module 1 also depends on the total inductance of the gate paths, oscillations strongly depend on the difference in inductance and path length of the two different groups 2 and 3 of semiconductor switches 4.

[0020] In other words, to enable fast switching, the module stray inductance must be low enough to avoid significant voltage overshoots, and the inductance imbalance must be small enough to avoid oscillations between the semiconductor switches.

[0021] Referring to FIG. 1 , the inductance of the gate path of the first group 2 can be described as the shared inductance L_shared + the interconnection inductance L_interconnection + the inductance L1, and the inductance of the second gate path can be described as the shared inductance L_shared + L2. As can be seen from FIG. 1 , the connection path to the first group 2 is longer than the connection path to the second group 3. According to this embodiment, a portion of the gate path to the first group 2 is realized by the interconnect bridge 6. With regard to the very close cross-sectional parallel arrangement of the source path from the module source contact 7 to the source terminal of the switch 4, the inductance of this portion of the gate path can be reduced. In fact, the gate inductance of the gate path to the first group 2 can be reduced by about 50%.

[0022] The proposed features can be particularly beneficial in terms of the design of complex high-power modules based on a large number of silicon carbide or gallium nitride switches arranged on several substrates and connected in parallel, however the concepts of the present disclosure can also be implemented in smaller power modules such as that shown in FIG.

[0023] Paralleling a large number of semiconductor switches 4 to achieve the intended current density / rated current is a typical configuration for power semiconductor modules 1. This also applies to silicon carbide and gallium nitride semiconductor switches, for example, since their footprint is smaller than Si technology switches, and therefore more switches need to be paralleled to enable similar current switching.

[0024] 2 illustrates the effect of the interconnect bridge in such an embodiment. For example, ten semiconductor switches 4 may be grouped on one substrate of the module and another ten semiconductor switches 4 may be grouped on another substrate of the module. The twenty semiconductor devices 4 located on both substrates are connected in parallel. In a half-bridge module configuration, two such substrates would represent the top or bottom of the module. Two other such substrates connected in parallel would form the other switch of the half-bridge module.

[0025] In the diagram of FIG. 2, the relative gate inductance is shown as a percentage of the maximum value for each switch located on one of the two parallel-connected boards. This means that switches 1 to 10 belong to a first group 2, and switches 11 to 20 belong to a second group 3. As can be seen from the dotted line 8, which shows the gate inductance of a conventional wire-bonded power semiconductor module, the maximum difference between gate inductances is 19%, while the difference within a group is only 6%. As can be seen from the solid line 9, the use of interconnect bridge 6 can reduce the inductance of the gate path of first group 2. In the configuration with interconnect bridge 6, the maximum difference in gate inductance is only 12%.

[0026] Another benefit is reduced oscillations, which can increase switching speed. Applicant's measurements show that the amplitude of gate voltage oscillations can be reduced by approximately 70%. The reduced oscillations can also reduce power loss over switching time.

[0027] Another positive effect of using the concepts of the present disclosure is that the resistance of the gate path can be reduced to a value at least below 2 Ω, which can be realized as a semiconductor resistor and does not require additional manufacturing steps.

[0028] The present disclosure has the advantage that resistors may be omitted, or at least implemented as substrate resistors, to dampen vibrations.

[0029] 3 shows a more detailed view of two groups 2 and 3 of semiconductor switches 4. The semiconductor switches 4 are disposed on a metallization layer. Portion 15 of the metallization layer is used as the drain connection. Another portion of the metallization layer is separated to form gate group contacts 13, also referred to as control group contacts 13. Yet another portion of the metallization is separated as source group contacts 14, also referred to as first group contacts 14. This applies to both the substrates of groups 2 and 3.

[0030] The gate terminal 10 of switch 4 is connected to a first side metallization 11, which appears as the top side metallization in Figure 3, and from there to a gate group contact 13 shown for group 2 on the left. The first side metallization can also be split into two parts connected via a resistor 24 and a bond wire, for example, as shown for group 3 on the right. In this way, a resistor 24 with a value of less than 2 Ω is incorporated into the gate path to damp oscillations.

[0031] The source terminals of the switches 4 are connected to further metallization 16 forming the source wiring and from there to the first group contacts 14. For the connections between the substrates, which also means the connections between the different switch groups, an interconnect bridge 6 according to the present disclosure is used.

[0032] FIG. 4 shows a more detailed view of the interconnect bridge 6. It includes two conductive layers 17 and 18. Layer 18 is used as the gate connection, and layer 17 is used as the source connection. These two layers are separated by an insulating layer, not shown in this drawing. On both sides of the interconnect bridge 6, there are provided legs 19 for the gate connection and legs 20 for the source connection. These legs are connected to the control group contacts 13 and the first group contacts 14, for example, by welding, sintering, soldering, or adhesive.

[0033] FIG. 5 shows a more detailed view of the interconnect bridge 6. As can be seen, the conductive layers 17 and 18 are separated by an insulating layer 21. The closer the conductive layers 17 and 18 are, the better the inductive coupling between them. And the better this coupling, the lower the inductance of the gate connection. Therefore, a thin insulating layer is beneficial for the performance of the power semiconductor module. It is beneficial for the insulating layer to have a thickness of less than 150 micrometers, or even less than 80 micrometers. A realistic value is 30 to 150 micrometers.

[0034] If reducing the thickness of a layer results in an undesirable decrease in the mechanical stability of the bridge, this mechanical stability can be increased by adding one or more additional layers. An exemplary embodiment of an interconnect bridge 6 with increased mechanical stability is shown in Figures 6 and 7. According to this embodiment, the interconnect bridge comprises a stack of layers having, as a series of layers, an insulating protective layer 25, followed by a first metallization 26 for a first potential, a thin insulating layer 27, a second metallization 28 for a second potential, and a second insulating protective layer 29. For example, both layers 25 and 26 and layers 29 and 28 are provided as a PCB.

[0035] On the opposite side of the second insulating protective layer 29, terminals 30 and 36 are arranged, which are used to electrically connect both metallizations, i.e., the first metallization 26 and the second metallization 28. To this end, the metallizations 26 and 28 can be accessed from the terminal side of the second insulating protective layer 29, for example, by means of vias.

[0036] Figure 7 is a cross-sectional view of the embodiment of Figure 7. Terminals 30 and 36 for two potentials that may be associated with gate and source connections are connected by vias to the first metallization 26 and the second metallization 28, respectively.

[0037] The mechanical stability is increased compared to the embodiments of Figures 4 and 5. This can be beneficial in the case of very long interconnect bridges and also opens up the possibility to minimize the thickness of the insulating layer, since it does not have to provide a mechanical function to mechanically stabilize the interconnect bridge.

[0038] Another possibility for mechanically stabilizing the interconnect bridge is to use adhesive somewhere between the terminals to support the bridge, which can be implemented, for example, in connection with all embodiments of the present disclosure.

[0039] FIG. 8 illustrates yet another embodiment of the present disclosure. Here, groups 2 and 3 of semiconductor switches are integrated within submodule 31. Two additional groups of semiconductor switches, 32 and 33, are integrated within second submodule 34. Each of submodules 31 and 34 includes intergroup connections via interconnection bridge 6, as described in the previous figures. Additionally, for gate connections between first submodule 31 and second submodule 34, an interconnection bridge 35, formed similarly to interconnection bridge 6 for intergroup connections within each of submodules 31 and 34, is used. However, according to this embodiment, interconnection bridge 35 cannot sufficiently equalize the difference in gate inductance of the gate paths to submodules 31 and 34. Therefore, an additional compensation structure 36 is provided in accordance with the second aspect of the present disclosure, as described above. The compensation structure results in an increase in the inductance of the gate connection paths to the switches in first submodule 31. Both the reduction in inductance due to the interconnect bridge 35 and the increase in inductance due to the compensation structure 36 contribute to more equal inductance in the gate connection paths of both sub-modules 31 and 34 .

[0040] It should be noted that for the technical effect of the interconnection bridges 6 and 35 both the gate and source connection paths are required, whereas for the compensation structure 36 only the gate path needs to be modified.

[0041] Regarding the realization of the compensation structure, Figures 9 to 12 show easy realization possibilities. Figure 9 shows a serpentine structure in which the connection between contact points 38 and 39 is increased by the serpentine structure. In Figure 10, islands 40 are formed in the metallization 22 of the substrate 23 and are connected by bond wires 41. In this way, the current path between connection points 38 and 39 is also extended.

[0042] In Figure 11, a spiral structure is used to a similar effect. 12, the structure of FIG. 11 is used, but the bond wires do not fully utilize the spiral structure. In this way, the structure 36 of this configuration can be tailored to the specific needs of each group, depending on the geometry within the power semiconductor module 1.

[0043] For the embodiment shown in FIG. 3, the compensation structure can also be realized in the metallization 11.

[0044] The embodiments shown in Figures 1 to 12 above illustrate exemplary embodiments of the improved configuration of the power semiconductor module. Therefore, these embodiments do not constitute an exhaustive list of all embodiments according to the improved configuration. Actual configurations may vary from the illustrated embodiments in terms of configuration or devices. [Explanation of symbols]

[0045] Reference sign 1 Power semiconductor module 2. First group of semiconductor switches 3. Second group of semiconductor switches 4. Solid-state switches 5 Module Gate Contacts 6 Interconnection Bridges 7 Module Source Contact 8 Gate inductance in case of conventional wire bonding 9 Gate inductance in case of interconnected bridge 10 Gate terminal 11 First side metallization 13 Control group contact / Gate group contact 14 First Group Contact / Source Group Contact 15 Second group contact / Drain group contact 16 Other Metallization / Source Group Contacts 17 Conductive layer 18 Conductive layer 19 Gate connection leg 20 Source connection leg 21 Insulating layer 23 Circuit Board 24 resistor 25 First insulating protective layer 26 First Bridge Metallization 27 Insulating layer 28 Second Bridge Metallization 29 Second insulating protective layer 30 First bridge terminal 31 First Submodule 32 Third group of semiconductor switches 33 Semiconductor Switches Group 4 34 Second submodule 35 Interconnecting Bridges 36 First bridge terminal 38 First Connection Point 39 Second connection point 40 Metallization Island 41 Bond wire

Claims

1. A power semiconductor module, a plurality of semiconductor switches arranged in a plurality of groups, each semiconductor switch having a first terminal and a second terminal with a controlled path therebetween, and a control terminal; The power semiconductor module comprises: a plurality of first group contacts each connected to the first terminals of the semiconductor switches of that group; a plurality of second group contacts each connected to the second terminals of the semiconductor switches of that group; a plurality of control group contacts each connected to the control terminals of the semiconductor switches in that group; an interconnection bridge connecting the control group contacts of the plurality of groups and connecting the first group contacts of the plurality of groups; The power semiconductor module, wherein the interconnect bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

2. 2. The power semiconductor module according to claim 1, wherein the layer structure is formed as a printed circuit board.

3. The power semiconductor module according to claim 2 , wherein the layer structure is formed as a flexible printed circuit board.

4. 2. The power semiconductor module according to claim 1, wherein the layer structure is formed by a ceramic substrate having a two-sided metallization.

5. 2. The power semiconductor module of claim 1, wherein the interconnect bridge includes a plurality of first legs provided at a first end of the interconnect bridge and a plurality of second legs provided at a second end of the interconnect bridge.

6. 6. The power semiconductor module of claim 5, wherein each leg of the interconnection bridge is connected to an associated group contact by a solder connection, a welded connection, a sintered connection or an adhesive connection.

7. 2. The power semiconductor module according to claim 1, wherein the plurality of semiconductor switches are at least one of MOSFETs or IGBTs based on Si or wide bandgap materials.

8. The power semiconductor module according to claim 1 , wherein each of the plurality of semiconductor switches comprises a wide bandgap semiconductor material.

9. The power semiconductor module of claim 1 , further comprising a module control contact directly connected to the control terminals of at least one group of the plurality of semiconductor switches.

10. a resistor having a resistance of less than 2 ohms; and a module control contact, 2. The power semiconductor module of claim 1, wherein the resistor is connected between the module control contact and the control terminal of at least one group of the plurality of semiconductor switches.

11. 11. The power semiconductor module of claim 10, wherein the resistor is a semiconductor resistor disposed on a metallization.

12. 2. The power semiconductor module according to claim 1, wherein the maximum difference in gate inductance within a group is 2 nH.

13. The power semiconductor module according to claim 1 , wherein the power semiconductor module is a switch or a half bridge.

14. The power semiconductor module according to claim 1 , wherein the insulating layer has a thickness of less than 150 μm.

15. The power semiconductor module according to claim 14 , wherein the insulating layer has a thickness of less than 80 μm.

16. A power semiconductor module, a first group of semiconductor switches; a second group of semiconductor switches; Each of the semiconductor switches in the first group and the second group has a first terminal and a second terminal with a controlled path therebetween, and a control terminal; The power semiconductor module comprises: a first group contact connected to the first terminal of the first group of semiconductor switches; a second group contact connected to the first terminal of the second group of semiconductor switches; a first control group contact connected to the control terminal of the first group of semiconductor switches; a second control group contact connected to the control terminal of the second group of semiconductor switches; an interconnection bridge connecting the first control group contacts to the second control group contacts and connecting the first group contacts to the second group contacts; The power semiconductor module, wherein the interconnect bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

17. a third group of semiconductor switches; a fourth group of semiconductor switches; Each of the semiconductor switches in the third group and the fourth group has a first terminal and a second terminal with a controlled path provided therebetween, and a control terminal; The power semiconductor module comprises: a third group contact connected to the first terminal of the third group of semiconductor switches; a fourth group contact connected to the first terminal of the fourth group of semiconductor switches; a third control group contact connected to the control terminal of the third group of semiconductor switches; a fourth control group contact connected to the control terminal of the fourth group of semiconductor switches; a second interconnection bridge connecting the third control group contacts to the fourth control group contacts and connecting the third group contacts to the fourth group contacts; 17. The power semiconductor module of claim 16, further comprising: a third interconnection bridge connecting the interconnection bridge to the second interconnection bridge such that the control terminals of the first and second groups are connected to the control terminals of the third and fourth groups, and the first terminals of the first and second groups are connected to the first terminals of the third and fourth groups.

18. a third group contact connected to the second terminal of the first group of semiconductor switches; 17. The power semiconductor module according to claim 16, further comprising: a fourth group contact connected to the second terminal of the second group of semiconductor switches.

19. A power semiconductor module, a plurality of semiconductor switches arranged in a plurality of groups, each semiconductor switch including a wide bandgap semiconductor material, each semiconductor switch having a first terminal and a second terminal with a controlled path therebetween, and a control terminal; The power semiconductor module comprises: a plurality of first group contacts each connected to the first terminals of the semiconductor switches of that group; a plurality of second group contacts each connected to the second terminals of the semiconductor switches of that group; a plurality of control group contacts each connected to the control terminals of the semiconductor switches in that group; a module first terminal contact connected to the plurality of first group contacts; a module control contact connected to the plurality of control group contacts; a resistor connected between the module control contact and at least one of the plurality of control group contacts, the resistor having a resistance of less than 2 ohms; an interconnection bridge connecting the control group contacts of the plurality of groups and connecting the first group contacts of the plurality of groups; The power semiconductor module, wherein the interconnect bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

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