Signal transmission devices, electronic devices, vehicles

Abstract

A signal transmission device for transmitting a power transistor drive signal to a secondary circuit system from a primary circuit system while insulating the interval between the primary circuit system and the secondary circuit system, said device having: a first abnormality detection circuit configured so as to detect abnormalities in the primary circuit system; a second abnormality detection circuit configured so as to detect abnormalities in the secondary circuit system; a first signal transmission path configured so as to transmit detection results of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the interval between the primary circuit system and the secondary circuit system; and a self-diagnosis circuit configured so as to self-diagnose the first abnormality detection circuit, the second abnormality detection circuit and the first signal transmission path.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a signal transmission device, and an electronic device and a vehicle using the same. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-011108 Summary of the Invention [Problem to be solved by the invention]

[0005] However, there is room for improvement in the self-diagnosis function of conventional signal transmission devices.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a signal transmission device that can perform appropriate self-diagnosis, and an electronic device and a vehicle that use the same. [Means for solving the problem]

[0007] For example, a signal transmission device disclosed in this specification transmits a drive signal for a power transistor from a primary circuit system to a secondary circuit system while isolating the primary circuit system from the secondary circuit system, and includes a first abnormality detection circuit configured to detect an abnormality in the primary circuit system, a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system, a first signal transmission path configured to transmit the detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system, and a self-diagnosis circuit configured to self-diagnose each of the first abnormality detection circuit, the second abnormality detection circuit, and the first signal transmission path. [Effects of the Invention]

[0008] According to the invention disclosed in this specification, it is possible to provide a signal transmission device capable of performing appropriate self-diagnosis, and an electronic device using the same. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9]FIG. 9 is a diagram schematically showing a layout example of a transchip. [Figure 10] FIG. 10 is a diagram showing an embodiment of a signal transmission device. [Figure 11] FIG. 11 is a diagram showing a configuration example of an electronic device on which a signal transmission device is mounted. [Figure 12] FIG. 12 is a diagram showing a configuration example of a self-diagnosis circuit. [Figure 13] FIG. 13 is a diagram showing a first example (when power is turned on) of a self-diagnosis operation. [Figure 14] FIG. 14 is a diagram showing a second example (when UV2 is detected and released) of a self-diagnosis operation. [Figure 15] FIG. 15 is a diagram showing timing constraint conditions of various signals. [Figure 16] FIG. 16 is a diagram showing a first embodiment of a BIST instruction transmission method. [Figure 17] FIG. 17 is a diagram showing a second embodiment of a BIST instruction transmission method. [Figure 18] FIG. 18 is a diagram showing a first example (TL < T < TH) of a BIST instruction transmission operation. [Figure 19] FIG. 19 is a diagram showing a second example (T < TL) of a BIST instruction transmission operation. [Figure 20] FIG. 20 is a diagram showing a third example (T > TH) of a BIST instruction transmission operation. [Figure 21] FIG. 21 is a diagram showing the appearance of a vehicle on which an electronic device is mounted.

MODE FOR CARRYING OUT THE INVENTION

[0010] <(Basic Configuration) of Signal Transmission Device> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0022] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0026] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6.

[0033] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0087] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0091] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage insulation to be achieved.

[0092] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed at a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0135] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0137] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <Signal transmission device> 10 is a diagram showing an embodiment of a signal transmission device. The signal transmission device 400 of this embodiment is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s and drives the gate of a power transistor (not shown) provided in the secondary circuit system 400s while electrically insulating the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system). The signal transmission device 400 can be understood as corresponding to the signal transmission device 200 described above.

[0156] The signal transmission device 400 has a plurality of external terminals (in this figure, power supply terminals VCC1 and VCC2, ground terminals GND1 and GND2, negative power supply terminal VEE2, input terminals INA and INB, output terminals OUT1H and OUT1L, fault terminal FLT, ready terminal RDY, enable terminal ENA, overheat / load power supply abnormality detection terminal TO_VH, short circuit detection terminal SCPIN, self-diagnosis on terminal BISTON, and self-diagnosis output terminal BISTOUT) as means for establishing electrical connection with the outside of the device.

[0157] On the first side (= the left side in this figure) of the package forming the signal transmission device 400, there are arranged, in order from top to bottom, a ground terminal GND1, a fault terminal FLT, an enable terminal ENA, an input terminal INA, an input terminal INB, a ready terminal RDY, a power supply terminal VCC1, a self-diagnosis output terminal BISTOUT, a self-diagnosis on terminal BISTON, and a ground terminal GND1.

[0158] On the other hand, on the second side of the package (= the side opposite to the first side mentioned above, the right side in this figure), there are arranged, in order from top to bottom, a negative power supply terminal VEE2, an output terminal OUT1L, an output terminal OUT1H, a power supply terminal VCC2, an overheat / load power supply abnormality detection terminal TO_VH, a ground terminal GND2, a short circuit detection terminal SCPIN, and a negative power supply terminal VEE2.

[0159] In this way, the external terminals of the primary circuit system 400p (GND1, FLT, ENA, INA and INB, RDY, VCC1, BISTOUT, BISTON) can be concentrated on the first side of the package, and the external terminals of the secondary circuit system 400s (VEE2, OUT1L, OUT1H, VCC2, TO_VH, GND2, SCPIN) can be concentrated on the second side of the package.

[0160] A ground terminal GND1 and a negative power supply terminal VEE2 should be disposed at both ends of each of the first and second sides of the package. That is, two ground terminals GND1 and two negative power supply terminals VEE2 should be provided.

[0161] The signal transmission device 400 can be widely applied to a wide range of applications (such as motor drivers or DC / DC converters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0162] Continuing with reference to Fig. 10, the internal configuration of the signal transmission device 400 will be described. The signal transmission device 400 of this configuration example is configured by sealing a controller chip 410 (corresponding to the first chip), a driver chip 420 (corresponding to the second chip), and a transformer chip 430 (corresponding to the third chip) in a single package.

[0163] The controller chip 410 is a semiconductor chip that integrates circuit elements of a primary circuit system 400p that operates upon receiving a supply of power supply voltage VCC1 (for example, up to 7V relative to GND1). The controller chip 410 also integrates, for example, a logic circuit 411, a UVLO [under-voltage lock out] / OVLO [over-voltage lock out] circuit 412, and NMOSFETs 413 to 415.

[0164] The logic circuit 411 generates a drive pulse signal PWM for a power transistor (not shown) in response to the input pulse signals INA and INB. For example, if INB=H (logical level when disabled), PWM=L (fixed value), and if INB=L (logical level when enabled), PWM=INA. The logic circuit 411 also monitors various abnormality detection signals (low voltage, overvoltage, short circuit, open circuit, overheat, load power supply abnormality, etc.) of the signal transmission device 400 and drives the NMOSFETs 413 and 414 based on the monitoring results, thereby determining the logical levels of the fault signal FLT and the ready signal RDY. The logic circuit 411 also switches the operation of the entire signal transmission device 400 (enable / disable) in response to the enable signal ENA.

[0165] Furthermore, the logic circuit 411 also has the function of performing a self-diagnosis (so-called BIST [built-in self test]) of each part of the signal transmission device 400 in response to the self-diagnosis on signal BISTON, and determining the logic level of the self-diagnosis output signal BISTOUT by driving the NMOSFET 415 based on the self-diagnosis result. In other words, the logic circuit 411 functions as a part of the self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0166] The UVLO / OVLO circuit 412 detects an undervoltage / overvoltage of the power supply voltage VCC1, and outputs the detection result to the logic circuit 411.

[0167] The NMOSFET 413 connects / disconnects the fault terminal FLT and the ground terminal in response to an instruction from the logic circuit 411. For example, when the driver chip 420 detects overheating or an abnormality in the load power supply, the NMOSFET 413 turns on and the fault terminal FLT goes low (= the logic level when an abnormality is detected).

[0168] The NMOSFET 414 connects / disconnects the ready terminal RDY and the ground terminal in response to an instruction from the logic circuit 411. For example, when a low voltage or an overvoltage is detected in either the controller chip 410 or the driver chip 420, the NMOSFET 414 turns on and the ready terminal RDY goes low (= the logic level when an abnormality is detected).

[0169] The NMOSFET 415 establishes or breaks conduction between the self-diagnosis output terminal BISTOUT and the ground terminal in response to an instruction from the logic circuit 411. For example, when the self-diagnosis result of the signal transmission device 400 is NG, the NMOSFET 415 turns on and the self-diagnosis output terminal BISTOUT becomes low level (= the logic level when an abnormality is detected).

[0170] The driver chip 420 is a semiconductor chip that integrates circuit elements of the secondary circuit system 400s that operates upon receiving a supply of power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 420 integrates, for example, a logic circuit 421, a UVLO / OVLO circuit 422, comparators 423 and 424, a PMOSFET 425, and NMOSFETs 426 and 427.

[0171] The logic circuit 421 drives the gates of power transistors (not shown) connected to the output terminals OUT1H and OUT1L by turning on / off the PMOSFET 425 and the NMOSFET 426 in response to a drive pulse signal PWM input via the transformer chip 430. The output terminals OUT1H and OUT1L may be short-circuited to each other outside the signal transmission device 400. The logic circuit 421 also has a function of transmitting various abnormality detection signals (low voltage, overvoltage, short circuit, open, overheat, load power supply abnormality, etc.) from the driver chip 420 to the controller chip 410 via the transformer chip 430.

[0172] Furthermore, the logic circuit 421 also has a function of transmitting the self-diagnosis result (BIST_result) on the driver chip 420 side to the controller chip 410 via the transformer chip 430. In other words, the logic circuit 421 functions as a part of the self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0173] The UVLO / OVLO circuit 422 detects an undervoltage / overvoltage of the power supply voltage VCC2, and outputs the detection result to the logic circuit 421.

[0174] The comparator 423 monitors the terminal voltage of the overheat / load power supply abnormality detection terminal TO_VH to detect overheating of the power transistor or overvoltage of the load power supply.

[0175] The comparator 424 monitors the terminal voltage of the short-circuit detection terminal SCPIN to detect short-circuits in the power transistors (detection of penetration between the upper and lower power transistors).

[0176] The PMOSFET 425 establishes / cuts conduction between the power supply terminal and the output terminal OUT1H in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a high level, the PMOSFET 425 turns on, and the output terminal OUT1H (and therefore the output pulse signal applied to the gate of the power transistor) becomes a high level.

[0177] The NMOSFET 426 connects / disconnects the output terminal OUT1L and the ground terminal in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a low level, the NMOSFET 426 turns on, and the output terminal OUT1L (and therefore the output pulse signal applied to the gate of the power transistor) becomes a low level.

[0178] In this way, the PMOSFET 425 and the NMOSFET 426 function as a half-bridge output stage (CMOS (complementary MOS) inverter stage) for gate driving.

[0179] The NMOSFET 427 establishes / disconnects conduction between the ground terminal GND2 and the short-circuit detection terminal SCPIN in response to an instruction from the logic circuit 421. For example, the NMOSFET 427 is turned off when OUT1H=H, and turned on when OUT1H=L. The NMOSFET 427 functions as a discharge switch that discharges an external capacitor (not shown) connected between SCPIN and GND2 by turning on / off in a complementary manner with a power transistor (not shown).

[0180] The transformer chip 430 is a semiconductor chip that integrates a transformer for transmitting signals in both directions while insulating the controller chip 410 and the driver chip 420 from each other.

[0181] The signal transmission device 400 of this configuration example has an independent transformer chip 430 equipped with only a transformer, in addition to the controller chip 410 and the driver chip 420, and these three chips are sealed in a single package.

[0182] With this configuration, the controller chip 410 and the driver chip 420 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0183] Furthermore, the controller chip 410 and the driver chip 420 can both be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which contributes to shortening development time and reducing development costs.

[0184] Furthermore, even when a DC isolation element other than a transformer (e.g., a photocoupler) is used, it can be easily accommodated by simply replacing the transformer chip 430, eliminating the need to redevelop the controller chip 410 and the driver chip 420, thereby contributing to shortening the development period and reducing development costs.

[0185] <Electronic equipment> 11 is a diagram showing an example of the configuration of an electronic device equipped with a signal transmission device 400. Electronic device A of this example configuration has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU 3, and a motor 4.

[0186] The upper gate drivers IC1H(u / v / w) drive the upper power transistors 2H(u / v / w) by generating upper gate drive signals in response to upper gate control signals input from the ECU 3 while insulating the ECU 3 from the upper power transistors 2H(u / v / w).

[0187] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0188] The signal transmission device 400 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0189] The upper power transistors 2H (u / v / w) are connected between the power system power supply terminal (= application terminal of the load power supply voltage PVDD) and each phase input terminal of the motor 4 as upper switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0190] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the power system ground terminal as lower switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0191] In this figure, an IGBT [insulated gate bipolar transistor] is used as the upper power transistor 2H(u / v / w) and the lower power transistor 2L(u / v / w), but it is also possible to use, for example, a MOSFET [metal oxide semiconductor field effect transistor] instead of the IGBT.

[0192] The ECU 3 drives the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively, thereby controlling the rotational drive of the motor 4. The ECU 3 also has the function of monitoring the fault terminals FLT and ready terminals RDY of the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), and performing various safety controls based on the monitoring results.

[0193] Furthermore, the ECU 3 uses the self-diagnosis on signal BISTON to output the self-diagnosis results of the signal transmission device 400, and also has the function of checking whether the various protection circuits (low voltage protection, overvoltage protection, overheat protection, and short circuit protection) of the signal transmission device 400 are normal or not based on the logic level of the self-diagnosis output signal BISTOUT.

[0194] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0195] <Self-diagnosis circuit> 12 is a diagram showing an example of the configuration of a self-diagnosis circuit incorporated in the signal transmission device 400. The self-diagnosis circuit B of this example configuration includes the aforementioned logic circuits 411 and 421 as part thereof, as well as switches SW11 to SW14 and switches SW21 to SW28. Furthermore, transformers TR1 to TR5 are integrated into the transformer chip 430 as isolation elements related to the self-diagnosis circuit B.

[0196] First, the controller chip 410 will be described.

[0197] The logic circuit 411 includes, as functional blocks related to the self-diagnosis circuit B, for example, a logic unit 411a, an edge detection unit 411b, a pulse transmission unit 411c, a logic unit 411d, latches 411e and 411f, a NAND gate 411g, a latch 411h, an edge detection unit 411i, and a flip-flop 411j.

[0198] When an undervoltage or overvoltage is detected in either the UVLO / OVLO circuits 412 or 422, the logic unit 411a raises the gate signal S411a of the NMOSFET 414 to high level to turn on the NMOSFET 414, thereby lowering the ready signal RDY to low level (=the logic level when an abnormality is detected). The detection results of the UVLO / OVLO circuit 412 (=the overvoltage detection signal OV1 and the undervoltage detection signal UV1) are directly input to the logic unit 411a. On the other hand, the detection results of the UVLO / OVLO circuit 422 (=the overvoltage detection signal OV2 and the undervoltage detection signal UV2) are once input to the logic circuit 421 and then transmitted to the logic unit 411a via transformers TR1 and TR2.

[0199] The edge detection unit 411b detects the falling edge of the gate signal S411a (and consequently the rising edge of the ready signal RDY) and outputs the detection result to the pulse transmission unit 411c.

[0200] When the edge detection unit 411b detects the falling edge of the gate signal S411a, the pulse transmission unit 411c transmits a pulse signal S411c (=a self-diagnosis command to the driver chip 420) to the logic circuit 421 via the transformer TR3.

[0201] When the driver chip 420 detects overheating (or an abnormality in the load power supply) or a short circuit (vertical feedthrough) in the power transistor, the logic unit 411d raises the gate signal S411d of the NMOSFET 413 to high level to turn on the NMOSFET 413, thereby lowering the fault terminal FLT to low level (= the logic level when an abnormality is detected). The detection result of overheating or short circuiting (= the overheating detection signal OT and the short circuit detection signal SC) is once input to the logic circuit 421 and then transmitted to the logic unit 411d via the transformer TR4.

[0202] The latch 411e latches the gate signal S411d at a predetermined timing to generate a latch signal S411e and outputs it to the NAND gate 411g.

[0203] The latch 411f latches the secondary-side BIST result (=pulse signal S421e) transmitted from the logic circuit 421 via the transformer TR5 at a predetermined timing, thereby generating a latch signal S411f and outputting it to the NAND gate 411g.

[0204] The NAND gate 411g receives the gate signal S411a, the latch signals S411e and S411f, and the overvoltage detection signal OV1 and undervoltage detection signal UV1 as inputs to generate the NAND signal S411g. Therefore, the NAND signal S411g goes to a high level when at least one of the above five signals is at a low level (= a logic level when no abnormality is detected), and goes to a low level when all of the above five signals are at a high level (= a logic level when an abnormality is detected).

[0205] The latch 411h latches the NAND signal S411g at a predetermined timing to generate a latch signal S411h and output it to the flip-flop 411j.

[0206] The edge detector 411i detects the rising edge of the self-diagnosis ON signal BISTON and generates a pulse in the clock signal S411i of the flip-flop 411j.

[0207] The flip-flop 411j receives the latch signal S411h at the pulse generation timing of the clock signal S411i and outputs it as a gate signal S411j of the NMOSFET 415. When the gate signal S411j is at a high level, the NMOSFET 415 turns on and the self-diagnosis output signal BISTOUT turns to a low level (=the logic level when the self-diagnosis is NG), and when the gate signal S411j is at a low level, the NMOSFET 415 turns off and the self-diagnosis output signal BISTOUT turns to a high impedance state (=the logic level when the self-diagnosis is OK).

[0208] The UVLO / OVLO circuit 412 is one of the targets to be diagnosed by the self-diagnosis circuit B, and includes comparators 412a and 412b.

[0209] The comparator 412a compares the voltage to be monitored (DIV11 or VCC1) input to the non-inverting input terminal (+) with the overvoltage detection threshold input to the inverting input terminal (-) to generate an overvoltage detection signal OV1. The overvoltage detection signal OV1 goes to high level (=logical level in the event of an abnormality) when the voltage to be monitored is higher than the overvoltage detection threshold, and goes to low level (=logical level in the event of a normal state) when the voltage to be monitored is lower than the overvoltage detection threshold.

[0210] The comparator 412b compares the voltage to be monitored (DIV12 or GND1) input to its inverting input terminal (-) with the low-voltage detection threshold input to its non-inverting input terminal (+) to generate the low-voltage detection signal UV1. The low-voltage detection signal UV1 goes high (=logical level in the event of an abnormality) when the voltage to be monitored is lower than the low-voltage detection threshold, and goes low (=logical level in the event of a normal state) when the voltage to be monitored is higher than the low-voltage detection threshold.

[0211] The switch SW11 is connected between the application terminal of the divided voltage DIV11 (=divided voltage of the power supply voltage VCC1) and the non-inverting input terminal (+) of the comparator 412a. The switch SW11 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW12 is connected between the application terminal of the power supply voltage VCC1 and the non-inverting input terminal (+) of the comparator 412a. The switch SW12 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV11 is input to the non-inverting input terminal (+) of the comparator 412a as the voltage to be monitored mentioned above during non-BIST, and the power supply voltage VCC1 is input during BIST.

[0212] The switch SW13 is connected between the application terminal of the divided voltage DIV12 (=divided voltage of the power supply voltage VCC1) and the inverting input terminal (-) of the comparator 412b. The switch SW13 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW14 is connected between the application terminal of the ground voltage GND1 and the inverting input terminal (-) of the comparator 412b. The switch SW14 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV12 is input to the inverting input terminal (-) of the comparator 412b as the voltage to be monitored mentioned above during non-BIST, and the ground voltage GND1 is input during BIST.

[0213] The switches SW11 to SW14 are each turned on / off in response to a primary self-diagnosis signal BIST 1. For example, the primary self-diagnosis signal BIST 1 is at a low level during BIST and at a high level during non-BIST.

[0214] Next, the explanation will continue with a focus on the driver chip 420.

[0215] The logic circuit 421 includes, as functional blocks related to the self-diagnosis circuit B, for example, a logic unit 421a, a pulse receiving unit 421b, a logic unit 421c, an AND gate 421d, and an oscillator 421e.

[0216] The logic unit 421a transmits the detection results of the UVLO / OVLO circuit 422 (= overvoltage detection signal OV2 and undervoltage detection signal UV2) to the logic unit 411a via transformers TR1 and TR2. For example, the logic unit 421a stops the generation of both pulse signals S421a1 and S421a2 (and thus the driving of both transformers TR1 and TR2) when an undervoltage or overvoltage is detected. The logic unit 411a detects that the generation of both pulse signals S421a1 and S421a2 (and thus the driving of both transformers TR1 and TR2) has stopped, and recognizes that an undervoltage or overvoltage has been detected by the logic unit 421a. On the other hand, the logic unit 421a drives the transformer TR1 or TR2 using the pulse signal S421a1 or S421a2 when the undervoltage or overvoltage detection is released (when no undervoltage or overvoltage is detected). For example, when the gate signal (OUTH) of the power transistor is at a high level, the transformer TR1 is driven using the pulse signal S421a1, and when the gate signal (OUTH) is at a low level, the transformer TR2 is driven using the pulse signal S421a2.

[0217] The pulse receiving unit 421b generates a secondary-side self-diagnosis signal BIST2 in response to a pulse signal S411c (=a self-diagnosis command to the driver chip 420) received via the transformer TR3.

[0218] The logic unit 421c transmits the overheating or short-circuiting detection result (= overheating detection signal OT and short-circuiting detection signal SC) to the logic unit 411d via the transformer TR4. For example, when overheating or short-circuiting is detected, the logic unit 421c drives the transformer TR4 using a pulse signal S421c.

[0219] The AND gate 421d receives the overvoltage detection signal OV2, the undervoltage detection signal UV2, the overheat detection signal OT, and the short-circuit detection signal SC as inputs and generates an AND signal S421d. Therefore, the AND signal S421d goes low when at least one of the above four signals is low (= the logical level when no abnormality is detected), and goes high when all of the above four signals are high (= the logical level when an abnormality is detected).

[0220] When the AND signal S421d rises to a high level, the oscillator 421e transmits a pulse signal S421e (=a self-diagnosis result for the controller chip 410, for example, 10 MHz, 3 CLK) to the logic circuit 411 via the transformer TR5.

[0221] The UVLO / OVLO circuit 422 is one of the targets to be diagnosed by the self-diagnosis circuit B, and includes comparators 422a and 422b. The comparators 423 and 424 are also one of the targets to be diagnosed by the self-diagnosis circuit B.

[0222] The comparator 422a compares the voltage to be monitored (DIV21 or VCC2) input to the non-inverting input terminal (+) with the overvoltage detection threshold input to the inverting input terminal (-) to generate an overvoltage detection signal OV2. The overvoltage detection signal OV2 goes to high level (=logical level in the event of an abnormality) when the voltage to be monitored is higher than the overvoltage detection threshold, and goes to low level (=logical level in the event of a normal state) when the voltage to be monitored is lower than the overvoltage detection threshold.

[0223] The comparator 422b compares the voltage to be monitored (DIV22 or GND2) input to its inverting input terminal (-) with the low-voltage detection threshold input to its non-inverting input terminal (+) to generate the low-voltage detection signal UV2. The low-voltage detection signal UV2 goes high (=logical level in the event of an abnormality) when the voltage to be monitored is lower than the low-voltage detection threshold, and goes low (=logical level in the event of a normal state) when the voltage to be monitored is higher than the low-voltage detection threshold.

[0224] The comparator 423 compares the monitored voltage (TO_VH or GND2) input to its inverting input terminal (-) with the overheat detection threshold input to its non-inverting input terminal (+) to generate an overheat detection signal OT. The overheat detection signal OT goes to high level (=logical level in the abnormal state) when the monitored voltage is lower than the overheat detection threshold, and goes to low level (=logical level in the normal state) when the monitored voltage is higher than the overheat detection threshold.

[0225] The comparator 424 compares the voltage to be monitored (SCPIN or VREG) input to its non-inverting input terminal (+) with the short circuit detection threshold input to its inverting input terminal (-) to generate a short circuit detection signal SC. The short circuit detection signal SC goes to high level (=logical level in the event of an abnormality) when the voltage to be monitored is higher than the short circuit detection threshold, and goes to low level (=logical level in the event of a normal state) when the voltage to be monitored is lower than the short circuit detection threshold.

[0226] The switch SW21 is connected between the application terminal of the divided voltage DIV21 (=divided voltage of the power supply voltage VCC2) and the non-inverting input terminal (+) of the comparator 422a. The switch SW21 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW22 is connected between the application terminal of the power supply voltage VCC2 and the non-inverting input terminal (+) of the comparator 422a. The switch SW22 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV21 is input to the non-inverting input terminal (+) of the comparator 422a as the voltage to be monitored mentioned above during non-BIST, and the power supply voltage VCC2 is input during BIST.

[0227] The switch SW23 is connected between the application terminal of the divided voltage DIV22 (=divided voltage of the power supply voltage VCC2) and the inverting input terminal (-) of the comparator 422b. The switch SW23 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW24 is connected between the application terminal of the ground voltage GND2 and the inverting input terminal (-) of the comparator 422b. The switch SW24 is turned on during BIST and turned off during non-BIST. That is, the divided voltage DIV22 is input to the inverting input terminal (-) of the comparator 422b as the voltage to be monitored mentioned above during non-BIST, and the ground voltage GND2 is input during BIST.

[0228] The switch SW25 is connected between the application terminal of the short circuit detection voltage SCPIN (=terminal voltage of the SCPIN terminal) and the non-inverting input terminal (+) of the comparator 424. The switch SW25 is turned off during BIST and turned on during non-BIST. On the other hand, the switch SW26 is connected between the application terminal of the internal voltage VREG and the non-inverting input terminal (+) of the comparator 424. 6 is turned on during BIST and turned off during non-BIST. That is, the short circuit detection voltage SCPIN is input to the non-inverting input terminal (+) of the comparator 424 during non-BIST as the voltage to be monitored, and the internal voltage VREG is input during BIST. Also, the NMOSFET 427 is turned off during BIST.

[0229] The switch SW27 is connected between the application terminal of the overheat detection voltage TO_VH (=terminal voltage of the overheat / load power supply abnormality detection terminal TO_VH) and the inverting input terminal (-) of the comparator 423. The switch SW27 is turned off during BIST and turned on during non-BIST. 8 is connected between the application terminal of the ground voltage GND2 and the inverting input terminal (-) of the comparator 423. 8 is turned on during BIST and turned off during non-BIST. That is, the inverting input terminal (-) of the comparator 423 receives the overheat detection voltage TO_VH as the voltage to be monitored during non-BIST, and receives the ground voltage GND2 as the voltage to be monitored during BIST.

[0230] The switches SW21 to SW28 are turned on / off in response to the secondary self-diagnosis signal BIST2. For example, the secondary self-diagnosis signal BIST2 is at a low level during BIST and at a high level during non-BIST.

[0231] The above-mentioned self-diagnosis circuit B diagnoses the UVLO / OVLO circuit 412 (comparators 412a and 412b), the UVLO / OVLO circuit 422 (comparators 422a and 422b), the overheat detection circuit (comparator 423), and the short-circuit detection circuit (comparator 424), as well as the first signal transmission path (transformers TR1 and TR2 for RDY output, and transformer TR4 for FLT output) that transmits the abnormality detection result of the driver chip 420 to the controller chip 410, and can confirm whether each functional block is operating normally.

[0232] For example, to diagnose whether comparators 412a and 412b, comparators 422a and 422b, and comparators 423 and 424 are operating correctly, a test voltage outside the normal input range (for example, power supply voltages VCC1 and VCC2, or ground voltages GND1 and GND2, or internal voltage VREG) is applied as the monitored voltage input to each, and it is confirmed that each abnormality detection signal (OV1 / UV1, OV2 / UV2, SC, OT) is at a high level (= the logical level when an abnormality is detected).

[0233] Furthermore, to diagnose whether the first signal transmission path (transformers TR1 and TR2 for RDY output and transformer TR4 for FLT output) is operating correctly, it is sufficient to confirm that the ready signal RDY and the fault signal FLT are at a low level (= the logical level when an abnormality is detected) by the logic units 411a and 411d, in other words, that the gate signals S411a and S411d are at a high level.

[0234] When all of the above diagnostic targets are operating correctly, the five signals (S411a, S411e, S411f, OV1, and UV1) input to the NAND gate 411g are all at high level (=logical level when an abnormality is detected), and the NAND signal S411g is at low level. Therefore, when the self-diagnosis on signal BISTON is raised to high level, the NMOSFET 415 is turned off, and the self-diagnosis output signal BISTOUT is at high impedance (=logical level when the self-diagnosis is OK).

[0235] On the other hand, if at least one of the above-mentioned diagnostic targets is not operating correctly, at least one of the five signals (S411a, S411e, S411f, OV1, and UV1) input to the NAND gate 411g will be at low level (= the logic level when no abnormality is detected), and the NAND signal S411g will be at high level. Therefore, when the self-diagnosis on signal BISTON is raised to high level, the NMOSFET 415 is turned on, and the self-diagnosis output signal BISTOUT will be at low level (= the logic level when the self-diagnosis is NG).

[0236] As described above, the signal transmission device 400 of this configuration example has a first abnormality detection circuit (UVLO / OVLO circuit 412) configured to detect an abnormality in the controller chip 410 provided in the primary circuit system 400p, a second abnormality detection circuit (UVLO / OVLO circuit 422, comparator 423 for overheat detection, comparator 424 for short circuit detection) configured to detect an abnormality in the driver chip 420 provided in the secondary circuit system 400s, a first signal transmission path (TR1, TR2, and TR4) configured to transmit the detection results (OV2, UV2, OT, and SC) of the second abnormality detection circuit from the secondary circuit system 400s to the primary circuit system 400p while insulating the primary circuit system 400p from the secondary circuit system 400s, and a self-diagnosis circuit B configured to self-diagnose each of the above-mentioned first abnormality detection circuit (412), second abnormality detection circuit (422, 423, 424), and first signal transmission path (TR1, TR2, TR4).

[0237] In addition, the self-diagnosis circuit B includes a second signal transmission path (421d, 421e and TR5) configured to transmit the self-diagnosis result of the second abnormality detection circuit (422, 423, 424) from the driver chip 420 of the secondary circuit system 400s to the controller chip 410 of the primary circuit system 400p while insulating the controller chip 410 of the primary circuit system 400p from the driver chip 420 of the secondary circuit system 400s.

[0238] Referring to this figure, it is desirable that the second signal transmission path be configured to transmit the abnormality detection results (OV2, UV2, OT, and SC) in the driver chip 420 to the controller chip 410 as a single pulse signal S421e by using an AND gate 421d, an oscillator 421e, and a transformer TR5.

[0239] <Self-diagnosis operation> FIG. 13 is a diagram showing a first example of self-diagnostic operation (at power-on), and depicts, from top to bottom, power supply voltages VCC1 and VCC2, a ready signal RDY, a fault signal FLT, an enable signal ENA, an input pulse signal INA, an output pulse signal OUT1 (corresponding to the aforementioned output pulse signal OUT1H), a self-diagnostic on signal BISTON, a self-diagnostic output signal BISTOUT, and an internal BIST signal BISTINT (= a logic signal generated inside the logic circuit 411 to set the total self-diagnostic period).

[0240] After power-on, at time t11, the UVLO for each of the power supply voltages VCC1 and VCC2 is released, and when the ready signal RDY rises from low to high (= the ready terminal RDY is in high impedance), the internal BIST signal BISTINT rises to high, and self-diagnostic operation begins.

[0241] At this time, the switches SW11 and SW13, and the switches SW21, SW23, SW25, and SW27 are turned off, and the switches SW12 and SW14, and the switches SW22, SW24, SW26, and SW28 are turned on.

[0242] That is, a test voltage outside the normal input range (for example, power supply voltages VCC1 and VCC2, or ground voltages GND1 and GND2, or internal voltage VREG) is applied to comparators 412a and 412b, comparators 422a and 422b, and comparators 423 and 424 as the monitored voltage to be input to each of them.

[0243] The internal BIST signal BISTINT does not depend on the enable signal ENA, but on the rising edge of the ready signal RDY. The high-level period of the internal BIST signal BISTINT (corresponding to the total self-diagnosis period) can be preset using a built-in timer. This configuration eliminates the need for a self-diagnosis completion flag.

[0244] During the self-diagnosis operation, the input pulse signals INA and INB and the enable signal ENA are disabled. That is, during the self-diagnosis operation, the output pulse signal OUT1 (the aforementioned OUT1H and OUT1L) is fixed to a low level, and the power transistor is maintained in an off state.

[0245] Similarly, during the self-diagnosis operation, the self-diagnosis on signal BISTON (and hence the self-diagnosis output signal BISTOUT) may be disabled. For example, the self-diagnosis on signal BISTON may be masked. Therefore, even if the self-diagnosis on signal BISTON is raised to a high level during the self-diagnosis operation, the self-diagnosis output signal BISTOUT remains fixed at a low level.

[0246] Furthermore, during the self-diagnostic operation, neither the ready signal RDY nor the fault signal FLT is fixed, but remains at a logic level according to the internal state of the signal transmission device 400. This makes it possible to confirm from outside the device that the self-diagnostic operation is being performed.

[0247] At time t12, when a predetermined period T1 (for example, a maximum of 150 μs) has elapsed since the start of the self-diagnostic operation (time t11), switches SW11 and SW13, as well as switches SW21, SW23, SW25 and SW27, are turned on, and switches SW12 and SW14, as well as switches SW22, SW24, SW26 and SW28, are turned off.

[0248] That is, the comparators 412a and 412b, the comparators 422a and 422b, and the comparators 423 and 424 are respectively applied with the voltages to be monitored (divided voltages DIV11 and DIV12, divided voltages DIV21 and DIV22, overheat detection voltage TO_VH, and short-circuit detection voltage SCPIN).

[0249] At this time, the ready signal RDY rises to high level, but the rising edge of the ready signal RDY should be ignored while the internal BIST signal BISTINT is high level so that the self-diagnosis operation does not start again. In other words, even if RDY goes from low to high level during self-diagnosis operation, the built-in timer that counts the high-level period of the internal BIST signal BISTINT is not reset.

[0250] After that, at time t13, when a predetermined period T2 (for example, a maximum of 250 μs) has elapsed since the above-mentioned switch change (time t12), the internal BIST signal BISTINT falls to low level, and the above-mentioned series of self-diagnosis operations are terminated. After this, the input pulse signals INA and INB, the enable signal ENA, and the self-diagnosis on signal BISTON are all enabled.

[0251] For example, when the self-diagnosis on signal BISTON is raised to high level at any timing, after a predetermined period T3 has elapsed, the self-diagnosis result at that time is latched and output as the self-diagnosis output signal BISTOUT. At this time, if the self-diagnosis result is NG, BISTOUT=L (dashed line), and if the self-diagnosis result is OK, BISTOUT=HiZ (solid line). The signal latch of the self-diagnosis output signal BISTOUT should be reset at the falling edge of the ready signal RDY.

[0252] If comparator 412b or 422b has failed and the ready signal RDY does not rise to high level even after power is turned on, the self-diagnosis operation cannot be started. However, if the ready signal RDY remains low level even after power is turned on, it is clear that some abnormality has occurred in signal transmission device 400, so there is no particular problem even if the self-diagnosis operation cannot be started.

[0253] FIG. 14 is a diagram showing a second example of self-diagnostic operation (when UV2 is detected and then released), and similarly to FIG. 13, from top to bottom, it depicts the power supply voltages VCC1 and VCC2, the ready signal RDY, the fault signal FLT, the enable signal ENA, the input pulse signal INA, the output pulse signal OUT1 (corresponding to the output pulse signal OUT1H mentioned above), the self-diagnostic on signal BISTON, the self-diagnostic output signal BISTOUT, and the internal BIST signal BISTINT.

[0254] As shown in this diagram, the self-diagnostic operation described above is executed not only at power-on (FIG. 13), but also, for example, after UVLO is detected for the power supply voltage VCC2 at time t20, when the UVLO is released at time t21. Note that the self-diagnostic operation from time t21 onwards is the same as that from time t11 onwards in FIG. 13, so a duplicated explanation will be omitted.

[0255] <Timing constraints> FIG. 15 is a diagram showing the timing constraints of various signals related to the self-diagnostic operation, depicting, from top to bottom, the ready signal RDY, the fault signal FLT, the primary-side self-diagnostic signal BIST1, the drive pulse for the transformer TR, the secondary-side self-diagnostic signal BIST2, and the internal BIST signal BISTINT.

[0256] In this figure, the logic level of the internal BIST signal BISTINT is inverted from that in Figures 13 and 14. In this way, the logic levels of various signals including the internal BIST signal BISTINT are arbitrary.

[0257] The hatched areas of the ready signal RDY and the fault signal FLT indicate that the logic levels change as the self-diagnostic operation proceeds.

[0258] First, we will explain the periods Ta, Te, Tf, and Tg shown in this figure. The period Ta, which is from when the ready signal RDY rises to high level at time t31 to when the secondary-side self-diagnosis signal BIST2 falls to low level at time t32, corresponds to the period during which a self-diagnosis command is transmitted from the primary circuit system 400p to the secondary circuit system 400s.

[0259] Furthermore, the period Td during which the primary-side self-diagnosis signal BIST1 is maintained at a low level from time t31 to t34 corresponds to the self-diagnosis period (typ. 70 μs) of the first abnormality detection circuit (eg, UVLO / OVLO circuit 412).

[0260] Furthermore, the period Te during which the secondary-side self-diagnosis signal BIST2 is maintained at a low level from time t32 to t33 corresponds to the self-diagnosis period (typ 30 μs) of the second abnormality detection circuit (e.g., UVLO / OVLO circuit 422, comparator 423 for overheating detection, and comparator 424 for short-circuit detection).

[0261] Furthermore, the period Tf from when the secondary-side self-diagnostic signal BIST2 rises to high level at time t33 to when the driver chip 420 is restored to normal at time t35 corresponds to the protection retention period (typically 70 μs) after the abnormality detection of the secondary circuit system 400s is released.

[0262] Furthermore, the period Tg during which the internal BIST signal BISTINT is maintained at a low level from time t31 to time t36 corresponds to the total self-diagnosis period (typ. 200 μs).

[0263] Here, as a first timing constraint, it is desirable to set the respective periods so that the maximum value of Ta+Te+Tf is shorter than the minimum value of Tg.

[0264] Furthermore, although not explicitly shown in this figure, if the abnormality detection mask period (noise filter period) of the second abnormality detection circuit (e.g., UVLO / OVLO circuit 422, overheat detection comparator 423, and short circuit detection comparator 424) is Tb and the self-diagnosis result transmission period from the secondary circuit system 400s to the primary circuit system 400p is Tc, then as the second timing constraint, it is desirable to set each period so that the maximum value of Ta+Tb+Tc is shorter than the minimum value of Td.

[0265] Furthermore, as a third timing constraint, it is desirable to set the respective periods so that the maximum value of Tb is shorter than the minimum value of Te.

[0266] <Means for transmitting BIST commands to secondary circuits> Figure 16 is a diagram showing a first embodiment (pulse number discrimination) of a method for transmitting a self-diagnosis command (= a command instructing the start of self-diagnosis operation in the secondary circuit system 400s, hereinafter sometimes referred to as a BIST command) from the primary circuit system 400p to the secondary circuit system 400s.

[0267] First, prior to describing the BIST command transmission method in the self-diagnostic circuit B, the isolated signal transmission circuit C, which is the main functional block of the signal transmission device 400, will be briefly described.

[0268] The isolated signal transmission circuit C transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s while isolating the primary circuit system 400p from the secondary circuit system 400s via transformers TR11 and TR12 integrated on a transformer chip 430. Referring to this figure, the isolated signal transmission circuit C transmits an input pulse signal IN of the primary circuit system 400p (e.g., the aforementioned input pulse signal INA) as an output pulse signal OUT of the secondary circuit system 400s (e.g., the aforementioned output pulse signal OUT1H).

[0269] For example, the isolated signal transmission circuit C includes a pulse transmitting unit 411x, a pulse receiving unit 421x, transformers TR11 and TR12, and buffers BUF1 and BUF2.

[0270] The pulse transmitting unit 411x pulse-drives either one of the transmission pulse signals S411 and S412 in accordance with the logic level of the input pulse signal IN. For example, when notifying that the input pulse signal IN is at a high level, the pulse transmitting unit 411x pulse-drives (outputs a single or multiple transmission pulses) the transmission pulse signal S411 to be applied to the primary winding of the transformer TR11, and when notifying that the input pulse signal IN is at a low level, the pulse transmitting unit 411x pulse-drives the transmission pulse signal S412 to be applied to the primary winding of the transformer TR12.

[0271] For example, the pulse transmitting unit 411x generates seven pulses at 10 MHz when the transmission pulse signals S411 and S412 are pulse-driven.

[0272] The pulse transmitting unit 411x is one of the functional blocks included in the logic circuit 411 mentioned above, and is integrated into the controller chip 410 of the primary circuit system 400p.

[0273] The pulse receiving unit 421x generates an output pulse signal OUT in response to received pulse signals S421 and S422 input from transformers TR11 and TR12 via buffers BUF1 and BUF2, respectively. For example, when the pulse receiving unit 421x detects an induced pulse of received pulse signal S421 appearing in the secondary winding of transformer TR11 in response to pulse driving of transmission pulse signal S411, the pulse receiving unit 421x raises the output pulse signal OUT to a high level. On the other hand, when the pulse receiving unit 421x detects an induced pulse of received pulse signal S422 appearing in the secondary winding of transformer TR12 in response to pulse driving of transmission pulse signal S412, the pulse receiving unit 421x lowers the output pulse signal OUT to a low level. In other words, the logic level of the output pulse signal OUT switches in response to the logic level of the input pulse signal IN.

[0274] The pulse receiving unit 421x is one of the functional blocks included in the logic circuit 421 described above, and is integrated in the driver chip 420 of the secondary circuit system 400s.

[0275] The transformer TR11 outputs a received pulse signal S421 from its secondary winding in response to a transmitted pulse signal S411 input to its primary winding, while the transformer TR12 outputs a received pulse signal S422 from its secondary winding in response to a transmitted pulse signal S412 input to its primary winding.

[0276] The transformers TR11 and TR12 are both integrated into the transformer chip 430. The transformer chip 430 uses the transformers TR11 and TR12 to insulate the controller chip 410 from the driver chip 420, and outputs the transmission pulse signals S411 and S412 input from the pulse transmitting unit 411x to the pulse receiving unit 421x as reception pulse signals S421 and S422, respectively.

[0277] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S411 and S412 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 400p to the secondary circuit system 400s via two transformers TR11 and TR12.

[0278] Here, it is desirable that the self-diagnosis circuit B be configured to share part of the isolated signal transmission circuit C as a means for transmitting a BIST command from the primary circuit system 400p to the secondary circuit system 400s, more specifically, to share the transformer TR12 (=transformer for transmitting a gate-off signal for a power transistor) of the isolated signal transmission circuit C as the transformer TR3 in Figure 12.

[0279] Referring to this figure, in the self-diagnosis circuit B of this configuration example, when the edge detection unit 411b detects the falling edge of the gate signal S411a, the pulse transmission unit 411c pulse-drives the transmission pulse signal S412 applied to the primary winding of the transformer TR12 (corresponding to the transformer TR3), thereby transmitting a BIST command to the secondary circuit system 400s. Meanwhile, the pulse reception unit 421b receives the reception pulse signal S422 transmitted via the transformer TR12 (corresponding to the transformer TR3) and generates a secondary-side self-diagnosis signal BIST2.

[0280] By adopting such a configuration, it is not necessary to provide a dedicated signal transmission path (a separate transformer), and therefore it is possible to reduce the size of the transformer chip 430 (and therefore the entire signal transmission device 400).

[0281] However, when the transformer TR12 of the isolated signal transmission circuit C is shared as described above, it is necessary to determine whether the received pulse signal S422 transmitted via the transformer TR12 is a gate-off signal for the power transistor or a BIST command.

[0282] Therefore, the self-diagnosis circuit B (particularly the pulse transmitting unit 411c) drives the transmission pulse signal S412, which originally functions as a gate-off signal for the power transistor, with a different number of pulses than normal, and transmits a BIST command from the primary circuit system 400p to the secondary circuit system 400s by realizing signal discrimination based on the difference in the number of pulses.

[0283] For example, the pulse transmitting unit 411x of the isolated signal transmission circuit C generates seven pulses at 10 MHz in the transmission pulse signal S412 when turning off the power transistor, while the pulse transmitting unit 411c of the self-diagnosis circuit B generates 15 pulses at 10 MHz in the transmission pulse signal S412 when transmitting a BIST command.

[0284] Therefore, for example, the pulse receiving unit 421b of the self-diagnostic circuit B counts the number of pulses in the received pulse signal S422 using the counter b10, and when the number of pulses in the received pulse signal S422 is 8 or more (for example, 11), it can determine that the received pulse signal S422 is a BIST command and generate the secondary-side self-diagnostic signal BIST2. Even when a BIST command is determined to be a BIST command with 11 pulses, it is possible to provide redundancy as a measure against missing pulses by generating 15 pulses.

[0285] After detecting the BIST command, the pulse receiving unit 421b sets the driver chip 420 in the BIST mode for a predetermined period (corresponding to the period Te in FIG. 15, max 35 μs, min 20 μs), and releases the BIST mode after the predetermined period has elapsed. With this configuration, it is not necessary to receive a BIST mode release signal from the controller chip 410.

[0286] Furthermore, when the BIST command is transmitted, the transmission pulse signal S412 is pulse-driven, just as when the gate of the power transistor is turned off. Therefore, the output pulse signal OUT is lowered to a low level by the pulse receiving unit 421x of the isolated signal transmission circuit C, and the power transistor is turned off. Therefore, the motor 4 does not malfunction during the self-diagnosis of the signal transmission device 400.

[0287] Although not shown in the figure, it is advisable to incorporate a noise mask circuit in the pulse receiving units 421x and 421b as a means for suppressing malfunction due to common mode noise.Furthermore, it is advisable to incorporate an RC filter in the pulse receiving unit 421b to suppress fluctuations in the logic power supply as a means for suppressing logic errors in the counter b10.

[0288] During normal operation of the signal transmission device 400, the input pulse signal IN may alternate between high and low levels. In such cases, seven pulses appear in the received pulse signal S422 at each falling edge of the input pulse signal IN. Therefore, if such consecutive pulses are counted, there is a risk of misjudgment of the BIST command. Therefore, it is desirable to reset the counter b10 for the received pulse signal S422 each time a pulse is generated in the transmitted pulse signal S411 (and therefore in the received pulse signal S421).

[0289] However, the pulse transmitter 411x of the isolated signal transmission circuit C may have a function of detecting a mismatch between the input pulse signal IN and the output pulse signal OUT and repeating the pulse driving of the transmission pulse signal S411 or S412. In such a case, for example, if the input pulse signal IN is at a low level but the output pulse signal OUT remains at a high level, the transmission pulse signal S412 may be pulse-driven 11 or more times in succession (7 pulses × n repetitions). Therefore, in the first example BIST command transmission method that distinguishes signals based on differences in the number of pulses, even with the reset control of the counter b10 described above, there is a risk of misidentification of the BIST command.

[0290] Below, another BIST command transmission method (second embodiment) that can solve such a problem will be proposed.

[0291] FIG. 17 is a diagram showing a second embodiment (pulse period determination) of a method for transmitting a BIST command from a primary circuit system 400p to a secondary circuit system 400s. In the signal transmission device 400 of the present embodiment, a self-diagnosis circuit B (particularly a pulse transmission unit 411c) drives a transmission pulse signal S412 that originally functions as a gate-off signal of a power transistor at a pulse period (and thus a pulse frequency) different from the normal time, and realizes signal discrimination from the difference in the pulse period, thereby transmitting a BIST command from the primary circuit system 400p to the secondary circuit system 400s.

[0292] For example, as described above, when the pulse transmission unit 411x of the insulation signal transmission circuit C turns off the power transistor, it generates seven pulses of the transmission pulse signal S412 at 10 MHz (period T = 0.1 μs). On the other hand, when the pulse transmission unit 411c of the self-diagnosis circuit B transmits a BIST command, it generates seven pulses of the transmission pulse signal S412 at 1 MHz (period T = 1 μs).

[0293] Also, the pulse reception unit 421b of the self-diagnosis circuit B includes, for example, a period upper limit determination unit b11, a period lower limit determination unit b12, an inverter b13, an AND gate b14, a counter b15, and a latch b16.

[0294] The period upper limit determination unit b11 outputs an internal signal Sb1 for confirming that the pulse period T of the received pulse signal S422 is shorter than an upper limit period TH (for example, TH = 1.5 μs). The internal signal Sb1 becomes high-level, for example, at the pulse generation timing of the received pulse signal S422, and then becomes low-level when the upper limit period TH elapses without the next pulse being generated. That is, the internal signal Sb1 is maintained at a high level when T TH.

[0295] The lower limit period determination unit b12 outputs an internal signal Sb2 for confirming that the pulse period T of the received pulse signal S422 is longer than the lower limit period TL (for example, TH = 0.5 μs). The internal signal Sb2 becomes high level when, for example, after becoming low level at the pulse generation timing of the received pulse signal S422, the lower limit period TL has elapsed without the next pulse being generated. That is, the internal signal Sb2 is maintained at low level when T < TL, and rises to high level when T > TL. In other words, when T > TL, the internal signal Sb2 is pulse-driven at the pulse period T.

[0296] The inverter b13 generates an internal signal Sb3 by inverting the logic level of the received pulse signal S421 (corresponding to the gate-on signal). Therefore, the internal signal Sb3 becomes low level when the received pulse signal S421 is high level, and becomes high level when the received pulse signal S421 is low level.

[0297] The AND gate b14 generates an internal signal Sb4 by performing a logical product operation on the internal signals Sb1 and Sb3. Therefore, the internal signal Sb4 becomes low level when at least one of the internal signals Sb1 and Sb3 is low level, and becomes high level when both of the internal signals Sb1 and Sb3 are high level. That is, the internal signal Sb4 becomes low level when the pulse period T of the received pulse signal S422 is longer than the upper limit period TH, or when a pulse is generated in the received pulse signal S421.

[0298] The counter b15 generates an internal signal Sb4 by counting the number of pulses of the internal signal Sb2. For example, the counter b15 raises the internal signal Sb5 to high level when the number of pulses of the internal signal Sb2 reaches a predetermined threshold value (for example, 3 pulses). The count value of the counter b15 (= the number of pulses of the internal signal Sb2) is reset to zero when the internal signal Sb4 is lowered to low level.

[0299] The latch b16 receives the input of the internal signal Sb5 and generates a secondary side self-diagnosis signal BIST2. More specifically, the latch b16 holds the secondary side self-diagnosis signal BIST2 at the logic level in the BIST mode for a predetermined period (corresponding to the period Te in FIG. 15, max 35 μs, min 20 μs) from the rising timing of the internal signal Sb5, and may return the secondary side self-diagnosis signal BIST2 to the logic level when the BIST mode is released after the elapse of the predetermined period. By adopting such a configuration, it is not necessary to receive a BIST mode release signal from the controller chip 410.

[0300] According to the pulse receiving unit 42l b of this configuration example, when a plurality of received pulse signals S422 (for example, three or more) whose pulse period T falls within a predetermined range (TL < T < TH) are received, it can be determined that the received pulse signal S422 is a BIST command, and the secondary side self-diagnosis signal BIST2 can be generated. Even when the BIST command is determined by three pulses, redundancy can be provided as a countermeasure against pulse dropout by generating seven pulses.

[0301] Also, when transmitting the BIST command, the transmission pulse signal S412 is pulse-driven, similar to when the gate of the power transistor is turned off. Therefore, the output pulse signal OUT is lowered to the low level by the pulse receiving unit 421x of the insulation signal transmission circuit C, and the power transistor is turned off. Therefore, the motor 4 does not malfunction during the self-diagnosis of the signal transmission device 400.

[0302] Although not explicitly shown in this figure, a noise mask circuit may be incorporated into the pulse receiving units 421x and 421b as means for suppressing malfunction due to common mode noise. Further, an RC filter for suppressing fluctuations in the logic power supply may be incorporated into the pulse receiving unit 421b as means for suppressing logical corruption of the counter b15. These points are the same as those in the first example (pulse number discrimination) described above.

[0303] Also, as described above, in the normal operation of the signal transmission device 400, the high level and low level of the input pulse signal IN may be repeated. Here, when the pulse period of the input pulse signal IN and the pulse period (for example, 1 μs) of the transmission pulse signal S412 generated by the pulse transmission unit 411c of the self-diagnosis circuit B are close to each other, the pulse period T of the received pulse signal S422 generated at each falling edge of the input pulse signal IN may seem to fall within the previous predetermined range (TL < T < TH), which may cause misjudgment of the BIST command. Therefore, it is desirable that the counter b15 of the pulse reception unit 421b be reset every time a pulse of the transmission pulse signal S411 (and thus the received pulse signal S421) is generated, as in this configuration example.

[0304] Also, in the case of the BIST command transmission method of the second example that performs signal discrimination based on the difference in pulse periods, even if the pulse transmission unit 411x of the insulation signal transmission circuit C has a function of detecting a mismatch between the input pulse signal IN and the output pulse signal OUT and repeating the pulse drive of the transmission pulse signal S411 or S412, there is no concern of misjudgment of the BIST command.

[0305] FIG. 18 is a diagram showing a first example (TL < T < TH) of the BIST command transmission operation in the second embodiment, and depicts the received pulse signal S422, internal signals Sb1, Sb2, and Sb5, and the secondary self-diagnosis signal BIST2 in order from the top.

[0306] Note that in this figure, the logic level of the secondary self-diagnosis signal BIST2 is inverted from that in FIG. 15. Thus, the logic levels of various signals including the secondary self-diagnosis signal BIST2 are arbitrary.

[0307] When the pulse period T of the received pulse signal S422 falls within a predetermined range (TL < T < TH), continuous pulses are generated in the internal signal Sb2 while the internal signal Sb1 is maintained at a high level. At this time, the counter b15 continuously counts the number of pulses of the internal signal Sb2 without being reset, and raises the internal signal Sb5 to a high level when the count value reaches a predetermined threshold (three pulses in this figure). As a result, the secondary-side self-diagnosis signal BIST2 becomes high level, and the self-diagnosis operation of the driver chip 420 is performed over the period Te. Note that after the generation of the received pulse signal S422 stops and the upper limit period TH elapses, the internal signal Sb1 falls to a low level and the counter b15 is reset, so the internal signal Sb5 also falls to a low level.

[0308] FIG. 19 is a diagram showing a second example (T < TL) of the BIST command transmission operation in the second embodiment. Similar to the previous FIG. 18, the received pulse signal S422, the internal signals Sb1, Sb2, and Sb5, and the secondary-side self-diagnosis signal BIST2 are depicted in order from the top.

[0309] The second example in this figure corresponds to the case where the pulse period T of the received pulse signal S422 is short (for example, when the normal gate-off signal is being transmitted). In this case, the internal signal Sb2 does not rise to a high level (no pulse generation), so the count value of the counter b15 does not reach the predetermined threshold. As a result, the secondary-side self-diagnosis signal BIST 2 is maintained at a low level, so the driver chip 420 does not switch to the BIST mode. Note that after the generation of the received pulse signal S422 stops and the lower limit period TL elapses, the internal signal Sb2 rises to a high level and the count value is incremented by one, but then the internal signal Sb1 immediately falls to a low level and the counter b15 is reset, so the internal signal Sb5 does not rise to a high level.

[0310] FIG. 20 is a diagram showing a third example (T > TH) of the BIST command transmission operation in the second embodiment. Similar to the previous FIGS. 18 and 19, the received pulse signal S4 22, internal signals Sb1, Sb2 and Sb5, and secondary side self-diagnostic signal BIST2 are depicted.

[0311] The third example in this figure corresponds to the case where the pulse period T of the received pulse signal S422 is long (for example, when 0.1 MHz noise is periodically superimposed). In this case, the internal signal Sb2 rises to a high level and the count value is incremented by one each time a pulse of the received pulse signal S422 is generated, but the upper limit period TH has elapsed before the next pulse generation timing arrives, and the internal signal Sb1 falls to a low level, so the internal signal Sb5 does not rise to a high level. As a result, the secondary-side self-diagnosis signal BIST 2 is kept low so that the driver chip 420 does not switch into BIST mode.

[0312] <Application to vehicles> 21 is a diagram showing the appearance of a vehicle equipped with electronic devices. A vehicle X10 of this configuration example is equipped with electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown).

[0313] Vehicle X10 includes not only engine vehicles but also electric vehicles (battery electric vehicles [BEVs], hybrid electric vehicles [HEVs], plug-in hybrid electric vehicles [PHEVs / PHVs], or xEVs such as fuel cell electric vehicles / fuel cell vehicles [FCEVs / FCVs]).

[0314] For convenience of illustration, the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions.

[0315] The electronic device X11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0316] The electronic device X12 is a lamp control unit that controls the turning on and off of a high intensity discharged lamp (HID) or a daytime running lamp (DRL).

[0317] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0318] The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X10 (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0319] The electronic device X15 is a security control unit that controls the driving of door locks, burglar alarms, and the like.

[0320] The electronic equipment X16 is electronic equipment that is installed in the vehicle X10 at the factory as standard equipment or manufacturer options, such as wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroofs, and power seats.

[0321] The electronic device X17 is an electronic device that is optionally installed in the vehicle X10 as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0322] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0323] The electronic devices X11 to X18 can be understood as specific examples of the previously described electronic device A. That is, the signal transmitter 400 described above can be incorporated into any of the electronic devices X11 to X18.

[0324] <Summary> The following will provide a general overview of the various embodiments described above.

[0325] For example, the signal transmission device disclosed in this specification transmits a drive signal for a power transistor from a primary circuit system to a secondary circuit system while isolating the primary circuit system from the secondary circuit system, and is configured (first configuration) to have a first abnormality detection circuit configured to detect an abnormality in the primary circuit system, a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system, a first signal transmission path configured to transmit the detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system, and a self-diagnosis circuit configured to self-diagnose each of the first abnormality detection circuit, the second abnormality detection circuit, and the first signal transmission path.

[0326] In addition, in the signal transmission device having the above-mentioned first configuration, the self-diagnosis circuit may be configured (second configuration) to include a second signal transmission path configured to transmit the self-diagnosis result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system.

[0327] Furthermore, a signal transmission device having the first or second configuration may be configured (third configuration) such that the maximum value of Ta+Te+Tf is shorter than the minimum value of Tg, where Ta is the self-diagnosis command transmission period from the primary circuit system to the secondary circuit system, Te is the self-diagnosis period of the second abnormality detection circuit, Tf is the protection retention period after abnormality detection of the secondary circuit system is released, and Tg is the total self-diagnosis period.

[0328] Furthermore, a signal transmission device having any of the above first to third configurations may be configured (fourth configuration) in which, when the self-diagnosis command transmission period from the primary circuit system to the secondary circuit system is Ta, the abnormality detection mask period of the second abnormality detection circuit is Tb, the self-diagnosis result transmission period from the secondary circuit system to the primary circuit system is Tc, and the self-diagnosis period of the first abnormality detection circuit is Td, the maximum value of Ta+Tb+Tc is shorter than the minimum value of Td.

[0329] Alternatively, a signal transmission device having any of the first to fourth configurations above may be configured (fifth configuration) in which, when the abnormality detection mask period of the second abnormality detection circuit is Tb and the self-diagnosis period of the second abnormality detection circuit is Te, the maximum value of Tb is shorter than the minimum value of Te.

[0330] Furthermore, in a signal transmission device having any of the first to fifth configurations, the self-diagnosis circuit may be configured (sixth configuration) to transmit a self-diagnosis command from the primary circuit system to the secondary circuit system by driving the off signal of the power transistor with a different number of pulses than in normal times.

[0331] Furthermore, in a signal transmission device having any of the first to fifth configurations, the self-diagnosis circuit may be configured (seventh configuration) to transmit a self-diagnosis command from the primary circuit system to the secondary circuit system by driving the off signal of the power transistor at a pulse period different from that during normal operation.

[0332] Furthermore, a signal transmission device having any of the above first to seventh configurations may have a configuration (eighth configuration) in which a first chip on which circuit elements of the primary circuit system are integrated, a second chip on which circuit elements of the secondary circuit system are integrated, and a third chip on which an insulating element that provides insulation between the primary circuit system and the secondary circuit system is integrated are sealed in a single package.

[0333] Furthermore, for example, an electronic device disclosed in this specification has a power transistor and a gate driver IC that drives the gate of the power transistor, and the gate driver IC is configured to be a signal transmission device having any one of the first to eighth configurations (ninth configuration).

[0334] Furthermore, for example, the vehicle disclosed in this specification has a configuration (tenth configuration) including the electronic device having the ninth configuration described above.

[0335] <Other variations> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0336] 1H(u / v / w) High-side gate driver IC 1L(u / v / w) Lower gate driver IC 2H(u / v / w) Upper power transistor 2L(u / v / w) Lower power transistor 3 ECU 4 motors 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Signal Transmission Device (Insulated Gate Driver IC) 400p primary circuit system 400s secondary circuit system 410 controller chip 411 Logic Circuits 411a Logic section 411b Edge detection unit 411c Pulse transmitter 411d Logic section 411e, 411f latch 411g NAND gate 411h Latch 411i Edge detection section 411j flip-flops 411x Pulse transmitter 412 UVLO / OVLO Circuit 412a, 412b Comparators 413, 414, 415 NMOSFETs 420 driver chip 421 Logic Circuits 421a Logic section 421b Pulse receiver 421c Logic section 421d AND Gate 421e oscillator 421x Pulse receiver 422 UVLO / OVLO circuit 422a, 422b Comparators 423, 424 Comparator 425 PMOSFET 426 NMOSFET 427 NMOSFET (discharge switch) 430 Transformer Chip a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) b10 counter b11 Cycle upper limit judgment section b12 Period lower limit judgment section b13 inverter b14 AND gate b15 counter b16 Latch c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B Self-diagnosis circuit BUF1, BUF2 Schmitt buffers C. Isolated signal transmission circuit L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil SW11 to SW14, SW21 to SW28 switches T21, T22, T23, T24, T25, T26 external terminals TR1~TR5, TR11, TR12 transformers X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias X10 vehicle X11~X18 Electronic equipment

Claims

1. 1. A signal transmission device that transmits a drive signal for a power transistor from a primary circuit system to a secondary circuit system while isolating the primary circuit system from a secondary circuit system, a first abnormality detection circuit configured to detect an abnormality in the primary circuit system; a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system; a first signal transmission path configured to transmit a detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system; a diagnostic circuit configured to diagnose each of the first abnormality detection circuit, the second abnormality detection circuit, and the first signal transmission path; and the first abnormality detection circuit includes a first comparator that is an analog circuit; the second abnormality detection circuit includes a second comparator that is an analog circuit; The diagnostic circuit includes: the circuit for diagnosing the first abnormality detection circuit includes a first switch connected between an application terminal of a first monitored voltage and an input terminal of the first comparator, and a second switch connected between an application terminal of a first test voltage and the input terminal of the first comparator, and is configured to turn off the first switch and turn on the second switch when diagnosing the first comparator, and to turn on the first switch and turn off the second switch when not diagnosing the first comparator; the circuit for diagnosing the second abnormality detection circuit includes a third switch connected between an application terminal of a second monitored voltage and an input terminal of the second comparator, and a fourth switch connected between an application terminal of a second test voltage and the input terminal of the second comparator, and is configured to turn off the third switch and turn on the fourth switch when diagnosing the second comparator, and to turn on the third switch and turn off the fourth switch when not diagnosing the second comparator. Signal transmission device.

2. A signal transmission device as described in claim 1, wherein the diagnostic circuit includes a second signal transmission path configured to transmit the diagnostic result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while isolating the primary circuit system from the secondary circuit system.

3. 3. The signal transmission device according to claim 1, wherein the maximum value of Ta+Te+Tf is shorter than the minimum value of Tg, where Ta is the period for transmitting a diagnostic command from the primary circuit system to the secondary circuit system, Te is the period for diagnosing the second abnormality detection circuit, Tf is the period for maintaining protection after the abnormality detection of the secondary circuit system is released, and Tg is the total diagnostic period.

4. 4. A signal transmission device according to claim 1, wherein the maximum value of Ta+Tb+Tc is shorter than the minimum value of Td, where Ta is a diagnostic command transmission period from the primary circuit system to the secondary circuit system, Tb is an abnormality detection mask period of the second abnormality detection circuit, Tc is a diagnostic result transmission period from the secondary circuit system to the primary circuit system, and Td is a diagnosis period of the first abnormality detection circuit.

5. The signal transmission device according to any one of claims 1 to 4, wherein the maximum value of Tb is shorter than the minimum value of Te, where Tb is the abnormality detection mask period of the second abnormality detection circuit and Te is the diagnosis period of the second abnormality detection circuit.

6. The signal transmission device according to any one of claims 1 to 5, wherein the diagnostic circuit transmits a diagnostic command from the primary circuit system to the secondary circuit system by driving the off signal of the power transistor with a different number of pulses than that used in normal operation.

7. The signal transmission device according to any one of claims 1 to 5, wherein the diagnostic circuit transmits a diagnostic command from the primary circuit system to the secondary circuit system by driving the off signal of the power transistor at a pulse period different from that during normal operation.

8. a first chip on which circuit elements of the primary circuit system are integrated; a second chip on which circuit elements of the secondary circuit system are integrated; a third chip on which an insulating element for insulating between the primary circuit system and the secondary circuit system is integrated; 8. The signal transmission device according to claim 1, wherein the signal transmission device is sealed in a single package.

9. 9. An electronic device comprising: a power transistor; and a gate driver IC that drives a gate of the power transistor, wherein the gate driver IC is the signal transmission device according to claim 1.

10. A vehicle comprising the electronic device according to claim 9.

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