3D capacitance structure and method for fabricating the same

Abstract

To provide a 3D capacitance structure that increases capacitance and is resistant to structural collapse, and a method for manufacturing the same.SOLUTION: A 3D capacitance structure 10 includes multiple sub-capacitance stack structures SC and multiple first and second electrode contacts E1, E2. Each of the sub-capacitance stack structures includes a dielectric stack DS and lower and upper electrode structures LE, UE. The dielectric stack includes stacked dielectric layers and an etch stop layer. The lower electrode structure includes a lower electrode plate 112 and multiple lower electrode extensions 114 disposed within a lower dielectric layer 102. The upper electrode structure includes an upper electrode plate 116 and multiple upper electrode extensions 118 disposed within an upper dielectric layer 110. The first and second electrode contacts E1, E2 are connected to the lower electrode plate 112 and upper electrode plate 116 of two adjacent layers within the sub-capacitance stack structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a capacitance structure, and more particularly to a 3D capacitance structure and a method for fabricating the same. [Background technology]

[0002] Due to technological bottlenecks caused by the continuous shrinking of chips, the industry is turning from process improvements that increase the number of transistors per silicon wafer area to complex system-level chip designs with relatively controllable costs to improve overall performance, with emphasis on "chiplets" that enable high transistor density and performance at relatively low costs.

[0003] Chiplets are created by dividing many elements originally contained in a single chip into multiple smaller units, redesigning and remanufacturing each unit with enhanced functionality, and then forming a system chip using advanced packaging technology.

[0004] However, a single capacitor in a chiplet is limited to being fabricated on a silicon substrate, and since it is not possible to create a capacitor with excessive capacitance, the capacitance is also limited and cannot be increased. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a 3D capacitance structure and a method for manufacturing the same, which can increase capacitance and make the structure less susceptible to collapse by forming closely stacked 3D capacitance structures. [Means for solving the problem]

[0006] The 3D capacitance structure of the present invention includes a substrate, multiple sub-capacitance stack structures, multiple first electrode contacts, and multiple second electrode contacts. The sub-capacitance stack structures are disposed on the substrate, and each sub-capacitance stack structure includes a dielectric stack, a lower electrode structure, and an upper electrode structure. The dielectric stack includes a stacked lower dielectric layer, a lower etch-stop layer, an intermediate dielectric layer, an upper etch-stop layer, and an upper dielectric layer. The lower electrode structure includes a lower electrode plate disposed within the lower dielectric layer and multiple lower electrode extensions extending upward from the lower electrode plate and penetrating the lower etch-stop layer into the intermediate dielectric layer. The upper electrode structure includes an upper electrode plate disposed within the upper dielectric layer and multiple upper electrode extensions extending downward from the upper electrode plate and penetrating the upper etch-stop layer and intermediate dielectric layer onto the lower etch-stop layer. The multiple first electrode contacts are respectively connected to two adjacent lower electrode plates in the sub-capacitance stack structure. The multiple second electrode contacts are respectively connected to two adjacent upper electrode plates in the sub-capacitance stack structure.

[0007] The method for manufacturing a 3D capacitance structure of the present invention includes the steps of: (a) forming a first bottom electrode plate on a substrate; (b) forming a first dielectric stack on the first bottom electrode plate, the first dielectric stack including a stacked bottom dielectric layer, an etching stop layer, and an upper dielectric layer; (c) forming a plurality of first bottom electrode extensions in the first dielectric stack, the plurality of bottom electrode extensions penetrating the etching stop layer from the first bottom electrode plate upward into the upper dielectric layer; (d) forming a second dielectric stack, the structure of the second dielectric stack being the same as that of the first dielectric stack; (e) forming a plurality of first top electrode extensions in the second dielectric stack, the plurality of first top electrode extensions penetrating the etching stop layer of the second dielectric stack and extending onto the etching stop layer of the first dielectric stack; (f) forming a first top electrode plate in the upper dielectric layer of the second dielectric stack, the first top electrode plate being connected to the plurality of first top electrode extensions; and (g) forming a third dielectric stack, the structure of the third dielectric stack being the same as that of the first dielectric stack. (g) a step in which the second dielectric stack is the same as the first dielectric stack; (h) a step in which a first contact opening is formed through the third dielectric stack, the second dielectric stack, and the first dielectric stack until the first bottom electrode plate is exposed; (i) a step in which a bottom electrode plate groove is formed in an upper dielectric layer of the third dielectric stack, the bottom electrode plate groove together with the first contact opening constituting a first dual damascene opening; (j) a step in which a conductive material is formed in the first dual damascene opening to simultaneously form a first electrode contact and a second bottom electrode plate; (k) a step in which steps (b) through (d) are repeated to form a fourth dielectric stack, a plurality of second bottom electrode extensions, and a fifth dielectric stack; (l) a step in which a second contact opening is formed through the fifth dielectric stack, the fourth dielectric stack, and the third dielectric stack until a first top electrode plate is exposed; and (m) a step in which a plurality of extension openings is formed through the fifth dielectric stack and the upper dielectric layer of the fourth dielectric stack until an etch stop layer of the fourth dielectric stack is exposed.The method includes: (n) forming a top electrode plate groove in the top dielectric layer of the fifth dielectric stack, wherein the top electrode plate groove, the plurality of extension openings, and the second contact opening constitute a second dual damascene opening; (o) forming a conductive material in the second dual damascene opening to simultaneously form a second electrode contact, a plurality of second top electrode extensions, and a second top electrode plate; and (p) repeating steps (g) to (o) at least once.

[0008] As described above, the present invention stacks multiple sub-capacitance stack structures and directly connects the sub-capacitance stack structures with electrode contacts to form a closely stacked, high-capacity 3D structure, making the structure less susceptible to collapse. Furthermore, by providing an etching stop layer within the sub-capacitance stack structure, the thickness of each layer can be controlled, resulting in an optimal stack. In other words, an optimal upper limit arrangement can be obtained as needed. [Effects of the Invention]

[0009] In order to make the above features of the present invention more clearly understandable, the present invention will be described in detail below with reference to embodiments and accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a 3D capacitance structure according to a first embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of the 3D capacitance structure taken along line II' in FIG. 1; [Figure 3] 2 is a cross-sectional view of another 3D capacitance structure taken along line II' of FIG. 1. [Figure 4] FIG. 2 is a cross-sectional view of a 3D capacitance structure according to a second embodiment of the present invention. [Figure 5A] 10A-10C are cross-sectional schematic diagrams of different stages in the manufacturing process of a 3D capacitance structure according to a third embodiment of the present invention. [Figure 5B]10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5C] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5D] 10A-10C are cross-sectional schematic diagrams illustrating a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5E] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5F] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5G] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5H] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5I] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5J] 10A-10C are cross-sectional schematic diagrams illustrating a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5K] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5L] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5M] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5N] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5O] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5P] 10A-10C are cross-sectional schematic views of a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5Q] 10A-10C are cross-sectional schematic diagrams illustrating a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5R] 10A-10C are cross-sectional schematic diagrams illustrating a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. [Figure 5S] 10A-10C are cross-sectional schematic diagrams illustrating a stage in the manufacturing process of a 3D capacitance structure according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a cross-sectional view of a 3D capacitance structure 10 according to a first embodiment of the present invention. Referring to FIG. 1, the 3D capacitance structure 10 of this embodiment includes a substrate 100, a plurality of sub-capacitance stack structures SC, a plurality of first electrode contacts E1, and a plurality of second electrode contacts E2. The sub-capacitance stack structures SC are disposed on the substrate 100, and each sub-capacitance stack structure SC includes a dielectric stack DS, a lower electrode structure LE, and an upper electrode structure UE. The dielectric stack DS includes a lower dielectric layer 102, a lower etch stop layer 104, an intermediate dielectric layer 106, an upper etch stop layer 108, and an upper dielectric layer 110, which are stacked one on the other. In one embodiment, the lower dielectric layer 102, the intermediate dielectric layer 106, and the upper dielectric layer 110 include silicon oxide, and the lower etch stop layer 104 and the upper etch stop layer 108 include silicon nitride. However, the present invention is not limited thereto. The lower electrode structure LE includes a lower electrode plate 112 disposed in the lower dielectric layer 102 and a plurality of lower electrode extensions 114 extending upward from the lower electrode plate 112 and penetrating the lower etch stop layer 104 into the intermediate dielectric layer 106. The upper electrode structure UE includes an upper electrode plate 116 disposed in the upper dielectric layer 110 and a plurality of upper electrode extensions 118 extending downward from the upper electrode plate 116 and penetrating the upper etch stop layer 108 and the intermediate dielectric layer 106 onto the lower etch stop layer 104. In other words, the 3D capacitance structure 10 has three sub-capacitance stack structures SC. However, the present invention is not limited thereto. In another embodiment, the number of stacks in the sub-capacitance stack structure SC may be greater.

[0012] 1, the extension directions of the lower electrode extension portion 114 and the upper electrode extension portion 118 are perpendicular to the surface direction of the substrate 100. The surface directions of the lower electrode plate 112 and the upper electrode plate 116 are perpendicular to the extension directions of the first electrode contact E1 and the second electrode contact E2.

[0013] 1 , the plurality of first electrode contacts E1 are respectively connected to two adjacent lower electrode plates 112 in the sub-capacitance stack structure SC, with each first electrode contact E1 directly contacting the adjacent upper lower electrode plate 112 and lower lower electrode plate 112. The plurality of second electrode contacts E2 are respectively connected to two adjacent upper electrode plates 116 in the sub-capacitance stack structure SC, with each second electrode contact E2 directly contacting the adjacent upper upper electrode plate 116 and lower upper electrode plate 116. Because the heights of the first electrode contacts E1 and second electrode contacts E2 connecting the upper and lower sub-capacitance stack structures SC are fixed to approximately one dielectric stack DS, a stacked 3D capacitance structure 10 can be constructed without the need for any other connecting structure. Additionally, the upper etch stop layer 108 and the lower etch stop layer 104 in the dielectric stack DS are advantageous for controlling the thickness of each layer, for example, the size (e.g., height) of the upper electrode extension 118 can be controlled via the lower etch stop layer 104, thereby obtaining an optimal stack. Also, another etch stop layer 120 may be added between the upper and lower sub-capacitance stack structures SC to serve as a stop layer during the formation of the lower electrode plate 112.

[0014] An internal wiring structure can be formed on the substrate 100 to connect the wiring of the 3D capacitance structure 10 to the outside or other components. For example, the internal wiring structure includes an insulating layer 122 covering the entire 3D capacitance structure 10, a first contact C1 connected to one lower electrode plate 112, a second contact C2 connected to one upper electrode plate 116, a first metal layer 124 located on the insulating layer 122 and connected to the first contact C1, and a second metal layer 126 located on the insulating layer 122 and connected to the second contact C2. However, the present invention is not limited thereto. In another embodiment, the internal wiring structure can include multiple first contacts C1 and multiple second contacts C2, and their positions can be changed as needed.

[0015] FIG. 2 is a cross-sectional view of the 3D capacitance structure 10 taken along line I-I' in FIG. 1. Because FIG. 1 shows a cross section in the xz plane and FIG. 2 shows a cross section in the yz plane, FIG. 2 only shows the dielectric stack DS, upper electrode plate 116, lower electrode plate 112, and lower electrode extension 114 of the sub-capacitance stack structure SC, with the dotted line indicating the position of the upper electrode extension 118. Therefore, the lower electrode extension 114 and the upper electrode extension 118 of the first embodiment may have a stripe structure intersecting along the x direction. However, the present invention is not limited to this.

[0016] Figure 3 is a cross-sectional view of another type of 3D capacitance structure 10 taken along line I-I' in Figure 1. Figure 3 is also a cross-section in the yz plane, showing that the bottom electrode extensions 114 and top electrode extensions 118 are columnar structures intersecting along the x and y directions. Because the area between the bottom electrode extensions 114 and top electrode extensions 118 in Figure 3 is larger than that in the structure in Figure 2, Figure 3 has a larger capacitance compared to Figure 2, with all other structures remaining the same.

[0017] 4 is a cross-sectional view of a 3D capacitance structure 40 according to a second embodiment of the present invention, in which the same element symbols as those in the first embodiment are used to represent the same or similar parts and components. Contents relating to the same or similar parts and components can be referred to in the first embodiment, and therefore will not be repeated here.

[0018] Referring to FIG. 4 , the 3D capacitance structure 40 of the second embodiment is essentially the same as the 3D capacitance structure 10 of the first embodiment, except that the 3D capacitance structure 40 has a total of eight sub-capacitance stack structures SC. To ensure the structural stability of the first contacts C1 and prevent collapse, the eight sub-capacitance stack structures SC are divided into two groups, with one first contact C1 for every four lower electrode plates 112. The first contacts C1 are connected in series to the first metal layer 124. The second electrode contacts E2 and C2 between the upper electrode plates 116 can maintain their original design due to their relatively small size. However, the present invention is not limited thereto. In another embodiment, the connection design between the upper electrode plates 116 may be interchanged with the connection design between the lower electrode plates 112.

[0019] 5A to 5S are cross-sectional views illustrating a manufacturing process of a 3D capacitance structure according to a third embodiment of the present invention. Referring to FIG. 5A, the manufacturing method of this embodiment first forms a first lower electrode plate 502 on a substrate 500 using a method such as electroplating (step (a)). Then, a first dielectric stack DS1 can be formed on the first lower electrode plate 502 (step (b)). The first dielectric stack DS1 includes a stacked lower dielectric layer LD, an etching stop layer SL, and an upper dielectric layer UD. Then, photolithography and etching processes can be used to form multiple extension openings 504 in the first dielectric stack DS1. Because there is an etching selectivity between the etching stop layer SL and the upper and lower dielectric layers UD and LD in the first dielectric stack DS1, different etching gases are used to etch different materials in the etching process for forming the extension openings 504.

[0020] 5B, a conductive material M1 is then filled into the extension openings 504 using a method such as electroplating to form a plurality of first bottom electrode extensions 506 in the first dielectric stack DS1 (step (c)). The first bottom electrode extensions 506 extend upward from the first bottom electrode plate 502 through the etching stop layer SL into the upper dielectric layer UD. In one embodiment, the extension direction of the plurality of first bottom electrode extensions 506 is perpendicular to the surface direction of the substrate 500.

[0021] 5C, a planarization process may be performed first, for example, using a chemical mechanical polishing (CMP) method to leave the first bottom electrode extension 506, and then a second dielectric stack DS2 may be formed (step (d)). The structure of the second dielectric stack DS2 is the same as that of the first dielectric stack DS1, but the thickness and material of each layer of the second dielectric stack DS2 can be adjusted as needed and do not need to be exactly the same as that of the first dielectric stack DS1.

[0022] Then, referring to FIG. 5D, photolithography and etching processes can be used to form multiple extension openings 508 in the second dielectric stack DS2 until the etching stop layer SL of the first dielectric stack DS1 is exposed, which can serve as the intended formation locations for the upper electrode extensions.

[0023] 5E, another photolithography and etching process can be used to form a top electrode plate groove 510 in the upper dielectric layer UD of the second dielectric stack DS2. The top electrode plate groove 510 and the extension opening 508 constitute a dual damascene opening.

[0024] 5F, a conductive material M2 is then filled into the top electrode plate groove 510 and the extension opening 508 using a method such as electroplating to form a plurality of first top electrode extensions 512 in the second dielectric stack DS2 (step (e)), and a first top electrode plate 514 is formed in the upper dielectric layer UD of the second dielectric stack DS2 (step (f)). Since this embodiment employs a dual damascene process, the first top electrode plate 514 and the plurality of first top electrode extensions 512 connected to each other can be formed simultaneously. However, the present invention is not limited thereto. In another embodiment, the plurality of first top electrode extensions 512 may be formed first, and then the first top electrode plate 514 may be formed. The first top electrode extension 512 extends through the etching stop layer SL of the second dielectric stack DS2 and onto the etching stop layer SL of the first dielectric stack DS1. That is, the size (e.g., height) of the first top electrode extension 512 can be precisely controlled via the etching stop layer SL. In one embodiment, the extension direction of the plurality of first upper electrode extensions 512 is perpendicular to the surface direction of the substrate 500. In one embodiment, the plurality of first lower electrode extensions 506 and the plurality of first upper electrode extensions 512 have a stripe structure intertwined along the x direction (similar to the structure in FIG. 2). In another embodiment, the plurality of first lower electrode extensions 506 and the plurality of first upper electrode extensions 512 have a columnar structure intertwined along the x and y directions (similar to the structure in FIG. 3).

[0025] 5G, a planarization process is first performed using a method such as CMP to leave the first upper electrode extension 512 and the first upper electrode plate 514, and then a third dielectric stack DS3 can be formed (step (g)). The structure of the third dielectric stack DS3 is the same as that of the first dielectric stack DS1, but the thickness and material of each layer of the third dielectric stack DS3 can be adjusted as needed and do not need to be exactly the same as that of the first dielectric stack DS1.

[0026] Next, referring to FIG. 5H, a photolithography and etching process can be used to form a first contact opening EO1 that penetrates the third dielectric stack DS3, the second dielectric stack DS2, and the first dielectric stack DS1 until the first lower electrode plate 502 is exposed (step (h)).

[0027] 5I, a bottom electrode plate groove 516 is formed in the upper dielectric layer UD of the third dielectric stack DS3, and the bottom electrode plate groove 516 and the first contact opening EO1 constitute a first dual damascene opening (step (i)). Furthermore, in this embodiment, in the step of forming the bottom electrode plate groove 516 described above, the etch stop layer SL of the third dielectric stack DS3 can be used as a stop layer.

[0028] 5J, a conductive material can be formed in the bottom electrode plate groove 516 and the first contact opening EO1 (first dual damascene opening) using electroplating to simultaneously form the first electrode contact E1 and the second bottom electrode plate 518 (step (j)). In one example, the extension direction of the first electrode contact E1 is perpendicular to the surface direction of the first bottom electrode plate 502.

[0029] Next, referring to FIG. 5K, the steps of forming the first dielectric stack DS1 to forming the second dielectric stack DS2 can be repeated to form a fourth dielectric stack DS4, multiple second lower electrode extensions 520, and a fifth dielectric stack DS5 (step (k)).

[0030] Next, referring to FIG. 5L, a second contact opening EO2 can be formed through the fifth dielectric stack DS5, the fourth dielectric stack DS4, and the third dielectric stack DS3 until the first upper electrode plate 514 is exposed (step (l)).

[0031] 5M, a mask layer 522 is first formed on the fifth dielectric stack DS5 to fill the second contact openings EO2. Here, the mask layer 522 is, for example, SOC or photoresist. Then, a photolithography process can be used to form multiple mask openings 524 in the mask layer 522, which are intended to form the upper electrode extensions.

[0032] 5N, using the mask layer 522 of FIG. 5M as an etching mask, the fifth dielectric stack DS5 exposed from the mask openings 524 is etched and removed until the etch stop layer SL of the fourth dielectric stack DS4 is exposed, thereby forming a plurality of extension openings 526 (step (m)). Then, the mask layer 522 of FIG. 5M is removed.

[0033] 5O, a photolithography and etching process can be used to form a top electrode plate groove 528 in the top dielectric layer UD of the fifth dielectric stack DS5 (step (n)). The above-mentioned top electrode plate groove 528, the plurality of extension openings 526, and the second contact opening EO2 constitute a second dual damascene opening.

[0034] 5P, a conductive material is formed in the upper electrode plate groove 528, the extension opening 526, and the second contact opening EO2 (second dual damascene opening) using electroplating, thereby simultaneously forming the second electrode contact E2, the plurality of second upper electrode extensions 530, and the second upper electrode plate 532 (step (o)). In one embodiment, the extension direction of the second electrode contact E2 is perpendicular to the surface direction of the first upper electrode plate 514.

[0035] 5Q, the steps from FIG. 5G to FIG. 5P can be repeated at least once (step (p)) to form a 3D capacitance structure 50. The present invention is not limited thereto, and the above steps can be repeated more times as needed to form a 3D capacitance structure having a greater number of stacks.

[0036] 5R, to connect the wiring of the 3D capacitance structure 50 to the outside or other elements, an internal wiring structure can be formed on the substrate 500. For example, first, spaces for contacts are defined on the side surfaces of the 3D capacitance structure 50, and then an insulating layer 534 is formed to cover the entire 3D capacitance structure 50.

[0037] 5S, first, a first contact C1 connected to one first lower electrode plate 502 and a second contact C2 connected to one second upper electrode plate 532 are formed in an insulating layer 534, and then a first metal layer 536 connected to the first contact C1 and a second metal layer 538 connected to the second contact C2 are formed on the insulating layer 534. However, the present invention is not limited thereto. In another embodiment, the internal wiring structure may include a plurality of first contacts C1 and a plurality of second contacts C2, and their positions may be changed as needed.

[0038] As described above, the present invention allows for the formation of a closely stacked, high-capacitance 3D structure by stacking multiple sub-capacitance stack structures and directly connecting the sub-capacitance stack structures with electrode contacts, thereby increasing capacitance and making the multilayer structure less susceptible to collapse. Furthermore, by providing an etching stop layer within the above-described sub-capacitance stack structure, the thickness of each layer can be controlled, resulting in an optimal stack. In other words, an optimal upper limit arrangement can be achieved as needed.

[0039] Although the present invention has been disclosed by the above embodiments, the present invention is not limited to these. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention, and the scope of protection of the present invention is defined by the following claims. [Industrial Applicability]

[0040] The 3D capacitance structure and its manufacturing method of the present invention can be applied to a large-capacity semiconductor capacitance structure and its manufacturing method. [Explanation of symbols]

[0041] 10, 40, 50 3D capacitance structure 100, 500 boards 102, LD lower dielectric layer 104 Lower etch stop layer 106 Intermediate dielectric layer 108 Upper etch stop layer 110, UD upper dielectric layer 112 Lower electrode plate 114 Lower electrode extension part 116 Upper electrode plate 118 Upper electrode extension part 120 Etching stop layer 122, 534 insulating layer 124, 536 1st metal layer 126, 538 2nd metal layer 502 1st lower electrode plate 504, 508, 526 Extension opening 506 First lower electrode extension part 510 Upper electrode plate groove 512 First upper electrode extension part 514 1st upper electrode plate 516 Lower electrode plate groove 518 Second lower electrode plate 520 Second lower electrode extension part 522 Mask Layer 524 Mask Opening 528 Upper electrode plate groove 530 Second upper electrode extension part 532 2nd upper electrode plate C1 First Contact C2 Second Contact DS Dielectric Stack DS1 First Dielectric Stack DS2 Second Dielectric Stack DS3 Third Dielectric Stack DS4 4th Dielectric Stack DS5 5th Dielectric Stack E1 First electrode contact E2 Second electrode contact EO1 First contact opening EO2 Second contact opening LE bottom electrode structure M1, M2 conductor material SC Sub-capacitance stack structure SL Etching stop layer UE upper electrode structure

Claims

1. A substrate; disposed on the substrate, a dielectric stack including a stacked lower dielectric layer, a lower etch stop layer, an intermediate dielectric layer, an upper etch stop layer, and an upper dielectric layer; a lower electrode structure including a lower electrode plate disposed within the lower dielectric layer and a plurality of lower electrode extensions extending upward from the lower electrode plate and penetrating the lower etch stop layer into the intermediate dielectric layer; an upper electrode structure including an upper electrode plate disposed within the upper dielectric layer and directly contacting the upper etch stop layer, and a plurality of upper electrode extensions extending downward from the upper electrode plate to above the lower etch stop layer, passing through the upper etch stop layer and the intermediate dielectric layer; a plurality of sub-capacitance stack structures each including: a plurality of first electrode contacts respectively connecting the lower electrode plates of two adjacent layers in the plurality of sub-capacitance stack structures; a plurality of second electrode contacts respectively connecting the upper electrode plates of two adjacent layers in the plurality of sub-capacitance stack structures; A 3D capacitance structure comprising:

2. The 3D capacitance structure according to claim 1 , wherein the extension directions of the plurality of lower electrode extension portions and the plurality of upper electrode extension portions are perpendicular to the surface direction of the substrate.

3. The 3D capacitance structure according to claim 1 , wherein the plane direction of the lower electrode plate and the upper electrode plate is perpendicular to the extension direction of the plurality of first electrode contacts and the plurality of second electrode contacts.

4. The 3D capacitance structure of claim 1 , wherein the plurality of bottom electrode extensions and the plurality of top electrode extensions are in a stripe structure intertwined along the x-direction.

5. The 3D capacitance structure of claim 1 , wherein the plurality of bottom electrode extensions and the plurality of top electrode extensions are columnar structures intertwined along the x and y directions.

6. 10. The 3D capacitance structure of claim 1, wherein the lower dielectric layer, the middle dielectric layer, and the upper dielectric layer comprise silicon oxide, and the lower etch stop layer and the upper etch stop layer comprise silicon nitride.

7. 1. A method for manufacturing a 3D capacitance structure, comprising: (a) forming a first lower electrode plate on a substrate; (b) forming a first dielectric stack on the first lower electrode plate, the first dielectric stack including a lower dielectric layer, an etch stop layer, and an upper dielectric layer stacked together; (c) forming a plurality of first bottom electrode extensions in the first dielectric stack, the plurality of first bottom electrode extensions penetrating the etch stop layer upward from the first bottom electrode plate into the upper dielectric layer; Step (d) of forming a second dielectric stack, the second dielectric stack having the same structure as the first dielectric stack; (e) forming a plurality of first top electrode extensions in the second dielectric stack, the plurality of first top electrode extensions extending through an etch stop layer of the second dielectric stack and onto an etch stop layer of the first dielectric stack; (f) forming a first upper electrode plate in the upper dielectric layer of the second dielectric stack in direct contact with the etch stop layer of the second dielectric stack, the first upper electrode plate being connected to the plurality of first upper electrode extensions; Step (g) of forming a third dielectric stack, the structure of said third dielectric stack being the same as that of said first dielectric stack; (h) forming a first contact opening through the third dielectric stack, the second dielectric stack, and the first dielectric stack until the first bottom electrode plate is exposed; (i) forming a bottom electrode plate trench in an upper dielectric layer of the third dielectric stack, the bottom electrode plate trench together with the first contact opening forming a first dual damascene opening; (j) forming a conductive material in the first dual damascene opening and simultaneously forming a first electrode contact and a second bottom electrode plate in direct contact with an etch stop layer of the third dielectric stack; (k) repeating steps (b) through (d) to form a fourth dielectric stack, a plurality of second bottom electrode extensions, and a fifth dielectric stack; (l) forming a second contact opening through the fifth dielectric stack, the fourth dielectric stack, and the third dielectric stack until the first top electrode plate is exposed; (m) forming a plurality of extension openings through the fifth dielectric stack and the upper dielectric layer of the fourth dielectric stack until an etch stop layer of the fourth dielectric stack is exposed; (n) forming a top electrode plate groove in an upper dielectric layer of the fifth dielectric stack, the top electrode plate groove, the plurality of extension openings, and the second contact opening comprising a second dual damascene opening; (o) forming a conductive material in the second dual damascene opening to simultaneously form a second electrode contact, a plurality of second top electrode extensions, and a second top electrode plate in direct contact with an etch stop layer of the fifth dielectric stack; Step (p) of repeating steps (g) through (o) at least once; A method for manufacturing a 3D capacitance structure comprising:

8. The method for manufacturing a 3D capacitance structure according to claim 7 , wherein the extension direction of the plurality of first lower electrode extension portions and the plurality of first upper electrode extension portions is perpendicular to the surface direction of the substrate.

9. The method for manufacturing a 3D capacitance structure according to claim 7 , wherein the surface direction of the first lower electrode plate and the first upper electrode plate is perpendicular to the extension direction of the first electrode contact and the second electrode contact.

10. The method for manufacturing a 3D capacitance structure according to claim 7 , wherein the plurality of first lower electrode extensions and the plurality of first upper electrode extensions have a stripe structure intersecting along the x direction.

11. The method for manufacturing a 3D capacitance structure according to claim 7 , wherein the plurality of first lower electrode extensions and the plurality of first upper electrode extensions have a columnar structure intersecting along the x-direction and the y-direction.

12. The method for fabricating a 3D capacitance structure according to claim 7 , wherein the step of forming the bottom electrode plate groove uses an etch stop layer of the third dielectric stack as a stop layer.

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