Power Conversion Device

Abstract

To provide a power conversion device capable of suppressing both noise peak value and noise average value and also suppressing current distortion by setting fluctuations of a common mode voltage that becomes a factor of common mode noise to be equal to or less than a prescribed number of times even when measured at any timing.SOLUTION: A power conversion device includes: an inverter circuit 28 for applying a phase voltage at a connection point of upper and lower arm switching elements 18A to 18F of each phase to a load; and a control device 21. The control device 21 controls switching of the upper and lower arm switching elements 18A to 18F so that the number of times of fluctuations of a common mode voltage in a predetermined measurement bandwidth is equal to or less than a predetermined specification number of times N (N is an integer of one or more) regardless of measurement timing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion device that converts a DC voltage into an AC voltage. [Background technology]

[0002] Various pulse width modulation (PWM) techniques have been proposed to suppress conducted noise propagating to power supplies, but these methods can be broadly divided into two categories: one method completely suppresses fluctuations in common-mode voltage, which is the cause of common-mode noise, and the other method partially suppresses common-mode voltage while allowing it to fluctuate.

[0003] The former method is pulse width modulation, which outputs only odd voltage vectors or only even voltage vectors. This method makes it possible to completely suppress fluctuations in common mode voltage within a carrier cycle. There is also pulse width modulation, which switches between outputting only odd voltage vectors or only even voltage vectors depending on the electrical angle phase. This method also makes it possible to significantly suppress fluctuations in common mode voltage (see, for example, Patent Document 1).

[0004] The latter technique includes pulse width modulation, which synchronizes (shifts) the rising and falling timing of the phase voltage of a specific phase with the rising and falling timing of the phase voltage of another phase in a PWM pattern (see, for example, Patent Document 2).Furthermore, fluctuations in the common mode voltage can also be suppressed by pulse width modulation of two-phase modulation, which fixes the switching of one phase and switches the other two phases (see, for example, Patent Document 3).

[0005] However, although the former method (Patent Document 1) is the most effective method for suppressing common-mode voltage fluctuations, it has the drawback of being limited in the linear output region (the maximum amplitude at which the voltage vector can make one rotation at a certain radius) due to limitations on the voltage vector that can be used, and thus limiting the modulation rate that can be output. As a result, when driving a compressor motor, for example, noise associated with current distortion is excited, making it difficult to apply, or when the rotation speed and modulation rate are high, it is necessary to switch modulation methods as in Patent Document 3.

[0006] In contrast, the latter method (Patent Document 2 and Patent Document 3) can utilize the linear output region up to the normal maximum and can achieve a high modulation rate, but is still inferior to the former method in suppressing fluctuations in common-mode voltage. Note that Patent Document 3 switches between two-phase modulation and three-phase modulation depending on the operating region, and while it is possible to switch between the former and latter methods in a similar manner, a switching shock occurs when switching between pulse-width modulation methods. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 5397448 [Patent Document 2] WO2019 / 180763 [Patent Document 3] Patent No. 5298003 [Patent Document 4] Patent No. 5976067 Summary of the Invention [Problem to be solved by the invention]

[0008] Here, noise measurement in a typical three-phase inverter is performed by connecting a line-input artificial mains network (LISN) to the input, and then capturing and measuring the output of this artificial mains network with a spectrum analyzer or EMC receiver. These spectrum analyzers and EMC receivers have a specified measurement bandwidth known as the resolution bandwidth (RBW), and for noise measurement, the interval specified by this measurement bandwidth becomes the measurement window (frequency window), and the frequency components within the measurement window are output as spectral intensity. In this case, if the same frequency component exists multiple times within the measurement window, the spectral intensity is integrated for each occurrence.

[0009] Figure 10 shows such a measurement window and the measured waveform. Note that Figure 10 shows the case of FFT analysis. FFT analysis is performed only on the waveform observed in the measurement window. Therefore, as long as the window length of the measurement window and the period of the measured waveform match, as shown in Figure 10, there is no problem. However, if the measurement window and the period of the measured waveform differ, as shown in Figure 11, frequency analysis will be performed on a discontinuous waveform, as shown in Figure 12. This will result in the observation of a frequency spectrum that does not actually exist, and there is also the risk that the intensity of the spectrum will be overestimated depending on the phase observed in the measurement window. To address this issue, a window function is used in FFT analysis, and in spectrum analyzers and EMC receivers, the IF filter (bandpass filter) corresponds to the window function.

[0010] In EMI testing, measurements like the one above are performed for a specified period of time at each frequency point. The maximum value of the time response at each frequency point is the noise peak value, and the average value of the time response is the noise average value. On the other hand, the conventional common mode noise suppression method mentioned above is based on pulse shifting, so there are operations where common mode voltage fluctuations are concentrated.

[0011] Figure 13 shows an example of common-mode noise (conductive noise) generated in this conventional common-mode noise suppression method. In the example of Figure 13, common-mode noise generation is suppressed to two times in each control cycle, with common-mode noise occurring four times in the measurement window indicated by X1 in the figure and occurring twice in the measurement window indicated by X3. However, in the measurement window indicated by X2 where common-mode voltage fluctuations are concentrated, it is measured as occurring six times, which creates a problem in that the noise peak value is measured as six times.

[0012] For example, in Patent Document 4, a carrier waveform that has been spectrum-spread by a carrier generation unit is calculated for each of three phases in accordance with a spectrum spread index defined by a spectrum spread index command generation unit, and the switching frequency of each phase is spread by spectrum spread, thereby reducing the peak of electromagnetic noise caused by switching.However, in the noise measurement described above, this only reduces the noise average value, and actually worsens the noise peak value.

[0013] The present invention has been made to solve the above-mentioned conventional technical problems, and has an object to provide a power conversion device that can suppress both the noise peak value and the noise average value and also suppress current distortion by keeping the fluctuations in common-mode voltage, which is a cause of common-mode noise, below a specified number of times regardless of when the measurement is made. [Means for solving the problem]

[0014] The power conversion device of the present invention converts DC voltage into AC voltage and includes an inverter circuit that applies a phase voltage at a connection point between upper and lower arm switching elements of each phase to a load, and a control device that controls the switching of each upper and lower arm switching element, and the control device controls the switching of the upper and lower arm switching elements so that the number of fluctuations of the common mode voltage in a predetermined measurement bandwidth is kept below a predetermined specified number N (N is an integer equal to or greater than 1) regardless of the measurement timing.

[0015] The power conversion device of the invention of claim 2 is characterized in that in the above invention, the control device controls the number of fluctuations of the common mode voltage to a specified number N or less by simultaneously switching the upper and lower arm switching elements of different phases with opposite polarities to each other.

[0016] The power conversion device of the invention of claim 3 is characterized in that in the invention of claim 1, the control device has a voltage pattern group generation unit that references the voltage vector pattern in the previous control cycle and generates a plurality of voltage vector patterns in which the number of fluctuations of the common mode voltage in the measurement bandwidth is equal to or less than a specified number N regardless of the measurement timing.

[0017] The power conversion device of the invention of claim 4 is characterized in that in the above invention, when the switching frequency is greater than the measurement bandwidth, the voltage pattern group generation unit generates a voltage vector pattern that simultaneously switches upper and lower arm switching elements of different phases with opposite polarities to each other by outputting an even voltage vector after an even voltage vector, or an odd voltage vector after an odd voltage vector, in one control period, and sets the number of fluctuations of the common mode voltage to a specified number N or less.

[0018] The power conversion device of the invention of claim 5 is characterized in that in the invention of claim 3 or claim 4, the voltage pattern group generation unit generates multiple voltage vector patterns by adding a constraint that the number of switching times of each phase in one control period is equal to or less than a predetermined limit number.

[0019] The power conversion device of the invention of claim 6 is characterized in that in the invention of claim 3 or claim 4, the control device has a current command calculation unit that calculates a current command value, a current prediction calculation unit that calculates a current prediction value of each voltage vector pattern generated by the voltage pattern group generation unit, and an optimal voltage pattern selection unit that selects, from each voltage vector pattern generated by the voltage pattern group generation unit, a voltage vector pattern that minimizes the error between the current command value and the current prediction value.

[0020] The power conversion device of the invention of claim 7 is characterized in that in the above invention, the inverter circuit applies a phase voltage at a connection point of the upper and lower arm switching elements of each phase to the motor to drive it.

[0021] The power conversion device of the invention of claim 8 is characterized in that in the invention of claim 6, the optimal voltage pattern selection unit selects the optimal voltage vector pattern based on the number of fluctuations of the common mode voltage and the error between the current command value and the current predicted value.

[0022] The power conversion device of the invention of claim 9 is characterized in that in the above invention, the optimal voltage pattern selection unit assigns a higher priority to the number of fluctuations of the common mode voltage than to the error between the current command value and the current prediction value, and selects the optimal voltage vector pattern. [Effects of the Invention]

[0023] According to the present invention, a power conversion device for converting DC voltage to AC voltage includes an inverter circuit that applies a phase voltage at a connection point between upper and lower arm switching elements of each phase to a load, and a control device that controls the switching of each upper and lower arm switching element, and the control device controls the switching of the upper and lower arm switching elements so that the number of common-mode voltage fluctuations in a predetermined measurement bandwidth is equal to or less than a predetermined number N (N is an integer greater than or equal to 1) regardless of the measurement timing, thereby suppressing and minimizing both the average value and peak value of common-mode noise generated by common-mode voltage fluctuations. It also becomes possible to suppress electromagnetic interference to peripheral devices caused by concentrated common-mode voltage fluctuations and concentrated common-mode noise.

[0024] In this case, if the control device controls the number of fluctuations of the common-mode voltage to a specified number N or less by simultaneously switching the upper and lower arm switching elements of different phases with opposite polarities, as in the invention of claim 2, it becomes possible to smoothly control the number of fluctuations of the common-mode voltage to a specified number N or less, particularly when the switching frequency is higher than the measurement bandwidth.

[0025] Furthermore, as in the invention of claim 3, if the control device is configured to have a voltage pattern group generation unit that references the voltage vector pattern in the previous control cycle and generates a plurality of voltage vector patterns that keep the number of fluctuations of the common-mode voltage in the measurement bandwidth below a specified number N regardless of the measurement timing, it becomes possible to effectively control the peak value of the common-mode noise to below the specified number N.

[0026] In this case, as in the invention of claim 4, when the switching frequency is greater than the measurement bandwidth, the voltage pattern group generation unit outputs an even voltage vector after an even voltage vector, or an odd voltage vector after an odd voltage vector, in one control cycle to generate voltage vector patterns that simultaneously switch upper and lower arm switching elements of different phases with opposite polarities to each other, and the number of fluctuations of the common mode voltage is set to a specified number N or less.

[0027] Furthermore, as in the invention of claim 5, if the voltage pattern group generation unit generates multiple voltage vector patterns by adding a constraint that the number of switching times for each phase in one control cycle is equal to or less than a predetermined limit, it becomes possible to prevent the inconvenience of the switching frequency exceeding the rated frequency of the semiconductors that make up the control device.

[0028] Furthermore, according to the invention of claim 6, the control device is configured to include a current command calculation unit that calculates a current command value, a current prediction calculation unit that calculates a current prediction value for each voltage vector pattern generated by the voltage pattern group generation unit, and an optimal voltage pattern selection unit that selects, from the voltage vector patterns generated by the voltage pattern group generation unit, a voltage vector pattern that minimizes the error between the current command value and the current prediction value, thereby making it possible to suppress the average value of common-mode noise while taking current response into consideration.In addition, since current distortion can be suppressed over the entire operating range, noise is less likely to be excited, making it extremely effective when driving a motor as a load, as in the invention of claim 7.

[0029] In this case, if the optimum voltage pattern selection unit selects the optimum voltage vector pattern based on the number of fluctuations of the common-mode voltage and the error between the current command value and the current prediction value, as in the invention of claim 8, it becomes possible to smoothly achieve both suppression of common-mode noise and improvement of current response.

[0030] Furthermore, as in the invention of claim 9, if the optimal voltage pattern selection unit assigns a higher priority to the number of fluctuations of the common-mode voltage than to the error between the current command value and the current prediction value and selects the optimal voltage vector pattern, it becomes possible to select an optimal voltage vector pattern with good current response while reliably suppressing fluctuations in the common-mode voltage. [Brief explanation of the drawings]

[0031] [Figure 1] 1 is an electrical circuit diagram of a power conversion device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a diagram illustrating the relationship between voltage vectors and phase voltages. [Figure 3] FIG. 10 is a diagram showing voltage vectors (output basic vectors). [Figure 4] 2 is a diagram illustrating an example of a voltage vector pattern generated by a voltage pattern group generating unit of the control device of FIG. 1. FIG. [Figure 5] 1. FIG. 4 is a diagram illustrating an example of a search operation for a voltage vector pattern by a voltage pattern group generating unit of the control device of FIG. [Figure 6] 2 is a diagram showing an operation waveform at a low modulation rate in the power conversion device of the present invention shown in FIG. 1. FIG. [Figure 7] 2 is a diagram showing an operation waveform at a medium modulation factor in the power conversion device of the present invention shown in FIG. 1. FIG. [Figure 8] 2 is a diagram showing an operation waveform at a high modulation rate in the power conversion device of the present invention shown in FIG. 1. FIG. [Figure 9] 2 is a diagram showing an example of common mode noise generation in the case of the power conversion device of the present invention shown in FIG. 1. FIG. [Figure 10]10A and 10B are diagrams illustrating a measurement window and a measurement waveform when the window length of the measurement window and the period of the measurement waveform match. [Figure 11] 10A and 10B are diagrams illustrating a measurement window and a measurement waveform when the window length of the measurement window and the period of the measurement waveform are different. [Figure 12] 12 is a diagram showing a measured waveform to be analyzed in the case of FIG. 11. FIG. [Figure 13] 10A and 10B are diagrams illustrating an example of common mode noise generated in a conventional power conversion device. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. A power conversion device 1 of the embodiment to which the present invention is applied drives a motor 8 (load) of a so-called inverter-integrated electric compressor that constitutes a refrigerant circuit of a vehicle air conditioner mounted on a vehicle such as an electric automobile.

[0033] (1) Circuit configuration of power conversion device 1 1, the power conversion device 1 of the embodiment includes a three-phase inverter circuit 28 and a control device 21. The inverter circuit 28 is a circuit that converts the DC voltage of a DC power source (vehicle battery: for example, DC 350 V) 29 into a three-phase AC voltage (U-phase voltage Vu, V-phase voltage Vv, W-phase voltage Vw) and applies it to the motor 8. In this case, the motor 8 of the embodiment is an IPMSM (Interior Permanent Magnet Synchronous Motor).

[0034] The inverter circuit 28 includes a U-phase half-bridge circuit 19U, a V-phase half-bridge circuit 19V, and a W-phase half-bridge circuit 19W. Each of the half-bridge circuits 19U to 19W for each phase includes upper arm switching elements 18A to 18C and lower arm switching elements 18D to 18F. Furthermore, a flywheel diode 31 is connected in anti-parallel to each of the switching elements 18A to 18F. In this embodiment, each of the upper and lower arm switching elements 18A to 18F is configured as an insulated gate bipolar transistor (IGBT) incorporating a MOS structure in the gate portion.

[0035] The collectors of the upper arm switching elements 18A to 18C of the inverter circuit 28 are connected to an upper arm power supply line (positive bus) 10 of the DC power supply 29. On the other hand, the emitters of the lower arm switching elements 18D to 18F of the inverter circuit 28 are connected to a lower arm power supply line (negative bus) 15 of the DC power supply 29.

[0036] In this case, the emitter of upper arm switching element 18A and the collector of lower arm switching element 18D of U-phase half-bridge circuit 19U are connected in series, the emitter of upper arm switching element 18B and the collector of lower arm switching element 18E of V-phase half-bridge circuit 19V are connected in series, and the emitter of upper arm switching element 18C and the collector of lower arm switching element 18F of W-phase half-bridge circuit 19W are connected in series.

[0037] The connection point between the upper arm switching element 18A and the lower arm switching element 18D of the U-phase half-bridge circuit 19U (midpoint of the upper and lower arms: U-phase voltage Vu) is connected to the U-phase armature coil of the motor 8, the connection point between the upper arm switching element 18B and the lower arm switching element 18E of the V-phase half-bridge circuit 19V (midpoint of the upper and lower arms: V-phase voltage Vv) is connected to the V-phase armature coil of the motor 8, and the connection point between the upper arm switching element 18C and the lower arm switching element 18F of the W-phase half-bridge circuit 19W (midpoint of the upper and lower arms: W-phase voltage Vw) is connected to the W-phase armature coil of the motor 8.

[0038] (2) Configuration of the control device 21 Next, the control device 21 is composed of a microcomputer (semiconductor) having a processor, and in this embodiment, receives a rotation speed command value from the vehicle's ECU and a motor current (phase current) from the motor 8, and based on these, controls the ON / OFF state (switching) of each of the switching elements 18A to 18F of the inverter circuit 28. Specifically, it controls the gate voltage applied to the gate of each of the switching elements 18A to 18F.

[0039] The control device 21 of the embodiment has a dq-axis current command calculation unit 33 as a current command calculation unit, a voltage pattern group generation unit 34, a dq-axis current prediction calculation unit 35 as a current prediction calculation unit, an optimal voltage pattern selection unit 36, a gate driver 37, and current sensors 26A and 26B each consisting of a current transformer for measuring a U-phase current iu and a W-phase current iw, which are motor currents (phase currents) of the U and W phases flowing through the motor 8. In addition, an electrical angle θrm is obtained from the motor 8.

[0040] In the embodiment, U-phase current iu is measured by current sensor 26A, W-phase current iw is measured by current sensor 26B, and V-phase current iv is calculated from these, but all phase currents iu, iv, and iw may be measured by current sensors. Furthermore, the method of detecting the motor current of each phase is not particularly limited, as it can be measured by current sensors 26A and 26B as in the embodiment, or by detecting the current value of lower arm power supply line 15 using a shunt resistor and estimating the current from that current value and the operating state of motor 8.

[0041] (3) Gate Driver 37 First, the gate driver 37 generates gate voltages for the switching elements 18A and 18D of the U-phase inverter 19U, the gate voltages for the switching elements 18B and 18E of the V-phase inverter 19V, and the gate voltages for the switching elements 18C and 18F of the W-phase inverter 19W based on the optimal voltage vector pattern selected by the optimal voltage pattern selection unit 36 ​​as described below.

[0042] Each of the switching elements 18A-18F of the inverter circuit 28 is driven to turn on / off based on the gate voltage output from the gate driver 37. That is, when the gate voltage is in the ON state (a predetermined voltage value), the switching element operates ON, and when the gate voltage is in the OFF state (zero), the switching element operates OFF. If the switching elements 18A-18F are the IGBTs described above, the gate driver 37 is a circuit for applying the gate voltage to the IGBTs based on a PWM signal, and is composed of a photocoupler, a logic IC, a transistor, etc.

[0043] The voltage at the connection point between the upper arm switching element 18A and the lower arm switching element 18D of the U-phase half-bridge circuit 19U is applied (output) to the U-phase armature coil of the motor 8 as a U-phase voltage Vu (phase voltage), the voltage at the connection point between the upper arm switching element 18B and the lower arm switching element 18E of the V-phase half-bridge circuit 19V is applied (output) to the V-phase armature coil of the motor 8 as a V-phase voltage Vv (phase voltage), and the voltage at the connection point between the upper arm switching element 18C and the lower arm switching element 18F of the W-phase half-bridge circuit 19W is applied (output) to the W-phase armature coil of the motor 8 as a W-phase voltage Vw (phase voltage).

[0044] (4) dq axis current command calculation section 33 The dq-axis current command calculation unit 33 of the embodiment calculates the d-axis current command value i d ref and the q-axis current command value i q ref In this case, the q-axis current command value i q ref is calculated from the PI calculation and the relational expression between the q-axis current and torque. In the notation of the formula to be described later, the d-axis current command value i d ref and the q-axis current command value i q ref The subscript and superscript are written in the same position vertically, but are the same as the notation above (the same applies below).

[0045] Here, the high and low states of the U-phase voltage Vu, V-phase voltage Vv, and W-phase voltage Vw applied to the armature coils of each phase of the motor 8 can be summarized and expressed as the states of eight voltage vectors (output fundamental vectors) V0 to V7 as shown in Fig. 2. Of these, V1, V3, and V5 are odd-numbered voltage vectors, V2, V4, and V6 are even-numbered voltage vectors, and V0 and V7 are zero-voltage vectors. When each voltage vector is shown in the voltage space of the αβ axes, it becomes as shown in Fig. 3.

[0046] (5) Voltage pattern group generator 34 Next, the voltage pattern group generator 34 of the embodiment references the voltage vector pattern in the previous control cycle and generates a plurality of voltage vector patterns in which the number of fluctuations of the common mode voltage Vc of the motor 8 in the measurement bandwidth in the noise measurement described above is equal to or less than a predetermined specified number N regardless of the measurement timing, and the number of switching times in one control cycle is equal to or less than a predetermined limit number M. In the embodiment, the switching frequency is assumed to be sufficiently greater than the measurement bandwidth.

[0047] That is, the voltage pattern group generating unit 34 of the embodiment generates voltage vector pattern candidates by setting the following constraints, taking into consideration the measurement bandwidth and the number of switching times (switching frequency) of each phase of the inverter circuit 28. Constraint 1: No matter when the measurement is performed, the number of fluctuations in the common mode voltage Vc must be less than or equal to the specified number N. This specified number N is an integer greater than or equal to 1, but in the following explanation, N=1. Constraint 2: In the voltage vector pattern output in one control cycle, the number of switching operations (switching frequency) of each phase of the inverter circuit 28 must be equal to or less than the limit number M. This limit number M is a value that does not exceed the rated switching frequency of the switching elements (semiconductors) that make up the inverter circuit 28, and in the following explanation, M=2.

[0048] (5-1) Operation of the voltage pattern group generator 34 The operation procedure of the voltage pattern group generator 34 of this embodiment will be specifically described below with reference to Figures 4 and 5. In this embodiment, the voltage vector resolution for one control cycle is set to 5 (five intervals), and the voltage vector pattern for the previous control cycle in this case is shown on the left side of Figure 4, while an example of a voltage vector pattern determined as a candidate for the current control cycle is shown on the right side. Note that steps 1 to 6 in Figure 4 correspond to steps 1 to 6 in Figure 5, with the voltage vector pattern for the previous control cycle being determined in step 1, and the voltage vector pattern for the current control cycle being determined in step 6. Also, V1 to V6 in each figure are the voltage vectors (output fundamental vectors other than the zero voltage vector) described above.

[0049] In step 1, the voltage pattern group generation unit 34 first refers to the voltage vector patterns (V4, V4, V2, V3, V5) in the previous control cycle. Here, when even voltage vectors V2, V4, V6 are output after even voltage vectors V2, V4, V6, the upper and lower arm switching elements 18A-18F of different phases are simultaneously switched with opposite polarities to each other, so the common mode voltage Vc does not fluctuate. Similarly, when odd voltage vectors V1, V3, V5 are output after odd voltage vectors V1, V3, V5, the upper and lower arm switching elements 18A-18F of different phases are simultaneously switched with opposite polarities to each other, so the common mode voltage Vc does not fluctuate.

[0050] On the other hand, if an odd-numbered voltage vector is output after an even-numbered voltage vector, or if an even-numbered voltage vector is output after an odd-numbered voltage vector, the common-mode voltage Vc will fluctuate. In the voltage vector pattern in the previous control cycle, an odd-numbered voltage vector V3 was output after an even-numbered voltage vector V2, so the common-mode voltage Vc fluctuated once, satisfying the aforementioned specified number of times N (1: constraint 1). Therefore, a voltage vector that can be output after the last odd-numbered voltage vector V5 is searched for that does not cause fluctuations in the common-mode voltage Vc, and in step 1 of this embodiment, for example, the odd-numbered voltage vector V5 is selected.

[0051] Next, in step 2, a search is made for a voltage vector to be output after the final voltage vector V5 of the voltage vector pattern (V4, V2, V3, V5, V5) determined in step 1. In this case, the common-mode voltage Vc has still fluctuated once, so a voltage vector that does not fluctuate the common-mode voltage Vc is searched for, and in step 2 of this embodiment, for example, an odd-numbered voltage vector V1 is selected.

[0052] Next, in step 3, a search is made for the voltage vector to be output after the final voltage vector V1 of the voltage vector pattern (V2, V3, V5, V5, V1) determined in step 2. In this case, since there is no fluctuation in the common-mode voltage Vc, all voltage vectors become candidates, and in step 3 of this embodiment, for example, the odd-numbered voltage vector V3 is selected.

[0053] Next, in step 4, a search is made for a voltage vector to be output after the final voltage vector V3 of the voltage vector pattern (V3, V5, V5, V1, V3) determined in step 3. In this case as well, since there is no fluctuation in the common-mode voltage Vc, all voltage vectors become candidates, and in step 4 of the embodiment, for example, the odd-numbered voltage vector V3 is selected.

[0054] In step 1 of Figure 5, although odd-numbered voltage vector V5 is used, other odd-numbered voltage vectors V1 and V3 may also be used. Similarly, in step 2, odd-numbered voltage vector V1 is used, but other odd-numbered voltage vectors V3 and V5 may also be used. Furthermore, in step 3, odd-numbered voltage vector V3 is used, but other voltage vectors V1, V2, V4 to V6 may also be used. Similarly, in step 4, odd-numbered voltage vector V3 is used, but other voltage vectors V1, V2, V4 to V6 may also be used, and options that result in the number of fluctuations of the common-mode voltage Vc being N(1) or less are output sequentially.

[0055] Next, in step 5, a search is made for a voltage vector to be output after the final voltage vector V3 of the voltage vector pattern (V5, V5, V1, V3, V3) determined in step 4. In this case, since there is no fluctuation in the common-mode voltage Vc, all voltage vectors are candidates, but constraint 2 is also taken into consideration. In this case, a search is made for a voltage vector (a voltage vector that satisfies constraint 2 on the number of switching times) in which the number of switching times (switching frequency) of each phase is equal to or less than the aforementioned limit M(2). In this embodiment, in step 6, even-numbered voltage vector V4 is determined as the voltage vector that satisfies constraint 1 on the fluctuation in the common-mode voltage Vc and constraint 2 on the number of switching times. This becomes the voltage vector pattern (V5, V1, V3, V3, V4) for the current control cycle shown in Figure 4, and is saved as a candidate for the voltage vector pattern to be output.

[0056] As described above, the voltage vector pattern for the current control cycle is searched for by referring to the voltage vector pattern for the previous control cycle. The number of combinations of voltage vector patterns resulting from the search varies depending on the voltage vector pattern for the previous control cycle, but in this embodiment, there are a maximum of approximately 400 combinations (set of voltage vector patterns). Furthermore, the search for constraint 1 regarding fluctuations in the common-mode voltage Vc is performed at every step in FIG. 5. By considering fluctuations in the common-mode voltage Vc at every step in this way, a voltage vector pattern is established that keeps the number of fluctuations in the common-mode voltage Vc at N(1) or less, regardless of where the measurement is performed. This search for voltage vector patterns by the voltage pattern group generator 34 suppresses the peak value of common-mode noise at the input voltage vector pattern stage.

[0057] (6) dq-axis current prediction calculation unit 34 Next, the dq-axis current prediction calculation unit 34 of the embodiment calculates the d-axis current i d and q-axis current i q The d-axis current i d and q-axis current i qThe prediction formula is derived by discretizing (zero-order hold) the state equation of the IPMSM shown in formula (I) as shown in formulas (II) and (III).

[0058]

number

[0059] In addition, in the formula (I), i d is the d-axis current, i q is the q-axis current, v d is the d-axis voltage, v q is the q-axis voltage, L d is the d-axis inductance, L q is the q-axis inductance, R a is the winding resistance, k E is the induced voltage constant, ω re is the electrical angular velocity.

[0060]

number

[0061] In Equation (II) and Equation (III), x(t) is the state quantity (dq-axis current) at time t, x[k] is the state quantity (discrete expression) at the k-th sample point, u(t) is the input at time t (the control input is the dq-axis voltage, the disturbance input is the induced voltage, and the input is the sum of the control input and the disturbance input), u[k] is the input (discrete expression) at the k-th sample point, A c is the free motion parameter of the state quantity in the continuous domain, b c is the parameter that affects the state of the input in the continuous domain, A d is parameter A c Representation in the discrete domain of b d is the parameter b c Representation in the discrete domain, T p is the prediction cycle for model prediction.

[0062] In equation (III), x[k] is the k-th state quantity, which is the initial value of the dq-axis current output by the dq-axis current command calculation unit 33. The second state quantity x[k+1] (dq-axis current) is predicted from this initial value. The dq-axis current prediction calculation unit 34 solves equation (III) for each interval of the voltage vector pattern described above, and calculates an instantaneous predicted value for each interval (five intervals in this embodiment) and an average predicted value for the control period.

[0063] When the control period is divided into five sections as described above, the prediction formulas are as shown in the following formulas (IV) to (VII). Note that the A matrix and the b matrix are the electrical angular velocity ω re However, since there is little fluctuation per control cycle, it is set to an approximately constant value.

[0064]

number

[0065]

number

[0066]

number

[0067] In the formula (IV), x[k+1] to x[k+5] are predicted values ​​corresponding to the first to fifth sections of the voltage vector pattern. dqn αβ is the rotation matrix at the k+n sample point. dqn Although αβ and αβ are written in the same position above and below, they are the same. Also, in formula (VII), vαβ n is the αβ voltage input at the k+n sample point.

[0068] The voltage vector of the control input is defined on the αβ coordinate system. Therefore, at each sampling point, a dq axis transformation is performed taking into account the phase lead for each prediction period (the underlined part of formula (VI)).

[0069] (7) Optimal voltage pattern selection unit 36 Next, the optimum voltage pattern selection unit 36 ​​of the embodiment selects the current command value (d-axis current command value i) calculated by the dq-axis current command calculation unit 33 from the set (maximum 400 patterns) of voltage vector patterns that satisfy the constraint conditions (constraint conditions 1 and 2) generated by the voltage pattern group generation unit 34. d ref , q-axis current command value i q ref ) and the current value prediction value (d-axis current i d , q-axis current i q ) is selected to minimize the error.

[0070] (7-1) Operation of the optimal voltage pattern selection unit 36 Specifically, the optimum voltage pattern selection unit 36 ​​of the embodiment calculates the cost of each voltage vector pattern using the following formulas (VIII) to (XI). As a result of the cost calculation, the voltage vector pattern with the smallest cost C (evaluation index) is output as the optimum voltage vector pattern.

[0071]

number

[0072] In equation (VIII), C is the cost of the voltage vector pattern, W max is the weighting coefficient for the ripple caused by vector switching (weighting coefficient for the maximum instantaneous error cost), W ave is the weighting coefficient for the responsiveness of the dq-axis current (weighting coefficient for the average error cost), W Vc is a weighting coefficient (weighting coefficient for the number of common-mode voltage fluctuations) that determines the control priority of the common-mode voltage fluctuation and current error (error between the current command value and the current prediction value). Also, C Vc is the number of common-mode voltage fluctuations in the voltage vector pattern, E max is the maximum instantaneous error cost, E ave is the average error cost.

[0073]

number

[0074] In addition, in the formula (X), W d is the d-axis weighting coefficient, W q is the q-axis weighting coefficient, max() is a function that outputs the maximum value of the argument in (), abs() is a function that outputs the absolute value of the argument in (), x ref [k] is the state command value (i d ref [k] is the d-axis current command value, i q ref [k] is the q-axis current command value.

[0075] The first and second terms on the right side of Equation (VIII) are the costs due to current error (the error between the current command value and the predicted current value), and the third term is the cost due to common-mode voltage fluctuations. The optimal voltage pattern selector 36 of the present embodiment basically selects the voltage vector pattern with the smallest current error cost from among the voltage vector patterns without common-mode voltage fluctuations as the optimal voltage vector pattern. That is, the number of common-mode voltage fluctuations is given higher priority than the current error (the error between the current command value and the predicted current value). Furthermore, if the current error is too large in a voltage vector pattern without common-mode voltage fluctuations, the voltage vector pattern with the smallest current error cost is selected from among the voltage vector patterns including common-mode voltage fluctuations as the optimal voltage vector pattern.

[0076] Each weighting factor W max , W ave , W VcThe ratio of these determines up to what current error ([A]) priority will be given to a voltage vector pattern with no common-mode voltage fluctuations. This makes it possible to select a voltage vector pattern with good current response, i.e., with little current error, while suppressing common-mode voltage fluctuations. Note that here, only the number of times the common-mode voltage fluctuates in each control cycle is optimized, which means that the noise average value is suppressed. This is because an evaluation is made at each control cycle as to whether or not to fluctuate the common-mode voltage.

[0077] (7-2) Example of optimal voltage vector pattern selection Next, an example of selecting an optimal voltage vector pattern using Equation (VIII) will be described. max = 1.0, weighting factor W ave = 1.0, weighting factor W Vc = 2.5, E max =1.0, E ave =1.0, C Vc Voltage vector pattern 1 with E = 0 and max =0.0, E ave =0.0, C Vc Consider voltage vector pattern 2 with common mode voltage fluctuations. Voltage vector pattern 1 has no common mode voltage fluctuations but has a slight current error, while voltage vector pattern 2 shows an ideal current response but has common mode voltage fluctuations.

[0078] In the above case, the cost C1 of the voltage vector pattern 1 and the cost C2 of the voltage vector pattern 2 derived from the formula (VIII) are as follows: C1=1.0×1.0+1.0×1.0+2.5×0.0=2.0 C2=1.0×0.0+1.0×0.0+2.5×1.0=2.5 In the case of the above weighting coefficient ratio, although there is a current error, voltage vector pattern 1 without common-mode voltage fluctuations is selected as the optimal voltage vector pattern.

[0079] Also, E max =2.0, E ave =2.0, CVc = 0 voltage vector pattern 3 and E max =0.0, E ave =1.0, C Vc Consider voltage vector pattern 4 where V = 1.0. Both voltage vector pattern 3 and voltage vector pattern 4 are cases where a current error exists.

[0080] In the above case, the cost C3 of the voltage vector pattern 3 and the cost C4 of the voltage vector pattern 4 derived from the formula (VIII) are as follows: C3=1.0×2.0+1.0×2.0+2.5×0.0=4.0 C4=1.0×0.0+1.0×1.0+2.5×1.0=3.5 Voltage vector pattern C4 has good current response even when common-mode voltage fluctuations are taken into account, and voltage vector pattern C3 has no common-mode voltage fluctuations, but the current error is too large, so when comparing the costs of C4 and C3, voltage vector pattern 4 is selected as the optimal voltage vector pattern.

[0081] As a result of the evaluation using the above-mentioned formula (VIII), the optimum voltage pattern selector 36 of the embodiment basically prioritizes a voltage vector pattern without common-mode voltage fluctuations in terms of cost. Even when there is no common-mode voltage fluctuation, if the current error is large, a voltage vector pattern with a small current error and common-mode voltage fluctuations is selected as the optimum voltage vector pattern.

[0082] The optimization calculation of Equation (VIII) is performed in each control cycle, and the current error is minimized while suppressing the common-mode voltage fluctuation through sequential optimization. Therefore, the current error is minimized while suppressing the noise average value.

[0083] Figures 6 to 9 show the results obtained with the present invention. Figure 6 shows the waveforms of the U-phase current iu and common-mode voltage Vc at a low modulation factor, Figure 7 shows the waveforms of the U-phase current iu and common-mode voltage Vc at a medium modulation factor, and Figure 8 shows the waveforms of the U-phase current iu and common-mode voltage Vc at a high modulation factor. At a low modulation factor, the common-mode voltage Vc does not fluctuate, but as the modulation factor increases from the medium modulation factor to the high modulation factor, fluctuations in the common-mode voltage Vc occur. However, it can be seen that the current response is improved while the fluctuations in the common-mode voltage Vc are suppressed in all operating ranges.

[0084] Also, Fig. 9 shows an example of common mode noise (conductive noise) generated by the results of the present invention for comparison with the conventional example in Fig. 13. As is clear from Fig. 9, no matter what timing the measurement is made, the number of times noise occurs within the window separated by the measurement window is four (two times in each control cycle), and the noise peak value is suppressed.

[0085] As described above, according to the power conversion device 1 of the present invention, the control device 21 generates a voltage vector pattern in which the number of fluctuations in the common-mode voltage Vc within a predetermined measurement bandwidth is equal to or less than a predetermined number N (N is an integer equal to or greater than 1), regardless of the measurement timing, and controls the switching of the upper and lower arm switching elements 18A-18F. This makes it possible to suppress and minimize both the average value and peak value of common-mode noise generated by fluctuations in the common-mode voltage Vc. It also makes it possible to suppress the occurrence of electromagnetic interference in peripheral devices caused by concentrated fluctuations in the common-mode voltage Vc and the concentrated generation of common-mode noise.

[0086] Furthermore, in the embodiment, the control device 21 simultaneously switches the upper and lower arm switching elements 18A to 18F of different phases with opposite polarities to each other, thereby keeping the number of fluctuations of the common mode voltage Vc below the specified number N. Therefore, particularly when the switching frequency is higher than the measurement bandwidth, the number of fluctuations of the common mode voltage Vc can be smoothly controlled to be below the specified number N.

[0087] Furthermore, in the embodiment, the control device 21 includes a voltage pattern group generation unit 34 that references the voltage vector pattern in the previous control cycle and generates a plurality of voltage vector patterns that keep the number of fluctuations of the common-mode voltage Vc in the measurement bandwidth below a specified number N regardless of the measurement timing, so that the peak value of the common-mode noise can be effectively controlled to below the specified number N.

[0088] In this case, when the switching frequency is greater than the measurement bandwidth, the voltage pattern group generation unit 34 of the embodiment generates voltage vector patterns that simultaneously switch the upper and lower arm switching elements 18A to 18F of different phases with opposite polarities by outputting even voltage vectors V2, V4, V6 followed by even voltage vectors V2, V4, V6, or odd voltage vectors V1, V3, V5 followed by odd voltage vectors V1, V3, V5 in one control period, and the number of fluctuations of the common mode voltage Vc is set to a specified number N or less.Furthermore, a plurality of voltage vector patterns are generated by adding a constraint that the number of switching times of each phase in one control period is set to a predetermined limit number M or less.Therefore, it is possible to prevent the switching frequency from exceeding the rated switching frequency of the switching elements (semiconductors) that make up the inverter circuit 28.

[0089] Furthermore, in the embodiment, the control device 21 determines the current command value (d-axis current command value i d ref , q-axis current command value i q ref ) of each voltage vector pattern generated by the voltage pattern group generation unit 34. d , q-axis current i q) and an optimum voltage pattern selection unit 36 ​​that selects, from among the voltage vector patterns generated by the voltage pattern group generation unit 34, a voltage vector pattern that minimizes the error between the current command value and the current prediction value, thereby making it possible to suppress the average value of common-mode noise while taking current response into consideration.In addition, since current distortion can be suppressed over the entire operating range, noise is less likely to be excited, which is extremely effective when driving a motor 8 as a load as in this embodiment.

[0090] In this case, in the embodiment, the optimum voltage pattern selection unit 36 ​​selects the optimum voltage vector pattern based on the number of fluctuations of the common-mode voltage Vc and the error (current error) between the current command value and the current prediction value, so that it is possible to smoothly achieve both suppression of the common-mode noise Vc and improvement of the current response.

[0091] Furthermore, in this embodiment, the optimal voltage pattern selection unit 36 ​​selects the optimal voltage vector pattern by giving a higher priority to the number of fluctuations of the common-mode voltage Vc than to the error (current error) between the current command value and the current prediction value. This makes it possible to select an optimal voltage vector pattern with good current response while reliably suppressing fluctuations in the common-mode voltage Vc.

[0092] It should be noted that the numerical values ​​shown in the embodiments are not limited to those. Also, although the embodiments have been described using an example of driving a motor (load) of an electric compressor, the present invention is not limited to this and is also effective when driving a motor other than the motor of an electric compressor. Furthermore, in the inventions other than claim 9, the present invention can be applied to various power conversion devices that convert DC voltage into AC voltage using an inverter and apply it to a load. [Explanation of symbols]

[0093] 1 Power conversion device 8 motors 18A~18F Upper and lower arm switching elements 19U U-phase inverter 19V V-phase inverter 19W W-phase inverter 21 Control device 28 Inverter circuit 33 dq axis current command calculation section (current command calculation section) 34 Voltage pattern group generator 35 dq axis current prediction calculation unit (current prediction calculation unit) 36 Optimal voltage pattern selection section 37 Gate Driver

Claims

1. 1. A power conversion device for converting DC voltage into AC voltage, an inverter circuit that applies a phase voltage at a connection point of the upper and lower arm switching elements of each phase to a load; a control device for controlling switching of the upper and lower arm switching elements, The control device controls the switching of the upper and lower arm switching elements so that the number of fluctuations of the common mode voltage in a predetermined measurement bandwidth is equal to or less than a predetermined specified number N (N is an integer equal to or greater than 1), regardless of measurement timing.

2. 2. The power conversion device according to claim 1, wherein the control device controls the number of fluctuations of the common mode voltage to be equal to or less than the specified number N by simultaneously switching the upper and lower arm switching elements of different phases with polarities opposite to each other.

3. 2. The power conversion device according to claim 1, wherein the control device includes a voltage pattern group generation unit that references a voltage vector pattern in a previous control cycle and generates a plurality of voltage vector patterns in which the number of fluctuations of the common-mode voltage in the measurement bandwidth is equal to or less than the specified number N regardless of measurement timing.

4. 4. The power conversion device according to claim 3, wherein, when a switching frequency is greater than the measurement bandwidth, the voltage pattern group generation unit generates voltage vector patterns that simultaneously switch the upper and lower arm switching elements of different phases with opposite polarities to each other by outputting an even voltage vector after an even voltage vector, or an odd voltage vector after an odd voltage vector, in one control period, and sets the number of fluctuations of the common mode voltage to be equal to or less than the specified number N.

5. 5. The power conversion device according to claim 3, wherein the voltage pattern group generation unit generates the plurality of voltage vector patterns by adding a constraint that the number of times each phase is switched in one control period is equal to or less than a predetermined limit number of times.

6. The control device a current command calculation unit that calculates a current command value; a current prediction calculation unit that calculates a current prediction value of each voltage vector pattern generated by the voltage pattern group generation unit; 5. The power conversion device according to claim 3, further comprising an optimal voltage pattern selection unit that selects, from the voltage vector patterns generated by the voltage pattern group generation unit, a voltage vector pattern that minimizes an error between the current command value and the current prediction value.

7. 7. The power conversion device according to claim 6, wherein the inverter circuit applies a phase voltage at a connection point of the upper and lower arm switching elements of each phase to the motor to drive it.

8. 7. The power conversion device according to claim 6, wherein the optimal voltage pattern selection unit selects an optimal voltage vector pattern based on the number of fluctuations of the common-mode voltage and an error between the current command value and the current prediction value.

9. 9. The power conversion device according to claim 8, wherein the optimal voltage pattern selection unit selects the optimal voltage vector pattern by assigning a higher priority to the number of fluctuations of the common mode voltage than to an error between the current command value and the current prediction value.

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