Current sampling zero offset correction method and device

Abstract

The invention provides a current sampling zero offset correction method and device. The current sampling zero-bias correction method comprises the following steps: determining a correction trigger opportunity, wherein the correction trigger opportunity is a moment when an output voltage vector of a power converter is in a zero vector state and a theoretical value of current flowing through a current sampling resistor is zero; sampling a current sampling channel through an analog-to-digital converter at a correction triggering time, and obtaining original sampling data under a zero current condition; processing the original sampling data to obtain a current zero current bias value and updating the stored current bias data variable; a corrected current value is determined based on the updated current bias data variable. By setting the specific correction triggering time and correction mechanism, the current sampling zero bias can be dynamically tracked and corrected online, automatically and in real time in the whole operation process of the driver, adverse effects caused by static deviation and dynamic temperature excursion are overcome, and the control precision and robustness of the system under all working conditions are improved.

Description

Technical Field

[0001] This application relates to the field of current bias correction technology, and in particular to a current sampling zero bias correction method and device, which is especially applicable to drive control systems of permanent magnet synchronous motors, brushless DC motors and other motors that use multi-resistor sampling schemes. Background Technology

[0002] In motor drivers, high-precision, real-time sampling of motor phase currents is fundamental to achieving high-performance vector control (such as field-oriented control). One common current sampling scheme is the "three-resistance sampling method," the basic principle of which is as follows: Figure 1 As shown in the diagram, in this structure, the sources of the lower arm switches (S2, S4, S6) of the three-phase inverter bridge are connected in series with sampling resistors (R1, R2, R3) and grounded. By measuring the voltage across these resistors and performing signal conditioning (including amplification, filtering, and level shifting) through the corresponding operational amplifiers (A1, A2, A3), the current flowing through each phase can be deduced. The analog-to-digital converter (ADC) module of the microprocessor (MCU) samples the conditioned voltage signal and participates in the calculation of the control algorithm.

[0003] To obtain an accurate absolute current value, the "zero current bias" must be subtracted from the raw value read by the ADC. This bias refers to the ADC value corresponding to the voltage signal output by the sampling circuit when the motor current is theoretically zero. Ideally, when the current is zero, the voltage across the sampling resistor is zero, the op-amp output should be the reference midpoint voltage, and the ADC reading should correspond to a fixed intermediate code value. However, in actual hardware circuits, due to the following two inherent defects, the zero current bias is not a constant value:

[0004] First, there are inherent static manufacturing tolerances in the components. Every electronic component that makes up the sampling circuit, including the resistance deviation of the sampling resistor, the input offset voltage of the operational amplifier, the parasitic parameters of the PCB layout, and the offset of the ADC channel itself, has manufacturing tolerances. This causes the zero-bias ADC code values ​​exhibited by different drivers, and even different phase sampling channels of the same driver, to differ even under the same zero-current conditions; that is, there is an "initial bias".

[0005] Secondly, and more critically, is the dynamic temperature drift characteristic of component parameters. The key parameters of components such as resistors and operational amplifiers drift with changes in the driver's power consumption and ambient temperature during operation. For example, the input offset voltage of an operational amplifier changes with temperature, and the resistance of the sampling resistor also has a temperature coefficient. This leads to a serious problem: during operation, the driver's actual zero-current bias point changes slowly and in real time with operating conditions and temperature, i.e., there is "dynamic bias drift."

[0006] Currently, many drivers employ a simple one-time calibration strategy: after system power-on initialization and before motor start-up, when the motor current is confirmed to be zero, the control MCU performs one or more ADC samplings on each current sampling channel, and stores the obtained average value as a fixed "zero current bias value" for subsequent correction of all current values.

[0007] However, this method has significant limitations: it can only compensate for some of the aforementioned static initial deviations, but it is completely unable to cope with the dynamic bias drift caused by temperature rise during system operation. As the driver continues to operate, the temperature gradually increases, and the actual zero bias point deviates from the fixed value stored at startup. If this outdated data is used for correction, it will introduce continuous current sampling errors. This error will be directly injected into the current loop, leading to torque fluctuations, reduced efficiency, increased noise, and even system oscillations, severely restricting the performance and reliability of the motor control system in wide-temperature-range, high-precision application scenarios. Summary of the Invention

[0008] The purpose of this application is to provide a current sampling zero bias correction method and device to solve the technical problem that dynamic bias drift caused by temperature rise during system operation leads to deviation in current sampling and further affects the motor control effect.

[0009] To achieve the above and other related objectives, a first aspect of this application provides a current sampling zero-bias correction method. The current sampling zero-bias correction method includes: determining a correction trigger timing, wherein the correction trigger timing is the moment when the output voltage vector of the power converter is in a zero-vector state and the theoretical value of the current flowing through the current sampling resistor is zero;

[0010] At the specified correction triggering time, the current sampling channel is sampled by an analog-to-digital converter to obtain the original sampling data under zero current conditions;

[0011] The original sampled data is processed to obtain the current zero current bias value;

[0012] Update the stored current bias data variable using the current zero current bias value; and

[0013] The corrected current value is determined based on the updated current bias data variables.

[0014] In some embodiments of the first aspect of this application, when the power converter employs seven-segment space vector pulse width modulation, the correction triggering timing is the moment when the count value of the PWM carrier counter is equal to a preset period value or equal to 0.

[0015] In some embodiments of the first aspect of this application, when the power converter employs five-segment space vector pulse width modulation, the correction triggering timing is when the count value of the PWM carrier counter is equal to the preset period value.

[0016] In some embodiments of the first aspect of this application, before the correction triggering timing, the current sampling channel is sampled by the analog-to-digital converter, the method further includes:

[0017] Determine the current output voltage vector state;

[0018] Based on the output voltage vector state, determine the valid sampling phase in the current current sampling channel.

[0019] In some embodiments of the first aspect of this application, the effective sampling phase is the phase in which the lower bridge arm is turned on and current flows through the current sampling resistor under the current voltage vector state.

[0020] In some embodiments of the first aspect of this application, the three-phase zero bias correction for the current cycle is completed when the current bias data variables of phase U, phase V and phase W are updated at least once within a preset time window.

[0021] In some embodiments of the first aspect of this application, determining a corrected current value based on the updated current bias data variable includes: subtracting the updated current bias data variable from the original current value read from the analog-to-digital converter during current measurement to obtain the corrected current value.

[0022] In some embodiments of the first aspect of this application, the current sampling channel is sampled multiple times consecutively at a single correction trigger timing.

[0023] In some embodiments of the first aspect of this application, processing the raw sampled data to obtain the current zero-current bias value includes:

[0024] For the original sampled data obtained from multiple consecutive samplings, an arithmetic mean calculation or a median filtering calculation is performed to obtain the current zero current bias value.

[0025] To achieve the above and other related objectives, a second aspect of this application provides a current sampling zero-bias correction device. The current sampling zero-bias correction device includes: a microcontroller;

[0026] The current sampling circuit is configured to sense the current in the three-phase inverter circuit and convert it into a voltage signal;

[0027] An analog-to-digital converter, connected to the current sampling circuit, is configured to convert the voltage signal into a digital sample value;

[0028] The memory is configured to store at least one current bias data variable;

[0029] The microcontroller is configured to perform the current sampling zero-bias correction method as described in any of the first aspects of this application.

[0030] As described above, the current sampling zero-bias correction method and apparatus of this application have the following beneficial effects:

[0031] First, this application solves the technical problem of dynamic bias drift caused by temperature rise during system operation by periodically triggering the update of current bias data during system operation, so that the current sampling reference can "follow" the actual operating point of the circuit in real time. This ensures that the absolute accuracy of current sampling can be maintained at a high level from cold start to thermal stability under various load and temperature conditions.

[0032] Second, by continuously eliminating the measurement error introduced by zero bias drift, this application provides a more "real" feedback signal for the current loop, avoiding the risk of controller misjudgment (such as false overcurrent) or control instability caused by long-term accumulated sampling deviation, thus improving the robustness of the system in long-term operation.

[0033] Third, this application explicitly proposes an optimized scheme for correction using the inherent zero vector moment in seven-segment SVPWM, and innovatively proposes a solution for five-segment SVPWM and other systems without long zero vector sequences. Whether using the "phase-by-phase cumulative update method" that combines carrier specific moments with state recognition, or the software-driven "forced zero vector insertion" method, both ensure safe and effective correction under different PWM modulation strategies. This makes the technology highly versatile and applicable to various motor drive platforms.

[0034] Fourth, the core of this application is implemented using an original algorithm, eliminating the need for additional dedicated calibration hardware circuits (such as high-precision reference sources, switching devices, etc.). It primarily utilizes existing resources in the control system, such as ADCs and PWM timers. This method achieves an order-of-magnitude improvement in sampling accuracy and a significant enhancement in system reliability at the cost of minimal CPU computational overhead, offering extremely high cost-effectiveness and facilitating upgrades and mass applications on existing products. Attached Figure Description

[0035] Figure 1 The diagram shows the basic path of a current sampling scheme based on the three-resistor sampling method.

[0036] Figure 2 The diagram shown is a flowchart of the current sampling zero bias correction method described in the embodiments of this application.

[0037] Figure 3aThe diagram shows the three-phase PWM waveform and voltage force application time of the seven-segment SVPWM described in this application embodiment.

[0038] Figure 3b The diagram shows the circuit schematic for the correction triggering timing of the seven-segment SVPWM as described in the embodiments of this application.

[0039] Figure 4a The diagram shows the three-phase PWM waveform and voltage force application time of the five-segment SVPWM described in this application embodiment.

[0040] Figure 4b The diagram shows the circuit schematic for the correction triggering timing of the five-segment SVPWM as described in the embodiments of this application.

[0041] Figure 5 The diagram shown is a basic schematic of the current sampling scheme of the two-resistor sampling method described in the embodiments of this application.

[0042] Figure 6 The diagram shows the circuit schematic for the correction triggering timing of the seven-segment SVPWM based on the two-resistor sampling method described in the embodiments of this application.

[0043] Figure 7a The diagram shows the circuit schematic for the correction triggering timing of the five-segment SVPWM based on the two-resistor sampling method described in the embodiment of this application.

[0044] Figure 7b The diagram shows the circuit schematic for the correction triggering timing of a five-segment SVPWM based on a two-resistor sampling method according to another embodiment of this application.

[0045] Figure 7c The diagram shows the circuit schematic of the correction triggering timing of the five-segment SVPWM based on the two-resistor sampling method according to another embodiment of this application.

[0046] Figure 8 The diagram shown is a structural schematic of the current sampling zero bias correction device described in an embodiment of this application.

[0047] Label Explanation

[0048] 1 microcontroller 2 Current sampling circuit 3 Three-phase inverter circuit 4 Analog-to-digital converter 5 memory 6 PWM generation unit S21~S25 step Detailed Implementation

[0049] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0050] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] This application provides a current sampling zero bias correction method and apparatus. By periodically triggering the update of current bias data during system operation, the current sampling reference can "follow" the actual operating point of the circuit in real time, ensuring that the absolute accuracy of current sampling can be maintained at a high level under various load and temperature environments from cold start to thermal stability. This solves the technical problem of dynamic bias drift caused by temperature rise during system operation.

[0052] The principles and implementation methods of the current sampling zero bias correction method and device described in this application will be explained in detail below with reference to the accompanying drawings, so that those skilled in the art can understand the current sampling zero bias correction method and device of this embodiment without creative effort.

[0053] To facilitate understanding of the embodiments of this application, the appendix will be consulted first. Figure 2 Detailed explanation, such as Figure 2 As shown, the current sampling zero bias correction method of this application embodiment includes steps S21 to S25.

[0054] Step S21: Determine the correction trigger timing. The correction trigger timing is when the output voltage vector of the power converter is in a zero vector state and the theoretical value of the current flowing through the current sampling resistor is zero.

[0055] Step S22: At the calibration triggering time, the current sampling channel is sampled by an analog-to-digital converter to obtain the original sampling data under zero current conditions.

[0056] Specifically, the current sampling channel is sampled multiple times consecutively at a single correction trigger point.

[0057] In this embodiment, when the power converter uses seven-segment space vector pulse width modulation, the correction triggering time is when the count value of the PWM carrier counter is equal to the preset period value or equal to 0.

[0058] like Figure 3a The diagram shows the three-phase PWM waveforms and voltage vector application timing of a seven-segment SVPWM. This diagram clearly illustrates the generation of the three-phase PWM waveforms and the timing of voltage vector application within sector I (0°≤θ<60°) of a complete seven-segment SVPWM.

[0059] The seven-segment SVPWM waveform in the figure consists of two effective voltage vectors and two zero voltage vectors, with each sector (Sector I-VI) employing a combination of two adjacent effective vectors and a zero vector. Within a single PWM cycle T, the voltage vectors are arranged in a seven-segment structure of "zero vector - effective vector - zero vector - reverse conduction effective vector - zero vector," forming a symmetrical switching sequence. The zero voltage vectors include U0 (000), U7 (111), and U0 (000).

[0060] Specifically, when the carrier counter's count value equals the preset period value, i.e., the PRD setting value, the correction trigger timing is reached, and bias sampling is performed. Figure 3a In the middle, the time of the bias sampling point is T0 / 2. At this time, the switch state is 111, the upper bridge arms of U phase, V phase and W phase are all on, and the lower bridge arms are all off.

[0061] Specifically, such as Figure 3b As shown, when inverter switches S1, S3, and S5 are turned on, no current flows through sampling resistors R1, R2, and R3. At this time, the output of operational amplifiers A1, A2, and A3 is the zero-current bias voltage, which is used as the zero-current bias value.

[0062] In this embodiment, when the power converter uses five-segment space vector pulse width modulation, the correction triggering time is when the count value of the PWM carrier counter is equal to the preset period value.

[0063] like Figure 4a The diagram shows the three-phase PWM waveform and voltage vector application time of a five-segment SVPWM. This diagram clearly illustrates the generation of the three-phase PWM waveform and the timing of voltage vector application in sector I (0°≤θ<60°) of a complete five-segment SVPWM.

[0064] The five-segment SVPWM waveform in the figure consists of two effective voltage vectors and one zero voltage vector, with each sector (Sector I-VI) using a combination of two adjacent effective voltage vectors. Within a single PWM cycle T, the voltage vectors are arranged in a five-segment structure of "zero vector-effective vector-effective vector-effective vector-zero vector". The zero voltage vector includes U0 (000).

[0065] Specifically, when the carrier counter's count value equals the preset period value, i.e., the PRD setting value, the correction trigger timing is reached, and bias sampling is performed. Figure 4a In the middle, the time of the bias sampling point is T2. At this time, the switch state is 011. The upper bridge arm of phase U is off and the lower bridge arm is on. The upper bridge arms of phases V and W are both on and the lower bridge arms are both off.

[0066] Specifically, such as Figure 4b As shown, inverter switches S2, S3, and S5 are turned on, current flows through sampling resistor R1, and no current flows through sampling resistors R2 and R3. At this time, the outputs of operational amplifiers A2 and A3 are the zero-current bias voltage of phase V and phase W, respectively. These zero-current bias voltages of phase V and phase W are used as the zero-current bias values ​​of phase V and phase W.

[0067] In some implementations, during five-segment space vector pulse width modulation, before sampling the current sampling channel via an analog-to-digital converter at the corrected trigger timing, the following steps are also included: determining the current output voltage vector state; and determining the effective sampling phase in the current current sampling channel based on the output voltage vector state.

[0068] The effective sampling phase is the phase in which the lower bridge arm is conducting and the current flows through the current sampling resistor under the current voltage vector state.

[0069] In this embodiment, in conjunction with the appendix Figure 4a and appendix Figure 4b Phase V and phase W are the effective sampling phases.

[0070] Furthermore, the three-phase zero-bias correction for the current cycle is completed when the current bias data variables of phases U, V, and W are updated at least once within a preset time window.

[0071] Step S23: Process the raw sampled data to obtain the current zero current bias value.

[0072] Specifically, for the raw sampling data obtained from multiple consecutive samplings, an arithmetic mean calculation or median filtering calculation is performed to obtain the current zero current bias value.

[0073] Step S24: Update the stored current bias data variable using the current zero current bias value.

[0074] Specifically, the stored current bias data variable is directly replaced with the current zero current bias value.

[0075] Optionally, a first-order low-pass filter can be used to update the stored current bias data variables.

[0076] Specifically, according to the formula

[0077]

[0078] Perform calculations, where For the updated current bias data variables, The current bias data variable before the update. This is the current zero current bias value. Let be the filter coefficients and satisfy... .

[0079] Step S25: Determine the corrected current value based on the updated current bias data variables.

[0080] Specifically, in subsequent current measurements, the corrected current value is obtained by subtracting the updated current bias data variable from the original current value read from the analog-to-digital converter.

[0081] The current sampling zero-bias correction method provided in this application embodiment is also applicable to current sampling schemes based on the two-resistor sampling method.

[0082] like Figure 5 The diagram shows the basic principle of the current sampling scheme using the two-resistor sampling method. In this structure, the sources of the lower arm switches (S4, S6) of the three-phase inverter bridge are connected in series with sampling resistors (R2, R3) and grounded. By measuring the voltage across these resistors and performing signal conditioning (including amplification, filtering, and level shifting) through the corresponding operational amplifiers (A2, A3), the current flowing through each phase can be deduced. The analog-to-digital converter (ADC) module of the microprocessor (MCU) samples the conditioned voltage signal and participates in the calculation of the control algorithm.

[0083] When the carrier signal is equal to 0, the inverter bridge outputs a zero vector voltage U0 (000). At this time, the V-phase current signal and the W-phase current signal can be acquired. According to Kirchhoff's current law, the U-phase current signal can be obtained.

[0084] Under the seven-segment SVPWM waveform condition, when the carrier counter count value is equal to the preset period value, i.e. the PRD setting value, the correction triggering time is reached. At this time, the three-phase inverter bridge outputs a zero vector voltage U7 (111). The upper bridge arms of phases U, V, and W are all turned on, and the lower bridge arms are all turned off.

[0085] like Figure 6 As shown, when inverter switches S1, S3, and S5 are turned on, no current flows through sampling resistors R2 and R3. At this time, the outputs of operational amplifiers A2 and A3 are the zero-current bias voltage of phase V and phase W, respectively. These zero-current bias voltages of phase V and phase W are used as the zero-current bias values ​​of phase V and phase W, respectively.

[0086] Under the five-segment SVPWM waveform condition, when the carrier counter count value is equal to the preset period value, i.e. the PRD setting value, the conduction status of the inverter varies depending on the sector where the output voltage vector is located. Depending on the voltage sector where the target voltage vector is located, it is necessary to collect the "V phase zero current bias value", "W phase zero current bias value", or "V phase and W phase zero current bias value" according to the actual situation.

[0087] Optionally, when the count value of the wave counter is equal to the preset period value, i.e. the PRD setting value, the output voltage vector may be U4 (011), U6 (101), or U2 (110).

[0088] like Figure 7a As shown, when the carrier counter count value equals the preset period value, i.e., the PRD setting value, and the correction trigger is triggered, the output voltage vector of the five-segment SVPWM waveform is U4 (011). In this case, the inverter switches S2, S3, and S5 are turned on, and no current flows through the sampling resistors R2 and R3. At this time, the output results of the operational amplifiers A2 and A3 are the zero-current bias voltage of phase V and the zero-current bias voltage of phase W, respectively. These zero-current bias voltages of phase V and phase W are used as the zero-current bias values ​​of phase V and phase W, respectively.

[0089] like Figure 7b As shown, when the carrier counter count value equals the preset period value, i.e., the PRD setting value, and the correction trigger timing is triggered, the output voltage vector of the five-segment SVPWM waveform is U6 (101), where the inverter switches S1, S4, and S5 are turned on, current flows through the sampling resistor R2, and no current flows through the sampling resistor R3. At this time, the output signal of the operational amplifier A2 is 0, which cannot be used as the zero current bias voltage of phase V. The result output by the operational amplifier A3 is the zero current bias voltage of phase W. This zero current bias voltage of phase W is used as the zero current bias value of phase W.

[0090] like Figure 7cAs shown, when the carrier counter count value equals the preset period value, i.e. the PRD setting value, and the correction trigger timing is triggered, the output voltage vector of the five-segment SVPWM waveform is U2 (110). In this case, the inverter switches S1, S3, and S6 are turned on, current flows through the sampling resistor R3, and no current flows through the sampling resistor R2. At this time, the output signal of the operational amplifier A3 is 0, which cannot be used as the zero current bias voltage of phase W. The result of the output of the operational amplifier A2 is the zero current bias voltage of phase V. This zero current bias voltage of phase V is used as the zero current bias value of phase V.

[0091] The scope of protection of the current sampling zero bias correction method in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting or replacing steps in the prior art based on the principle of this application is included within the scope of protection of this application.

[0092] This application also provides a current sampling zero bias correction device, which can implement the current sampling zero bias correction method of this application. However, the implementation device of the current sampling zero bias correction method of this application includes, but is not limited to, the structure of the current sampling zero bias correction device listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principle of this application are included within the protection scope of this application.

[0093] Please see Figure 8 The image shows a current sampling zero-bias correction device provided in an embodiment of this application. The current sampling zero-bias correction device 80 includes:

[0094] microcontroller;

[0095] The current sampling circuit is configured to sense the current in the three-phase inverter circuit and convert it into a voltage signal;

[0096] An analog-to-digital converter, connected to a current sampling circuit, is configured to convert a voltage signal into a digital sample value;

[0097] The memory is configured to store at least one current bias data variable;

[0098] The microcontroller is configured to perform actions as described in any embodiment of this application and the appendix. Figure 2 -Appendix Figure 7c The current sampling zero-bias correction method is shown.

[0099] Since the specific implementation of this embodiment corresponds to the aforementioned method embodiment, the same details will not be repeated here, and those skilled in the art should also understand this. Figure 8The division of the modules in the embodiments is only a logical functional division. In actual implementation, they can be fully or partially integrated into one or more physical entities. These modules can be fully implemented in software through processing element calls, fully implemented in hardware, or some modules can be implemented in software through processing element calls and some modules can be implemented in hardware.

[0100] It should be noted that the above division of modules is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, module x can be a separate processing element, or it can be integrated into a chip in the aforementioned device. Alternatively, it can be stored as program code in the memory of the aforementioned device, and its function can be called and executed by a processing element of the device. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, the steps of the above method or the various modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0101] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be through some interfaces, or indirect couplings or communication connections between devices, modules, or units, and may be electrical, mechanical, or other forms. Modules / units described as separate components may or may not be physically separate. Components shown as modules / units may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the purpose of the embodiments of this application according to actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0102] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0104] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0105] In summary, this application provides a current sampling zero-bias correction method and apparatus. By periodically triggering and updating the current bias data during system operation, this application enables the current sampling reference to "follow" the actual operating point of the circuit in real time. This ensures that the absolute accuracy of current sampling remains at a high level under various load and temperature environments, from cold start to thermal stability. This solves the technical problem of dynamic bias drift caused by temperature rise during system operation. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0106] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A current sampling zero offset correction method, characterized by, The method comprises: determining a correction trigger timing, the correction trigger timing being a moment when a power converter output voltage vector is in a zero vector state and a theoretical value of a current flowing through a current sampling resistor is zero; at the correction trigger timing, sampling a current sampling channel by an analog-to-digital converter to obtain original sampling data under a zero current condition; processing the original sampling data to obtain a current zero current bias value; updating a stored current bias data variable using the current zero current bias value; and determining a corrected current value based on the updated current bias data variable.

2. The current sampling zero offset correction method of claim 1, wherein, When the power converter adopts seven-segment space vector pulse width modulation, the correction trigger timing is a moment when a count value of a PWM carrier counter is equal to a preset period value or equal to 0.

3. The current sampling zero bias correction method according to claim 1, characterized in that, when the power converter adopts five-segment space vector pulse width modulation, the correction trigger timing is a moment when a count value of a PWM carrier counter is equal to a preset period value.

4. The current sampling zero offset correction method of claim 3, wherein, Before sampling the current sampling channel by the analog-to-digital converter at the correction trigger timing, the method further comprises: judging a current output voltage vector state; determining an effective sampling phase in the current current sampling channel according to the output voltage vector state.

5. The current sampling zero offset correction method of claim 4, wherein, The effective sampling phase is a phase in which a lower bridge arm is turned on and a current flows through the current sampling resistor under the current voltage vector state.

6. The current sampling zero offset correction method of claim 3, wherein, When the current bias data variables of the U-phase, the V-phase and the W-phase are all updated at least once within a preset time window, then a current round of three-phase zero bias correction is completed.

7. The current sampling zero offset correction method of claim 1, wherein, Determining a corrected current value based on the updated current bias data variable comprises: subtracting the updated current bias data variable from an original current value read from the analog-to-digital converter during current measurement to obtain the corrected current value.

8. The current sampling zero offset correction method of claim 1, wherein, The current sampling channel is continuously sampled multiple times at a single correction trigger timing.

9. The current sampling zero offset correction method of claim 8, wherein, Processing the original sampling data to obtain a current zero current bias value comprises: performing arithmetic mean value calculation or median filtering calculation on the original sampling data sampled continuously multiple times to obtain the current zero current bias value.

10. A current sampling zero offset correction device, characterized by, The device comprises: a microcontroller; a current sampling circuit configured to sense a current of a three-phase inverter circuit and convert the current into a voltage signal; an analog-to-digital converter connected to the current sampling circuit and configured to convert the voltage signal into a digital sampling value; a memory configured to store at least one current bias data variable; wherein the microcontroller is configured to perform the current sampling zero bias correction method according to any one of claims 1 to 9.

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